A method for fabricating a low-capacitance, low-residual-voltage TVS device and the TVS device itself.

Abstract

This invention provides a method for fabricating a low-capacitance, low-residual-voltage TVS device and the TVS device itself, comprising: step S1, forming a P-type buried layer in a predetermined region of an N-type substrate; step S2, forming an epitaxial transition layer on the aforementioned surface, and growing an N-type epitaxial layer on the epitaxial transition layer; step S3, forming an SN layer and an SP layer in the N-type epitaxial layer; step S4, etching deep trenches in the N-type epitaxial layer, the deep trenches being filled with polysilicon in situ, the deep trenches including two first deep trenches and two second deep trenches; and step S5, depositing a dielectric layer, etching contact holes, and depositing a metal layer on the aforementioned surface. Beneficial effects: This invention innovatively employs an NPN structure, ensuring the current-carrying capacity of the device by precisely controlling the depth of the isolation deep trenches, while simultaneously reducing the clamping voltage. It can be widely applied to the protection of various high-speed data transmission ports; near-intrinsic high-resistivity epitaxy is obtained on a substrate with a high concentration of P-type buried layers, thereby ensuring the low-capacitance characteristics of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a low-capacitance, low-residual-voltage TVS device and the TVS device itself. Background Technology

[0002] Low-capacitance, low-residual-voltage transient diodes (TVS) are widely used for voltage transient and surge protection in high-frequency circuits. They consist of an avalanche diode with low breakdown voltage and a low-capacitance switching transistor. The low-capacitance switching transistor requires the growth of an almost intrinsic ultra-high resistivity N-type epitaxial layer on a high-density P-type buried layer and substrate. Chip capacitance and residual voltage are critical parameters that must be considered. Excessive capacitance will cause high-frequency signal distortion under capacitive loads, while high residual voltage will negatively impact downstream circuitry. Manufacturing a chip that simultaneously meets the requirements of low capacitance and low residual voltage is a significant challenge in TVS product development.

[0003] like Figure 1 As shown, this is a conventional PNP structure TVS device, such as... Figure 2 The diagram shows the equivalent circuit of a conventional PNP TVS device. The breakdown voltage diode Z1 is formed by an SP layer, an N-type epitaxial layer (Nepi), an N-type buried layer, and a P-type substrate (Psub). It has a relatively high residual voltage. The low-capacitance switching transistor D1 is formed by the SP layer and the N-type epitaxial layer. Its capacitance is significantly affected by the depth and side area of ​​the SP junction; poor process control can lead to excessive capacitance. Because the DTI deep trench penetrates into the substrate (Psub), the current-carrying junction formed by the N-type buried layer and the P-type substrate can only utilize the bottom area of ​​the N-type buried layer, which limits the current-carrying capacity of the TVS device to some extent. In addition to the DTI deep trench for isolation, a contact trench filled with a doped polysilicon layer at the bottom of the epitaxial layer is also provided. This inevitably increases the lateral area of ​​the device significantly, which is very detrimental to miniaturized packaging, increases cost, and makes it difficult to achieve extremely low device capacitance. This greatly limits the device's application in high-speed data ports. In summary, conventional PNP structure TVS devices have drawbacks such as poor current carrying capacity, high residual voltage, and unstable capacitance, making them difficult to meet the application requirements of high-speed data ports. Summary of the Invention

[0004] To address the above technical problems, this invention provides a method for fabricating a low-capacitance, low-residual-voltage TVS device and the TVS device itself.

[0005] The technical problem solved by this invention can be achieved by the following technical solutions:

[0006] A method for fabricating a low-capacitance, low-residual-voltage TVS device includes:

[0007] Step S1: Form a P-type buried layer in a predetermined region of an N-type substrate;

[0008] Step S2: An epitaxial transition layer is formed on the upper surface of the N-type substrate and the P-type buried layer, and an N-type epitaxial layer is grown on the upper surface of the epitaxial transition layer; wherein, during the growth of the N-type epitaxial layer, the P-type buried layer is reflected into the N-type epitaxial layer;

[0009] Step S3: Form an SN layer and an SP layer in the N-type epitaxial layer. The SN layer corresponds to the P-type buried layer in the longitudinal direction. Then, perform high-temperature annealing on the SN layer and the SP layer simultaneously.

[0010] Step S4: Etch deep trenches in the N-type epitaxial layer and fill the deep trenches with polysilicon in situ. The deep trenches include two first deep trenches that extend downward from the upper surface of the N-type epitaxial layer to the P-type buried layer; and two second deep trenches that extend downward from the upper surface of the SP layer through the SP layer.

[0011] Step S5: Deposit a dielectric layer on the above surface, etch contact holes corresponding to the SN layer and the SP layer, and deposit metal layers in the contact holes respectively.

[0012] Preferably, in step S1, the ion implantation element of the P-type buried layer is B or BF2, the implantation dose is 5E15-1.5E16, and the implantation energy is 60keV-80keV.

[0013] Preferably, before step S2, the method further includes:

[0014] A silicon dioxide dielectric layer is formed on the upper surface of the N-type substrate.

[0015] Preferably, in step S2, the resistivity of the N-type epitaxial layer is 200 ohm·cm-300 ohm·cm, and the thickness of the N-type epitaxial layer is 6 μm-10 μm.

[0016] Preferably, in step S2, the thickness of the epitaxial transition layer is 0.3µm-2µm;

[0017] The resistivity of the epitaxial transition layer is 0.5 ohm·cm.

[0018] Preferably, in step S3, the ion implantation elements of the SN layer are P and AS, the implantation dose is 1E15-8E15, and the implantation energy is 50keV-80keV.

[0019] The SP layer is implanted with B as the ion implantation element, with an implantation dose of 1E15-8E15 and an implantation energy of 50keV-80keV.

[0020] The annealing temperature is 1100°-1150°, and the annealing time is 60-90 min.

[0021] Preferably, in step S4, the spacing between the two first deep grooves is 0.3 to 0.5 times the width of the P-type buried layer.

[0022] Preferably, in step S4, the depth of the deep groove is 5um-8um, and the width of the deep groove is 1.2um.

[0023] Preferably, the area of ​​the P-type buried layer is greater than the area enclosed by the two first deep trenches.

[0024] This invention also provides a low-capacitance, low-residual-voltage TVS device, prepared using the method described above, comprising:

[0025] A P-type buried layer is formed in a predetermined region of an N-type substrate;

[0026] An epitaxial transition layer is formed on the upper surface of the N-type substrate and the P-type buried layer;

[0027] An N-type epitaxial layer is formed on the upper surface of the epitaxial transition layer;

[0028] An SN layer is formed in the N-type epitaxial layer, and the SN layer corresponds to the P-type buried layer in the longitudinal direction;

[0029] An SP layer is formed within the N-type epitaxial layer.

[0030] Multiple deep trenches are filled with polycrystalline silicon in situ. Each deep trench includes a first deep trench that extends downward from the upper surface of the epitaxial layer into the P-type buried layer; and a second deep trench that extends downward from the upper surface of the SP layer through the SP layer.

[0031] A dielectric layer is formed on the upper surface of the epitaxial layer and has contact holes corresponding to the SN layer and the SP layer etched therein, wherein a metal layer is deposited in the contact holes.

[0032] The advantages or beneficial effects of the technical solution of this invention are as follows:

[0033] The TVS device of this invention innovatively forms a unique NPN structure through an SN layer-N-type epitaxial layer-P-type buried layer-N-type substrate. Compared with conventional PNP structure formed by N-type buried layer, it has lower residual voltage, greater current carrying capacity, and reduced clamping voltage, and can be widely used for the protection of various high-speed data transmission ports. Near-intrinsic high-resistivity epitaxy is obtained on a substrate with a high concentration of P-type buried layer, thereby ensuring the low capacitance characteristics of the device. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a conventional PNP structure TVS device in the prior art;

[0035] Figure 2 This is a schematic diagram of the equivalent circuit of a conventional PNP structure TVS device in the prior art;

[0036] Figures 3a-3h This is a schematic diagram of each step in the fabrication method of a low-capacitance, low-residual-voltage TVS device in a preferred embodiment of the present invention.

[0037] Figure 4 This is an equivalent schematic diagram of the low-capacitance, low-residual-voltage TVS device prepared in a preferred embodiment of the present invention.

[0038] Figure 5 This is a schematic diagram of the equivalent circuit of the low-capacitance, low-residual-voltage TVS device prepared in a preferred embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0041] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0042] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a method for fabricating a low-capacitance, low-residual-voltage TVS device is provided, belonging to the field of semiconductor technology. Figures 3a-3h As shown, it includes:

[0043] Step S1, as follows Figure 3a and 3b As shown, a P-type buried layer 2 is formed in a predetermined region of an N-type substrate 1;

[0044] First, an N-type substrate 1 is provided, with a resistivity of less than 0.08 ohm·cm. Then, a P-type buried layer 2 is defined by photolithography and implanted with ions in a portion of the N-type substrate 1.

[0045] In a preferred embodiment, in step S1, the ion implantation element of the P-type buried layer 2 is B or BF2, the implantation dose is 5E15-1.5E16, and the implantation energy is 60kev-80kev.

[0046] Furthermore, the width of the P-type buried layer 2 should be set to be relatively large, which is beneficial to obtaining a diode with a larger junction area. The specific width can be set according to the actual device.

[0047] Step S2, as follows Figure 3c As shown, an epitaxial transition layer is formed on the upper surface of the N-type substrate 1 and the P-type buried layer 2, and an N-type epitaxial layer 3 is grown on the upper surface of the epitaxial transition layer; wherein, during the growth of the N-type epitaxial layer 3, the P-type buried layer 2 is reflected into the N-type epitaxial layer 3.

[0048] Specifically, an N-type epitaxial layer 3 is grown on the surface of the N-type substrate 1. Since the P-type buried layer 2 is highly doped and the growth temperature of high-resistivity epitaxy is relatively high, typically between 1130 and 1180 degrees Celsius, an N-type epitaxial transition layer is needed to effectively suppress the back-propagation of boron in the P-type buried layer during the high-resistivity epitaxy growth process. Simultaneously, during the high-resistivity epitaxy growth process, the P-type buried layer 2 will undergo some upward reflection, which will then propagate into the N-type epitaxial layer 3.

[0049] In a preferred embodiment, before step S2, the method further includes:

[0050] A silicon dioxide dielectric layer is formed on the upper surface of the N-type substrate 1.

[0051] It is important to note that obtaining high-quality near-intrinsic epitaxy on a substrate with a high concentration of P-type buried layer 2 is crucial, as it directly affects the device's capacitance. In this embodiment of the invention, silicon dioxide and silicon nitride dielectrics are deposited before epitaxy growth to provide back sealing and prevent phosphorus from the N-type substrate 1 from diffusing into it during the high-resistivity epitaxy growth process. Furthermore, a high-concentration N-type epitaxial transition layer is grown before the high-resistivity epitaxy to effectively suppress the back diffusion of boron in the P-type buried layer.

[0052] In a preferred embodiment, in step S2, the resistivity of the N-type epitaxial layer 3 is 200 ohm·cm-300 ohm·cm, and the thickness of the N-type epitaxial layer 3 is 6 μm-10 μm.

[0053] In a preferred embodiment, in step S2, the thickness of the epitaxial transition layer is 0.3µm-2µm;

[0054] The resistivity of the epitaxial transition layer is 0.5 ohm·cm.

[0055] Specifically, the appropriate thickness of the epitaxial transition layer is also very important. If the thickness is too thin, the overflow of boron in the P-type buried layer cannot be suppressed. If the thickness is too thick, the top reflection of the P-type buried layer 2 cannot penetrate the high-concentration N-type epitaxial transition layer. The junction of the low-capacitance switching transistor is formed by the P-type buried layer 2 and the N-type transition layer. Compared with the junction formed by the P-type buried layer 2 and the N-type epitaxial layer 3, the junction capacitance is larger, making it impossible to form a low-capacitance TVS device.

[0056] Step S3, as follows Figure 3d , 3e As shown in 3f, SN layer 4 and SP layer 5 are formed in N-type epitaxial layer 3. SN layer 4 corresponds to P-type buried layer 2 in the longitudinal direction. Then, SN layer 4 and SP layer 5 are simultaneously subjected to high-temperature annealing.

[0057] Specifically, after photolithographic definition in the N-type epitaxial layer 3, the SN layer 4 is formed by ion implantation. The ion implantation elements of the SN layer 4 are P and AS, the implantation dose is 1E15-8E15, and the implantation energy is 50keV-80keV.

[0058] Furthermore, after photolithographic definition in the N-type epitaxial layer 3, the SP layer 5 is formed by ion implantation. The ion implantation element of the SP layer 5 is B, the implantation dose is 1E15-8E15, and the implantation energy is 50keV-80keV.

[0059] Then, the device is placed in the furnace tube for high-temperature annealing of SP layer 5 and SN layer 4 to activate the injected elements. The annealing temperature is 1100°-1150° and the annealing time is 60-90 min.

[0060] Step S4, as follows Figure 3g As shown, deep trenches are etched in the N-type epitaxial layer 3 and polysilicon is filled in situ in the deep trenches. The deep trenches include two first deep trenches 61, which extend downward from the upper surface of the N-type epitaxial layer 3 to the P-type buried layer 2; and two second deep trenches 62, which extend downward from the upper surface of the SP layer 5 through the SP layer 5.

[0061] Specifically, a deep DTI trench is formed in the N-type epitaxial layer 3 by a dry etching process. After etching, the trench is filled with in-situ poly to achieve the isolation effect. Compared with SiO2, the in-situ poly has lower filling stress and better filling effect.

[0062] In a preferred embodiment, the depth of the deep groove is 5µm-8µm, and the width of the deep groove is 1.2µm.

[0063] Specifically, in order to meet the high requirements of residual voltage and current carrying capacity of TVS devices, the effective area of ​​the diode Z1 with breakdown voltage needs to be specially controlled in this embodiment of the invention. After growing the N-type high-resistivity epitaxial layer, the degree of reflection of the P-type buried layer is confirmed by slicing and SEM staining, so as to determine the depth of the DTI isolation trench. The requirement is that the depth of the isolation trench should be just enough to isolate the P-type buried layer 2, but it must not be etched through the P-type buried layer and extend into the N-type substrate.

[0064] Furthermore, if the depth of the first deep trench 61 extends into the N-type substrate 1, the effective area of ​​the diode Z1 formed by the N-type substrate 1 and the P-type buried layer 2 will be greatly reduced when current flows from IO2 to IO1. This will not only weaken the current carrying capacity of the device but also bring the negative impact of high residual voltage. If the depth of the first deep trench is too shallow, it will not be able to surround the P-type buried layer 2, the device capacitance will become very large, and it will also affect the breakdown voltage and leakage current of the device.

[0065] In a preferred embodiment, the spacing between the first deep trenches 61 on both sides of the SN layer 4 is 0.3 to 0.5 times the width of the P-type buried layer 2, which is beneficial for obtaining a switching transistor with a smaller PN junction area.

[0066] Specifically, the smaller spacing between the first deep trenches 61 on both sides of the SN layer 4 is to control the contact area between the P-type buried layer 2 and the N-type epitaxial layer 3, thereby minimizing the capacitance of the diode D1 and thus obtaining a low-capacitance TVS device.

[0067] In a preferred embodiment, the area of ​​the P-type buried layer 2 is larger than the area enclosed by the two first deep trenches.

[0068] Specifically, the above-mentioned P-type buried layer 2 has more surface reflection after the growth of N-type epitaxial layer 3, and the area of ​​P-type buried layer 2 must be much larger than the area surrounded by DTI deep trenches on both sides of the isolation SN layer 4, thereby greatly increasing the effective area of ​​the breakdown voltage diode Z1 and enhancing the current carrying capacity of the device.

[0069] Step S5, as follows Figure 3h As shown, a dielectric layer 7 is deposited on the surface, and contact holes corresponding to the SN layer 4 and SP layer 5 are etched out, and metal layers 8 are deposited in the contact holes respectively.

[0070] Specifically, a layer of SiO2 is deposited as the medium for the contact holes, and the thickness of the medium layer 7 is 0.6um-0.8um; the contact holes are defined by photolithography and dry etching and metal is deposited as electrodes IO1 and IO2. The metal layer 8 can be ALsiCu with a thickness of 4um-5um.

[0071] This invention also provides a low-capacitance, low-residual-voltage TVS device, which is prepared using the fabrication method for a low-capacitance, low-residual-voltage TVS device as described above. Figure 4 As shown, it includes:

[0072] A P-type buried layer 2 is formed in a predetermined region of an N-type substrate 1;

[0073] An epitaxial transition layer is formed on the upper surface of the N-type substrate 1 and the P-type buried layer 2;

[0074] An N-type epitaxial layer 3 is formed on the upper surface of the epitaxial transition layer;

[0075] An SN layer 4 is formed in the N-type epitaxial layer 3, and the SN layer 4 corresponds to the P-type buried layer 2 in the longitudinal direction;

[0076] One SP layer 5 is formed within the N-type epitaxial layer 3.

[0077] Multiple deep trenches are filled with polycrystalline silicon in situ. The deep trenches include a first deep trench 61, which extends downward from the upper surface of the N-type epitaxial layer 3 into the P-type buried layer 2; and a second deep trench 62, which extends downward from the upper surface of the SP layer 5 through the SP layer 5.

[0078] A dielectric layer 7 is formed on the upper surface of the N-type epitaxial layer 3, and contact holes corresponding to the SN layer 4 and SP layer 5 are etched therein, with a metal layer 8 deposited in the contact holes.

[0079] In the preferred embodiments described above, such as Figure 4 The diagram shown is an equivalent schematic of the low-capacitance, low-residual-voltage TVS device prepared according to an embodiment of the present invention; Figure 5 The diagram shown is the corresponding equivalent circuit diagram. The device consists of a low-capacitance switch D1, a low-breakdown-voltage diode Z1, and a low-capacitance switch D2. A unique NPN structure is formed through the SN layer 4-N-type epitaxial layer 3-P-type buried layer 2-N-type substrate 1. Compared with conventional PNP structures formed using N-type buried layers, it has a lower residual voltage and a greater current carrying capacity.

[0080] Among them, the low breakdown voltage diode Z1 is formed by the bottom and side of the N-type substrate 1 and the P-type buried layer 2, the low capacitance switch D1 is formed by the area defined by the two first deep trenches 61 on the top of the P-type buried layer 2 and the N-type epitaxial layer 3, and the low capacitance switch D2 is formed by the SP layer 5 and the N-type epitaxial layer 3. Since the width of the P-type buried layer 2 is much larger than the distance between the two first deep trenches 61, the diode Z1 has a larger PN junction area, while the PN junction area of ​​the switch D1 is smaller. The junction area of ​​the diode Z1 is more than 3 times that of the junction area of ​​the switch D1. Therefore, this device has the dual characteristics of large surge capability and small parasitic capacitance.

[0081] When a high potential is applied to the first port IO1 and a low potential is applied to the second port IO2, the current flows from the SP layer 5 through the N-type epitaxial layer 3 to the N-type substrate 1, and then directly through the switch D2 to the second port IO2. When a high potential is applied to the second port IO2 and a low potential is applied to the first port IO1, the current flows from the N-type substrate 1 through the P-type buried layer 2 and the N-type epitaxial layer 3 to the SN layer 4, and then to the first port IO1.

[0082] The above technical solution has the following advantages or beneficial effects: The TVS device of the present invention innovatively forms a unique NPN structure through SN layer-N-type epitaxial layer-P-type buried layer-N-type substrate. Compared with conventional PNP structure formed by N-type buried layer, it has lower residual voltage, greater current carrying capacity, and reduced clamping voltage. It can be widely used for the protection of various high-speed data transmission ports. Near-intrinsic high-resistivity epitaxy is obtained on a substrate with high concentration of P-type buried layer, thereby ensuring the low capacitance characteristics of the device.

[0083] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a low-capacitance, low-residual-voltage TVS device, characterized in that, include: Step S1: Form a P-type buried layer in a predetermined region of an N-type substrate; Step S2: An epitaxial transition layer is formed on the upper surface of the N-type substrate and the P-type buried layer, and an N-type epitaxial layer is grown on the upper surface of the epitaxial transition layer; wherein, during the growth of the N-type epitaxial layer, the P-type buried layer is reflected into the N-type epitaxial layer; the thickness of the epitaxial transition layer is 0.3um-2um. Step S3: Form an SN layer and an SP layer in the N-type epitaxial layer. The SN layer corresponds to the P-type buried layer in the longitudinal direction. Then, perform high-temperature annealing on the SN layer and the SP layer simultaneously. Step S4: Etch deep trenches in the N-type epitaxial layer and fill the deep trenches with polysilicon in situ. The deep trenches include two first deep trenches that extend downward from the upper surface of the N-type epitaxial layer to the P-type buried layer; and two second deep trenches that extend downward from the upper surface of the SP layer through the SP layer. Step S5: Deposit a dielectric layer on the above surface, etch contact holes corresponding to the SN layer and the SP layer, and deposit metal layers in the contact holes respectively.

2. The method for fabricating a low-capacitance, low-residual-voltage TVS device according to claim 1, characterized in that, In step S1, the ion implantation element of the P-type buried layer is B or BF2, the implantation dose is 5E15-1.5E16, and the implantation energy is 60keV-80keV.

3. The method for fabricating a low-capacitance, low-residual-voltage TVS device according to claim 1, characterized in that, Before step S2, the method further includes: A silicon dioxide dielectric layer is formed on the upper surface of the N-type substrate.

4. The method for fabricating a low-capacitance, low-residual-voltage TVS device according to claim 1, characterized in that, In step S2, the resistivity of the N-type epitaxial layer is 200 ohm·cm-300 ohm·cm, and the thickness of the N-type epitaxial layer is 6 μm-10 μm.

5. The method for fabricating a low-capacitance, low-residual-voltage TVS device according to claim 1, characterized in that, In step S2, the resistivity of the epitaxial transition layer is 0.5 ohm·cm.

6. The method for fabricating a low-capacitance, low-residual-voltage TVS device according to claim 1, characterized in that, In step S3, the ion implantation elements of the SN layer are P and AS, the implantation dose is 1E15-8E15, and the implantation energy is 50keV-80keV. The SP layer is implanted with B as the ion implantation element, with an implantation dose of 1E15-8E15 and an implantation energy of 50keV-80keV. The annealing temperature is 1100°-1150°, and the annealing time is 60-90 min.

7. The method for fabricating a low-capacitance, low-residual-voltage TVS device according to claim 1, characterized in that, In step S4, the spacing between the two first deep grooves is 0.3 to 0.5 times the width of the P-type buried layer.

8. The method for fabricating a low-capacitance, low-residual-voltage TVS device according to claim 1, characterized in that, In step S4, the depth of the deep groove is 5um-8um, and the width of the deep groove is 1.2um.

9. The method for fabricating a low-capacitance, low-residual-voltage TVS device according to claim 1, characterized in that, The area of ​​the P-type buried layer is greater than the area enclosed by the two first deep trenches.

10. A low-capacitance, low-residual-voltage TVS device, characterized in that, The low-capacitance, low-residual-voltage TVS device is prepared using the fabrication method described in any one of claims 1-9, comprising: A P-type buried layer is formed in a predetermined region of an N-type substrate; An epitaxial transition layer is formed on the upper surface of the N-type substrate and the P-type buried layer; An N-type epitaxial layer is formed on the upper surface of the epitaxial transition layer; An SN layer is formed in the N-type epitaxial layer, and the SN layer corresponds to the P-type buried layer in the longitudinal direction; An SP layer is formed within the N-type epitaxial layer. Multiple deep trenches are filled with polycrystalline silicon in situ. Each deep trench includes a first deep trench that extends downward from the upper surface of the N-type epitaxial layer into the P-type buried layer; and a second deep trench that extends downward from the upper surface of the SP layer through the SP layer. A dielectric layer is formed on the upper surface of the N-type epitaxial layer and has contact holes corresponding to the SN layer and the SP layer etched therein, wherein a metal layer is deposited in the contact holes.

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