ESD protection device, manufacturing method and chip

Abstract

The application discloses an ESD protection device, a manufacturing method and a chip, and relates to the technical field of semiconductor devices. The ESD protection device comprises a semiconductor substrate, an N-type well region and a P-type well region formed on the semiconductor substrate, a first N-type heavily doped region and a first P-type heavily doped region formed on the N-type well region, and a second N-type heavily doped region and a second P-type heavily doped region formed on the P-type well region. The second N-type heavily doped region is arranged opposite to the first P-type heavily doped region, and the second P-type heavily doped region is arranged opposite to the first N-type heavily doped region. The ESD protection device provided by the application can not only save the area of the chip, but also form multiple groups of parasitic NPN triodes and PNP triodes in parallel in the ESD protection device, so that the turn-on voltage of the parasitic NPN triode and PNP triode is smaller and the turn-on is more uniform, thereby improving the stability of the ESD protection device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and particularly relates to an ESD protection device, a manufacturing method and a chip. BACKGROUND

[0002] With the feature size of the manufacturing process of a semiconductor integrated circuit (IC) becoming smaller and smaller, the size of a chip also becomes smaller and smaller, and the anti-static ability of the chip becomes more and more important. The destructive influence of electro-static discharge (ESD) on the chip is more and more significant.

[0003] A silicon control rectifier (SCR) can be used for an electro-static discharge protection circuit of a chip. However, the traditional SCR protection device has the defects of occupying a large chip area, the turn-on voltage of a parasitic NPN triode and a PNP triode being high, and turn-on being uneven, which leads to poor stability of the SCR protection device. SUMMARY

[0004] The application provides an ESD protection device, a manufacturing method and a chip, and aims to solve the technical problems of the traditional SCR protection device, such as occupying a large chip area, the turn-on voltage of a parasitic NPN triode and a PNP triode being high, and turn-on being uneven.

[0005] A first aspect of the application provides an ESD protection device, comprising:

[0006] a semiconductor substrate;

[0007] an N-type well region and a P-type well region, which are formed on the semiconductor substrate and in contact with each other;

[0008] a first N-type heavily doped region and a first P-type heavily doped region, which are formed on the N-type well region;

[0009] a second N-type heavily doped region and a second P-type heavily doped region, which are formed on the P-type well region; wherein the second N-type heavily doped region is arranged opposite to the first P-type heavily doped region, and the second P-type heavily doped region is arranged opposite to the first N-type heavily doped region;

[0010] a first dielectric isolation layer, which is formed on the first N-type heavily doped region and the first P-type heavily doped region;

[0011] a second dielectric isolation layer, which is formed on the second N-type heavily doped region and the second P-type heavily doped region;

[0012] an anode metal layer, which is formed on the first N-type heavily doped region, the first P-type heavily doped region, the first dielectric isolation layer, the second N-type heavily doped region and the second P-type heavily doped region.

[0013] a cathode metal layer formed on the second N-type heavily doped region, the second P-type heavily doped region and the second dielectric isolation layer.

[0014] As an optional implementation of the first aspect, the N-type well region is a concave structure, and the first N-type heavily doped region and the first P-type heavily doped region are filled in the concave groove of the N-type well region.

[0015] As an optional implementation of the first aspect, the P-type well region is a concave structure, and the second N-type heavily doped region and the second P-type heavily doped region are filled in the concave groove of the P-type well region.

[0016] As an optional implementation of the first aspect, the first N-type heavily doped region and the second P-type heavily doped region are arranged in parallel.

[0017] As an optional implementation of the first aspect, the second N-type heavily doped region and the first P-type heavily doped region are arranged in parallel.

[0018] As an optional implementation of the first aspect, the number of the first N-type heavily doped region and the first P-type heavily doped region is multiple, and the number of the second N-type heavily doped region and the second P-type heavily doped region is multiple.

[0019] The multiple first N-type heavily doped regions and the multiple first P-type heavily doped regions are arranged alternately, and the multiple second N-type heavily doped regions and the multiple second P-type heavily doped regions are arranged alternately.

[0020] The multiple first N-type heavily doped regions and the multiple second P-type heavily doped regions are arranged in one-to-one correspondence, and the multiple second N-type heavily doped regions and the multiple first P-type heavily doped regions are arranged in one-to-one correspondence.

[0021] As an optional implementation of the first aspect, the distance between adjacent first N-type heavily doped regions is equal, and the distance between adjacent second N-type heavily doped regions is equal.

[0022] As an optional implementation of the first aspect, the width of the first P-type heavily doped region is equal to that of the corresponding second N-type heavily doped region.

[0023] The second aspect of the embodiments of the present application provides a manufacturing method of an ESD protection device, comprising:

[0024] forming an N-type well region and a P-type well region on a semiconductor substrate, the N-type well region and the P-type well region being in contact with each other;

[0025] forming a first N-type heavily doped region and a first P-type heavily doped region on the N-type well region, and forming a second N-type heavily doped region and a second P-type heavily doped region on the P-type well region; wherein the second N-type heavily doped region is arranged opposite to the first P-type heavily doped region, and the second P-type heavily doped region is arranged opposite to the first N-type heavily doped region.

[0026] A first dielectric isolation layer is formed on the first N-type heavily doped region and the first P-type heavily doped region, and a second dielectric isolation layer is formed on the second N-type heavily doped region and the second P-type heavily doped region;

[0027] An anode metal layer is formed on the first N-type heavily doped region, the first P-type heavily doped region, and the first dielectric isolation layer, and a cathode metal layer is formed on the second N-type heavily doped region, the second P-type heavily doped region, and the second dielectric isolation layer.

[0028] A third aspect of this application provides a chip including at least one ESD protection device as described in the first aspect above, wherein different ESD protection devices are cascaded together.

[0029] The beneficial effects of the embodiments in this application compared with the prior art are:

[0030] By integrating the N-type heavily doped region and the P-type heavily doped region of the anode in a traditional SCR protection device into a first N-type heavily doped region and a first P-type heavily doped region, and integrating the N-type heavily doped region and the P-type heavily doped region of the cathode in a traditional SCR protection device into a second N-type heavily doped region and a second P-type heavily doped region, with the second N-type heavily doped region positioned opposite to the first P-type heavily doped region and the second P-type heavily doped region positioned opposite to the first N-type heavily doped region, not only can the chip area occupied by the traditional SCR protection device be saved, but multiple sets of parasitic NPN and PNP transistors can also be formed in the ESD protection device. This results in a lower turn-on voltage and more uniform turn-on of the parasitic NPN and PNP transistors, thereby improving the stability of the ESD protection device, which in turn improves the stability of the SCR protection device. Attached Figure Description

[0031] Figure 1 A schematic diagram of the structure of an ESD protection device provided in an embodiment of this application is shown;

[0032] Figure 2 for Figure 1 The diagram shows the structure of the parasitic NPN and PNP transistors in the ESD protection device.

[0033] Figure 3 The figure shows an application example diagram of an ESD protection device provided in an embodiment of this application;

[0034] Figure 4 A flowchart illustrating a method for manufacturing an ESD protection device according to an embodiment of this application is shown.

[0035] Figures 5 to 9 The following are schematic diagrams illustrating the manufacturing process of an ESD protection device provided in one embodiment of this application.

[0036] It is illustrated that:

[0037] 11, semiconductor substrate; 12, N-type well region; 13, P-type well region; 14, anode doped region; 141, first N-type heavily doped region; 142, first P-type heavily doped region; 15, cathode doped region; 151, second N-type heavily doped region; 152, second P-type heavily doped region; 16, first dielectric isolation layer; 17, second dielectric isolation layer; 18, anode metal layer; 19, cathode metal layer; 20, shallow trench isolation structure; R1, first parasitic resistance; R2, second parasitic resistance; Q1, NPN-type transistor; Q2, PNP-type transistor. DETAILED DESCRIPTION

[0038] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0039] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0040] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0041] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0042] With the feature size of the manufacturing process of semiconductor integrated circuits becoming smaller and smaller, the size of the chip is also becoming smaller and smaller, and the antistatic ability of the chip becomes more and more important. The destructive effect of electrostatic discharge on the chip is more and more significant.

[0043] Silicon controlled rectifier can be used in the electrostatic discharge protection circuit of the chip. For example, when the SCR is used to protect the pin of the chip, a safe discharge path can be provided for the current generated by the ESD event to avoid the ESD event from damaging the pin.

[0044] The working principle of the SCR protection device is as follows: the SCR protection device is composed of a parasitic PNP transistor and a parasitic NPN transistor. When the ESD event occurs, the pn junction composed of the N-type well region and the P-type well region of the SCR protection device is reversed biased. When the reverse bias voltage is greater than the avalanche breakdown voltage of the pn junction, a large number of electron-hole pairs are generated. When the electron current flows through the N-type well region, the emitter junction of the parasitic PNP transistor is positively biased. With the opening of the PNP transistor, the collector current of the PNP transistor flows through the P-type well region, and the emitter junction of the NPN transistor is positively biased, so that the NPN transistor is opened. Then, the collector current of the PNP transistor provides the base current for the NPN transistor, and the collector current of the NPN transistor provides the base current for the PNP transistor, thereby generating a positive feedback mechanism between the parasitic PNP transistor and the NPN transistor, so that the SCR is turned on, thereby providing a safe discharge path for the current generated by the ESD event, protecting the pin of the chip, and avoiding the pin from being damaged by the ESD event.

[0045] However, in the above-mentioned SCR protection device, the anode doped region and the cathode doped region occupy a large chip area, so that the opening voltage of the above-mentioned parasitic NPN transistor and PNP transistor is high and uneven, resulting in poor stability of the SCR protection device.

[0046] Therefore, the embodiments of the present application provide an ESD protection device, a manufacturing method and a chip. By reducing the chip area occupied by the heavy doped region included in the anode doped region and the cathode doped region in the ESD protection device, a plurality of groups of parallel parasitic NPN transistors and PNP transistors are formed in the ESD protection device, so that the opening voltage of the parasitic NPN transistor and PNP transistor is smaller and more uniform, thereby improving the stability of the ESD protection device, for example, improving the stability of the above-mentioned SCR protection device.

[0047] In order to illustrate the technical solutions described in the present application, the following specific embodiments are used for illustration.

[0048] Figure 1 The structure schematic diagram of the ESD protection device provided by an embodiment of the present application is shown. For the convenience of description, only the part related to the present embodiment is shown.

[0049] As Figure 1As shown in the figure, the ESD protection device provided by the embodiment includes a semiconductor substrate 11, an N-type well region 12, a P-type well region 13, a first N-type heavily doped region 141, a first P-type heavily doped region 142, a second N-type heavily doped region 151, a second P-type heavily doped region 152, a first dielectric isolation layer 16, a second dielectric isolation layer 17, an anode metal layer 18, and a cathode metal layer 19.

[0050] The material of the semiconductor substrate 11 is not limited in the embodiment. For example, the semiconductor substrate 11 can be a substrate made of silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or the like.

[0051] The N-type well region 12 and the P-type well region 13 are formed on the semiconductor substrate 11 and contact each other. The embodiment does not limit how to form the N-type well region 12 and the P-type well region 13. For example, the N-type well region 12 and the P-type well region 13 can be formed by ion implantation, diffusion, epitaxial growth, or the like.

[0052] The first N-type heavily doped region 141 and the first P-type heavily doped region 142 are respectively formed on the N-type well region 12.

[0053] Optionally, the first N-type heavily doped region 141 and the first P-type heavily doped region 142 are in contact.

[0054] Optionally, the first N-type heavily doped region 141 and the first P-type heavily doped region 142 are not in contact.

[0055] Optionally, the first N-type heavily doped region 141 and the first P-type heavily doped region 142 are anode doped regions 14 of the ESD protection device.

[0056] The anode doped region 14 can be understood as a doped region used as an anode of the ESD protection device. For example, when the ESD protection device is an SCR, the anode doped region 14 is used to connect a pin that needs to be protected in a chip.

[0057] The embodiment does not limit how to form the anode doped region 14. For example, the anode doped region 14 can be formed on the N-type well region 12 by ion implantation, diffusion, epitaxial growth, or the like, that is, the first N-type heavily doped region 141 and the first P-type heavily doped region 142 are formed.

[0058] Optionally, when the anode doped region 14 is formed by ion implantation, a selected-area ion implantation method can be used to form the anode doped region 14 in a specified area, as shown in the figure. Figure 1

[0059] The second N-type heavily doped region 151 and the second P-type heavily doped region 152 are respectively formed on the P-type well region 13.

[0060] ​Optionally, the second N-type heavily doped region 151 is in contact with the second P-type heavily doped region 152.

[0061] Optionally, the second N-type heavily doped region 151 is not in contact with the second P-type heavily doped region 152.

[0062] Optionally, the second N-type heavily doped region 151 and the second P-type heavily doped region 152 are cathode doped regions 15 of the ESD protection device.

[0063] The cathode doped regions 15 can be understood as the doped regions used as cathodes of the ESD protection device. For example, when the ESD protection device is an SCR, the cathode doped regions 15 are used to connect the ground of the chip.

[0064] The embodiment does not make a specific limitation on the process used to form the cathode doped regions 15. For example, the cathode doped regions 15, i.e., the second N-type heavily doped region 151 and the second P-type heavily doped region 152, can be formed on the P-type well region 13 by ion implantation, diffusion or epitaxial growth.

[0065] Optionally, when the cathode doped regions 15 are formed by ion implantation, a selective ion implantation method can be used to form the cathode doped regions 15 in the specified area, as shown in FIG. 2B. Figure 1

[0066] The second N-type heavily doped region 151 is arranged opposite to the first P-type heavily doped region 142, and the second P-type heavily doped region 152 is arranged opposite to the first N-type heavily doped region 141, so that the chip area occupied by the traditional SCR protection device can be saved.

[0067] The first dielectric isolation layer 16 is formed on the first N-type heavily doped region 141 and the first P-type heavily doped region 142, and the second dielectric isolation layer 17 is formed on the second N-type heavily doped region 151 and the second P-type heavily doped region 152.

[0068] The anode metal layer 18 is formed on the first N-type heavily doped region 141, the first P-type heavily doped region 142 and the first dielectric isolation layer 16. The cathode metal layer 19 is formed on the second N-type heavily doped region 151, the second P-type heavily doped region 152 and the second dielectric isolation layer 17.

[0069] It should be understood that the embodiment does not make a specific limitation on the structure and position of the first dielectric isolation layer 16, the second dielectric isolation layer 17, the anode metal layer 18 and the cathode metal layer 19. For example, a person skilled in the art can set them according to the relevant semiconductor device process technology (for example, CMOS preparation process).

[0070] As shown in FIG. 3A, the first dielectric isolation layer 16 is formed on the first N-type heavily doped region 141 and the first P-type heavily doped region 142. Figure 2 ​As shown, in the ESD protection device with the above structure, a plurality of groups of parallel parasitic NPN triodes Q1 and PNP triodes Q2 can be formed, each NPN triode Q1 has a first parasitic resistor R1 between the collector and the corresponding first N-type heavily doped region 141, each PNP triode Q2 has a second parasitic resistor R2 between the collector and the corresponding second P-type heavily doped region 152, the collector of the NPN triode Q1 is also connected to the base of the PNP triode Q2, and the collector of the PNP triode Q2 is also connected to the base of the NPN triode Q1. As an example, Figure 2 A group of parasitic NPN triodes Q1 and PNP triodes Q2 are shown.

[0071] Compared with the traditional ESD protection device, the ESD protection device provided by the embodiment can save the chip area occupied by the traditional SCR protection device, and a plurality of groups of parallel parasitic NPN triodes Q1 and PNP triodes Q2 can be formed in the ESD protection device, so that the turn-on voltage of the parasitic NPN triodes Q1 and PNP triodes Q2 is smaller and the turn-on is more uniform, thereby improving the stability of the ESD protection device, i.e., the stability of the SCR protection device.

[0072] Optionally, since the first N-type heavily doped region 141 and the first P-type heavily doped region 142 can be arranged in the anode doped region 14, and the second N-type heavily doped region 151 and the second P-type heavily doped region 152 can be arranged in the cathode doped region 15, the thicknesses of the first N-type heavily doped region 141, the first P-type heavily doped region 142, the second N-type heavily doped region 151, and the second P-type heavily doped region 152 can be better controlled, for example, the thicknesses of the respective heavily doped regions are consistent, so that the turn-on between the respective parasitic NPN triodes Q1 and PNP triodes Q2 is more uniform, and the turn-on of the parasitic NPN triodes Q1 and PNP triodes Q2 between different ESD protection devices is more uniform, thereby ultimately improving the stability of the ESD protection device.

[0073] As shown, Figure 3 As an optional implementation of the above embodiment, the ESD protection device provided by the embodiment is an SCR, the emitter of the PNP triode Q2 and the first end of the first parasitic resistor R1 are the anode of the SCR, and the emitter of the NPN triode Q1 and the second end of the second parasitic resistor R2 are the cathode of the SCR.

[0074] In the chip, the anode of the SCR is connected to the pin to be protected, and the cathode of the SCR is connected to the ground. When an ESD event occurs at the pin of the chip, the plurality of groups of parallel parasitic NPN triodes Q1 and PNP triodes Q2 in the SCR can be turned on at a smaller ESD current, thereby providing a safe discharge path for the current generated by the ESD event to avoid damage to the pin caused by the ESD event.

[0075] like Figure 1 As shown, as an optional implementation of the above embodiment, the N-type well region 12 has a concave structure, and the first N-type heavily doped region 141 and the first P-type heavily doped region 142 are filled in the groove of the N-type well region 12, so that the first N-type heavily doped region 141 and the first P-type heavily doped region 142 are in more sufficient contact with the N-type well region 12.

[0076] like Figure 1 As shown, in an optional embodiment of the above example, the P-type well region 13 has a concave structure, and the second N-type heavily doped region 151 and the second P-type heavily doped region 152 are filled in the groove of the P-type well region 13, so that the second N-type heavily doped region 151 and the second P-type heavily doped region 152 are in more sufficient contact with the P-type well region 13.

[0077] like Figure 1 As shown, in an optional implementation of the above embodiment, the first N-type heavily doped region 141 and the second P-type heavily doped region 152 are arranged in parallel. Figure 1 As shown, in an optional implementation of the above embodiment, the second N-type heavily doped region 151 is arranged in parallel with the first P-type heavily doped region 142. Optionally, this arrangement facilitates control of the turn-on voltage of each parasitic NPN transistor Q1 and PNP transistor Q2, for example, controlling the turn-on voltage of each parasitic NPN transistor Q1 and PNP transistor Q2 to be equal.

[0078] As an optional implementation of the above embodiments, there are multiple first N-type heavily doped regions 141 and first P-type heavily doped regions 142, and multiple second N-type heavily doped regions 151 and second P-type heavily doped regions 152.

[0079] Multiple first N-type heavily doped regions 141 and multiple first P-type heavily doped regions 142 are alternately arranged, and multiple second N-type heavily doped regions 151 and multiple second P-type heavily doped regions 152 are alternately arranged.

[0080] Multiple first N-type heavily doped regions 141 are arranged in a one-to-one correspondence with multiple second P-type heavily doped regions 152.

[0081] The above configuration can form multiple sets of parasitic NPN transistors Q1 and PNP transistors Q2 in parallel in the ESD protection device, thereby making the turn-on voltage of the parasitic NPN transistors Q1 and PNP transistors Q2 smaller and the turn-on more uniform.

[0082] As an optional implementation of the above embodiment, the distance between adjacent first N-type heavily doped regions 141 is equal.

[0083] For example, adjacent first N-type heavily doped regions 141 are spaced equally to facilitate adjustment of the turn-on voltage of the parasitic transistors (NPN transistor Q1 and PNP transistor Q2). For example, the turn-on voltage of each parasitic transistor is controlled to be equal.

[0084] It should be understood that, as another optional implementation of the above embodiments, the distance between adjacent first N-type heavily doped regions 141 may be unequal, in order to adjust the turn-on voltage of the parasitic transistors. For example, the turn-on voltages of each parasitic transistor may be controlled to be unequal.

[0085] As an optional implementation of the above embodiment, the distance between adjacent first P-type heavily doped regions 142 is equal.

[0086] For example, adjacent first P-type heavily doped regions 142 are spaced equally to facilitate adjustment of the turn-on voltage of parasitic transistors. For instance, the turn-on voltage of each parasitic transistor is controlled to be equal.

[0087] It should be understood that, as another optional implementation of the above embodiments, the distance between adjacent first P-type heavily doped regions 142 may be unequal, in order to adjust the turn-on voltage of the parasitic transistors. For example, the turn-on voltages of each parasitic transistor may be controlled to be unequal.

[0088] like Figure 1 As shown, in an optional implementation of the above embodiment, the widths of the first P-type heavily doped region 142 and the corresponding second N-type heavily doped region 151 are equal to facilitate adjustment of the turn-on voltage of the parasitic transistors. For example, the turn-on voltages of each parasitic transistor can be controlled to be equal.

[0089] like Figure 1 As shown, in an optional embodiment of the above example, the cathode doped region 15 and the anode doped region 14 have the same thickness. For example, thickness refers to... Figure 1 The distance shown is in the longitudinal direction (vertical direction). Optionally, this setting facilitates adjustment of the turn-on voltage of the parasitic transistors. For example, it controls the turn-on voltage of each parasitic transistor to be equal.

[0090] As an optional implementation of the above-mentioned embodiment, the N-type well region 12 is concave, the first N-type heavily doped region 141 and the first P-type heavily doped region 142 are filled in the concave groove of the N-type well region 12; the P-type well region 13 is concave, the second N-type heavily doped region 151 and the second P-type heavily doped region 152 are filled in the concave groove of the P-type well region 13; the first N-type heavily doped region 141 is arranged in parallel with the second P-type heavily doped region 152; the second N-type heavily doped region 151 is arranged in parallel with the first P-type heavily doped region 142; the number of the first N-type heavily doped region 141 and the first P-type heavily doped region 142 is multiple, and the number of the second N-type heavily doped region 151 and the second P-type heavily doped region 152 is multiple; the multiple first N-type heavily doped regions 141 are arranged in pairs of correspondence with the multiple second P-type heavily doped regions 152, and the multiple second N-type heavily doped regions 151 are arranged in pairs of correspondence with the multiple first P-type heavily doped regions 142; the distance between adjacent first N-type heavily doped regions 141 is equal, and the distance between adjacent second N-type heavily doped regions 151 is equal; the width of the first P-type heavily doped region 142 corresponding to the second N-type heavily doped region 151 is equal. Optionally, this arrangement facilitates adjustment of the turn-on voltage of the parasitic triode. For example, the turn-on voltages of the respective parasitic triodes are equal.

[0091] The ESD protection device provided by the above-mentioned embodiment can not only save the chip area occupied by the traditional SCR protection device, but also form multiple groups of parallel parasitic NPN triodes Q1 and PNP triodes Q2 in the ESD protection device, so that the turn-on voltage of the parasitic NPN triode Q1 and the PNP triode Q2 is smaller and the turn-on is more uniform, thereby improving the stability of the ESD protection device.

[0092] As shown in FIG. 1, Figure 4 In another embodiment of the present application, a manufacturing method of an ESD protection device is also provided to solve the technical problems of the traditional ESD protection device, such as large chip area, high turn-on voltage of the parasitic NPN triode Q1 and the PNP triode Q2, and uneven turn-on.

[0093] As shown in FIG. 1, Figure 4 The manufacturing method comprises the following steps:

[0094] S101, form the N-type well region 12 and the P-type well region 13 on the semiconductor substrate 11, and the N-type well region 12 and the P-type well region 13 are in contact with each other. The embodiment does not limit the forming sequence between the N-type well region 12 and the P-type well region 13.

[0095] Optionally, as shown in the figure, the N-type well region 12 and the P-type well region 13 can be formed on the semiconductor substrate 11 by ion implantation, diffusion or epitaxial growth. Figure 5

[0096] Optionally, the semiconductor substrate 11 can be a substrate made of silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN) or silicon carbide (SiC) and the like.

[0097] S102, form the first N-type heavily doped region 141 and the first P-type heavily doped region 142 on the N-type well region 12 respectively, and form the second N-type heavily doped region 151 and the second P-type heavily doped region 152 on the P-type well region 13 respectively.

[0098] Among them, the second N-type heavily doped region 151 is arranged opposite to the first P-type heavily doped region 142, and the second P-type heavily doped region 152 is arranged opposite to the first N-type heavily doped region 141.

[0099] Optionally, as shown in the figure, the first N-type heavily doped region 141 and the first P-type heavily doped region 142 can be formed on the N-type well region 12 by ion implantation, diffusion or epitaxial growth, and the second N-type heavily doped region 151 and the second P-type heavily doped region 152 can be formed on the P-type well region 13 by ion implantation, diffusion or epitaxial growth. Figure 6

[0100] It should be understood that the embodiment does not specifically limit the sequence between the first N-type heavily doped region 141, the first P-type heavily doped region 142, the second N-type heavily doped region 151 and the second P-type heavily doped region 152.

[0101] In the manufacturing method provided by the embodiment, the anode doped region 14 formed at the same time includes the first N-type heavily doped region 141 and the first P-type heavily doped region, and the cathode doped region 15 formed at the same time includes the second N-type heavily doped region 151 and the second P-type heavily doped region 152, so that the cathode doped region 15 is arranged opposite to the anode doped region 14, thereby reducing the occupied area of the cathode doped region 15 and the anode doped region 14, and further reducing the occupied area of the ESD protection device, and forming multiple groups of parallel parasitic NPN triodes Q1 and PNP triodes Q2.

[0102] ​​S103, forming a first dielectric isolation layer 16 on the first N-type heavily doped region 141 and the first P-type heavily doped region 142, and forming a second dielectric isolation layer 17 on the second N-type heavily doped region 151 and the second P-type heavily doped region 152.

[0103] Optionally, the present embodiment does not make specific limitation on the sequence of forming the first dielectric isolation layer 16 and the second dielectric isolation layer 17.

[0104] S104, forming an anode metal layer 18 on the first N-type heavily doped region 141, the first P-type heavily doped region 142 and the first dielectric isolation layer 16, and forming a cathode metal layer 19 on the second N-type heavily doped region 151, the second P-type heavily doped region 152 and the second dielectric isolation layer 17.

[0105] Optionally, the present embodiment does not make specific limitation on the sequence of forming the anode metal layer 18 and the cathode metal layer 19.

[0106] The present embodiment can obtain an ESD protection device as shown in Figure 1 by the above S101-S104.

[0107] As shown in Figure 7 , Figure 8 and Figure 9 , as an optional implementation of the present embodiment, after step S102, the manufacturing method provided by the present embodiment further includes the following steps:

[0108] S1021, using a shallow trench isolation (STI) technology, forming a shallow trench isolation structure 20 on the N-type well region 12 and the P-type well region 13, for separating the cathode doped region 15 and the anode doped region 14 of the ESD protection device.

[0109] Optionally, the two sides of the ESD protection device also have the shallow trench isolation structure 20.

[0110] It should be understood that the present embodiment does not make specific limitation on the structure and position of the first dielectric isolation layer 16, the second dielectric isolation layer 17, the anode metal layer 18, the cathode metal layer 19 and the shallow trench isolation structure 20. For example, a person skilled in the art can set them according to the relevant semiconductor device process technology (for example, CMOS preparation process).

[0111] The ESD protection device manufactured by the manufacturing method has the advantages that the chip area occupied by the traditional SCR protection device can be saved, and multiple groups of parasitic NPN triodes Q1 and PNP triodes Q2 in parallel can be formed in the ESD protection device, so that the turn-on voltage of the parasitic NPN triodes Q1 and PNP triodes Q2 is smaller and the turn-on is more uniform, thereby improving the stability of the ESD protection device.

[0112] Optionally, the gap at the lower surface of the anode metal layer 18 and the cathode metal layer 19 can be filled by a passivation layer (not shown in the figure), which is not limited in the embodiment. For example, a person skilled in the art can set it according to the related semiconductor device process technology (for example, CMOS preparation process).

[0113] The ESD protection device manufactured by the manufacturing method provided in the embodiment can be applied to protect a chip, the anode metal layer 18 is connected to a pin of the chip to be protected, and the cathode metal layer 19 is connected to the ground of the chip, so as to provide a safe discharge path for the current generated by the ESD event, thereby avoiding damage to the pin caused by the ESD event.

[0114] It should be understood that the manufacturing method provided in the embodiment can manufacture an ESD protection device Figures 1 to 3 The ESD protection device provided in the embodiment also has the advantages of Figures 1 to 3 The embodiment has the advantages of

[0115] In another embodiment of the present application, a chip is also provided, which includes at least one ESD protection device provided in the above embodiment, and the different ESD protection devices are cascaded.

[0116] When the chip includes one ESD protection device, the anode of the ESD protection device is connected to a pin of the chip, and the cathode of the ESD protection device is connected to the ground of the chip, so as to achieve ESD protection.

[0117] When the chip includes multiple ESD protection devices, the multiple ESD protection devices are cascaded, that is, the anodes of the multiple ESD protection devices are connected to the pins of the chip, and the cathodes of the multiple ESD protection devices are connected to the ground of the chip, so as to improve the protection level of the chip. Optionally, a high protection level means that the ESD current that can be borne is larger, and the chip can be better protected to avoid damage to the pins of the chip caused by the ESD event.

[0118] As an example, the ESD protection device is an SCR.

[0119] When the SCR is used to protect a pin of a chip, a safe discharge path can be provided for the current generated by the ESD event, so as to avoid damage to the pin caused by the ESD event.

[0120] The working principle of the SCR protection device is as follows: the SCR protection device is composed of multiple groups of parasitic PNP transistors Q2 and NPN transistors Q1 in parallel. When an ESD event occurs, the pn junction formed by the N-type well region 12 and the P-type well region 13 of the SCR protection device is reverse biased. When the reverse bias voltage is greater than the avalanche breakdown voltage of the pn junction, a large number of electron-hole pairs are generated. When the electron current flows through the N-type well region 12, the emitter junction of the parasitic PNP transistor Q2 is forward biased. With the opening of the PNP transistor Q2, the collector current of the PNP transistor Q2 flows through the P-type well region 13, and the emitter junction of the NPN transistor Q1 is forward biased, so that the NPN transistor Q1 is opened. Then, the collector current of the PNP transistor Q2 provides the base current for the NPN transistor Q1, and the collector current of the NPN transistor Q1 provides the base current for the PNP transistor Q2, thereby generating a positive feedback mechanism between the parasitic PNP transistor Q2 and the NPN transistor Q1, so that the SCR is turned on, thereby providing a safe discharge path for the current generated by the ESD event, protecting the pins of the chip and avoiding damage to the pins caused by the ESD event.

[0121] The chip provided by the embodiment can set the ESD protection device in a smaller area. The opening voltage of each parasitic NPN transistor Q1 and PNP transistor Q2 in the ESD protection device is smaller and more uniform, and the stability of the ESD protection device and the chip is higher.

[0122] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the foregoing embodiments of the present application have been described in detail, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. An ESD protection device, characterized in that, include: Semiconductor substrate; An N-type well region and a P-type well region are formed on the semiconductor substrate, and the N-type well region and the P-type well region are in contact with each other. The first N-type heavily doped region and the first P-type heavily doped region are respectively formed on the N-type well region; the first N-type heavily doped region and the first P-type heavily doped region serve as the anode doped region of the ESD protection device; A second N-type heavily doped region and a second P-type heavily doped region are formed on the P-type well region, respectively; wherein, the second N-type heavily doped region is disposed opposite to the first P-type heavily doped region, and the second P-type heavily doped region is disposed opposite to the first N-type heavily doped region; the second N-type heavily doped region and the second P-type heavily doped region serve as the cathode doped regions of the ESD protection device. A first dielectric isolation layer is formed on the first N-type heavily doped region and the first P-type heavily doped region; The second dielectric isolation layer is formed on the second N-type heavily doped region and the second P-type heavily doped region; An anode metal layer is formed on the first N-type heavily doped region, the first P-type heavily doped region, and the first dielectric isolation layer; A cathode metal layer is formed on the second N-type heavily doped region, the second P-type heavily doped region, and the second dielectric isolation layer.

2. The ESD protection device according to claim 1, characterized in that, The N-type well region has a concave structure, and the first N-type heavily doped region and the first P-type heavily doped region fill the groove of the N-type well region.

3. The ESD protection device according to claim 1, characterized in that, The P-type well region has a concave structure, and the second N-type heavily doped region and the second P-type heavily doped region fill the groove of the P-type well region.

4. The ESD protection device according to claim 1, characterized in that, The first N-type heavily doped region and the second P-type heavily doped region are arranged in parallel.

5. The ESD protection device according to claim 1, characterized in that, The second N-type heavily doped region is arranged in parallel with the first P-type heavily doped region.

6. The ESD protection device according to claim 1, characterized in that, The number of the first N-type heavily doped region and the first P-type heavily doped region is multiple, and the multiple first N-type heavily doped regions and the multiple first P-type heavily doped regions are alternately arranged; The number of the second N-type heavily doped region and the second P-type heavily doped region is multiple, and the multiple second N-type heavily doped regions and the multiple second P-type heavily doped regions are alternately arranged; Multiple first N-type heavily doped regions are arranged in a one-to-one correspondence with multiple second P-type heavily doped regions, and multiple second N-type heavily doped regions are arranged in a one-to-one correspondence with multiple first P-type heavily doped regions.

7. The ESD protection device according to claim 6, characterized in that, The distance between adjacent first N-type heavily doped regions is equal, and the distance between adjacent second N-type heavily doped regions is equal.

8. The ESD protection device according to claim 1, characterized in that, The width of the first P-type heavily doped region is equal to the width of the corresponding second N-type heavily doped region.

9. A method for manufacturing an ESD protection device, characterized in that, include: An N-type well region and a P-type well region are formed on a semiconductor substrate, wherein the N-type well region and the P-type well region are in contact with each other; A first N-type heavily doped region and a first P-type heavily doped region are formed on the N-type well region, and a second N-type heavily doped region and a second P-type heavily doped region are formed on the P-type well region; wherein, the second N-type heavily doped region is disposed opposite to the first P-type heavily doped region, and the second P-type heavily doped region is disposed opposite to the first N-type heavily doped region. A first dielectric isolation layer is formed on the first N-type heavily doped region and the first P-type heavily doped region, and a second dielectric isolation layer is formed on the second N-type heavily doped region and the second P-type heavily doped region; An anode metal layer is formed on the first heavily doped N-type region, the first heavily doped P-type region, and the first dielectric isolation layer; and a cathode metal layer is formed on the second heavily doped N-type region, the second heavily doped P-type region, and the second dielectric isolation layer; the first heavily doped N-type region and the first heavily doped P-type region serve as the anode doping regions of the ESD protection device. ， The second N-type heavily doped region and the second P-type heavily doped region serve as the cathode doped regions of the ESD protection device.

10. A chip, characterized in that, It includes at least one ESD protection device as described in any one of claims 1 to 8, with different ESD protection devices cascaded together.

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