A method for improving the ability to plan multiple blocks on a single wafer

Abstract

The present invention discloses a manufacturing method for improving the planning of multiple different blocks on a single wafer, comprising the following steps: step S1, planning multiple blocks; step S2, setting multiple different correction values; step S3, determining a wiring method for the correction values, and leading the wiring layer to the top metal wiring layer during the physical layout implementation process; step S4, sample testing, testing different blocks separately, and selecting the block that best meets the design goals after the test is completed; step S5, the entire wafer only needs to modify the top metal mask based on the original data to enable large-scale mass production of chips. This manufacturing method not only saves a lot of valuable time, effectively improves the success rate of single wafers, shortens the chip design cycle, and reduces costs, but also avoids the problem of tight production capacity.

Description

Technical field

[0001] The present invention relates to wafer tape-out technology, and in particular to a method for improving the production of multiple different blocks on a single wafer. [Background Technology]

[0002] In the existing technology, independent tape-out wafers are usually single-project wafers. However, in special cases, in order to save tape-out costs and produce a large number of chips at the same time, a tape-out format in which multiple chips are arranged on a single wafer is adopted, that is, independent tape-out of multi-project wafers.

[0003] For single-project wafers, since there's only one project on the entire wafer, the layout is relatively simple and regular, all chips are the same size, and all scribe lanes are the same. A single block on a wafer is identical, meaning that if a problem occurs with that block, the entire wafer suffers. Given tight global wafer production capacity, this is undoubtedly a waste of resources and increases chip design cycles, thereby reducing the competitiveness of chip design companies within the industry.

[0004] For multi-project wafers, a single wafer contains two or more types of chips, and the sizes of each chip may be different; therefore, in a multi-project wafer, the layout of various chips is diverse.

[0005] At the same time, after tape-out, both single-project and multi-project wafers need to undergo mid-stage testing on a probe station. In order to successfully complete the mid-stage testing of multi-project wafers and ensure that the map files can be used in subsequent processing after mid-stage testing, the multi-project wafer panel must meet certain rules.

[0006] The above situation requires defect analysis of wafers during the production and manufacturing process of multi-project wafers. As the number of product types in multi-project wafers increases, it is impossible to monitor the defect level of each product. That is, it is necessary to combine multiple products on the same platform to analyze the defect level. However, there are great differences in the grain size and number of grains of each product. When performing defect scanning, the effective scanning area of ​​the product with more grains is smaller than that of the product with fewer grains. If n particles are randomly scattered, due to the difference in scanning area, the number of defects detected on the product with more grains is less than that of the product with fewer grains (defects are randomly distributed). If the current analysis method is used, it is impossible to accurately mix products with different numbers of grains together to analyze the defect level.

[0007] Therefore, the existing analysis method of multi-project wafers also increases the chip design cycle, thereby reducing the competitiveness of chip design companies in the industry. There is an urgent need to improve the existing multi-project wafer manufacturing method to improve the detection efficiency of subsequent processes. [Summary of the invention]

[0008] The present invention provides a manufacturing method for improving the planning of multiple different blocks on a single wafer, effectively improving the success rate of a single wafer, shortening the chip design cycle and reducing costs.

[0009] The technical solution adopted by the present invention to solve its technical problem is:

[0010] A method for improving the planning of multiple different blocks on a single wafer is provided, and is used to plan multiple different blocks on a single wafer. The method comprises the following steps:

[0011] Step S1: Plan multiple blocks

[0012] Multiple different blocks are planned on a single wafer. The different blocks have the same size and shape but only differ in the connections of the top n metal layers. n is a positive integer greater than or equal to 1. If n is 1, the blocks only differ in the connections of the top metal layer. If n is 2, the blocks differ in the connections of the top two metal layers. Similarly, if n is m, the blocks differ in the connections of the top m metal layers.

[0013] Step S2, setting multiple different correction values

[0014] When n=1, different blocks only have different metal connections on the top layer. When n=2, different blocks have different metal connections on the top two layers. Similarly, when n=m, different blocks have different metal connections on the top m layers.

[0015] Then, the metal option is used to obtain different trim values ​​for the relevant parameters corresponding to different blocks.

[0016] Specifically, according to the characteristics of the circuit, multiple important parameters with correction functions are designed. Each parameter is 0 or 1. Then, according to different parameters, they are encoded in BCD code to obtain different correction values ​​for the relevant parameters corresponding to different blocks.

[0017] Step S3, determine the connection method of the correction value

[0018] During the physical layout implementation process, the wiring layer is led to the top metal wiring layer. After parameter encoding, the correction value corresponding to 1 is connected to the power line VDD or the high-level clamp unit through the layout physical connection, and the correction value corresponding to 0 is connected to the top ground line VSS or the low-level clamp unit through the physical layout connection, forming a design according to the process metal line mask selection method;

[0019] Step S4: Sample testing

[0020] After chip production is complete, sample testing is conducted, testing different blocks separately. After the test is completed, the block that best meets the design goals is selected. Without additional tape-out, the top-level metal mask is directly modified in the original data, that is, the correction values ​​of other blocks are changed to the same as the correction values ​​of the block that best meets the design goals.

[0021] In the layout data, the correction value 1 is changed to 0, that is, the original top metal layer connected to the power line VDD or the high-level clamping unit is changed to the ground line VSS or the low-level clamping unit; the correction value 0 is changed to 1, that is, the original top metal layer connected to the ground line VSS or the low-level clamping unit is changed to the power line VDD or the high-level clamping unit;

[0022] In step S5, the entire wafer only needs to modify the highest metal layer mask based on the original data to carry out large-scale mass production of chips.

[0023] Furthermore, the BCD (Binary-Coded Decimal) code in step S2 includes 8421 BCD code, 2421 BCD code or 5421 BCD code.

[0024] Furthermore, the step S2 further includes:

[0025] In step S2, multiple different trim values ​​are set for multiple important parameters in the chip control circuit, including the output voltage U, the signal modulation mode M, and the charging mode P. Then, a value that meets the design requirements is selected from the multiple different trim values.

[0026] Furthermore, the step S2 further includes:

[0027] When eight modules, namely A, B, C, D, E, F, G and H, are planned on the wafer, the voltage U, signal modulation mode M and charging mode P of module A are set to 000 respectively; and so on.

[0028] Set the voltage U, signal modulation mode M, and charging mode P of block B to 001 respectively;

[0029] Set the voltage U, signal modulation mode M, and charging mode P of the C module block to 010 respectively;

[0030] Set the voltage U, signal modulation mode M, and charging mode P of the D module block to 011 respectively;

[0031] Set the voltage U, signal modulation mode M, and charging mode P of the E module block to 100 respectively;

[0032] Set the voltage U, signal modulation mode M, and charging mode P of the F module block to 101 respectively;

[0033] Set the voltage U, signal modulation mode M, and charging mode P of the G module block to 110 respectively;

[0034] Set the voltage U, signal modulation mode M, and charging mode P of the H module block to 111 respectively;

[0035] Based on step S2 and step S3, step S4 further includes:

[0036] Test the different blocks A, B, C, D, E, F, G, and H corresponding to modules A, B, C, D, E, F, G, and H respectively. After the test, select the block A that best meets the design goals. Without adding additional tape-outs, directly modify the top-level metal mask in the original data. That is, change the correction values ​​in other blocks B, C, D, E, F, G, and H to the same value of 000 as the correction value of block A.

[0037] The specific operation is: first locate the area of ​​block B, and find out that the original correction value of block B is 001. The correction value of block B needs to be changed to the same correction value 000 as block A. It is found that the difference between the original correction value 001 of block B and the changed value 000 is the rightmost bit. Just change the rightmost 1 to 0, that is, in the layout data, change the original top-level metal connection to the power line VDD or the high-level clamping unit to the ground line VSS or the low-level clamping unit. The same is true for other blocks. In this way, the entire wafer only needs to change the top-level metal layer mask based on the original data to carry out large-scale chip production.

[0038] The beneficial effects of the present invention are:

[0039] The manufacturing method provided by the present invention plans multiple different blocks on a single wafer. These different blocks have the same size and shape, but different metal connections in the highest n layers of the layout wiring (n is a positive integer greater than or equal to 1). If n is 1, the cost of modifying the mask later is lower and the efficiency is higher. The method solves the problem of low chip success rate and waste of resources and time caused by single wafer and single block in wafer fabs, greatly improves the success rate of chip production on a single wafer, shortens the entire chip development and design cycle, improves the competitiveness of enterprises in the entire industry, and reduces costs, promoting the rapid development of enterprises and even the entire industry.

Brief Description of the Drawings

[0040] Figure 1 The left side of the present invention is a functional block diagram of a wafer having only one identical block named A, and the right side is a functional block diagram of a wafer having eight different blocks;

[0041] Figure 2 It is a schematic flow diagram of the present invention. [Specific implementation method]

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0043] A method for improving the planning of multiple different blocks on a single wafer wafer is used to plan multiple different blocks on a single wafer wafer, such as Figure 2 As shown, the production method comprises the following steps:

[0044] Step S1: Plan multiple blocks

[0045] Multiple different blocks are planned on a single wafer. The different blocks have the same size and shape but only differ in the top n metal layers. n is a positive integer greater than or equal to 1. If n is 1, the different blocks only differ in the top metal layer. If n is 1, the cost of modifying the mask later is lower and the efficiency is higher. If n is 2, the different blocks have different metal connections in the top two layers. Similarly, if n is m, the different blocks have different metal connections in the top m layers.

[0046] Step S2, setting multiple different trim values

[0047] For example, when n=1, different blocks only have different top-level metal connections. When n=2, different blocks have different top-two metal connections. Similarly, when n=m, different blocks have different top-m metal connections. Then, using the metal option mask, different trim values ​​(trim) are obtained for the relevant parameters corresponding to different blocks.

[0048] Specifically, based on the characteristics of the circuit, multiple important parameters with trimmable values ​​are designed, each parameter being 0 or 1. Then, based on the different parameters, they are encoded using BCD (Binary-Coded Decimal) code to obtain different trim values ​​(trim) for the relevant parameters corresponding to different blocks. BCD (Binary-Coded Decimal) codes include but are not limited to 8421 BCD code, 2421 BCD code, or 5421 BCD code.

[0049] In step S2, multiple different trim values ​​are set for multiple important parameters in the chip control circuit. These multiple important parameters include output voltage U, signal modulation mode M, and charging mode P. Generally, a value that meets the design requirements is selected from the multiple different trim values.

[0050] For example, Figure 1As shown, when eight modules, namely module A, module B, module C, module D, module E, module F, module G and module H, are planned on the wafer, the voltage U, signal modulation mode M and charging mode P of module A are set to 000 respectively; and similarly, the BCD encoding of the parameters can have eight settings from 000 to 111. In this embodiment, eight actual designs are used for illustration.

[0051] Set the voltage U, signal modulation mode M, and charging mode P of block B to 001 respectively;

[0052] Set the voltage U, signal modulation mode M, and charging mode P of the C module block to 010 respectively;

[0053] Set the voltage U, signal modulation mode M, and charging mode P of the D module block to 011 respectively;

[0054] Set the voltage U, signal modulation mode M, and charging mode P of the E module block to 100 respectively;

[0055] Set the voltage U, signal modulation mode M, and charging mode P of the F module block to 101 respectively;

[0056] Set the voltage U, signal modulation mode M, and charging mode P of the G module block to 110 respectively;

[0057] Set the voltage U, signal modulation mode M, and charging mode P of the H module block to 111 respectively;

[0058] Step S3, determine the connection method of the correction value (trim)

[0059] During the physical layout implementation process, the wiring layer is brought to the top metal wiring layer. After parameter encoding, the trim value (trim) corresponding to 1 is connected to the power line VDD or the high-level clamp unit (tie-high) through the layout physical connection, and the trim value (trim) corresponding to 0 is connected to the top ground line VSS or the low-level clamp unit (tie-low) through the physical layout connection, forming a design according to the process metal line mask selection method (metal option);

[0060] Step S4: Sample testing

[0061] After chip production is complete, sample testing is performed on different blocks. After the testing is completed, the block that best meets the design goals is selected. Without additional tape-out, the top metal mask is directly modified in the original data. That is, the trim values ​​of other blocks are changed to the same as the trim values ​​of the block that best meets the design goals.

[0062] In the layout data, if the trim value (trim) 1 is changed to 0, the original top metal layer connected to the power line (VDD) or the high-level clamping unit (tie-high) is changed to the ground line (VSS) or the low-level clamping unit (tie-low); if the trim value (trim) 0 is changed to 1, the original top metal layer connected to the ground line (VSS) or the low-level clamping unit (tie-low) is changed to the power line (VDD) or the high-level clamping unit (tie-high);

[0063] For example, test blocks A, B, C, D, E, F, G, and H corresponding to modules A, B, C, D, E, F, G, and H, respectively. After the test, select block A that best meets the design goals. Without adding additional tape-outs, directly modify the top-level metal mask in the original data. That is, change the trim values ​​in blocks B, C, D, E, F, G, and H to the same value of 000 as the trim value of block A.

[0064] The specific operation is: first locate the area of ​​block B, and find out that the original trim value (trim) of block B is 001. The trim value (trim) of block B needs to be changed to the same trim value (trim) as block A, 000. It is found that the difference between the original trim value (trim) 001 of block B and the modified value 000 is the rightmost bit. Just change the rightmost 1 to 0, that is, in the layout data, change the original top layer metal connection to the power line VDD or the high-level clamp unit (tie-high) to the ground line VSS or the low-level clamp unit (tie-low). The same is true for other blocks.

[0065] In step S5, the entire wafer only needs to change the highest metal layer mask based on the original data to carry out large-scale mass production of chips, which not only saves a lot of valuable time but also avoids the problem of tight production capacity.

[0066] In this embodiment, to avoid the drawback of having only one identical block per wafer, multiple different blocks are planned on a single wafer. These different blocks differ in the top n metal layers (n is a positive integer greater than or equal to 1). If n is 1, the cost of modifying the mask later is lower and efficiency is higher. This solves the problem of low chip success rate and wasted resources and time caused by wafer fabs using only one wafer and one block. It not only improves the success rate of single wafers, but also shortens the chip design cycle and reduces costs.

[0067] To make it easier to understand this production method, let's take an example: a single wafer is planned to have 8 different blocks, and only the top metal connection is different. 8 blocks with different masks can produce 8 different chips. After the 8 different chips are tested, the success rate of passing the test is also increased by nearly 8 times. If one chip among the 8 passes the test, then the next version of the wafer can be mass-produced by changing only the top metal mask, effectively improving the success rate of a single wafer and shortening the chip design cycle, thereby reducing the cost of tapeout.

[0068] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of implementation of the present invention. Any equivalent changes made based on the shape, structure and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for improving the planning of multiple different blocks on a single wafer, for planning multiple different blocks on a single wafer, characterized in that: The preparation method comprises the following steps: Step S1: Plan multiple blocks Multiple different blocks are planned on a single wafer. The different blocks have the same size and shape but only differ in the connections of the top n metal layers. n is a positive integer greater than or equal to 1. If n is 1, the blocks only differ in the connections of the top metal layer. If n is 2, the blocks differ in the connections of the top two metal layers. Similarly, if n is m, the blocks differ in the connections of the top m metal layers. Step S2, setting multiple different correction values When n=1, different blocks only have different metal connections on the top layer. When n=2, different blocks have different metal connections on the top two layers. Similarly, when n=m, different blocks have different metal connections on the top m layers. Then, the process metal wire mask selection method is used to obtain different correction values ​​of relevant parameters corresponding to different blocks; Specifically, according to the characteristics of the circuit, multiple important parameters with correction functions are designed. Each parameter is 0 or 1. Then, according to different parameters, they are encoded in BCD code to obtain different correction values ​​for the relevant parameters corresponding to different blocks. Step S3, determine the connection method of the correction value During the physical layout implementation process, the wiring layer is led to the top metal wiring layer. After parameter encoding, the correction value corresponding to 1 is connected to the power line VDD or the high-level clamp unit through the layout physical connection, and the correction value corresponding to 0 is connected to the top ground line VSS or the low-level clamp unit through the physical layout connection, forming a design according to the process metal line mask selection method; Step S4: Sample testing After chip production is complete, sample testing is conducted, testing different blocks separately. After the test is completed, the block that best meets the design goals is selected. Without additional tape-out, the top-level metal mask is directly modified in the original data, that is, the correction values ​​of other blocks are changed to the same as the correction values ​​of the block that best meets the design goals. In the layout data, the correction value 1 is changed to 0, that is, the original top metal layer connected to the power line VDD or the high-level clamping unit is changed to the ground line VSS or the low-level clamping unit; the correction value 0 is changed to 1, that is, the original top metal layer connected to the ground line VSS or the low-level clamping unit is changed to the power line VDD or the high-level clamping unit; In step S5, the entire wafer only needs to modify the highest metal layer mask based on the original data to carry out large-scale mass production of chips.

2. The method for improving the planning of multiple blocks on a single wafer according to claim 1, characterized in that: The BCD code in step S2 includes 8421 BCD code, 2421 BCD code or 5421 BCD code.

3. The method for improving the planning of multiple blocks on a single wafer according to claim 1, characterized in that: The step S2 further includes: In step S2, multiple different correction values ​​are set for multiple important parameters in the chip control circuit, including the output voltage U, the signal modulation mode M and the charging mode P. Then, a value that meets the design requirements is selected from the multiple different correction values.

4. The method for improving the planning of multiple blocks on a single wafer according to claim 2, characterized in that: The step S2 further includes: When eight modules, namely A, B, C, D, E, F, G and H, are planned on the wafer, the voltage U, signal modulation mode M and charging mode P of module A are set to 000 respectively; and so on. Set the voltage U, signal modulation mode M, and charging mode P of block B to 001 respectively; Set the voltage U, signal modulation mode M, and charging mode P of the C module block to 010 respectively; Set the voltage U, signal modulation mode M, and charging mode P of the D module block to 011 respectively; Set the voltage U, signal modulation mode M, and charging mode P of the E module block to 100 respectively; Set the voltage U, signal modulation mode M, and charging mode P of the F module block to 101 respectively; Set the voltage U, signal modulation mode M, and charging mode P of the G module block to 110 respectively; Set the voltage U, signal modulation mode M, and charging mode P of the H module block to 111 respectively; Based on step S2 and step S3, step S4 further includes: Test blocks A, B, C, D, E, F, G, and H corresponding to modules A, B, C, D, E, F, G, and H, respectively. After the test, select block A that best meets the design goals. Without adding additional tape-outs, directly modify the top-level metal mask in the original data. That is, change the correction values ​​in blocks B, C, D, E, F, G, and H to the same value of 000 as the correction value of block A. The specific operation is: first locate the area of ​​block B, and find out that the original correction value of block B is 001. The correction value of block B needs to be changed to the same correction value 000 as block A. It is found that the difference between the original correction value 001 of block B and the changed value 000 is the rightmost bit. Just change the rightmost 1 to 0, that is, in the layout data, change the original top-level metal connection to the power line VDD or the high-level clamping unit to the ground line VSS or the low-level clamping unit. The same is true for other blocks. In this way, the entire wafer only needs to change the top-level metal layer mask based on the original data to carry out large-scale chip production.

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