Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a preparation method thereof, and the semiconductor device comprises a driving backboard, a bonding layer, a display pixel area and a plurality of interconnection layers, a plurality of electrode contacts are arranged on one side of the driving backboard at intervals, the bonding layer is arranged on the side of the driving backboard provided with the electrode contacts, and a through hole is arranged on the bonding layer and in contact with each electrode contact; the display pixel area comprises a plurality of light emitting units arranged on the side of the bonding layer away from the driving backboard at intervals, and the anodes of the plurality of light emitting units are connected with the bonding layer; the interconnection layer, the light emitting unit and the through hole are in one-to-one correspondence, a part of the interconnection layer is accommodated in the through hole and connected with the electrode contact, and another part of the interconnection layer is arranged on the side of the bonding layer facing the light emitting unit and connected with the cathode of the light emitting unit. The semiconductor device can reduce the etching space required in preparation, is beneficial to further miniaturization of the semiconductor device, does not need to use extremely high alignment accuracy, and simplifies the preparation process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In traditional semiconductor devices, functional devices and the driving circuits used to control these devices are typically distributed on different wafers or substrates. Currently, semiconductor devices are generally integrated by interconnecting the wafers containing the functional devices and the substrates containing the driving circuits through metal bonding. However, in existing semiconductor device structures, because the driving end metal pads on the substrate correspond one-to-one with the functional devices on the wafer, a large etching space is required during fabrication to achieve one-to-one isolation etching between the bonding metal and the functional devices. Alternatively, extremely high alignment precision is required to fabricate multiple driving end metal pads that correspond one-to-one with multiple functional devices. This significantly limits further miniaturization of semiconductor devices. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor device and its fabrication method to address the technical problems that limit the further miniaturization of semiconductor devices caused by the shortcomings of existing semiconductor device fabrication processes, such as the need to reserve a large etching space and high bonding alignment accuracy.

[0004] A semiconductor device, the semiconductor device comprising:

[0005] A drive backplate, wherein multiple electrode contacts are spaced apart on one side of the drive backplate;

[0006] A bonding layer is disposed on the side of the drive back plate where the electrode contacts are disposed, and through holes are provided in the bonding layer at the parts that contact each of the electrode contacts;

[0007] The display pixel area includes multiple light-emitting units spaced apart on the side of the bonding layer away from the driving backplate, and the anodes of the multiple light-emitting units are all connected to the bonding layer.

[0008] Multiple interconnect layers are provided, and the interconnect layers, the light-emitting units, and the vias are in a one-to-one correspondence. A portion of the interconnect layer is housed in the via and connected to the electrode contacts. Another portion of the interconnect layer is disposed on the side of the bonding layer facing the light-emitting unit and connected to the cathode of the light-emitting unit.

[0009] In one embodiment, the bonding layer includes a first bonding layer and a second bonding layer bonded to each other. The first bonding layer is prepared on the surface of the driving backplate where the electrode contacts are provided, and the second bonding layer is electrically connected to the light-emitting unit.

[0010] In one embodiment, a first insulating dielectric layer is disposed between the interconnect layer and the bonding layer.

[0011] In one embodiment, a second insulating dielectric layer is disposed on the bonding layer within the light-emitting unit and the display pixel area.

[0012] In one embodiment, the bonding layer has multiple through holes at the contact points with each of the electrode contacts, and each of the electrode contacts is electrically connected to the cathodes of multiple light-emitting units.

[0013] In one embodiment, a first metal film layer is disposed on the driving backplate surrounding the display pixel area, and the first metal film layer is electrically connected to the circuit components on the driving backplate.

[0014] In one embodiment, a second metal film layer is disposed on the bonding layer surrounding the display pixel area, and the second metal film layer is electrically connected to the circuit components on the driving backplane.

[0015] In one embodiment, a method for fabricating a semiconductor device is also provided, the method comprising the following steps:

[0016] A first bonding layer is prepared on a drive backplate having electrode contacts;

[0017] A second bonding layer is fabricated on a target wafer having a compound semiconductor, the second bonding layer being electrically connected to the compound semiconductor;

[0018] The first bonding layer and the second bonding layer are bonded together to form a bonding layer;

[0019] Multiple light-emitting units are fabricated by patterning the compound semiconductor to form a display pixel area on the driving backplane;

[0020] Through-holes exposing the electrode contacts are formed on the bonding layer by an etching process;

[0021] An interconnect layer is formed at the through-hole to electrically connect the cathode of the light-emitting unit to the electrode contacts.

[0022] In one embodiment, before depositing an interconnect layer at the via to electrically connect the cathode of the light-emitting unit to the electrode contacts, the following step is further included:

[0023] A dielectric insulating layer is deposited covering the pixel display area;

[0024] The dielectric insulating layer is patterned to expose the electrode contacts, the cathode of the light-emitting unit, and the bonding layer located around the display pixel area.

[0025] In one embodiment, the driving backplate and the bonding layer located around the display pixel area are metal-coated.

[0026] In the aforementioned semiconductor device, through-holes are formed at the contact points between the bonding layer and the electrode contacts, allowing the interconnect layer to be filled at these holes. The interconnect layer connects the cathode of each light-emitting unit to the electrode contacts on the driving backplane, meaning the entire bonding layer does not need to be interrupted. Furthermore, the anodes of the multiple light-emitting units constituting the display pixel area are all connected to the bonding layer, enabling the multiple light-emitting units in the display pixel area to share a common anode. This results in full-surface conductivity of the bonding layer and higher reliability of the semiconductor device. Compared to semiconductor devices in conventional technologies, the bonding layer of the semiconductor device of this invention does not need to be etched and separated into multiple driving end metal pads corresponding one-to-one with multiple functional devices. This reduces the etching space required during fabrication, facilitating further miniaturization of the semiconductor device. Additionally, it eliminates the need for high alignment precision in bonding layer fabrication, simplifying the fabrication process.

[0027] The aforementioned method for fabricating a semiconductor device involves two aspects. First, it only patterns the compound semiconductor, isolating it to form multiple independent light-emitting units, but the bonding layer remains intact. This allows the multiple light-emitting units connected to the bonding layer to share a common anode, i.e., a common anode for the display pixel area. Second, it only requires creating vias at the contact points between the bonding layer and the electrode contacts. By depositing interconnect layers at these vias, the cathode of each light-emitting unit is electrically connected to its corresponding electrode contact. Therefore, the film structure on the bonding layer used for electrical connection with the anode of the light-emitting unit remains intact, resulting in more stable conductivity and higher reliability of the semiconductor device. This method surpasses the traditional technique of etching the bonding layer and device layer together to form a structure where multiple metal pads correspond one-to-one with multiple functional devices. In the semiconductor device fabrication method of the present invention, the bonding layer is formed by bonding the first bonding layer and the second bonding layer across the entire surface, and the bonding alignment accuracy requirement is low. The bonding layer is not completely isolated from the compound semiconductor. When only the compound semiconductor is patterned, the etching space required in the lateral direction is relatively small, and thus more light-emitting units can be fabricated on the same area of ​​the driving backplane, which is beneficial to further miniaturization of the semiconductor device. Attached Figure Description

[0028] Figure 1 A simplified flowchart of a method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0029] Figure 2 A simplified cross-sectional schematic diagram of the first bonding layer fabricated on the drive backplane according to an embodiment of the present invention;

[0030] Figure 3 A simplified cross-sectional schematic diagram of the second bonding layer fabricated on the target wafer according to an embodiment of the present invention;

[0031] Figure 4 A simplified cross-sectional schematic diagram of a compound semiconductor provided for an embodiment of the present invention;

[0032] Figure 5 A simplified cross-sectional schematic diagram of the bonding layer formed by bonding the first bonding layer and the second bonding layer according to an embodiment of the present invention;

[0033] Figure 6 This is a partial cross-sectional schematic diagram of a semiconductor device after removing the wafer substrate, provided in an embodiment of the present invention.

[0034] Figure 7 A partial cross-sectional schematic diagram of a display pixel area fabricated by patterning a compound semiconductor according to an embodiment of the present invention;

[0035] Figure 8 This is a partial top view of a display pixel area fabricated by patterning a compound semiconductor according to an embodiment of the present invention;

[0036] Figure 9 A partial cross-sectional schematic diagram of the display pixel area after etching of the light-emitting unit and bonding layer provided in an embodiment of the present invention;

[0037] Figure 10 This is a partial top view of the display pixel area after etching of the light-emitting unit and bonding layer provided in an embodiment of the present invention;

[0038] Figure 11 This is a partial cross-sectional schematic diagram of the dielectric insulating layer after it has been fabricated in the display pixel area, as provided in an embodiment of the present invention.

[0039] Figure 12 This is a partial cross-sectional schematic diagram of the display pixel area after the dielectric insulating layer has been patterned according to an embodiment of the present invention.

[0040] Figure 13 This is a partial top view of the display pixel area after the dielectric insulating layer has been patterned according to an embodiment of the present invention.

[0041] Figure 14 A simplified cross-sectional schematic diagram of a semiconductor device provided for an embodiment of the present invention;

[0042] Figure 15 A simplified structural diagram of a semiconductor device provided in an embodiment of the present invention.

[0043] Explanation of reference numerals in the attached figures:

[0044] 1-Drive backplane; 11-Electrode contacts; 12-Dielectric layer;

[0045] 2-Bonding layer; 21-First bonding layer; 22-Second bonding layer; 201-Through hole;

[0046] 3-Display pixel area; 31-Light-emitting unit; 32-P-type contact layer;

[0047] 300 - Compound semiconductor; 301 - First semiconductor; 302 - Active region; 303 - Second semiconductor; 304 - Buffer layer;

[0048] 4-Interconnection layer;

[0049] 5-Insulating dielectric layer; 51-First insulating dielectric layer; 52-Second insulating dielectric layer;

[0050] 61 - First metal film layer; 62 - Second metal film layer;

[0051] 700-Wafer substrate. Detailed Implementation

[0052] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0053] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0054] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0055] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0056] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0057] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0058] In traditional semiconductor device fabrication processes, high-temperature metal bonding interconnects the driver wafer with the target device. Etching then separates the metal bonding layer and the target device into multiple independent metal pads and devices, with each metal pad corresponding to a specific device. However, if this process involves bonding the metal bonding layer first and then etching the metal bonding layer and target device simultaneously, a large etching space is required during metal bonding to achieve the one-to-one isolation etching between the bonding metal and the device. Alternatively, if the process involves patterning before bonding, extremely high alignment precision is required, which affects the device size and integration density.

[0059] Combination Figure 1 , Figure 1 A simplified flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention is shown.

[0060] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0061] S10. A first bonding layer 21 is prepared on a drive backplate 1 having electrode contacts 11.

[0062] S20. A second bonding layer 22 is prepared on a target wafer having a compound semiconductor 300, and the second bonding layer 22 is electrically connected to the compound semiconductor 300.

[0063] S30. The first bonding layer 21 and the second bonding layer 22 are bonded together to form the bonding layer 2.

[0064] S40. Multiple light-emitting units 31 are fabricated by patterning compound semiconductor 300 to form display pixel area 3 on driving backplate 1.

[0065] S50. Through-holes 201 that expose electrode contacts 11 are formed on the bonding layer 21 by an etching process.

[0066] S60. An interconnect layer 4 is formed at the through hole 201 for electrically connecting the cathode of the light-emitting unit 31 to the electrode contact 11.

[0067] The method for fabricating a semiconductor device according to the embodiments of this application involves, on the one hand, patterning only the compound semiconductor 300 to isolate it into multiple independent light-emitting units 31, but without separating the bonding layer 2. This allows the multiple light-emitting units 31 connected to the bonding layer 2 to share a common anode, i.e., the display pixel area 3 shares a common anode. On the other hand, only through-holes 201 need to be opened at the contact points between the bonding layer 2 and the electrode contacts 11. By depositing an interconnect layer 4 at the through-holes 201, the cathode of each light-emitting unit 31 is electrically connected to the corresponding electrode contact 11. Therefore, the film structure on the bonding layer 2 used for electrical connection with the anode of the light-emitting unit 31 remains intact, the conductivity of the bonding layer 2 is more stable, and the reliability of the semiconductor device is higher.

[0068] Compared to traditional techniques that involve etching the metal bonding layer together with the target device to form a structure where multiple metal pads correspond one-to-one with multiple devices, the semiconductor device fabrication method of this application uses a bonding layer 2 formed by bonding the first bonding layer 21 and the second bonding layer 22 across the entire surface, which requires lower bonding alignment precision. Furthermore, the bonding layer 2 is not completely isolated from the compound semiconductor 300. When only the compound semiconductor 300 is patterned, the lateral etching space required is relatively small, resulting in a greater number of light-emitting units 31 fabricated on the same area of ​​the driving backplate 1, which is beneficial for further miniaturization of the semiconductor device.

[0069] In some embodiments, the driving backplane 1 may be a hybrid drive of one or more of the following: TFT thin film transistor, LTPS low-temperature polycrystalline silicon, CMOS integrated circuit, and high mobility transistor HEMT.

[0070] Combination Figure 2 , Figure 2 A simplified cross-sectional schematic diagram of the first bonding layer fabricated on the drive backplane is shown.

[0071] In some embodiments, the driving backplane 1 is a CMOS integrated circuit, and the CMOS integrated circuit has a dielectric layer 12, which can be a dielectric material such as silicon oxide or silicon nitride. A first bonding layer 21 is fabricated on the dielectric layer 12. The first bonding layer 21 can be a metallic material, such as one or more or at least two alloys of gold, nickel, tin, and indium. The first bonding layer 21 is a continuous structure on the dielectric layer 12 and has bonding function as well as functions such as conductivity, reflection, and heat dissipation.

[0072] In some embodiments, the first bonding layer 21 is a Ti / Au structured bonding film, wherein the thickness of Ti is 5 to 100 nm and the thickness of Au is 10 to 1000 nm.

[0073] In some embodiments, the arrangement of the plurality of electrode contacts 11 on the drive backplate 1 can be configured as needed, ensuring that the plurality of electrode contacts 11 are separated from each other. The electrode contacts 11 on the drive backplate 1 can be fabricated by the following steps: first, the drive backplate 1 is etched using a patterning process to fabricate an electrode support structure on the surface of the drive backplate 1; then, the electrode contacts 11 are fabricated on the electrode support structure.

[0074] In some embodiments, the electrode support structure may be a recess formed on the surface of the drive backplate 1. The shape of the motor contact 11 may be a cube, cuboid, trapezoid, or other structure.

[0075] Combination Figure 3 and Figure 4 , Figure 3 A simplified cross-sectional schematic diagram of the second bonding layer fabricated on the target wafer is shown. Figure 4 A simplified cross-sectional schematic diagram of a compound semiconductor is shown.

[0076] In some embodiments, a P-type contact layer 32 is first prepared on a target wafer having a compound semiconductor 300, and a second bonding layer 22 is prepared on the P-type contact layer 32. The second bonding layer 22 is electrically connected to the compound semiconductor 300 through the P-type contact layer 32.

[0077] In some embodiments, the target wafer has a typical diode optoelectronic device structure, including a wafer substrate 700 and a compound semiconductor 300. The compound semiconductor 300 includes a first semiconductor 301 for a P-type contact, an active region 302, a second semiconductor 303 for an N-type contact, and a buffer layer 304 for growing a high-quality compound material on the wafer substrate 700. A P-type contact layer 32 is fabricated on the first semiconductor 301 and is electrically interconnected with the first semiconductor 301.

[0078] In some embodiments, the target wafer can be a first-generation semiconductor material, a second-generation semiconductor material, or a third-generation semiconductor material. The target wafer can also be a semi-finished product or a finished device, such as optoelectronic material devices, laser-type devices, micromechanical devices, power electronic devices, and power radio frequency devices.

[0079] In some embodiments, the P-type contact layer 32 prepared on the target wafer is used to form a related electrical interconnect with the target wafer. The P-type contact layer 32 can be a film layer of ohmic contact or Schottky contact.

[0080] In some embodiments, the second bonding layer 22 may be a metal or its compound, such as an alloy of one or more of gold, nickel, tin, and indium. The second bonding layer 22 may also include non-metallic inorganic materials, such as single-layer or multi-layer semiconductor materials like silicon oxide, silicon nitride, titanium oxide, magnesium oxide, and aluminum oxide, or organic materials like polyimide. The second bonding layer 22 is a continuous structure and possesses bonding functionality as well as electrical conductivity, reflection, and heat dissipation functions.

[0081] In some embodiments, the P-type contact layer 32 is indium tin oxide with a thickness of 10 to 200 nm, and the second bonding layer 22 is a Ti / Au structure, wherein the Ti thickness is 5 to 100 nm and the Au thickness is 10 to 1000 nm.

[0082] Combination Figure 5 , Figure 5 A simplified cross-sectional schematic diagram is shown after the first bonding layer and the second bonding layer are bonded together to form a bonding layer.

[0083] In some embodiments, the first bonding layer 21 and the second bonding layer 22 are bonded together to form a bonding layer 2 by means of hot pressing or surface activation. The bonding layer 2 is a complete layered structure, thereby realizing the integration of the driving backplane 1 and the target wafer.

[0084] In some embodiments, before bonding the first bonding layer 21 and the second bonding layer 22, the surfaces of the first bonding layer 21 and the second bonding layer 22 need to be cleaned. This can be done by dry cleaning or wet cleaning processes to ensure that the surfaces of the first bonding layer 21 and the second bonding layer 22 are in good condition and do not affect subsequent bonding.

[0085] In some embodiments, the bonding layer 2 is a metal bonding structure, and the bonding layer 2 can be directly connected to the relevant electrical connections on the drive backplane 1.

[0086] In some embodiments, the bonding layer 2 is an inorganic material bonding structure, and an electrical connection can be formed with the P-type contact layer 32 of the light-emitting unit 31 by etching voids in the bonding layer 2 and filling the voids with a conductive film layer.

[0087] Combination Figure 6 , Figure 6 A schematic diagram of a partial cross-section of a semiconductor device after the wafer substrate has been removed is shown.

[0088] In some embodiments, prior to the patterning process of the compound semiconductor 300 in step S40, the process may further include:

[0089] Remove the wafer substrate 700 and buffer layer 304 to expose the second semiconductor 303, which will facilitate subsequent electrical connection to the electrode contacts 11 via interconnect layer 4.

[0090] In some embodiments, the process for removing the wafer substrate 700 includes methods such as laser lift-off, grinding and thinning, dry etching, or chemical cleaning. If the wafer substrate 700 is a sapphire substrate, laser lift-off can be used for removal; if the wafer substrate 700 is a silicon substrate, silicon carbide substrate, gallium nitride substrate, or gallium arsenide substrate, chemical removal or grinding can be used for removal.

[0091] In some embodiments, while ensuring the second semiconductor 304 is exposed, a portion of the wafer substrate 700 and the buffer layer 304 may be retained. The retained wafer substrate 700 may be used for subsequent electrical connections or for the fabrication of special structures, such as etching micro-vias on the retained wafer substrate 700 to restrict the light emission of the light-emitting unit 31.

[0092] Combination Figure 7 and Figure 8 , Figure 7 This diagram shows a partial cross-sectional view of a display pixel region fabricated using a patterned compound semiconductor. Figure 8 A partial top view of a display pixel area fabricated by patterning a compound semiconductor is shown.

[0093] In some embodiments, in step S40, a plurality of light-emitting units 31 are fabricated by patterning the compound semiconductor 300 to achieve isolation of the compound layer of the light-emitting units 31. At this time, the P-contact layer 32 of all light-emitting units 31 is connected to the bonding layer 2 so that the display pixel area 3 is a common anode.

[0094] In some embodiments, the plurality of light-emitting units 31 may be arranged in a neat, cross-shaped, or honeycomb pattern.

[0095] In some embodiments, the plurality of electrode contacts 11 and the plurality of light-emitting units 31 may be in a one-to-one relationship, and the cathode of each light-emitting unit 31 is electrically connected to one electrode contact 11, that is, the cathode electrical interconnection of the display pixel area of ​​the semiconductor device of this application can connect a single device.

[0096] In some embodiments, the number of light-emitting units 31 is greater than the number of electrode contacts 11, which can realize that each electrode contact 11 is electrically connected to the cathode of at least two light-emitting units 31. That is, the cathode electrical interconnection of the display pixel area of ​​the semiconductor device of this application can connect multiple devices, ensuring that other light-emitting devices can work normally when a single light-emitting device fails, and reducing the impact of dead spots on the use and yield of the overall integrated device.

[0097] Combination Figure 9 and Figure 10 , Figure 9 This diagram shows a partial cross-sectional view of the display pixel area after etching of the light-emitting unit and bonding layer. Figure 10 A partial top view of the display pixel area after etching of the light-emitting unit and bonding layer is shown.

[0098] In some embodiments, in step S50, a via 201 is formed on the bonding layer 21 by an etching process to expose the electrode contacts 11. The purpose of this step is to expose part of the electrode contacts 11 so that the electrode contacts 11 can be electrically connected to the second semiconductor 303, which serves as the cathode of the light-emitting unit 31, by subsequently fabricating the interconnect layer 4.

[0099] In some embodiments, the projected positions of the light-emitting unit 31 and the electrode contact 11 on the plane of the bonding layer 2 can be directly opposite each other. See Figure 9 In step 50, the etching location is on the light-emitting unit 31, that is, hole structures are etched on the light-emitting unit 31, the P-type contact layer, the bonding layer 2, and the dielectric layer 12. The hole structures etched on the light-emitting unit 31, the P-type contact layer, the bonding layer 2, and the dielectric layer 12 are connected to form a channel that exposes the electrode contact 11. This channel is used to accommodate part of the interconnect layer 4. The hole structure on the bonding layer 2 is the through hole 201.

[0100] In some embodiments, the projection positions of the light-emitting unit 31 and the electrode contact 11 on the plane of the bonding layer 2 can be staggered. In step 50, the etching position is between two adjacent light-emitting units 31 and directly opposite the electrode contact 11. That is, hole structures are etched on both the bonding layer 2 and the dielectric layer 12, and the hole structures etched on the bonding layer 2 and the dielectric layer 12 are connected to form a channel that exposes the electrode contact 11. This channel is used to accommodate part of the interconnect layer 4. The hole structure on the bonding layer 2 is the through hole 201.

[0101] In some embodiments, step 50 can be performed by etching at multiple locations to expose multiple portions of each electrode contact 11, so that each electrode contact 11 can be connected to multiple light-emitting units 31 through multiple interconnect layers 4 that are not connected to each other, thereby preventing short circuits when each electrode contact 11 is interconnected with multiple light-emitting units 31.

[0102] Combination Figures 11 to 13 , Figure 11 This diagram shows a partial cross-sectional view after a dielectric insulating layer has been fabricated in the display pixel area. Figure 12 This shows a partial cross-sectional schematic diagram of the display pixel area after the dielectric insulating layer has been patterned. Figure 13 A partial top view of the display pixel area after the dielectric insulating layer has been graphically processed is shown.

[0103] In some embodiments, before forming the interconnect layer 4 for electrically connecting the cathode of the light-emitting unit 31 to the electrode contact 11 by coating the through hole 201 in step S60, the following steps are further included:

[0104] See Figure 11 An insulating dielectric layer 5 is deposited to cover the display pixel area 3 so as to prevent short circuits in each light-emitting unit 31 when conductive materials are subsequently deposited in the display pixel area 3.

[0105] See Figure 12 The patterned insulating dielectric layer 5 exposes the electrode contacts 11, the second semiconductor 303 which serves as the cathode of the light-emitting unit 31, and the bonding layer 2 located around the display pixel area 3. The exposed electrode contacts 11 and the second semiconductor 303 are for subsequent electrical interconnection via the interconnect layer 4. The exposed bonding layer 2 is for subsequent use with external circuit elements.

[0106] In some embodiments, after patterning and removing part of the insulating dielectric layer 5, the remaining insulating dielectric layer 5 mainly includes a first insulating dielectric layer 51 and a second insulating dielectric layer 52. The first insulating dielectric layer 51 is located within the hole structure on the light-emitting unit 31, the P-type contact layer, the bonding layer 2, and the dielectric layer 12, and is used to electrically isolate the bonding layer 2, the P-type contact layer 32, and the portion of the light-emitting unit 31 other than the second semiconductor 303 from the interconnect layer 4. The purpose of the above-mentioned patterning of the insulating dielectric layer 5 is to expose only the portion of the electrode contacts 11 and the second semiconductor 303 that are electrically connected to the interconnect layer 4, and a portion of the bonding layer 2 surrounding the display pixel area 3. The first insulating dielectric layer 51 and the second insulating dielectric layer 52 left by the patterning process can prevent short circuits in the semiconductor device.

[0107] In some embodiments, when the etching position is on the light-emitting unit 31 in step S50, the insulating dielectric layer 5 is patterned and removed around the hole structure on the light-emitting unit 31 so that the exposed position of the second semiconductor 303 is closer to the electrode contact 11.

[0108] In some embodiments, the insulating dielectric layer 5 deposited over the display pixel area 3 can be achieved by processes such as CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), or spin coating.

[0109] In some embodiments, the insulating dielectric layer 5 may be a thin film such as silicon oxide, silicon nitride, or aluminum oxide, or a dielectric material such as polyimide.

[0110] Combination Figure 14 , Figure 14 A simplified cross-sectional schematic diagram of a semiconductor device is shown.

[0111] In some embodiments, after patterning the insulating dielectric layer 5, step 60 is performed, in which a metal film is deposited at the through hole 201 to form an interconnect layer 4 for electrically connecting the cathode of the light-emitting unit 31 to the electrode contact 11, thereby realizing the connection between the electrode contact 11 of the drive back plate 1 and the second semiconductor 301 of the compound semiconductor 300, forming a cathode contact.

[0112] In some embodiments, see Figure 14 When the etching position in step 50 is on the light-emitting unit 31, that is, hole structures are etched on the light-emitting unit 31, the P-type contact layer, the bonding layer 2, and the dielectric layer 12, a part of the interconnect layer 4 plated in step 60 is located in the hole structures etched on the light-emitting unit 31, the P-type contact layer, the bonding layer 2, and the dielectric layer 12, so as to realize the electrical connection between the interconnect layer 4 and the electrode contact 11. Another part of the interconnect layer 4 is located on the surface of the light-emitting unit 31 away from the driving backplate 1, that is, the interconnect layer 4 is electrically connected to the second semiconductor 303.

[0113] In some embodiments, when the etching location in step 50 is between two adjacent light-emitting units 31 and directly opposite the electrode contact 11, i.e., a hole structure is etched on the bonding layer 2 and the dielectric layer 12, a portion of the interconnect layer 4 plated in step 60 is located in the hole structure etched on the bonding layer 2 and the dielectric layer 12, realizing the electrical connection between the interconnect layer 4 and the electrode contact 11. Another portion of the interconnect layer 12 extends along the second insulating dielectric layer 52 toward the second semiconductor 303 exposed on the light-emitting unit 31, realizing the electrical connection between the interconnect layer 4 and the second semiconductor 303, and will not make electrical contact with the bonding layer 2, the P-type contact layer 32, or the parts of the light-emitting unit 31 other than the second semiconductor 303.

[0114] In some embodiments, the metal coating method in step 60 may be electron beam evaporation, thermal evaporation, sputtering, or the like.

[0115] Combination Figure 15 , Figure 15 A simplified schematic diagram of a semiconductor device is shown.

[0116] Simultaneously, the control electrodes (peripheral I / O) of the CMOS driving backplane and the peripheral common anode region are also coated with the same metal film around the light-emitting unit.

[0117] In some embodiments, step 60 is followed by the following step:

[0118] Metal coating is applied to the driving backplate 11 and bonding layer 2 located around the display pixel area 3 to serve as the interface for subsequent signal control and switching control.

[0119] In some embodiments, the metal film layer deposited on the driving backplate 11 located around the display pixel area 3 is a first metal film layer 61, and the first metal film layer 61 is electrically connected to the circuit components on the driving backplate 11.

[0120] In some embodiments, the metal coating deposited on the bonding layer 2 located around the display pixel area 3 is a second metal film layer 62, and the portion of the bonding layer 2 where the metal film layer is deposited is the portion of the bonding layer 2 exposed during the patterning process of the insulating dielectric layer 5.

[0121] Combination Figure 14 and Figure 15 , Figure 15 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown.

[0122] An embodiment of the present invention provides a semiconductor device including a driving backplane 1, a bonding layer 2, a display pixel area 3, and a plurality of interconnect layers 4.

[0123] In some embodiments, a plurality of electrode contacts 11 are spaced apart on one side of the driving backplate 1, and a bonding layer 2 is disposed on the side of the driving backplate 1 where the electrode contacts 11 are disposed. Through holes 201 are formed on the bonding layer 2 at the parts that contact each electrode contact 11. The display pixel area 3 includes a plurality of light-emitting units 31 spaced apart on the side of the bonding layer 2 away from the driving backplate 1, and the anodes of the plurality of light-emitting units 31 are all connected to the bonding layer 2. The interconnect layer 4, the light-emitting units 31, and the through holes 201 are in a one-to-one correspondence. A part of the interconnect layer 4 is housed in the through holes 201 and connected to the electrode contacts 11. Another part of the interconnect layer 4 is disposed on the side of the bonding layer 2 facing the light-emitting units 31 and connected to the cathode of the light-emitting units 31.

[0124] In the aforementioned semiconductor device, by opening a via 201 at the contact point between the bonding layer 2 and the electrode contact 11, an interconnect layer 4 is filled in the via 201. The cathode of each light-emitting unit 31 is connected to the electrode contact 11 on the driving backplate 1 using the interconnect layer 4, meaning that the entire film layer of the bonding layer 2 does not need to be isolated. Furthermore, the anodes of the multiple light-emitting units 31 constituting the display pixel area 3 are all connected to the bonding layer 2, so that the multiple light-emitting units 31 in the display pixel area 3 share a common anode, and the entire surface of the bonding layer 2 is conductive, resulting in higher reliability of the semiconductor device.

[0125] Compared to semiconductor devices in conventional technologies, the bonding layer 2 of the semiconductor device of the present invention does not need to be etched and separated into multiple driving end metal pads that correspond one-to-one with multiple functional devices. This reduces the etching space required during the fabrication process, which is beneficial for further miniaturization of the semiconductor device. At the same time, it eliminates the need for high alignment precision in the bonding layer fabrication, simplifying the fabrication process.

[0126] In some embodiments, the bonding layer 2 includes a first bonding layer 21 and a second bonding layer 22 bonded to each other. The first bonding layer 21 is prepared on the surface of the driving backplate 1 on which electrode contacts 11 are provided, and the second bonding layer 22 is electrically connected to the light-emitting unit 31.

[0127] In some embodiments, the second bonding layer 22 is electrically connected to the light-emitting unit 3 via a P-type contact layer 32. The function of the P-type contact layer 32 is to form a good ohmic contact with the compound semiconductor 300 of the light-emitting unit 31. Forming a good ohmic contact between the bonding layer 2 and the compound semiconductor 100 is beneficial for current input and output, and helps to maintain the stable performance of the semiconductor device.

[0128] In some embodiments, the light-emitting unit 31 has a first semiconductor 301 for a P-type contact, an active region 302, and a second semiconductor 303 for an N-type contact. The P-type contact layer 32 is electrically interconnected with the first semiconductor 301 and the bonding layer 2. Along the direction from the driving backplate 1 toward the light-emitting unit 31, the light-emitting unit 31 has the first semiconductor 301, the active region 302, and the second semiconductor 303 arranged sequentially. The second semiconductor 303 serves as the cathode of the light-emitting unit 31 and is connected to the electrode contact 11 through the interconnect layer 4.

[0129] In some embodiments, a first insulating dielectric layer 51 is disposed between the interconnect layer 4 and the bonding layer 2. The first insulating dielectric layer 51 is a portion of the insulating dielectric layer remaining after the patterned insulating dielectric layer 5 is processed. The first insulating dielectric layer 51 can at least isolate the interconnect layer 4 from the bonding layer 2 at the via 201.

[0130] In some embodiments, the light-emitting unit 31 and the electrode contact 11 are positioned opposite each other on the plane of the bonding layer 2. Opposite to the through-hole 201, the light-emitting unit 31, the P-type contact layer 32, and the dielectric layer 12 are all provided with through-hole structures, wherein the through-hole structures on the dielectric layer 12 and the P-type contact layer 32 are respectively connected to the through-hole 201, and the through-hole structure on the light-emitting unit 31 is connected to the through-hole structure on the P-type contact layer 32. Except for the first insulating dielectric layer 51 disposed between the interconnect layer 4 and the bonding layer 2, the first insulating dielectric layer 51 is sandwiched between the dielectric layer 12, the P-type contact layer 32, and the portion of the light-emitting unit 31 other than the cathode and the interconnect layer 4.

[0131] In the above structural configuration, with the light-emitting unit 31 and the electrode contact 11 projected onto the plane of the bonding layer 2 and facing each other, a contact hole is formed by the through-hole 201 and the holes that penetrate the light-emitting unit 31, the P-type contact layer 32, and the dielectric layer 12. This exposes the electrode contact 11, and an interconnect layer 4 is plated on and outside the contact hole to connect the electrode contact 11 to the second semiconductor 303. The first insulating dielectric layer 51 inside the contact hole ensures that the semiconductor device is protected against short circuits.

[0132] In some embodiments, a second insulating dielectric layer 52 is provided on the bonding layer 2 in the light-emitting unit 31 and the display pixel area 3, and the second insulating dielectric layer 52 can prevent short circuits in the semiconductor device.

[0133] In some embodiments, the light-emitting unit 31 and the electrode contact 11 are arranged at staggered positions on the plane of the bonding layer 2. A through-hole structure communicating with the via 201 is provided on the dielectric layer 12. The via 201 and the hole structure on the dielectric layer 12 together form a contact hole, so that the electrode contact 11 is exposed. For the interconnect layer 4 located outside the contact hole for connecting with the second semiconductor 303, the function of the second insulating dielectric layer 52 is to isolate the electrical contact between the interconnect layer 4 and the bonding layer 2, the P-type contact layer 32 and the parts of the light-emitting unit 31 other than the second semiconductor 303, so that the interconnect layer 4 only makes electrical contact with the second semiconductor 303, thus avoiding short circuits in the semiconductor device.

[0134] In some embodiments, the bonding layer 2 has multiple through holes 201 at the contact points with each electrode contact 11, so that each electrode contact 11 has multiple exposed parts, and each electrode contact 11 can be connected to multiple interconnect layers 4, so that each electrode contact 11 and the cathode of multiple light-emitting units 31 can be electrically connected through multiple interconnect layers 4 that are not connected to each other, preventing short circuits when each electrode contact 11 is interconnected with multiple light-emitting units 31.

[0135] In some embodiments, a first metal film layer 61 is disposed on the driving backplate 1 surrounding the display pixel area 3, and the first metal film layer 61 is electrically connected to the circuit components on the driving backplate 11. The first metal film layer 61 can serve as an interface for external signal control and switching control.

[0136] In some embodiments, a second metal film layer 62 is disposed on the bonding layer 2 surrounding the display pixel area 3, and the second metal film layer 62 is electrically connected to the circuit components on the driving backplane 11. The second metal film layer 62 can serve as an interface for external signal control and switching control.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A drive backplate (1) is provided with a plurality of electrode contacts (11) spaced apart on one side; the drive backplate (1) has a dielectric layer (12) located on the side of the electrode contacts (11) away from the drive backplate (1); A bonding layer (2) is disposed on the side of the drive backplate (1) where the electrode contacts (11) are disposed. Through holes (201) are provided in the bonding layer (2) at the parts that contact each of the electrode contacts (11). The bonding layer (2) includes a first bonding layer (21) and a second bonding layer (22) that are stacked and bonded together on the whole surface. The first bonding layer (21) is disposed on the dielectric layer (12). The display pixel area (3) includes multiple light-emitting units (31) spaced apart on the side of the bonding layer (2) away from the driving backplate (1). The light-emitting units (31) and the electrode contacts (11) are positioned opposite each other on the plane of the bonding layer (2). A P-type contact layer (32) is provided between the light-emitting units (31) and the second bonding layer (22). The anodes of the multiple light-emitting units (31) are connected to the second bonding layer (22) of the bonding layer (2) through the P-type contact layer (32). The light-emitting unit (31) has a hole structure that passes through the light-emitting unit (31), the P-type contact layer (32), the bonding layer (2), and the dielectric layer (12) in sequence. The hole structure on the bonding layer (2) is the through hole (201). Multiple interconnect layers (4), the interconnect layers (4), the light-emitting unit (31) and the via (201) are in a one-to-one correspondence. A part of the interconnect layer (4) is housed in the via (201) and connected to the electrode contact (11). Another part of the interconnect layer (4) is disposed on the side of the bonding layer (2) facing the light-emitting unit (31) and connected to the cathode of the light-emitting unit (31).

2. The semiconductor device according to claim 1, characterized in that, The bonding layer (2) includes a first bonding layer (21) and a second bonding layer (22) bonded together. The first bonding layer (21) is prepared on the surface of the driving backplate (1) where the electrode contacts (11) are provided. The second bonding layer (22) is electrically connected to the light-emitting unit (31).

3. The semiconductor device according to claim 1, characterized in that, A first insulating dielectric layer (51) is provided between the interconnect layer (4) and the bonding layer (2).

4. The semiconductor device according to claim 1, characterized in that, A second insulating dielectric layer (52) is provided on the bonding layer (2) within the light-emitting unit (31) and the display pixel area (3).

5. The semiconductor device according to claim 1, characterized in that, The bonding layer (2) has multiple through holes (201) at the contact points with each of the electrode contacts (11), and each of the electrode contacts (11) is electrically connected to the cathodes of multiple light-emitting units (31).

6. The semiconductor device according to claim 1, characterized in that, A first metal film layer (61) is provided on the driving backplate (1) surrounding the display pixel area (3), and the first metal film layer (61) is electrically connected to the circuit components on the driving backplate (1).

7. The semiconductor device according to claim 1, characterized in that, A second metal film layer (62) is disposed on the bonding layer (2) surrounding the display pixel area (3), and the second metal film layer (62) is electrically connected to the circuit components on the driving backplate (1).

8. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes the following steps: The driving backplate (1) has a dielectric layer (12), and a first bonding layer (21) is formed on the dielectric layer (12). The driving backplate (1) has electrode contacts (11). A P-type contact layer (32) is first prepared on a target wafer having a compound semiconductor (300), and a second bonding layer (22) is prepared on the P-type contact layer (32), wherein the second bonding layer (22) is electrically connected to the compound semiconductor (300) through the P-type contact layer (32); The first bonding layer (21) and the second bonding layer (22) are bonded together to form a bonding layer (2); Multiple light-emitting units (31) are fabricated by patterning the compound semiconductor (300) to form a display pixel area (3) on the driving backplate (1). Through-holes (201) that expose the electrode contacts (11) are formed on the bonding layer (21) by etching. The projection positions of the light-emitting unit (31) and the electrode contacts (11) on the plane of the bonding layer (2) can be directly opposite each other. Hole structures are etched on the light-emitting unit (31), the P-type contact layer (32), the bonding layer (2), and the dielectric layer (12). The hole structures formed by etching on the light-emitting unit (31), the P-type contact layer (32), the bonding layer (2), and the dielectric layer (12) are connected to form a channel that exposes the electrode contacts (11). The hole structure on the bonding layer (2) is the through-hole (201). An interconnect layer (4) is formed at the through hole (201) for electrically connecting the cathode of the light-emitting unit (31) to the electrode contact (11).

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, Before depositing an interconnect layer (4) at the through-hole (201) to electrically connect the cathode of the light-emitting unit (31) to the electrode contact (11), the following steps are also included: A dielectric insulating layer (5) is deposited covering the display pixel area (3); The dielectric insulating layer (5) is patterned to expose the electrode contacts (11), the cathode of the light-emitting unit (31), and the bonding layer (2) located around the display pixel area (3).

10. The method for fabricating a semiconductor device according to claim 8, characterized in that, Metal coating is applied to the driving backplate (1) and the bonding layer (2) located around the display pixel area (3).

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