A metal oxide semiconductor structure and a method of fabricating the same

Abstract

The application discloses a metal oxide semiconductor structure and a manufacturing method thereof. The metal oxide semiconductor structure comprises the following steps: providing a substrate of a first semiconductor type; forming at least two epitaxial layers on the surface of the substrate in sequence, each of the epitaxial layers is injected with deep energy level impurity ions to form deep energy level recombination centers; a column region is arranged in a partial region of each of the epitaxial layers, a gate structure is formed on the topmost epitaxial layer; first ions are injected into the surface of the topmost epitaxial layer to form a first source region and a second source region; a body region is formed below the first source region and the second source region; a source electrode is formed on the first source region, and a drain electrode is formed above the second source region. The metal oxide semiconductor structure can cause crystal atomic displacement to generate deep energy level recombination centers in each of the epitaxial layers during normal operation, thereby reducing the minority carrier lifetime and the carrier concentration, achieving the purpose of reducing the reverse recovery time of the semiconductor structure, and improving the reverse recovery characteristics of the parasitic body diode of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication, and more particularly to a metal-oxide-semiconductor structure and its fabrication method. Background Technology

[0002] Existing flyback switching power supplies, such as Figure 1 As shown, this flyback switching power supply consists of a wide-range input circuit, a primary power control circuit, a transformer, a secondary synchronous rectifier circuit, and a feedback network. In the primary power control circuit, the drain of switching transistor Q1 is connected to the primary side of transformer T1. When the controller drive is high, switching transistor Q1 is turned on, and energy is stored in transformer T1; when the controller drive is low, switching transistor Q1 is turned off, and energy is released through transformer T1 to the secondary synchronous rectifier circuit and the feedback network. After switching transistor Q1 is turned off, switching transistor Q2 in the secondary synchronous rectifier circuit, due to the long reverse recovery time of its body diode, does not respond and turn off in time, causing the primary and secondary switching transistors to conduct simultaneously. The conduction voltage VDS waveforms of the primary and secondary switching transistors are shown below. Figure 2 As shown, this generates a high peak voltage.

[0003] Currently, existing methods to address this voltage spike problem include electron irradiation of the secondary switching transistor or parallel connection of a Schottky diode to shorten the reverse recovery time and prevent simultaneous conduction of the primary and secondary switching transistors, thus avoiding voltage spikes. However, both of these improved switching transistor methods have the following drawbacks in flyback switching power supply applications:

[0004] While electron irradiation reduces the reverse recovery charge of the parasitic body diode, it also generates irradiation defects in the oxide layer, lowering the device's turn-on voltage and deteriorating its breakdown and conduction characteristics. Furthermore, irradiation is prone to high-temperature instability. If the recovery characteristics of the parasitic body diode are improved by connecting an additional Schottky diode in parallel, interconnect inductance will be introduced. This additional inductance will adversely affect high-efficiency systems, reducing circuit conversion efficiency and system reliability.

[0005] Therefore, improving the reverse recovery characteristics of parasitic diodes in semiconductor devices has become an urgent problem to be solved. Summary of the Invention

[0006] Based on this, it is necessary to provide a metal-oxide-semiconductor structure and its fabrication method to address the aforementioned technical problems, thereby solving the problem of poor reverse recovery characteristics of parasitic body diodes in existing metal-oxide-semiconductor structures. This prevents the application of the semiconductor structure in flyback switching power supplies from causing the primary and secondary switching transistors to conduct simultaneously, resulting in high peak voltages.

[0007] To achieve the above objectives, in a first aspect, a method for fabricating a metal-oxide-semiconductor structure is provided, comprising the following steps:

[0008] Provide a substrate of the first semiconductor type;

[0009] At least two epitaxial layers are sequentially formed on the surface of the substrate. The semiconductor type of each epitaxial layer is a first semiconductor type. Deep-level impurity ions are implanted into each epitaxial layer to form deep-level recombination centers. A pillar region is provided in a portion of each epitaxial layer. The semiconductor type of the pillar region is a second semiconductor type.

[0010] A gate structure is formed on the top epitaxial layer; first ions are implanted into the surface of the top epitaxial layer to form a first source region and a second source region; a body region is formed below the first source region and the second source region; a source is formed on the first source region and a drain is formed above the second source region.

[0011] Optionally, at least two epitaxial layers are sequentially formed on the substrate surface, each epitaxial layer being of a first semiconductor type, and deep-level impurity ions are implanted into each epitaxial layer to form deep-level recombination centers; pillar regions are provided in a portion of each epitaxial layer, including:

[0012] A first epitaxial layer of a first semiconductor type is grown on the surface of the substrate, and deep-level impurity ions are implanted into the surface of the first epitaxial layer to form deep-level recombination centers; ions of a second semiconductor type are implanted into a portion of the first epitaxial layer.

[0013] A second epitaxial layer of a first semiconductor type is grown on the surface of the first epitaxial layer, and deep-level impurity ions are implanted into the surface of the second epitaxial layer to form deep-level recombination centers; ions of a second semiconductor type are implanted into a portion of the second epitaxial layer.

[0014] Using a high-temperature annealing process, a column region of the second semiconductor type is formed in the portion of the region where ion implantation of the second semiconductor type is performed.

[0015] Optionally, after forming the second epitaxial layer, the process may also include forming a third epitaxial layer, or forming both a third and a fourth epitaxial layer.

[0016] Forming the third epitaxial layer includes: growing a third epitaxial layer of a first semiconductor type on the surface of the second epitaxial layer, implanting deep-level impurity ions into the surface of the third epitaxial layer, and implanting second semiconductor type ions into a portion of the third epitaxial layer;

[0017] Forming the fourth epitaxial layer includes: growing a fourth epitaxial layer of a first semiconductor type on the surface of the third epitaxial layer, implanting deep-level impurity ions into the surface of the fourth epitaxial layer, and implanting second semiconductor type ions into a portion of the fourth epitaxial layer.

[0018] Optionally, forming the gate structure on the topmost epitaxial layer includes:

[0019] A gate trench is formed on the topmost epitaxial layer using photolithography. An oxide layer is generated in the gate trench, and polysilicon is deposited on the upper surface of the oxide layer to form a polysilicon layer. An insulating layer is formed on the upper surface of the polysilicon layer to obtain the gate structure.

[0020] Optionally, the implantation of first ions into the surface of the topmost epitaxial layer to form a first source region and a second source region includes:

[0021] The surface of the top epitaxial layer is photolithographically ...

[0022] Optionally, the body region formed below the first source region and the second source region includes:

[0023] The surface of the top epitaxial layer is photolithographically ...

[0024] Optionally, forming a source on the first source region and a drain above the second source region includes:

[0025] Metal layers are disposed on the first source region and the second source region to form the source and drain.

[0026] In a second aspect, a metal-oxide-semiconductor structure is provided, comprising:

[0027] Substrate of the first semiconductor type;

[0028] At least two epitaxial layers are sequentially disposed on the surface of the substrate. The semiconductor type of each epitaxial layer is a first semiconductor type. Deep-level impurity ions are implanted into each epitaxial layer to form deep-level recombination centers. A pillar region is disposed in a portion of each epitaxial layer. The semiconductor type of the pillar region is a second semiconductor type.

[0029] A gate structure is disposed on the top epitaxial layer, and a first source region and a second source region are disposed within the top epitaxial layer. The first source region and the second source region are distributed on both sides of the gate structure, and a body region is disposed below the first source region and the second source region. A source electrode is disposed above the first source region, and a drain electrode is disposed above the second source region.

[0030] Optionally, two epitaxial layers are disposed on the surface of the substrate, namely:

[0031] A first epitaxial layer is disposed on the surface of the substrate, and deep-level impurity ions are implanted in the surface of the first epitaxial layer. A portion of the first epitaxial layer is implanted with ions of a second semiconductor type.

[0032] The second epitaxial layer is disposed on the first epitaxial layer, and deep-level impurity ions are implanted in the surface of the second epitaxial layer. Ions of a second semiconductor type are implanted in a portion of the second epitaxial layer.

[0033] Optionally, the substrate surface may further include a third epitaxial layer, or may further include a third epitaxial layer and a fourth epitaxial layer;

[0034] The third epitaxial layer is disposed on the second epitaxial layer, and deep-level impurity ions are implanted in the surface of the third epitaxial layer. A portion of the third epitaxial layer is implanted with ions of a second semiconductor type.

[0035] The fourth epitaxial layer is disposed on the third epitaxial layer, and deep-level impurity ions are implanted in the surface of the fourth epitaxial layer. A portion of the fourth epitaxial layer is implanted with ions of a second semiconductor type.

[0036] The above technical solution has the following beneficial effects:

[0037] The metal-oxide-semiconductor structure and its fabrication method of the present invention involve sequentially fabricating at least two epitaxial layers on a substrate, and implanting deep-level impurity ions via ion implantation during the fabrication of each epitaxial layer, ensuring that each epitaxial layer contains a certain amount of deep-level impurity ions. This improved metal-oxide-semiconductor structure, during normal operation, induces atomic displacement in the crystal, generating recombination centers at deep levels in each epitaxial layer. This reduces minority carrier lifetime and carrier concentration, thereby decreasing the reverse recovery time of the semiconductor structure and improving the reverse recovery characteristics of parasitic diodes in semiconductor devices.

[0038] Furthermore, when this type of metal-oxide-semiconductor structure is used as a secondary switch in a flyback switching power supply, the semiconductor structure can respond quickly and turn off extremely fast, greatly reducing the time when the primary and secondary switches are on simultaneously, thereby reducing the VDS turn-on voltage spike of the secondary switch. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a circuit diagram of a flyback switching power supply provided in the prior art;

[0041] Figure 2 This is a waveform diagram of the turn-on voltage VDS of the primary and secondary switching transistors in a flyback switching power supply provided in the prior art;

[0042] Figure 3 This is a flowchart illustrating the fabrication process of a metal-oxide-semiconductor structure provided in one embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of a substrate of a first semiconductor type provided in one embodiment of the present invention;

[0044] Figure 5a This is a schematic diagram of the first epitaxial layer provided in one embodiment of the present invention;

[0045] Figure 5b This is a schematic diagram of implanting ions of a second semiconductor type into the first epitaxial layer according to an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of the second epitaxial layer provided in one embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of a pillar region of a second semiconductor type provided in one embodiment of the present invention;

[0048] Figure 8 This is a schematic diagram of a gate structure provided in one embodiment of the present invention;

[0049] Figure 9 This is a schematic diagram of the first source region and the second source region provided in one embodiment of the present invention;

[0050] Figure 10 This is a schematic diagram of a body region formed below the first source region and the second source region provided in one embodiment of the present invention;

[0051] Figure 11 This is a diagram of a metal-oxide-semiconductor structure with two epitaxial layers provided in one embodiment of the present invention;

[0052] Figure 12 This is a diagram of a metal-oxide-semiconductor structure with three epitaxial layers provided in one embodiment of the present invention;

[0053] Figure 13 This is a diagram of a metal-oxide-semiconductor structure with four epitaxial layers provided in one embodiment of the present invention;

[0054] Figure 14 This is a waveform diagram of the on-state voltage VDS of the primary / secondary switching transistors in a flyback switching power supply provided in an embodiment of the present invention.

[0055] The symbols are explained as follows:

[0056] 1. Substrate; 21. First epitaxial layer; 22. Second epitaxial layer; 23. Third epitaxial layer; 3. Oxide layer; 4. Pillar region; 5. Polysilicon layer; 6. Insulating layer; 71. First source region; 72. Second source region; 81. First body region; 82. Second body region; 9. Source; 10. Drain; 11. Gate. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] It should also be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0059] It should also be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate components.

[0060] It should also be understood that the terms “upper,” “lower,” “left,” “right,” “front,” “back,” “bottom,” “middle,” “center,” “top,” etc., may be used herein to describe various elements, indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are used only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, these elements should not be limited by these terms.

[0061] These terms are used only to distinguish one element from another. For example, a first element may be referred to as the “upper” element, and similarly, a second element may be referred to as the “upper” element depending on the relative orientation of these elements, without departing from the scope of this disclosure.

[0062] To be further understood, the terms “comprising,” “including,” “including,” and / or “include” as used herein specify the presence of the said feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0063] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that the terms used herein should be interpreted as having the same meaning as they mean in the context of this specification and related art, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0064] In one embodiment, such as Figure 3 The method for fabricating the metal-oxide-semiconductor structure shown includes the following steps:

[0065] S101 provides a substrate of a first semiconductor type.

[0066] Among them, the formed substrate 1 is a silicon substrate, such as Figure 4 As shown; optionally, the first semiconductor type of the substrate 1 is N-type. In other examples, the first semiconductor type of the substrate 1 may also be P-type.

[0067] S102, at least two epitaxial layers are sequentially formed on the surface of the substrate, each epitaxial layer having a first semiconductor type, and deep-level impurity ions are implanted into each epitaxial layer to form deep-level recombination centers; a pillar region is provided in a portion of each epitaxial layer, and the semiconductor type of the pillar region is a second semiconductor type.

[0068] The formation sequence of multiple epitaxial layers is as follows: first, an epitaxial layer is deposited on the substrate surface, and deep-level impurity ions, such as gold ions or platinum ions, are implanted by ion implantation. Then, using photoresist as a barrier, ions of a second semiconductor type are implanted in a portion of the epitaxial layer. The above process is then repeated to process the next epitaxial layer.

[0069] Optionally, step S102 above specifically includes:

[0070] S1021, a first epitaxial layer 21 of a first semiconductor type is grown on the surface of the substrate 1. Deep-level impurity ions are implanted into the surface of the first epitaxial layer 21 to form deep-level recombination centers. Second semiconductor type ion implantation is then performed into a portion of the first epitaxial layer. The resulting first epitaxial layer is as follows: Figure 5a As shown.

[0071] After depositing the first epitaxial layer 21, photoresist is coated using the oxide layer 3 as a mask, and the photoresist acts as a barrier. Figure 5b The two partial regions shown are implanted with ions of a second semiconductor type; then, the photoresist and oxide layer 3 are removed.

[0072] S1022, a second epitaxial layer 22 of the first semiconductor type is grown on the surface of the first epitaxial layer 21; deep-level impurity ions are implanted into the surface of the second epitaxial layer 22 to form deep-level recombination centers; and second semiconductor type ion implantation is performed in a portion of the second epitaxial layer 22. The resulting second epitaxial layer is as follows: Figure 6 As shown.

[0073] Similar to the process in step S1021, after the second epitaxial layer 22 is deposited, the oxide layer is still used as a mask to coat photoresist. The photoresist acts as a barrier to implant ions of the second semiconductor type into two partial regions of the second epitaxial layer 22. After the implantation is completed, the photoresist and oxide layer are removed.

[0074] In this step, the two regions in the second epitaxial layer 22 used for ion implantation are in a vertically corresponding position to the two regions in the first epitaxial layer 21 used for ion implantation.

[0075] In steps S1021 and S1022 above, two epitaxial growths were performed respectively. For example, the thickness of each epitaxial growth ranged from 14 to 17 μm, and the implanted ion concentration was E18-19 / CM. 3 This allows for the formation of relatively ideal epitaxial layers and deep-level composite centers.

[0076] S1023, using a high-temperature annealing process, a second semiconductor type pillar region 4 is formed in the portion of the region where ion implantation of the second semiconductor type is performed, such as... Figure 7 As shown.

[0077] In this process, after forming multiple epitaxial layers, a high-temperature annealing process is used to form pillar regions in the regions where ions of a second semiconductor type are implanted into the epitaxial layers. For example, when the substrate is N-type, the corresponding first semiconductor type is N-type and the second semiconductor type is P-type, thus forming multiple N-type epitaxial layers and P-type pillar regions. In another embodiment, when the substrate is P-type, the corresponding first semiconductor type is P-type and the second semiconductor type is N-type, thus forming multiple P-type epitaxial layers and N-type pillar regions.

[0078] In this step, the preferred temperature conditions for the high-temperature annealing process are 950-1000℃, and the preferred time conditions are 80-120min.

[0079] S103 forms a gate structure on the top epitaxial layer.

[0080] Optionally, forming the gate structure on the topmost epitaxial layer includes:

[0081] A gate trench is formed on the topmost epitaxial layer using photolithography. An oxide layer 3 is formed within the gate trench, and polysilicon is deposited on the upper surface of the oxide layer 3 to form a polysilicon layer 5. An insulating layer 6 is formed on the upper surface of the polysilicon layer 5, thus obtaining the gate structure, i.e., a trench polysilicon gate. Figure 8 As shown.

[0082] In this process, after the gate trench is formed, an oxide layer 3 is generated inside the gate trench through a high-temperature oxidation process.

[0083] S104, implanting first ions into the surface of the top epitaxial layer to form a first source region 71 and a second source region 72; as shown... Figure 9 As shown.

[0084] Optionally, the implantation of first ions into the surface of the topmost epitaxial layer to form a first source region 71 and a second source region 72 includes:

[0085] The surface of the top epitaxial layer (referring to the second epitaxial layer 22 in this embodiment) is photolithographically ...22) is photolithographically lithographically lithographically lithographically lithographically lithographically 22, and a first doped element is implanted in the preset first photolithographically lithographically lithographically lithographically lithographically lithographically lithographically lithographically lithographically lithographically lithographically lithographically lithographically 22, and a diffusion push-bonding process is combined to form the first source region 71 and the second source region 72.

[0086] There are two preset first lithography areas, and the positions of the two preset first lithography areas are corresponding positions above the two pillar areas 4.

[0087] For example, when the epitaxial layer is N-type, the first dopant element implanted in the two preset first photolithography regions in this step is arsenic element, which is used to form N+ first source region 71 and N+ second source region 72.

[0088] S105, a body region is formed below the first source region and the second source region.

[0089] Optional, such as Figure 10 As shown, the volume region formed below the first source region and the second source region includes:

[0090] The surface of the top epitaxial layer is photolithographically ...

[0091] There are two preset second lithography areas, which are located below the two source areas 71 and 72 and above the two pillar areas 4.

[0092] For example, when the epitaxial layer is N-type, the second dopant element implanted in the two preset second photolithography regions in this step is boron, which is used to form the P-first body region 81 and the P-second body region 82.

[0093] After the body region is formed below the first source region and the second source region, a heat baking process can be performed. For example, the heat baking conditions can be baking at 430-450℃ for 30 minutes to achieve the effect of drying and shaping.

[0094] S106, a source is formed on the first source region, a drain is formed above the second source region, and a gate is formed on the gate structure.

[0095] Optionally, forming a source on the first source region, forming a drain above the second source region, and forming a gate on the gate structure includes:

[0096] Metal layers are respectively disposed on the first source region 71 and the second source region 72 to form the source electrode 9 and the drain electrode 10; a metal layer is disposed on the gate structure to form the gate electrode 11, as shown below. Figure 11 As shown.

[0097] Specifically, the front-side metallization, passivation, and PAD region etching are performed on the first source region 71, the second source region 72, the first body region 81, the second body region 82, the gate structure, and the top epitaxial layer. Passivation refers to sealing with borosilicate glass to achieve device passivation. After the front-side metallization, passivation, and PAD region etching, the back-side metallization process is required, in which a layer of metal is evaporated on the silicon epitaxial wafer substrate to obtain the aforementioned source 9, drain 10, and gate 11, thereby completing the overall device fabrication of the metal-oxide-semiconductor structure.

[0098] The method for fabricating a metal-oxide-semiconductor (MOS) structure in this embodiment involves a special treatment of the epitaxial layers on the substrate. Specifically, two epitaxial layers are fabricated sequentially on the substrate, and deep-level impurity ions are implanted during the fabrication of each epitaxial layer using ion implantation. This ensures that each epitaxial layer contains a certain amount of deep-level impurity ions. This improved process allows the resulting MOS structure to induce atomic displacement during normal operation, creating recombination centers at deep levels in each epitaxial layer. This reduces minority carrier lifetime and carrier concentration, thereby decreasing the reverse recovery time of the semiconductor structure.

[0099] In other embodiments, step S102 described above, after forming the second epitaxial layer, further includes forming a third epitaxial layer 23; as shown... Figure 12 As shown.

[0100] Forming the third epitaxial layer 23 includes: growing a third epitaxial layer 23 of a first semiconductor type on the surface of the second epitaxial layer 22, implanting deep-level impurity ions into the surface of the third epitaxial layer 23, and implanting second semiconductor type ions into a portion of the third epitaxial layer 23.

[0101] The method for fabricating a metal-oxide-semiconductor structure in this embodiment involves setting three epitaxial layers in the metal-oxide-semiconductor structure, with deep-level impurity ions implanted in each of the three epitaxial layers. This enables the semiconductor structure to generate recombination centers at three deep levels during operation, thereby improving the reverse recovery characteristics of the semiconductor structure and significantly shortening its reverse recovery time.

[0102] In other embodiments, step S102 described above, after forming the second epitaxial layer, further includes forming a third epitaxial layer 23 and a fourth epitaxial layer 24; as shown Figure 13 As shown.

[0103] Forming the third epitaxial layer 23 includes: growing a third epitaxial layer 23 of a first semiconductor type on the surface of the second epitaxial layer 22, implanting deep-level impurity ions into the surface of the third epitaxial layer 23, and implanting second semiconductor type ions into a portion of the third epitaxial layer 23.

[0104] The formation of the fourth epitaxial layer includes 24: growing a fourth epitaxial layer 24 of a first semiconductor type on the surface of the third epitaxial layer 23, implanting deep-level impurity ions into the surface of the fourth epitaxial layer 24, and implanting second semiconductor type ions into a portion of the fourth epitaxial layer 24.

[0105] The method for fabricating a metal-oxide-semiconductor structure in this embodiment involves setting four epitaxial layers in the metal-oxide-semiconductor structure, with deep-level impurity ions implanted in each of the four epitaxial layers. This enables the semiconductor structure to generate recombination centers at four deep levels during operation, improving the reverse recovery characteristics of the semiconductor structure and thus shortening the reverse recovery time.

[0106] In one embodiment, such as Figure 11 As shown, a metal-oxide-semiconductor structure is provided, characterized in that it comprises:

[0107] Substrate 1 of the first semiconductor type;

[0108] At least two epitaxial layers are sequentially disposed on the surface of the substrate 1. The semiconductor type of each epitaxial layer is a first semiconductor type. Deep-level impurity ions are implanted into each epitaxial layer to form deep-level recombination centers. A pillar region 4 is disposed in a portion of each epitaxial layer. The semiconductor type of the pillar region 4 is a second semiconductor type.

[0109] A gate structure is disposed on the top epitaxial layer. A first source region 71 and a second source region 72 are disposed within the top epitaxial layer. The first source region 71 and the second source region 72 are distributed on both sides of the gate structure. Body regions 81 and 82 are disposed below the first source region 71 and the second source region 72. A source electrode 9 is disposed above the first source region 71, and a drain electrode 10 is disposed above the second source region 72. A gate electrode 11 is disposed on the gate structure.

[0110] In this embodiment, two epitaxial layers are disposed on the surface of the substrate 1, namely:

[0111] A first epitaxial layer 21 is disposed on the surface of the substrate 1. Deep-level impurity ions are implanted in the surface of the first epitaxial layer 21, and ions of a second semiconductor type are implanted in a portion of the first epitaxial layer 21.

[0112] The second epitaxial layer 22 is disposed on the first epitaxial layer 21. Deep-level impurity ions are implanted in the surface of the second epitaxial layer 22, and ions of a second semiconductor type are implanted in a portion of the second epitaxial layer 22.

[0113] The metal-oxide-semiconductor (MOS) structure of this embodiment can induce atomic displacement during operation, generating recombination centers in two deep energy levels. This leads to a reduction in minority carrier lifetime and carrier concentration, effectively reducing the reverse recovery charge of the parasitic body diode in the semiconductor device, improving the reverse recovery characteristics of the parasitic body diode, and shortening the reverse recovery time. When this type of MOS structure is used as a secondary switch in a flyback switching power supply, the semiconductor structure can respond quickly and turn off extremely fast, greatly reducing the time when the primary and secondary switches are on simultaneously, thereby reducing the VDS turn-on voltage spike of the secondary switch.

[0114] In other embodiments, such as Figure 12 The metal-oxide-semiconductor structure shown further includes, on the surface of the substrate 1 of the semiconductor structure:

[0115] The third epitaxial layer 23 is disposed on the second epitaxial layer 22. Deep-level impurity ions are implanted in the surface of the third epitaxial layer 23, and ions of a second semiconductor type are implanted in a portion of the third epitaxial layer 23.

[0116] In other embodiments, such as Figure 13 The metal-oxide-semiconductor structure shown further includes, on the surface of the substrate 1 of the semiconductor structure:

[0117] The fourth epitaxial layer 24 is disposed on the third epitaxial layer 23. Deep-level impurity ions are implanted in the surface of the fourth epitaxial layer 24, and ions of a second semiconductor type are implanted in a portion of the fourth epitaxial layer 24.

[0118] In other embodiments, the substrate 1 of the semiconductor structure may further include more epitaxial layers, each of which is implanted with deep-level impurity ions, and corresponding portions of which are implanted with ions of a second semiconductor type.

[0119] The metal-oxide-semiconductor (MOS) structures described above can induce atomic displacement during operation, generating recombination centers in two or more (three or four) deep energy levels. This leads to a reduction in minority carrier lifetime and carrier concentration, effectively reducing the reverse recovery charge of parasitic diodes in semiconductor devices, improving the reverse recovery characteristics of parasitic diodes, and further shortening the reverse recovery time. When this type of MOS structure is used as a secondary switch in a flyback switching power supply, it can respond quickly and turn off extremely fast, ensuring that the VDS turn-on voltage of the primary / secondary switches is as... Figure 14 As shown, the primary and secondary switches are almost never on at the same time, thus reducing the VDS turn-on voltage spike of the secondary switch.

[0120] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for fabricating a metal-oxide-semiconductor structure, characterized in that, Includes the following steps: Provide a substrate of the first semiconductor type; At least two epitaxial layers are sequentially formed on the surface of the substrate. The semiconductor type of each epitaxial layer is a first semiconductor type. Deep-level impurity ions are implanted into each epitaxial layer to form deep-level recombination centers. A pillar region is provided in a portion of each epitaxial layer. The semiconductor type of the pillar region is a second semiconductor type. The deep-level impurity ions are implanted by ion implantation during the fabrication of each epitaxial layer, so that each epitaxial layer contains the deep-level impurity ions. A gate structure is formed on the top epitaxial layer; first ions are implanted into the surface of the top epitaxial layer to form a first source region and a second source region; a body region is formed below the first source region and the second source region; a source is formed on the first source region and a drain is formed above the second source region.

2. The method for fabricating a metal-oxide-semiconductor structure as described in claim 1, characterized in that, At least two epitaxial layers are sequentially formed on the substrate surface. Each epitaxial layer is of a first semiconductor type. Deep-level impurity ions are implanted into each epitaxial layer to form deep-level recombination centers. A pillar region is formed in a portion of each epitaxial layer, including: A first epitaxial layer of a first semiconductor type is grown on the surface of the substrate, and deep-level impurity ions are implanted into the surface of the first epitaxial layer to form deep-level recombination centers; ions of a second semiconductor type are implanted into a portion of the first epitaxial layer. A second epitaxial layer of a first semiconductor type is grown on the surface of the first epitaxial layer, and deep-level impurity ions are implanted into the surface of the second epitaxial layer to form deep-level recombination centers; ions of a second semiconductor type are implanted into a portion of the second epitaxial layer. Using a high-temperature annealing process, a column region of the second semiconductor type is formed in the portion of the region where ion implantation of the second semiconductor type is performed.

3. The method for fabricating a metal-oxide-semiconductor structure as described in claim 2, characterized in that, After the formation of the second epitaxial layer, the process also includes the formation of a third epitaxial layer, or the formation of a third epitaxial layer and a fourth epitaxial layer. Forming the third epitaxial layer includes: growing a third epitaxial layer of a first semiconductor type on the surface of the second epitaxial layer, implanting deep-level impurity ions into the surface of the third epitaxial layer, and implanting second semiconductor type ions into a portion of the third epitaxial layer; Forming the fourth epitaxial layer includes: growing a fourth epitaxial layer of a first semiconductor type on the surface of the third epitaxial layer, implanting deep-level impurity ions into the surface of the fourth epitaxial layer, and implanting second semiconductor type ions into a portion of the fourth epitaxial layer.

4. The method for fabricating a metal-oxide-semiconductor structure as described in claim 1, characterized in that, The formation of the gate structure on the topmost epitaxial layer includes: A gate trench is formed on the topmost epitaxial layer using photolithography. An oxide layer is generated in the gate trench, and polysilicon is deposited on the upper surface of the oxide layer to form a polysilicon layer. An insulating layer is formed on the upper surface of the polysilicon layer to obtain the gate structure.

5. The method for fabricating a metal-oxide-semiconductor structure as described in claim 4, characterized in that, The step of implanting a first ion into the surface of the topmost epitaxial layer to form a first source region and a second source region includes: The surface of the top epitaxial layer is photolithographically ...

6. The method for fabricating a metal-oxide-semiconductor structure as described in claim 1 or 5, characterized in that, The volume region formed below the first and second source regions includes: The surface of the top epitaxial layer is photolithographically ...

7. The method for fabricating a metal-oxide-semiconductor structure as described in claim 1 or 5, characterized in that, Forming a source electrode on the first source region and forming a drain electrode above the second source region includes: Metal layers are disposed on the first source region and the second source region to form the source and drain.

8. A metal-oxide-semiconductor structure, characterized in that, include: Substrate of the first semiconductor type; At least two epitaxial layers are sequentially disposed on the surface of the substrate. The semiconductor type of each epitaxial layer is a first semiconductor type. Deep-level impurity ions are implanted into each epitaxial layer to form deep-level recombination centers. A pillar region is disposed in a portion of each epitaxial layer. The semiconductor type of the pillar region is a second semiconductor type. In the fabrication process of each epitaxial layer, the deep-level impurity ions are implanted by ion implantation, so that each epitaxial layer contains the deep-level impurity ions. A gate structure is disposed on the top epitaxial layer, and a first source region and a second source region are disposed within the top epitaxial layer. The first source region and the second source region are distributed on both sides of the gate structure, and a body region is disposed below the first source region and the second source region. A source electrode is disposed above the first source region, and a drain electrode is disposed above the second source region.

9. The metal-oxide-semiconductor structure as described in claim 8, characterized in that, Two epitaxial layers are disposed on the surface of the substrate, namely: A first epitaxial layer is disposed on the surface of the substrate, and deep-level impurity ions are implanted in the surface of the first epitaxial layer. A portion of the first epitaxial layer is implanted with ions of a second semiconductor type. The second epitaxial layer is disposed on the first epitaxial layer, and deep-level impurity ions are implanted in the surface of the second epitaxial layer. Ions of a second semiconductor type are implanted in a portion of the second epitaxial layer.

10. The metal-oxide-semiconductor structure as described in claim 9, characterized in that, The substrate surface further includes a third epitaxial layer, or it may include a third epitaxial layer and a fourth epitaxial layer; The third epitaxial layer is disposed on the second epitaxial layer, and deep-level impurity ions are implanted in the surface of the third epitaxial layer. A portion of the third epitaxial layer is implanted with ions of a second semiconductor type. The fourth epitaxial layer is disposed on the third epitaxial layer, and deep-level impurity ions are implanted in the surface of the fourth epitaxial layer. A portion of the fourth epitaxial layer is implanted with ions of a second semiconductor type.

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