A semiconductor device and its manufacturing method

Abstract

This application provides a semiconductor device and a method for manufacturing the same, including a substrate and a source, drain, and channel structure disposed on one side of the substrate. The substrate includes a bottom fin structure. Along a first direction, a bottom gate is disposed on both sides of the bottom fin structure. The bottom gate extends along a direction perpendicular to the plane of the substrate and is connected to a top gate. That is, by disposing a bottom gate around the bottom fin structure, conductivity control of the bottom fin structure can be achieved using the bottom gate. This can increase the conduction current of the semiconductor device in the on state and reduce the leakage current of the semiconductor device in the off state. In addition, since the top gate and the bottom gate are connected, heat in the channel structure can be conducted to the substrate using the top gate and the bottom gate, enhancing the heat dissipation effect of the semiconductor device and improving the performance of the finally manufactured semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate FinFETs are limited by gate failure and leakage current degradation at nodes below 3 nanometers (nm). Since the Nanosheet Gate-all-round Field-Effect Transistor (Nanosheet GAAFET) breaks through the 3nm node limitation, it has received widespread attention and research.

[0003] Nanosheet GAAFET is a novel device featuring a gate-around structure and stacked horizontal nanosheets (NS) as the conductive channel. In terms of gate control, the gate-around structure offers better gate control than FinFET devices, effectively suppressing short-channel effects. Regarding current drive, Nanosheet GAAFET exhibits bulk inversion carriers, and the increased effective gate width and vertical nanosheet stacking design significantly enhance the device's current drive performance.

[0004] However, current Nanosheet GAAFETs have large leakage current and poor heat dissipation performance, resulting in increased device power consumption and decreased overall performance. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which can reduce the leakage current of the semiconductor device, enhance the heat dissipation effect, and improve the performance of the finally manufactured semiconductor device.

[0006] This application provides a semiconductor device, the semiconductor device comprising:

[0007] Substrate;

[0008] A source, drain, and channel structure are disposed on one side of the substrate, wherein the channel structure is located between the source and the drain, and the channel structure comprises a stack of multiple nanosheets.

[0009] The substrate includes a bottom fin structure, and the projections of the bottom fin structure and the channel structure overlap in a direction perpendicular to the plane of the substrate.

[0010] The gate includes a top gate and a bottom gate. The top gate surrounds the nanosheet along a first direction. The bottom gate is disposed on both sides of the bottom fin structure and extends along a direction perpendicular to the plane of the substrate and is connected to the top gate. The first direction is perpendicular to the line connecting the source and the drain.

[0011] Optionally, a shallow trench isolation is provided between the bottom fin structure and the bottom gate, wherein the bottom gate extends in the shallow trench isolation along a direction perpendicular to the plane of the substrate.

[0012] Optionally, along the first direction, the width of the bottom fin structure is smaller than the width of the nanosheet.

[0013] Optionally, along the second direction, the source and the drain overlap with the projection of the bottom fin structure, respectively, where the second direction is the direction of the line connecting the source and the drain.

[0014] Optionally, the performance of the semiconductor device can be controlled by adjusting the height of the bottom gate, the width of the bottom gate along a first direction, or the length of the bottom gate along a second direction, where the second direction is the line connecting the source and the drain.

[0015] Optionally, the bottom gate material is one or more of W, Al, Cu, Ti, Co, Pt, Ta, and nitrides.

[0016] This application provides a method for manufacturing a semiconductor device, the method comprising:

[0017] A substrate is provided, and a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer are formed on one side of the substrate;

[0018] The stacked structure and the substrate are etched to form a fin structure, the fin structure including a bottom fin structure formed from the substrate;

[0019] Shallow grooves are formed around the bottom fin structure for isolation;

[0020] The stacked structure is etched to form a source region and a drain region, and a channel region is formed between the source region and the drain region;

[0021] A source and a drain are formed in the source region and the drain region, respectively.

[0022] Etching the shallow trench isolation forms a bottom gate insertion hole;

[0023] A gate material is filled into the bottom gate insertion hole to form a bottom gate. The first semiconductor layer is replaced with a top gate. The top gate surrounds the second semiconductor layer. A stack of multiple second semiconductor layers forms a channel structure. Along a first direction, the bottom gate is disposed on both sides of the bottom fin structure. The bottom gate extends along a direction perpendicular to the plane of the substrate and is connected to the top gate. The first direction is perpendicular to the line connecting the source and the drain.

[0024] Optionally, etching the stacked structure and the substrate to form the fin structure includes:

[0025] The substrate is etched and narrowed to form a bottom fin structure.

[0026] Optionally, etching the stacked structure to form the source and drain regions includes:

[0027] The stacked structure is over-etched until a portion of the substrate thickness is removed, forming the source and drain regions.

[0028] Optionally, replacing the first semiconductor layer with the top gate includes:

[0029] The first semiconductor layer is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers.

[0030] The top gate is formed by filling multiple of the gaps to be filled.

[0031] This application provides a semiconductor device, which includes a substrate and a source, a drain, and a channel structure disposed on one side of the substrate. The channel structure is located between the source and the drain and includes a stack of multiple nanosheets. The substrate includes a bottom fin structure. In a direction perpendicular to the plane of the substrate, the projections of the bottom fin structure and the channel structure overlap, that is, the bottom fin structure is located below the channel structure. The semiconductor device also includes a gate, which includes a top gate and a bottom gate. The top gate surrounds the nanosheets along a first direction. The bottom gate is disposed on both sides of the bottom fin structure and extends along a direction perpendicular to the plane of the substrate and is connected to the top gate. The first direction is the direction perpendicular to the line connecting the source and the drain. That is, by setting the bottom gate around the bottom fin structure, the conductivity control of the bottom fin structure can be achieved by using the bottom gate. This can increase the conduction current of the semiconductor device in the on state and reduce the leakage current of the semiconductor device in the off state. In addition, since the top gate and the bottom gate are connected, the heat in the channel structure can be conducted to the substrate using the top gate and the bottom gate, which enhances the heat dissipation effect of the semiconductor device and improves the performance of the finally manufactured semiconductor device. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application is shown;

[0034] Figure 2 and Figure 3 Provided for the embodiments of this application Figure 1 The diagram shows cross-sectional structures of a semiconductor device in various directions.

[0035] Figure 4A and Figure 4B Provided for the embodiments of this application Figure 1 The diagram shows cross-sectional structures of a semiconductor device in various directions.

[0036] Figure 5 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown;

[0037] Figures 6-21 show schematic diagrams of the structure of a semiconductor device manufactured according to the manufacturing method of the semiconductor device provided in the embodiments of this application. Detailed Implementation

[0038] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0039] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0040] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate FinFETs are limited by gate failure and leakage current degradation at nodes below 3 nanometers (nm). Since the Nanosheet Gate all-round Field-Effect Transistor (Nanosheet GAAFET) breaks through the 3nm node limitation, it has received widespread attention and research.

[0041] Nanosheet GAAFET is a novel device featuring a gate-around structure and stacked horizontal nanosheets (NS) as the conductive channel. In terms of gate control, the gate-around structure offers better gate control than FinFET devices, effectively suppressing short-channel effects. Regarding current drive, Nanosheet GAAFET exhibits bulk inversion carriers, and the increased effective gate width and vertical nanosheet stacking design significantly enhance the device's current drive performance.

[0042] However, the current stacked nanosheets have a large bottom fin, which causes leakage current in Nanosheet GAAFETs, further increasing the power consumption of the device. In addition, the horizontal nanosheets are suspended channel structures, and the channel structure is not directly connected to the substrate, making it difficult for the heat generated in the channel structure under high current to be effectively conducted through the substrate, thus posing a great challenge to the electrical and thermal performance and reliability of the device.

[0043] Based on this, embodiments of this application provide a semiconductor device, which includes a substrate and a source, a drain, and a channel structure disposed on one side of the substrate. The channel structure is located between the source and the drain and includes a stack of multiple nanosheets. The substrate includes a bottom fin structure. In a direction perpendicular to the plane of the substrate, the projections of the bottom fin structure and the channel structure overlap, that is, the bottom fin structure is located below the channel structure. The semiconductor device also includes a gate, which includes a top gate and a bottom gate. The top gate surrounds the nanosheets along a first direction, and the bottom gate is disposed on both sides of the bottom fin structure. The channel extends in a direction perpendicular to the plane of the substrate and connects to the top gate. The first direction is perpendicular to the line connecting the source and drain. In other words, by setting the bottom gate around the bottom fin structure, the conductivity of the bottom fin structure can be controlled by the bottom gate. This can increase the conduction current of the semiconductor device in the on state and reduce the leakage current of the semiconductor device in the off state. In addition, since the top gate and the bottom gate are connected, the heat in the channel structure can be conducted to the substrate through the top gate and the bottom gate, which enhances the heat dissipation effect of the semiconductor device and improves the performance of the final manufactured semiconductor device.

[0044] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0045] See Figure 1 The figure is a three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application.

[0046] The semiconductor device provided in this embodiment includes a substrate 110, a source 131, a drain 132, a channel structure, and a gate 160.

[0047] In the embodiments of this application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0048] In the embodiments of this application, a source 131, a drain 132, and a channel structure are disposed on one side of the substrate 110. The channel structure is disposed between the source 131 and the drain 132, and includes a stack of multiple nanosheets. The channel structure is obtained by removing the first semiconductor layer 121 from the stacked structure. The stacked structure is composed of alternating layers of the first semiconductor layer 121 and the second semiconductor layer 122. That is, the nanosheets in the channel structure are the second semiconductor layer 122 in the stacked structure. (Refer to...) Figure 2 and Figure 3 As shown, where, Figure 2 Provided for the embodiments of this application Figure 1The diagram shows a cross-sectional view of the semiconductor device along the XX direction. Figure 3 Provided for the embodiments of this application Figure 1 The diagram shows a cross-sectional structure of the semiconductor device in the YY direction. The cross-sectional structure in the YY direction is parallel to the gate line of the gate, and the cross-sectional structure in the XX direction is parallel to the fin line of the fin.

[0049] In embodiments of this application, the substrate 110 includes a bottom fin structure 111, and the projections of the bottom fin structure 110 and the channel structure overlap in a direction perpendicular to the plane of the substrate 110. That is, a bottom fin structure 111 is disposed below the channel structure, and the material of the bottom fin structure 111 is the same as the substrate material.

[0050] In the embodiments of this application, the gate 160 includes a top gate 161 and a bottom gate 162. The multiple nanosheets in the channel structure are spaced apart, and the top gate 160 is filled in the space. That is, the top gate 160 surrounds the nanosheets to form a ring gate structure.

[0051] refer to Figure 2 As shown, along the first direction, that is, along the line perpendicular to the connection between the source 131 and the drain 132, i.e., the YY direction, the bottom gate 162 is disposed on both sides of the bottom fin structure 111. In other words, the bottom gate 162 can control the carrier transport of the bottom fin structure 111 by being disposed around the bottom fin structure 111, thereby realizing the conductivity control of the bottom fin structure using the bottom gate.

[0052] In the embodiments of this application, the bottom gate 162 extends along a direction perpendicular to the plane of the substrate 110 and is connected to the top gate 161. That is, through the connection of the bottom gate 162 and the top gate 161, the switching of the semiconductor device can be controlled simultaneously by the bottom gate 162 and the top gate 161. Setting the bottom gate 162 can increase the conduction current of the semiconductor device in the on state and reduce the leakage current of the semiconductor device in the off state. In addition, since the top gate 161 and the bottom gate 162 are connected, the heat in the channel structure can be conducted to the substrate 110 by the top gate 161 and the bottom gate 162. That is, the high thermal conductivity of the gate 160 can be used to more effectively transfer the heat in the channel structure to the substrate 110, enhance the heat dissipation effect of the semiconductor device, and improve the performance of the finally manufactured semiconductor device.

[0053] In the embodiments of this application, a shallow trench isolation (STI) 203 is provided between the bottom fin structure 111 and the bottom gate 162, and the bottom gate 162 extends in the shallow trench isolation 203 along a direction perpendicular to the plane of the substrate 110. That is, the bottom gate 162 is equivalent to the top gate 161 extending downward and inserting into the shallow trench isolation 203, thereby controlling the parasitic FinFET formed by the bottom fin structure 111.

[0054] Specifically, the material of the bottom gate can be one or more of W, Al, Cu, Ti, Co, Pt, Ta, and nitrides.

[0055] In practical applications, by inserting a gate electrode downward in the shallow trench isolation 203, a parasitic FinFET is formed on the substrate 110, and together with the Nanosheet GAAFET formed by the horizontal nanosheet, a VeinFET device structure is formed, thereby comprehensively improving the electrical performance, thermal performance and reliability performance of the semiconductor device.

[0056] Shallow trench isolation 203 is disposed between different fins. The surface of the shallow trench isolation 203 away from the substrate 110 can be flush with, or higher than or lower than, the surface of the stacked structure in the fins near the substrate 110. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fins.

[0057] In the embodiments of this application, along the first direction, the width of the bottom fin structure 111 is smaller than the width of the nanosheet. That is, in the first direction, the fin width of the bottom fin structure 111 is smaller than the width of the nanosheet in the channel structure. The bottom gate 162 can more easily control the narrower bottom fin structure 111, and the narrower bottom fin structure 111 can also achieve size matching with the Nanosheet GAAFET device.

[0058] In the embodiments of this application, along the second direction, that is, along the line connecting the source 131 and the drain 132, i.e., the XX direction, the projections of the source 131 and the drain 132 overlap with those of the bottom fin structure 111. In other words, the surface of the source 131 and the drain 132 closest to the substrate 110 can be lower than the surface of the bottom fin structure 111 furthest from the substrate 110. Specifically, the distance between the surface of the source 131 and the drain 132 closest to the substrate 110 and the substrate 110 is less than the distance between the surface of the bottom fin structure 111 furthest from the substrate 110 and the substrate 110. By reducing the distance between the surface of the source 131 and the drain 132 closest to the substrate 110 and the substrate 110, the ability of the source 131 and the drain 132 to control the current can be optimized, and the performance of the parasitic FinFET can be adjusted.

[0059] In the embodiments of this application, the performance of the semiconductor device can be controlled by adjusting the height of the bottom gate 162, the width of the bottom gate 162 along the first direction, or the length of the bottom gate 162 along the second direction. That is, the height, width, and length of the bottom gate 162 can all be used as parameters to adjust the performance of the parasitic FinFET.

[0060] In embodiments of this application, a high-k dielectric layer 150 may also be disposed between the top gate 160 and the nanosheet, that is, the high-k dielectric layer 150 is disposed around the nanosheet, see reference. Figure 4A and Figure 4B As shown.

[0061] As an example, the material of the high-k dielectric layer 150 can be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0062] In embodiments of this application, the semiconductor device further includes a second sidewall 205, an isolation layer 207, a top dielectric layer 170, and a contact electrode 180.

[0063] The second sidewall 205 is disposed on the side of the channel structure away from the substrate 110, and a top gate 161 is located between the second sidewalls 205. An isolation layer 207 is disposed on the side of the source 131 or drain 132 away from the substrate 110, and a second sidewall 205 and a top gate 161 are located between the isolation layers 207.

[0064] The top dielectric layer 170 covers the isolation layer 207, the second sidewall 205 and the gate 160. The top dielectric layer 170 has a contact electrode 180 for electrically leading out the source 131 or the drain 132.

[0065] Therefore, the semiconductor device provided in this application includes a substrate and a source, a drain, and a channel structure disposed on one side of the substrate. The channel structure is located between the source and the drain and includes a stack of multiple nanosheets. The substrate includes a bottom fin structure. In a direction perpendicular to the plane of the substrate, the projections of the bottom fin structure and the channel structure overlap, that is, the bottom fin structure is located below the channel structure. The semiconductor device also includes a gate, which includes a top gate and a bottom gate. The top gate surrounds the nanosheets along a first direction. The bottom gate is disposed on both sides of the bottom fin structure and extends along a direction perpendicular to the plane of the substrate and is connected to the top gate. The first direction is the direction perpendicular to the line connecting the source and the drain. That is, by setting the bottom gate around the bottom fin structure, the conductivity control of the bottom fin structure is achieved by using the bottom gate. This can increase the conduction current of the semiconductor device in the on state and reduce the leakage current of the semiconductor device in the off state. In addition, since the top gate and the bottom gate are connected, the heat in the channel structure can be conducted to the substrate using the top gate and the bottom gate, which enhances the heat dissipation effect of the semiconductor device and improves the performance of the finally manufactured semiconductor device.

[0066] Based on the semiconductor device provided in the above embodiments, this application also provides a method for manufacturing a semiconductor device, and its working principle will be described in detail below with reference to the accompanying drawings.

[0067] See Figure 5 The figure is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of this application.

[0068] The method for manufacturing a semiconductor device provided in this application includes the following steps:

[0069] S101, a substrate 110 is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 is formed on one side of the substrate 110, with reference to... Figure 6A and Figure 6B As shown.

[0070] In the embodiments of this application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0071] As an example, the desired well depth can be achieved by implanting impurities into a bulk silicon substrate and then annealing it to form a highly doped well region. The doping type of the substrate 110 varies depending on the device type. For P-type semiconductor devices, the highly doped well region is an N-well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions. For N-type semiconductor devices, the highly doped well region is a p-well, and the implanted impurities are p-type impurity ions, such as boron (B) ions.

[0072] In the embodiments of this application, the performance of the final parasitic FinFET can be controlled by controlling the ion doping concentration in the substrate 110.

[0073] In embodiments of this application, a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 can be formed on one side of the substrate 110, as shown in the reference. Figure 6A and Figure 6B As shown, where, Figure 6A Provided for the embodiments of this application Figure 1 The diagram shows a cross-sectional view of the semiconductor device along the XX direction. Figure 6B Provided for the embodiments of this application Figure 1 The diagram shows a cross-sectional structure of the semiconductor device in the YY direction. The cross-sectional structure in the YY direction is parallel to the gate line of the gate, and the cross-sectional structure in the XX direction is parallel to the fin line of the fin.

[0074] The first semiconductor layer 121 and the second semiconductor layer 122 can be formed using an epitaxial process.

[0075] Specifically, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same. For example, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. Alternatively, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon-germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon.

[0076] In practical applications, silicon oxide may be formed on the substrate 110. The stacked structure can be formed after the silicon oxide on the substrate 110 is removed and the substrate 110 is cleaned.

[0077] S102, etching is performed on the stacked structure and substrate 110 to form a fin structure, reference. Figure 8A and Figure 8B As shown.

[0078] In the embodiments of this application, the stacked structure and the substrate 110 can be etched to form a fin structure, wherein the fin structure includes a bottom fin structure 111, which is obtained by etching the substrate 110.

[0079] The specific process for forming the fin structure is as follows:

[0080] S1021, Sidewall Transfer Process, Reference Figure 7A and Figure 7B As shown.

[0081] In the embodiments of this application, a self-aligned sidewall transfer process is used to form the first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is as follows: a sacrificial layer 202 is covered on the stacked structure. The material of the sacrificial layer 202 can be polycrystalline silicon or amorphous silicon. Part of the sacrificial layer 202 is etched away using photolithography to form a pattern. Silicon nitride material is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 202, so that only the first sidewall 201 on the stacked structure remains. The first sidewall 201 plays the role of a hard mask in the subsequent photolithography for forming fins.

[0082] S1022, forming a fin structure, reference. Figure 8A and Figure 8B As shown.

[0083] In the embodiments of this application, the stacked structure and the substrate 110 can be etched using an etching process to form multiple periodically distributed fins, as shown in the reference. Figure 8A and Figure 8B As shown, etching is performed using the first sidewall 201 as a mask to form a fin structure with a stacked structure. The upper part of the fin structure is the channel region 103 formed by the stacked structure, and the lower part is the bottom fin structure 111 formed by the substrate 110, forming a structure as shown. Figure 8A The fin structure shown includes not only a stacked structure but also a bottom fin structure 111 extending into the substrate 110. The etching process can be dry etching or wet etching; in one embodiment, reactive ion etching may be used. The upper part of the fin structure will be used to form nanosheets for semiconductor devices. Although Figure 8A A fin structure is shown, and it should be understood that any suitable number and shape of fin structure can be used in practical applications.

[0084] In the embodiments of this application, when etching the substrate 110 to form the bottom fin structure 111, a narrowing process of the bottom fin structure 111 can be performed to reduce the fin width of the bottom fin structure 111 in the first direction, so that in the parasitic FinFET subsequently formed, the bottom gate 162 can more easily control the narrower bottom fin structure 111.

[0085] S103, shallow groove isolation 203 is formed around the bottom fin structure 111, reference. Figure 9A and Figure 9B As shown.

[0086] In embodiments of this application, shallow trench isolation 203 can be formed between different fin structures. Specifically, a dielectric insulating material can be deposited first, followed by a planarization process, such as CMP, and then a selective etch-back process of the dielectric insulating material to expose the three-dimensional fin structure, thereby forming shallow trench isolation 203 between adjacent fin structures. The surface of the shallow trench isolation 203 away from the substrate 110 can be flush with, or higher than, the surface of the stacked structure in the fin structure near the substrate 110. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fin structures.

[0087] In practical applications, when forming shallow trench isolation 203, the first sidewall 201 can also be removed.

[0088] In the embodiments of this application, after forming the shallow trench isolation 203, a dummy fence 204 and a second sidewall 205 can also be formed. The specific process flow is as follows:

[0089] S1031, forming a dummy gate 204, reference. Figure 10A and Figure 10B As shown.

[0090] In the embodiments of this application, a dummy gate stack is formed on the exposed fin in a direction perpendicular to the fin lines, i.e., in the YY direction. The dummy gate stack is a multilayer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). The dummy gate stack can be formed using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The dummy gate stack spans the stack structure above the fin, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 can be polycrystalline silicon or amorphous silicon. The material of the hard mask layer can be oxides, carbides, organic materials, etc.

[0091] S1032, forming the second sidewall 205, reference. Figure 11A and Figure 11B As shown.

[0092] In the embodiments of this application, second sidewalls 205 can be provided on both sides of the dummy gate stack along the fin direction, i.e., the XX direction, and the thickness of the second sidewalls 205 on both sides is the same. The material of the second sidewalls 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0093] S104, etching is performed on the stacked structure to form source region 101 and drain region 102, reference. Figure 12A and Figure 12B As shown.

[0094] In embodiments of this application, the stacked structure can be etched to form a source region 101 and a drain region 102, wherein a channel region 103 is formed between the source region 101 and the drain region 102. (Refer to...) Figure 12A and Figure 12B As shown.

[0095] Specifically, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source and drain etching on the stacked structure through an etching process, specifically on the fin structure. The source region 101 and the drain region 102 no longer have a stacked structure after etching. (Refer to...) Figure 12B As shown.

[0096] In the embodiments of this application, when etching the stacked structure to form the source region 101 and the drain region 102, the stacked structure can be over-etched until a portion of the substrate 110 thickness is removed, so that the surface of the substrate 110 located in the source region 101 and the drain region 102 is lower than the surface of the substrate 110 located in the channel region 103.

[0097] Specifically, the performance of parasitic FinFETs can be adjusted by optimizing the current control capabilities of the source 131 and drain 132 by adjusting the etching depth of the source region 101 and drain region 102 on the substrate 110.

[0098] S105, source 131 and drain 132 are formed in source region 101 and drain region 102, respectively, for reference. Figure 15A and Figure 15B As shown.

[0099] In the embodiments of this application, after etching the stacked structure to form the source region 101 and the drain region 102, the source 131 and drain 132 can be selectively epitaxially formed outward from the source region 101 and the drain region 102, respectively, using the remaining second semiconductor layer 122 as the growth base. (Refer to...) Figure 15A and Figure 15B As shown.

[0100] Specifically, the source and drain materials may differ for different types of semiconductor devices. For P-type semiconductor devices, the source and drain epitaxial materials are boron-doped germanium silicon, i.e., SiGe:B. For N-type semiconductor devices, the source and drain epitaxial materials are phosphorus-doped silicon, i.e., Si:P.

[0101] In the embodiments of this application, a third sidewall 206 may be constructed before forming the source 131 and drain 132. The specific process flow is as follows:

[0102] S1051, forming a concave structure 401, reference. Figure 13A and Figure 13B As shown.

[0103] In the embodiments of this application, along the XX direction, the first semiconductor layer 121 in the stacked structure located in the channel region 103 is selectively etched, that is, only the first semiconductor layer 121 is etched, without damaging the second semiconductor layer 122. Along the XX direction, the portion of the first semiconductor layer 121 missing from the second semiconductor layer 122 forms a concave structure 401, that is, pull-back etching is performed, etching away a portion of the first semiconductor layer 121 from the source region 101 and drain region 102 towards the channel region 103. (Refer to...) Figure 13A and Figure 13B As shown.

[0104] S1052, forming the third sidewall 206, reference. Figure 14A and Figure 14B As shown.

[0105] In the embodiments of this application, after the first semiconductor layer 121 is etched, a dielectric material is deposited on the stacked structure located in the channel region 103, i.e., the periphery of the fins. The dielectric material is etched to form a third sidewall 206. The third sidewall 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane of the substrate 110. That is, the concave structure 401 caused by etching in S1051 is filled by the third sidewall 206. The material of the third sidewall 206 can be silicon nitride or silicon oxide.

[0106] In embodiments of this application, after forming the source 131 and drain 132, the dummy gate 204 can be removed, see reference. Figure 16A and Figure 16B As shown.

[0107] In embodiments of this application, an isolation layer 207 can be deposited on the surfaces of the dummy gate 204, source 131, and drain 132 to prevent short circuits between the dummy gate 204 and the source 131 or drain 132 in subsequent steps. The isolation layer 207 is then subjected to a chemical mechanical polishing process to planarize it. Then, as... Figure 16A and Figure 16B As shown, the dummy gate 204 formed by the aforementioned polycrystalline silicon or amorphous silicon is etched or etched away by selective etching or etching processes, that is, the dummy gate 204 is removed.

[0108] S106, Etch shallow trench isolation 203 to form bottom gate insertion hole 190, Reference Figure 17 As shown.

[0109] In embodiments of this application, shallow trench isolation 203 can be etched to form a bottom gate insertion hole 190. Along a first direction, that is, along the direction perpendicular to the line connecting the source 131 and the drain 132 (YY direction), the bottom gate insertion hole 190 is disposed on both sides of the bottom fin structure 111. (Refer to...) Figure 17 As shown, Figure 17 Provided for the embodiments of this application Figure 1 The diagram shows a cross-sectional view of the semiconductor device in the YY direction.

[0110] In practical applications, the depth of the bottom gate insertion hole 190 obtained by etching, the width of the bottom gate insertion hole 190 along the first direction, or the length of the bottom gate insertion hole 190 along the second direction can be adjusted by adjusting the etching conditions. In this way, the gate dielectric thickness of the parasitic FinFET and the electrical and thermal performance of the parasitic FinFET can be further controlled by the parameters of the bottom gate insertion hole 190 obtained by etching.

[0111] Specifically, the width of the bottom gate insertion hole 190 along the first direction can range from 1 to 1000 nm, and the depth of the bottom gate insertion hole 190 can range from 10 to 1000 nm.

[0112] S107, fill the bottom gate insertion hole 190 with gate material to form bottom gate 162, and replace the first semiconductor layer 121 with top gate 161, as shown in Figures 18-20.

[0113] In the embodiments of this application, a gate 160 of a semiconductor device can be formed. Specifically, a gate material can be filled into the bottom gate insertion hole 190 to form a bottom gate 162. The first semiconductor layer 121 can be replaced with a top gate 161. The bottom gate 162 extends along a direction perpendicular to the plane of the substrate 110 and is connected to the top gate 161, as shown in Figures 18-20.

[0114] The specific process flow is as follows:

[0115] S1071, Remove the first semiconductor layer 121 of the channel region 103, Reference Figure 18A and Figure 18B As shown.

[0116] In embodiments of this application, the first semiconductor layer 121 of the channel region 103 can be removed, i.e., a nanosheet channel release process can be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layers 122, see reference. Figure 18A and Figure 18B As shown.

[0117] Specifically, the first semiconductor layer 121 in the stacked structure located in the channel region 103 can be selectively etched to release the nanosheet channel. That is, the stacked structure exposed by the fins is processed to remove the first semiconductor layer 121 of each layer, which is the sacrificial layer, to release the nanosheets formed by the second semiconductor layer 122.

[0118] In the embodiments of this application, there are several possible ways to achieve nanosheet channel release for different types of devices:

[0119] In a first possible implementation, for both P-type and N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-laminated nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0120] In a second possible implementation, for a P-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon. Silicon is selectively removed, leaving the second semiconductor layer 122, i.e., silicon-germanium, to form a silicon-germanium stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon at a faster rate than silicon-germanium can be used.

[0121] In a third possible implementation, for N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0122] S1072, a high-k dielectric layer 150 is formed on the surface of the second semiconductor layer 122 and in the bottom gate insertion hole 190. Reference Figure 19A and Figure 19B As shown.

[0123] In embodiments of this application, after removing the first semiconductor layer 121, a high-k dielectric layer 150 can be formed on the surface of the second semiconductor layer 122 and on the bottom and sidewalls of the bottom gate insertion hole 190. The high-k dielectric layer 150 surrounds the surface of the second semiconductor layer 122 and covers the bottom and sidewalls of the bottom gate insertion hole 190. (See reference...) Figure 19A and Figure 19B As shown. Specifically, the material of the high-k dielectric layer 150 can be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO xOne or a combination of Ta2O5 or La2O3.

[0124] In embodiments of this application, the high-k dielectric layer 150 may further include an interface oxide layer (IL) (not shown).

[0125] S1073, gate material is filled into the bottom gate insertion hole 190 to form the bottom gate 162, and the top gate 161 is formed by filling the plurality of gaps 402 to be filled. (Reference) Figure 20A and Figure 20B As shown.

[0126] In the embodiments of this application, after the nanosheet channel is released, there are multiple gaps 402 to be filled between the multiple second semiconductor layers 122. Gate material can be filled into the multiple gaps 402 to form a top gate 161. The top gate 161 surrounds the second semiconductor layers 122, forming a ring gate structure. The stack of multiple second semiconductor layers 122 forms a channel structure, that is, a nanosheet channel for a semiconductor device. (Refer to...) Figure 20A and Figure 20B As shown.

[0127] In practical applications, in addition to forming a top gate 161 in the gap 402 to be filled, the top gate 161 also covers the space after the isolation layer 207 and the dummy gate 204 are removed. The gate 160 covered by the isolation layer 207 can be chemically mechanically polished to perform planarization.

[0128] In the embodiments of this application, while forming the top gate 161, the gate material also fills the bottom gate insertion hole 190 to form the bottom gate 162, forming the buried gate electrode of the top gate 161 extending downward in the STI to control the bottom fin structure 111.

[0129] In embodiments of this application, the gate 160 may further include a multilayer structure such as a diffusion barrier layer, a work function layer, and a conductive filling layer (not shown).

[0130] In embodiments of this application, after forming the gate 160, dielectric deposition can be performed on the top of the semiconductor device away from the substrate 110 to form a top dielectric layer 170, as shown in the reference. Figure 21A and Figure 21B As shown.

[0131] In the embodiments of this application, contact hole etching is performed in the top dielectric layer 170, etching down to the surface of the source 131 or drain 132, and metal material is deposited in the contact holes to form the contact electrodes 180 of the source 131 or drain 132. (Refer to...) Figure 4A and Figure 4B As shown, subsequent processes include multi-layer back-end interconnection and passivation protection.

[0132] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, structural embodiments are basically similar to method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The apparatus embodiments described above are merely illustrative. The units and modules described as separate components may or may not be physically separate. Furthermore, some or all of the units and modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0133] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Substrate; A source, drain, and channel structure are disposed on one side of the substrate, wherein the channel structure is located between the source and the drain, and the channel structure comprises a stack of multiple nanosheets. The substrate includes a bottom fin structure, and the projections of the bottom fin structure and the channel structure overlap in a direction perpendicular to the plane of the substrate. The gate includes a top gate and a bottom gate. The top gate surrounds the nanosheet along a first direction. The bottom gate is disposed on both sides of the bottom fin structure and extends along a direction perpendicular to the plane of the substrate and is connected to the top gate. The first direction is perpendicular to the line connecting the source and the drain.

2. The semiconductor device according to claim 1, characterized in that, A shallow trench isolation is provided between the bottom fin structure and the bottom gate, and the bottom gate extends in the shallow trench isolation along a direction perpendicular to the plane of the substrate.

3. The semiconductor device according to claim 1, characterized in that, Along the first direction, the width of the bottom fin structure is smaller than the width of the nanosheet.

4. The semiconductor device according to claim 1, characterized in that, Along the second direction, the source and the drain overlap with the projection of the bottom fin structure, respectively, where the second direction is the line connecting the source and the drain.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The performance of the semiconductor device is controlled by adjusting the height of the bottom gate, the width of the bottom gate along a first direction, or the length of the bottom gate along a second direction, where the second direction is the line connecting the source and the drain.

6. The semiconductor device according to any one of claims 1-4, characterized in that, The bottom gate is made of one or more of W, Al, Cu, Ti, Co, Pt, Ta, and nitrides.

7. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided, and a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer are formed on one side of the substrate; The stacked structure and the substrate are etched to form a fin structure, the fin structure including a bottom fin structure formed from the substrate; Shallow grooves are formed around the bottom fin structure for isolation; The stacked structure is etched to form a source region and a drain region, and a channel region is formed between the source region and the drain region; A source and a drain are formed in the source region and the drain region, respectively. Etching the shallow trench isolation forms a bottom gate insertion hole; A gate material is filled into the bottom gate insertion hole to form a bottom gate. The first semiconductor layer is replaced with a top gate. The top gate surrounds the second semiconductor layer. A stack of multiple second semiconductor layers forms a channel structure. Along a first direction, the bottom gate is disposed on both sides of the bottom fin structure. The bottom gate extends along a direction perpendicular to the plane of the substrate and is connected to the top gate. The first direction is perpendicular to the line connecting the source and the drain.

8. The manufacturing method according to claim 7, characterized in that, The etching of the stacked structure and the substrate to form the fin structure includes: The substrate is etched and narrowed to form a bottom fin structure.

9. The manufacturing method according to claim 8, characterized in that, The etching of the stacked structure to form the source and drain regions includes: The stacked structure is over-etched until a portion of the substrate thickness is removed, forming the source and drain regions.

10. The manufacturing method according to claim 7, characterized in that, The step of replacing the first semiconductor layer with the top gate includes: The first semiconductor layer is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers. The top gate is formed by filling multiple of the gaps to be filled.

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