Double heterojunction nitrogen-polar gallium nitride transistor and method of manufacturing the same

Abstract

The application discloses a double-heterojunction nitrogen-polarity-face gallium nitride transistor and a manufacturing method thereof, wherein the double-heterojunction nitrogen-polarity-face gallium nitride transistor comprises, from bottom to top, a substrate layer, a bonding layer, a support layer, a barrier layer, a channel layer made of GaN and a blocking layer made of AlGaN which are sequentially stacked, the support layer is made of p-GaN, the nitrogen-polarity face of the channel layer faces upward, a gate electrode, a source electrode and a drain electrode which form an ohmic contact with the channel layer are arranged above the channel layer, a Schottky contact is formed between the gate electrode and the blocking layer, and a passivation layer is formed between the gate electrode and the source electrode and between the gate electrode and the drain electrode. By arranging a blocking layer made of AlGaN between the gate electrode and the nitrogen-polarity face of the channel layer, the blocking layer covers the upper surface of the channel layer, so that the carrier is more localized in the gallium nitride channel layer, that is, the transistor has stronger channel effect inhibition capacity, and the leakage of the transistor is reduced; the support layer is made of p-GaN, so that the leakage between the transistor and the ground can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor transistor technology, and in particular to a double heterojunction nitrogen polar surface gallium nitride transistor and its manufacturing method. Background Technology

[0002] With the development of artificial intelligence and microelectronics technology, electronic transistor products such as mobile phones and computers have provided tremendous convenience to our lives and work. However, first-generation semiconductor silicon materials can no longer meet people's ever-changing needs in some fields. Therefore, people are constantly looking for other new semiconductor materials to achieve new functions in different scenarios. In the 1990s, third-generation semiconductor materials, represented by group III nitrides such as AlN (aluminum nitride), InN (indium nitride), and GaN (gallium nitride), have broad application prospects in ultra-high-speed microelectronic transistors, ultra-high-frequency microwave transistors, and optoelectronic transistors due to their higher electron mobility and wider wavelength coverage.

[0003] Existing gallium-polarized gallium nitride (GaN) transistors, due to their low work function, struggle to reduce contact resistance at ohmic contacts, resulting in strong self-heating. Consequently, under high-frequency, high-voltage operating conditions, thermal effects accumulate rapidly, leading to severe heat generation and negatively impacting the transistor's fundamental performance. This characteristic limits the application of GaN transistors with high electron mobility in high-frequency radio frequency (RF) fields. Current GaN transistors are manufactured by epitaxially growing a layer of GaN and then using a stripping technique to reverse the GaN layer into GaN for secondary epitaxy. This process involves numerous steps, and the defects introduced during secondary epitaxy are generally more numerous than those introduced during GaN epitaxy. This results in severe leakage current in the off-state, affecting the transistor's performance. Summary of the Invention

[0004] The main objective of this invention is to provide a double heterojunction nitrogen polar surface gallium nitride transistor and its manufacturing method, aiming to solve the problems of severe leakage current and poor crystal quality in existing gallium nitride transistors.

[0005] To achieve the above objectives, the present invention provides a dual heterojunction nitrogen-polarized gallium nitride transistor, comprising, from bottom to top, a substrate layer, a bonding layer, a support layer, a barrier layer, a channel layer made of GaN, and a barrier layer made of AlGaN. The support layer is made of p-GaN. The nitrogen-polarized surface of the channel layer faces upward, and a gate electrode and a source electrode and a drain electrode forming an ohmic contact with the channel layer are disposed above the channel layer. The source electrode and the drain electrode are respectively located on opposite sides of the channel layer. The two sides of the barrier layer are respectively connected to the source electrode and the drain electrode. The gate electrode is located between the source electrode and the drain electrode and is disposed on the barrier layer. A Schottky contact is formed between the gate electrode and the barrier layer. A passivation layer made of SiN is formed between the gate electrode and the source electrode and between the gate electrode and the drain electrode. The passivation layer is stacked above the barrier layer.

[0006] Preferably, the substrate layer is made of Si, Al2O3, or SiC; and / or,

[0007] The bonding layer is made of SnIn; and / or,

[0008] The barrier layer is made of AlGaN.

[0009] The present invention also provides a method for manufacturing a double heterojunction nitrogen polar surface gallium nitride transistor, applicable to the manufacture of the above-mentioned transistor, comprising the following steps:

[0010] Provide a substrate inside the cavity;

[0011] A buffer layer, a superlattice layer, and a merging layer are sequentially formed from bottom to top on the upper surface of the substrate;

[0012] A barrier layer, a channel layer and a barrier layer, a support layer, a bonding layer and a substrate layer are sequentially stacked from bottom to top on the upper surface of the merging layer to obtain an initial crystal. The barrier layer is made of AlGaN and the support layer is made of p-GaN.

[0013] The initial crystal is inverted so that the substrate is on top of the initial crystal;

[0014] Strip the substrate;

[0015] Etch the buffer layer, superlattice layer and merging layer;

[0016] A passivation layer is deposited on the upper surface of the barrier layer;

[0017] An ohmic contact region is formed on the upper surface of the passivation layer, the barrier layer and the passivation layer at the ohmic contact region are etched, and a drain electrode and a source electrode are fabricated within the ohmic contact region;

[0018] A Schottky contact region is formed on the upper surface of the passivation layer, the passivation layer at the Schottky contact region is etched, and a gate electrode is fabricated within the Schottky contact region.

[0019] Preferably, the step of sequentially forming a buffer layer, a superlattice layer, and a merging layer stacked from bottom to top on the upper surface of the substrate includes:

[0020] The buffer layer is formed by depositing AlN on the upper surface of the substrate using a metal-organic chemical vapor deposition process.

[0021] The superlattice layer is obtained by depositing multiple cycles of barrier layers and GaN layers on the upper surface of the buffer layer using a metal-organic chemical vapor deposition process. Each cycle is defined as the sequential deposition of one barrier layer and one GaN layer on the upper surface of the buffer layer.

[0022] The merged layer is formed by depositing on the surface of the superlattice layer using a metal-organic chemical vapor deposition process.

[0023] Preferably, the step of depositing AlN on the upper surface of the substrate to form the buffer layer by means of a metal-organic chemical vapor deposition process includes:

[0024] A 2nm to 3nm thick layer of metallic Al is deposited on the substrate;

[0025] The temperature inside the cavity is set to 900℃~950℃, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylaluminum flow rate is set to 19sccm~21sccm, the cavity pressure is set to 20Toor~30Toor, and AlN is grown in three dimensions at 10nm~20nm.

[0026] The temperature inside the cavity is set to 1000℃~1050℃, the ammonia flow rate is set to 2400sccm~2600sccm, and AlN is grown in two dimensions to 140nm~160nm to form the buffer layer.

[0027] The step of depositing multiple periods of AlGaN and GaN layers on the upper surface of the buffer layer using a metal-organic chemical vapor deposition process to obtain the superlattice layer includes:

[0028] The temperature inside the chamber is set to 1000℃~1050℃, the pressure is set to 30Toor~40Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 19sccm~21sccm, the trimethylaluminum flow rate is set to 9sccm~11sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. An AlGaN layer with a thickness of 3.6nm~4.4nm is deposited on the upper surface of the buffer layer.

[0029] The temperature inside the chamber is set to 1000℃~1050℃, the pressure is set to 30Toor~40Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 45sccm~55sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A GaN layer with a thickness of 7.2nm~8.8nm is deposited on the surface of the AlGaN layer.

[0030] The temperature inside the chamber is set to 1000℃~1050℃, the pressure is set to 30Toor~40Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 19sccm~21sccm, the trimethylaluminum flow rate is set to 9sccm~11sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. An AlGaN layer with a thickness of 3.6nm~4.4nm is deposited on the upper surface of the GaN layer.

[0031] The temperature inside the chamber is set to 1000℃~1050℃, the pressure is set to 30Toor~40Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 45sccm~55sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A GaN layer with a thickness of 7.2nm~8.8nm is deposited on the surface of the AlGaN layer.

[0032] The process is repeated 13 times, setting the temperature inside the chamber to 1000℃~1050℃, the pressure to 30Toor~40Toor, the ammonia flow rate to 1900sccm~2100sccm, the trimethylgallium flow rate to 19sccm~21sccm, the trimethylaluminum flow rate to 9sccm~11sccm, and the carrier gas flow rate to 1900sccm~2100sccm, to deposit an AlGaN layer with a thickness of 3.6nm~4.4nm on the surface of the GaN layer, thereby obtaining the superlattice layer.

[0033] The step of depositing AlGaN on the surface of the superlattice layer to form the merged layer by metal-organic chemical vapor deposition includes:

[0034] The temperature inside the chamber is set to 1000℃~1050℃, the pressure is set to 25Toor~35Toor, the ammonia flow rate is set to 1400sccm~1600sccm, the trimethylgallium flow rate is set to 45sccm~55sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A merging layer with a thickness of 90nm~110nm is deposited on the AlGaN / GaN superlattice layer.

[0035] Preferably, the step of forming a barrier layer, a channel layer, a potential barrier layer, a support layer, a bonding layer, and a substrate layer stacked sequentially from bottom to top on the upper surface of the merged layer to obtain the initial crystal includes:

[0036] The barrier layer is formed by depositing AlGaN on the surface of the merged layer using a metal-organic chemical vapor deposition process.

[0037] The channel layer is formed by depositing GaN on the upper surface of the barrier layer using a metal-organic chemical vapor deposition process.

[0038] The barrier layer is formed by depositing AlGaN on the upper surface of the channel layer using a metal-organic chemical vapor deposition process.

[0039] The p-GaN support layer is deposited on the surface of the barrier layer using a metal-organic chemical vapor deposition process.

[0040] The bonding layer is formed by depositing Sn / In on the upper surface of the support layer using a physical vapor deposition process.

[0041] The substrate layer is formed by bonding Si, Al2O3, or SiC to the surface of the bonding layer using a wafer bonding process.

[0042] Preferably, the step of depositing AlGaN on the surface of the merged layer to form the barrier layer using a metal-organic chemical vapor deposition process includes:

[0043] The temperature of the cavity is set to 1000℃~1050℃, the pressure is set to 20Toor~30Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 19sccm~21sccm, the trimethylaluminum flow rate is set to 4.5sccm~5.5sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. An AlGaN layer with a thickness of 10nm~20nm is deposited on the upper surface of the merging layer to form the barrier layer.

[0044] The step of depositing the trench layer on the upper surface of the barrier layer using a metal-organic chemical vapor deposition process includes:

[0045] The temperature of the cavity is set to 1000℃~1050℃, the pressure is set to 20Toor~30Toor, the ammonia flow rate is set to 2700sccm~3300sccm, the trimethylgallium flow rate is set to 19sccm~21sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A GaN layer with a thickness of 30nm~40nm is deposited on the upper surface of the barrier layer to form the channel layer.

[0046] The step of depositing the barrier layer on the upper surface of the channel layer using a metal-organic chemical vapor deposition process includes:

[0047] The temperature of the cavity is set to 1000℃~1100℃, the pressure is set to 25Toor~30Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 45sccm~55sccm, the trimethylaluminum flow rate is set to 9sccm~11sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. An AlGaN layer with a thickness of 18nm~22nm is deposited on the upper surface of the channel layer to form the barrier layer.

[0048] The step of depositing p-GaN on the surface of the barrier layer to form the support layer by metal-organic chemical vapor deposition includes:

[0049] The temperature of the cavity is set to 1000℃~1050℃, the pressure is set to 25Toor~30Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 72sccm~88sccm, the magnesia-dicenocene flow rate is set to 0.09sccm~0.11sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A 1.8um~2.2um thick layer of p-GaN is deposited on the upper surface of the barrier layer to form the support layer.

[0050] Preferably, the steps of forming an ohmic contact region on the upper surface of the passivation layer, etching the barrier layer and the passivation layer at the ohmic contact region, and fabricating a drain electrode and a source electrode within the ohmic contact region include:

[0051] A layer of photoresist is deposited on the upper surface of the passivation layer;

[0052] Etching removes the photoresist at the first preset location to form the ohmic contact area;

[0053] Etch the barrier layer and the passivation layer at the ohmic contact area to expose the corresponding channel layer;

[0054] 9 nm Ti, 100 nm Al, 30 nm Ni and 50 nm Au are sequentially deposited in the ohmic contact region by vacuum evaporation process.

[0055] Annealing at 750℃~850℃ for 25s~35s in an annealing furnace forms the drain electrode and the source electrode. Preferably, the steps of forming a Schottky contact region on the upper surface of the passivation layer, etching the passivation layer at the Schottky contact region, and fabricating a gate electrode within the Schottky contact region include:

[0056] A layer of photoresist is deposited on the passivation layer;

[0057] Etching removes the photoresist at the second preset location to form the Schottky contact area;

[0058] Etch the passivation layer at the corresponding Schottky contact area to expose the corresponding barrier layer;

[0059] Ni of 18 nm to 22 nm and Au of 90 nm to 110 nm are sequentially deposited in the Schottky contact region by vacuum evaporation process.

[0060] The gate electrode is formed by annealing at 650℃~750℃ for 25s~35s in an annealing furnace.

[0061] In the technical solution of this invention, GaN is used as the channel layer, and the side of GaN facing the electrode is a nitrogen polar surface. Each cell of the nitrogen polar surface has three dangling bonds, which greatly reduces the contact resistance when forming an ohmic contact with the metal, thereby reducing the self-heating effect of the transistor in the working state and reducing the heat generation of the transistor. At the same time, the nitrogen polar surface has more charge carriers, so the ohmic contact is simpler and the contact resistance is lower. However, it also makes the Schottky barrier of the gate electrode prone to leakage. Therefore, a barrier layer made of AlGaN is set between the gate electrode and the nitrogen polar surface of the channel layer. The barrier layer covers the upper surface of the channel layer, and the gate electrode is set in the middle of the barrier layer. At the same time, the barrier layer, the channel layer and the barrier layer form a double heterojunction, which makes the charge carriers more localized in the gallium nitride channel layer, that is, it has a stronger channel effect suppression capability and reduces the leakage of the transistor. The support layer is made of p-GaN, which can reduce the leakage between the transistor and ground, increase the voltage withstand performance of the transistor, and reduce the heat generation of the transistor. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0063] Figure 1 This is a schematic diagram of the structure of a dual heterojunction nitrogen polar surface gallium nitride transistor according to an embodiment of the present invention;

[0064] Figure 2 This is a schematic diagram of the structure of the initial crystal according to an embodiment of the present invention;

[0065] Figure 3 This is a schematic diagram of the structure of the initial crystal after flipping according to an embodiment of the present invention;

[0066] Figure 4 This is a flowchart illustrating a method for manufacturing a dual heterojunction nitrogen polar surface gallium nitride transistor according to an embodiment of the present invention.

[0067] Explanation of icon numbers:

[0068]

[0069] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0070] The technical solutions in this embodiment will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0071] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this embodiment are only used to explain the relative positional relationship and movement of each component in a specific posture (as shown in the attached figure). If the specific posture changes, the directional indicator will also change accordingly.

[0072] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0073] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0074] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible to those skilled in the art. If a combination of technical solutions contradicts each other or cannot be implemented, such a combination should be considered non-existent and not within the scope of protection claimed by the present invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0075] In this invention, the descriptions of directions such as "up," "down," "front," "back," "left," and "right" are as follows: Figure 1 The directions shown are for reference only and are used to interpret the location. Figure 1 The relative positional relationship between the components in the shown posture is such that if the specific posture changes, the directional indication will also change accordingly.

[0076] This invention proposes a dual heterojunction nitrogen polar surface gallium nitride transistor 1 and its manufacturing method.

[0077] Please see Figure 1 The dual heterojunction nitrogen-polarized gallium nitride transistor 11 of this embodiment includes a substrate layer 10, a bonding layer 20, a support layer 30, a barrier layer 40, a channel layer 50 made of GaN, and a barrier layer 60 made of AlGaN, which are stacked sequentially from bottom to top. The support layer 30 is made of p-GaN. The nitrogen-polarized surface of the channel layer 50 faces upward, and a gate electrode 82 and a source electrode 80 and a drain electrode 81 that form an ohmic contact with the channel layer 50 are disposed above the channel layer 50. Drain electrodes 81 are located on opposite sides of the channel layer 50. The two sides of the barrier layer 60 are connected to the source electrode 80 and the drain electrode 81, respectively. The gate electrode 82 is located between the source electrode 80 and the drain electrode 81 and is disposed on the barrier layer 60. A Schottky contact is formed between the gate electrode 82 and the barrier layer 60. A passivation layer 70 made of SiN is formed between the gate electrode 82 and the source electrode 80 and between the gate electrode 82 and the drain electrode 81. The passivation layer 70 is stacked on top of the barrier layer 60.

[0078] In the technical solution of this invention, GaN (gallium nitride) is used as the channel layer 50, and the side of GaN facing the electrode is a nitrogen-polarized surface. Each cell of the nitrogen-polarized surface has three dangling bonds, which greatly reduces the contact resistance when forming an ohmic contact with the metal, thereby reducing the self-heating effect of the transistor in the working state and reducing the heat generation of the transistor. At the same time, the nitrogen-polarized surface has more charge carriers, so the ohmic contact is simpler and the contact resistance is lower. However, this also makes the Schottky barrier of the gate electrode 82 prone to leakage. Therefore, the nitrogen-polarized surface between the gate electrode 82 and the channel layer 50... A barrier layer 60 made of AlGaN (aluminum gallium nitride) is disposed between the surface and the channel layer 50. The barrier layer 60 covers the upper surface of the channel layer 50, and the gate electrode 82 is disposed in the middle of the barrier layer 60. At the same time, the barrier layer 60, the channel layer 50 and the barrier layer 40 form a double heterojunction, which makes the carrier localization in the gallium nitride channel layer 50 greater, that is, it has a stronger channel effect suppression capability and reduces the leakage current of the transistor. The support layer 30 is made of p-GaN, which can reduce the leakage current between the transistor and ground, increase the voltage withstand performance of the transistor, and reduce the heat generation of the transistor.

[0079] In one embodiment, the substrate layer 10 is made of Si (silicon), Al2O3 (alumina), or SiC (silicon carbide); and / or, the bonding layer 20 is made of SnIn (indium tin); and / or, the support layer 30 is made of GaN (gallium nitride); and / or, the barrier layer 40 is made of AlGaN (aluminum gallium nitride). The substrate layer 10 can be made of one of silicon, alumina, or silicon carbide. Silicon is stable, easy to purify, and low in cost; alumina is heat-resistant, wear-resistant, and has good insulation and thermal conductivity; diamond is heat-resistant, chemically stable, and has fast heat dissipation; silicon carbide and gallium nitride have large band gaps, high electron drift saturation velocities, low dielectric constants, and good electrical conductivity; AlGaN has good chemical stability, extremely high melting point and thermal conductivity, and a large dielectric constant, making it suitable for fabricating high-frequency, high-power transistors.

[0080] The present invention also provides a method for manufacturing a double heterojunction nitrogen polar surface gallium nitride transistor, applicable to the manufacture of the above-mentioned transistor, comprising the following steps:

[0081] Please combine Figure 2 and Figure 4 S100: Provides a substrate inside the cavity;

[0082] An auxiliary substrate 90 is provided to facilitate the growth of subsequent buffer layer 91, superlattice layer 92 and merging layer 93;

[0083] S200: A buffer layer, a superlattice layer and a merging layer are sequentially formed from bottom to top on the upper surface of the substrate;

[0084] First, a buffer layer 91, a superlattice layer 92, and a merging layer 93 are used to buffer stress and improve the crystal quality of subsequent epitaxial materials.

[0085] S300: A barrier layer, a channel layer and a potential barrier layer, a support layer, a bonding layer and a substrate layer are sequentially formed from bottom to top on the upper surface of the merged layer to obtain an initial crystal. The barrier layer is made of AlGaN and the support layer is made of p-GaN.

[0086] Finally, a support layer is grown to maximize the crystal quality of the nitrogen-polarized gallium nitride high electron mobility transistor.

[0087] S400: Invert the initial crystal so that the substrate is on top of the initial crystal;

[0088] Please combine Figure 2 and Figure 3 The initial crystal 100 is inverted so that the nitrogen polar surface of the channel layer 50 faces upward, thereby installing the source electrode 80 and the drain electrode 81 on the nitrogen polar surface of the channel layer 50.

[0089] S500: Substrate stripping;

[0090] S600: Etching buffer layer, superlattice layer and merging layer;

[0091] The substrate 90, buffer layer 91, superlattice layer 92, and merging layer 93 are all peeled off to expose the barrier layer 94.

[0092] S700: A passivation layer is deposited on the upper surface of the barrier layer;

[0093] S800: An ohmic contact region is formed on the upper surface of the passivation layer, the barrier layer and passivation layer at the ohmic contact region are etched, and the drain electrode and source electrode are fabricated in the ohmic contact region.

[0094] S900: A Schottky contact region is formed on the upper surface of the passivation layer, the passivation layer at the Schottky contact region is etched, and a gate electrode is fabricated within the Schottky contact region.

[0095] This method is used to manufacture the above-mentioned double heterojunction nitrogen polar surface gallium nitride transistor 1. The specific structure of the double heterojunction nitrogen polar surface gallium nitride transistor 1 is as described in the above embodiments. Since this method adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0096] Unintentional doping of gallium nitride (GaN) materials during epitaxial growth typically results in n-type materials. Since the activation rate of Mg in GaN decreases, achieving p-type GaN often requires heavy doping. However, heavy doping often reduces the crystal quality of the epitaxial material, leading to rough interfaces and affecting subsequent epitaxial growth. This invention first grows the transistor structure epitaxially, then reverses the epitaxial layer using a peel-bonding process. This simpler process results in fewer defects and improves the crystal quality of the nitrogen-polarized GaN. Furthermore, the p-type GaN support layer is grown only at the end of the transistor's epitaxial growth, maximizing the crystal quality of the nitrogen-polarized GaN high electron mobility transistor.

[0097] In one embodiment, step S200 includes:

[0098] S210: An AlN (aluminum nitride) buffer layer is formed by depositing AlN (aluminum nitride) on the upper surface of a substrate using a metal-organic chemical vapor deposition process;

[0099] S220: A superlattice layer is obtained by depositing multiple cycles of barrier layers and GaN layers on the upper surface of a buffer layer using a metal-organic chemical vapor deposition process. One cycle is defined as the sequential deposition of one barrier layer and one GaN layer on the upper surface of the buffer layer.

[0100] S230: A merging layer is formed on the surface of the superlattice layer by metal-organic chemical vapor deposition (MOCVD). The MOCVD process deposits a buffer layer 91, a superlattice layer 92, and a merging layer 93, resulting in rapid film formation, high adhesion strength, and a smooth deposition surface, leading to better crystal quality. Simultaneously, the inclusion of the buffer layer 91, superlattice layer 92, and merging layer 93 reduces dislocation density, buffers stress, and improves the crystal quality of subsequent epitaxial materials.

[0101] Further, step S210 includes:

[0102] S2110: A 2nm-3nm thick layer of metallic Al is deposited on the substrate;

[0103] S2120: Set the temperature inside the chamber to 900℃~950℃, the ammonia flow rate to 1900sccm~2100sccm, the trimethylaluminum flow rate to 19sccm~21sccm, the chamber pressure to 20Toor~30Toor, and grow AlN in three dimensions to 10nm~20nm.

[0104] S2130: Set the temperature inside the chamber to 1000℃~1050℃, the ammonia flow rate to 2400sccm~2600sccm, and grow AlN 140nm~160nm in two dimensions to form a buffer layer.

[0105] In a preferred embodiment, a 2.5 nm thick layer of Al is deposited on the substrate. The temperature inside the cavity is set to 950 °C, the ammonia flow rate is set to 2000 sccm, the trimethylaluminum flow rate is set to 20 sccm, and the cavity pressure is set to 25 Toor. After three-dimensional growth of AlN for 15 nm, the temperature inside the cavity is increased to 1050 °C and the ammonia flow rate is increased to 2500 sccm, so that AlN can be grown in two dimensions with a thickness of 150 nm.

[0106] Step S220 includes:

[0107] S2210: Set the temperature inside the chamber to 1000℃~1050℃, the pressure to 30Toor~40Toor, the ammonia flow rate to 1900sccm~2100sccm, the trimethylgallium flow rate to 19sccm~21sccm, the trimethylaluminum flow rate to 9sccm~11sccm, and the carrier gas flow rate to 1900sccm~2100sccm. Deposit a barrier layer with a thickness of 3.6nm~4.4nm on the upper surface of the buffer layer.

[0108] S2220: Set the temperature inside the chamber to 1000℃~1050℃, the pressure to 30Toor~40Toor, the ammonia flow rate to 1900sccm~2100sccm, the trimethylgallium flow rate to 45sccm~55sccm, and the carrier gas flow rate to 1900sccm~2100sccm, and deposit a GaN layer with a thickness of 7.2nm~8.8nm on the upper surface of the barrier layer;

[0109] S2230: Set the temperature inside the chamber to 1000℃~1050℃, the pressure to 30Toor~40Toor, the ammonia flow rate to 1900sccm~2100sccm, the trimethylgallium flow rate to 19sccm~21sccm, the trimethylaluminum flow rate to 9sccm~11sccm, and the carrier gas flow rate to 1900sccm~2100sccm. Deposit a barrier layer with a thickness of 3.6nm~4.4nm on the upper surface of the GaN layer.

[0110] S2240: Set the temperature inside the chamber to 1000℃~1050℃, the pressure to 30Toor~40Toor, the ammonia flow rate to 1900sccm~2100sccm, the trimethylgallium flow rate to 45sccm~55sccm, and the carrier gas flow rate to 1900sccm~2100sccm, and deposit a GaN layer with a thickness of 7.2nm~8.8nm on the upper surface of the barrier layer;

[0111] S2250: Return to step S2230 13 times to obtain the superlattice layer;

[0112] In a preferred embodiment, the cavity temperature is set to 1050°C, the pressure is set to 35 Toor, the ammonia flow rate is set to 2000 sccm, the trimethylgallium flow rate is set to 20 sccm, the trimethylaluminum flow rate is set to 10 sccm, and the carrier gas flow rate is set to 2000 sccm to deposit a barrier layer with a thickness of 4 nm. Then, the cavity temperature is set to 1000°C, the pressure is set to 35 Toor, the ammonia flow rate is set to 2000 sccm, the trimethylgallium flow rate is set to 50 sccm, and the carrier gas flow rate is set to 2000 sccm to deposit a GaN layer with a thickness of 8 nm on the upper surface of the barrier layer. This process is repeated 14 times to form a superlattice layer.

[0113] Step S230 includes:

[0114] S2310: Set the temperature inside the chamber to 1000℃~1050℃, the pressure to 25Toor~35Toor, the ammonia flow rate to 1400sccm~1600sccm, the trimethylgallium flow rate to 45sccm~55sccm, and the carrier gas flow rate to 1900sccm~2100sccm, and deposit a merging layer with a thickness of 90nm~110nm on the AlGaN / GaN superlattice layer.

[0115] In a preferred embodiment, the temperature inside the cavity is set to 1000°C, the pressure is set to 30 Toor, the ammonia flow rate is set to 1500 sccm, the trimethylgallium flow rate is set to 50 sccm, and the carrier gas flow rate is set to 2000 sccm, and a merging layer with a thickness of 100 nm is deposited on the AlGaN / GaN superlattice layer.

[0116] Understandably, different equipment requires different temperatures and pressures, which need to be adjusted according to the actual situation. Temperature and pressure affect the quality of material growth. If the temperature is too high, the molecular atoms are highly active during the material growth process, reducing defects. At the same time, the deposited molecular atoms will undergo thermal diffusion at high temperatures, leading to blurred interfaces and reduced transistor performance. If the temperature is too low, the activity between molecular atoms is reduced, resulting in more defects. If the pressure is too high, the material growth tends to be three-dimensional, resulting in more dislocations between materials, affecting transistor leakage. If the pressure is reduced, the gas flow rate needs to be reduced, affecting the V / III ratio (i.e., the ratio of group V elements to group III elements) of the material growth, causing the material growth to tend to be three-dimensional, which still increases the material dislocations. Various gas flow rates are mainly used to control the V / III ratio of the material. Therefore, for the growth of different materials, it is necessary to control their temperature, pressure, and gas flow rate within a reasonable range. Setting the temperature, pressure, and gas flow rate within the above range can improve the growth quality and performance of the material. At the same time, the material being grown can be changed by adjusting the gas type.

[0117] In one embodiment, step S300 includes:

[0118] S310: An AlGaN barrier layer is formed by depositing AlGaN on the upper surface of the merged layer using a metal-organic chemical vapor deposition process;

[0119] S320: GaN is deposited on the upper surface of the barrier layer to form a channel layer by metal-organic chemical vapor deposition process;

[0120] S330: An AlGaN barrier layer is formed by depositing AlGaN on the upper surface of the channel layer using a metal-organic chemical vapor deposition process;

[0121] S340: A support layer is formed by depositing p-GaN on the surface of the barrier layer using a metal-organic chemical vapor deposition process;

[0122] S350: A bonding layer is formed by depositing Sn / In on the upper surface of the support layer using a physical vapor deposition process;

[0123] S360: A substrate layer is formed by bonding Si, Al2O3, or SiC to the surface of the bonding layer using a wafer bonding process.

[0124] Understandably, depositing the barrier layer 60, channel layer 50, barrier layer 40, and support layer 30 via metal-organic chemical vapor deposition (MOCVD) results in fast film formation, high adhesion strength, and a smooth deposition surface, leading to better crystal quality. Since the side of the channel layer 50 facing the barrier layer 60 is a nitrogen-polarized side, leakage issues exist when using Schottky contacts. Therefore, the barrier layer 60 is fabricated using an aluminum gallium nitride (AlGaN) material with a large bandgap to minimize leakage. The bonding layer 20 is deposited via physical vapor deposition (PVD). PVD is a simple process, environmentally friendly, pollution-free, requires less material, produces a uniform and dense film, and has strong adhesion to the substrate, resulting in a more stable bond between the bonding layer 20 and the support layer 30.

[0125] Further, step S310 includes:

[0126] S3110: Set the temperature of the cavity to 1000℃~1050℃, the pressure to 20Toor~30Toor, the ammonia flow rate to 1900sccm~2100sccm, the trimethylgallium flow rate to 19sccm~21sccm, the trimethylaluminum flow rate to 4.5sccm~5.5sccm, and the carrier gas flow rate to 1900sccm~2100sccm. Deposit a 10nm~20nm thick AlGaN layer on the upper surface of the merging layer to form a barrier layer.

[0127] Step S320 includes:

[0128] S3210: Set the temperature of the cavity to 1000℃~1050℃, the pressure to 20Toor~30Toor, the ammonia flow rate to 2700sccm~3300sccm, the trimethylgallium flow rate to 19sccm~21sccm, and the carrier gas flow rate to 1900sccm~2100sccm. Deposit a 30nm~40nm thick GaN layer on the upper surface of the barrier layer to form a channel layer.

[0129] Step S330 includes:

[0130] S3310: Set the temperature of the cavity to 1000℃~1100℃, the pressure to 25Toor~30Toor, the ammonia flow rate to 1900sccm~2100sccm, the trimethylgallium flow rate to 45sccm~55sccm, the trimethylaluminum flow rate to 9sccm~11sccm, and the carrier gas flow rate to 1900sccm~2100sccm. Deposit an AlGaN layer with a thickness of 18nm~22nm on the upper surface of the channel layer to form a barrier layer.

[0131] Step S340 includes:

[0132] S3410: Set the cavity temperature to 1000℃~1050℃, the pressure to 25Toor~30Toor, the ammonia flow rate to 1900sccm~2100sccm, the trimethylgallium flow rate to 72sccm~88sccm, the magnesia-dicenocene flow rate to 0.09sccm~0.11sccm, and the carrier gas flow rate to 1900sccm~2100sccm. Deposit a 1.8um~2.2um thick layer of p-GaN on the upper surface of the barrier layer to form a support layer.

[0133] In a preferred embodiment, the cavity temperature is set to 1030°C, the pressure to 25 Toor, the ammonia flow rate to 2000 sccm, the trimethylgallium flow rate to 20 sccm, the trimethylaluminum flow rate to 2 sccm, and the carrier gas flow rate to 2000 sccm. A 15 nm thick barrier layer is deposited on the upper surface of the merging layer. Alternatively, the cavity temperature is set to 1000°C, the pressure to 25 Toor, the ammonia flow rate to 3000 sccm, the trimethylgallium flow rate to 20 sccm, and the carrier gas flow rate to 2000 sccm. A 30 nm–40 nm thick GaN layer is deposited on the upper surface of the barrier layer to form a channel layer. The temperature was set to 1050℃, the pressure to 30 Toor, the ammonia flow rate to 2000 sccm, the trimethylgallium flow rate to 50 sccm, the trimethylaluminum flow rate to 10 sccm, and the carrier gas flow rate to 2000 sccm. A 20 nm thick AlGaN layer was deposited on the upper surface of the channel layer to form a barrier layer. The cavity temperature was set to 1000℃, the pressure to 30 Toor, the ammonia flow rate to 2000 sccm, the trimethylgallium flow rate to 80 sccm, the magnesia-dicenocene flow rate to 0.1 sccm, and the carrier gas flow rate to 2000 sccm. A 2 μm thick GaN layer was deposited on the upper surface of the barrier layer to form a support layer.

[0134] In one embodiment, step S800 includes:

[0135] S810: A layer of photoresist is deposited on the upper surface of the passivation layer.

[0136] S820: Etching removes the photoresist at the first preset position to form an ohmic contact area;

[0137] S830: Etch the barrier layer and passivation layer at the ohmic contact region to expose the corresponding channel layer; etch away the barrier layer and passivation layer to make the source electrode and drain electrode contact the channel layer, forming an ohmic contact;

[0138] S840: 9nm Ti, 100nm Al, 30nm Ni and 50nm Au are sequentially deposited in the ohmic contact region by vacuum evaporation process;

[0139] S850: Anneal at 750℃~850℃ for 25s~35s in an annealing furnace to form a drain electrode and a source electrode.

[0140] In a preferred embodiment, the annealing temperature is 800°C and the annealing time is 30 seconds. The vacuum evaporation process is simple to form a film, with high film purity and density, and unique film structure and performance. This improves the forming quality of the source electrode 80 and the gate electrode 82. The source electrode 80 and the drain electrode 81 form an ohmic contact with the nitrogen polar surface of the channel layer, resulting in lower contact resistance. Under high-frequency operation, this can greatly improve the self-heating effect of the transistor, thereby improving the efficiency of the transistor.

[0141] In one embodiment, step S900 includes:

[0142] S910: A layer of photoresist is deposited on the passivation layer.

[0143] S920: Etching removes the photoresist at the second preset position to form a Schottky contact area;

[0144] S930: Etch the passivation layer at the corresponding Schottky contact area to expose the corresponding barrier layer; etch away the passivation layer to make the gate electrode contact with the barrier layer, thereby forming a Schottky contact;

[0145] S940: Ni of 18nm to 22nm and Au of 90nm to 110nm are sequentially deposited in the Schottky contact region by vacuum evaporation process;

[0146] S950: Anneal at 650℃~750℃ for 25s~35s in an annealing furnace to form a grid electrode.

[0147] In a preferred embodiment, the annealing temperature is 700°C and the annealing time is 30 seconds. Since the Schottky contact will cause leakage of the gate electrode 82, the gate electrode 82 is formed on the barrier layer. An entire aluminum gallium nitride barrier layer is disposed below the gate electrode 82. The barrier layer covers the channel layer, making the carriers more localized in the gallium nitride channel layer, that is, having a stronger channel effect suppression capability and reducing the leakage of the gate electrode 82.

[0148] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A method for manufacturing a double heterojunction nitrogen polar surface gallium nitride transistor, characterized in that, Includes the following steps: Provide a substrate inside the cavity; A buffer layer, a superlattice layer, and a merging layer are sequentially formed from bottom to top on the upper surface of the substrate; A barrier layer, a channel layer and a barrier layer, a support layer, a bonding layer and a substrate layer are sequentially stacked from bottom to top on the upper surface of the merging layer to obtain an initial crystal. The barrier layer is made of AlGaN, the support layer is made of p-GaN, the barrier layer is made of AlGaN, and the bonding layer is made of SnIn. The initial crystal is inverted so that the substrate is on top of the initial crystal; Strip the substrate; Etch the buffer layer, superlattice layer and merging layer; A passivation layer is deposited on the upper surface of the barrier layer; An ohmic contact region is formed on the upper surface of the passivation layer, the barrier layer and the passivation layer at the ohmic contact region are etched, and a drain electrode and a source electrode are fabricated within the ohmic contact region; A Schottky contact region is formed on the upper surface of the passivation layer, the passivation layer at the Schottky contact region is etched, and a gate electrode is fabricated in the Schottky contact region, wherein the gate electrode is disposed in the middle of the barrier layer, and the side of the channel layer near the gate electrode is a nitrogen polar side. The step of sequentially forming a buffer layer, a superlattice layer, and a merging layer stacked from bottom to top on the upper surface of the substrate includes: The buffer layer is formed by depositing AlN on the upper surface of the substrate using a metal-organic chemical vapor deposition process. The superlattice layer is obtained by depositing multiple cycles of AlGaN and GaN layers on the upper surface of the buffer layer using a metal-organic chemical vapor deposition process. Each cycle is defined as the sequential deposition of one AlGaN layer and one GaN layer on the upper surface of the buffer layer. The merged layer is formed by depositing GaN on the surface of the superlattice layer using a metal-organic chemical vapor deposition process.

2. The method for manufacturing a double heterojunction nitrogen polar surface gallium nitride transistor as described in claim 1, characterized in that, The step of depositing AlN on the upper surface of the substrate to form the buffer layer by metal-organic chemical vapor deposition includes: A 2nm~3nm thick layer of metallic Al is deposited on the substrate; The temperature inside the cavity is set to 900℃~950℃, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylaluminum flow rate is set to 19sccm~21sccm, the cavity pressure is set to 20Toor~30Toor, and AlN is grown in three dimensions at 10nm~20nm. The temperature inside the cavity is set to 1000℃~1050℃, the ammonia flow rate is set to 2400sccm~2600sccm, and AlN is grown in two dimensions at 140nm~160nm to form the buffer layer. The step of depositing multiple periods of AlGaN and GaN layers on the upper surface of the buffer layer using a metal-organic chemical vapor deposition process to obtain the superlattice layer includes: The temperature inside the cavity is set to 1000℃~1050℃, the pressure is set to 30Toor~40Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 19sccm~21sccm, the trimethylaluminum flow rate is set to 9sccm~11sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. An AlGaN layer with a thickness of 3.6nm~4.4nm is deposited on the upper surface of the buffer layer. The temperature inside the cavity is set to 1000℃~1050℃, the pressure is set to 30Toor~40Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 45sccm~55sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A GaN layer with a thickness of 7.2nm~8.8nm is deposited on the surface of the AlGaN layer. The temperature inside the cavity is set to 1000℃~1050℃, the pressure is set to 30Toor~40Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 19sccm~21sccm, the trimethylaluminum flow rate is set to 9sccm~11sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. An AlGaN layer with a thickness of 3.6nm~4.4nm is deposited on the upper surface of the GaN layer. The temperature inside the cavity is set to 1000℃~1050℃, the pressure is set to 30Toor~40Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 45sccm~55sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A GaN layer with a thickness of 7.2nm~8.8nm is deposited on the surface of the AlGaN layer. The process is repeated 13 times, setting the temperature inside the cavity to 1000℃~1050℃, the pressure to 30Toor~40Toor, the ammonia flow rate to 1900sccm~2100sccm, the trimethylgallium flow rate to 19sccm~21sccm, the trimethylaluminum flow rate to 9sccm~11sccm, and the carrier gas flow rate to 1900sccm~2100sccm, to deposit an AlGaN layer with a thickness of 3.6nm~4.4nm on the upper surface of the GaN layer, thereby obtaining the superlattice layer. The step of depositing the merged layer on the surface of the superlattice layer using a metal-organic chemical vapor deposition process includes: The temperature inside the cavity is set to 1000℃~1050℃, the pressure is set to 25Toor~35Toor, the ammonia flow rate is set to 1400sccm~1600sccm, the trimethylgallium flow rate is set to 45sccm~55sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A merging layer with a thickness of 90nm~110nm is deposited on the superlattice layer.

3. The method for manufacturing a double heterojunction nitrogen polar surface gallium nitride transistor as described in claim 1, characterized in that, The step of forming a barrier layer, a channel layer, a potential barrier layer, a support layer, a bonding layer, and a substrate layer stacked sequentially from bottom to top on the upper surface of the merged layer to obtain an initial crystal includes: The barrier layer is formed by depositing AlGaN on the surface of the merged layer using a metal-organic chemical vapor deposition process. The channel layer is formed by depositing GaN on the upper surface of the barrier layer using a metal-organic chemical vapor deposition process. The barrier layer is formed by depositing AlGaN on the upper surface of the channel layer using a metal-organic chemical vapor deposition process. The support layer is formed by depositing p-GaN on the surface of the barrier layer using a metal-organic chemical vapor deposition process. The bonding layer is formed by depositing Sn / In on the upper surface of the support layer using a physical vapor deposition process. The substrate layer is formed by bonding Si, Al2O3, or SiC to the surface of the bonding layer using a wafer bonding process.

4. The method for manufacturing a double heterojunction nitrogen polar surface gallium nitride transistor as described in claim 3, characterized in that, The step of depositing AlGaN on the surface of the merged layer to form the barrier layer by metal-organic chemical vapor deposition includes: The temperature of the cavity is set to 1000℃~1050℃, the pressure is set to 20Toor~30Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 19sccm~21sccm, the trimethylaluminum flow rate is set to 4.5sccm~5.5sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. An AlGaN layer with a thickness of 10nm~20nm is deposited on the upper surface of the merging layer to form the barrier layer. The step of depositing the trench layer on the upper surface of the barrier layer using a metal-organic chemical vapor deposition process includes: The temperature of the cavity is set to 1000℃~1050℃, the pressure is set to 20Toor~30Toor, the ammonia flow rate is set to 2700sccm~3300sccm, the trimethylgallium flow rate is set to 19sccm~21sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A GaN layer with a thickness of 30nm~40nm is deposited on the upper surface of the barrier layer to form the channel layer. The step of depositing the barrier layer on the upper surface of the channel layer using a metal-organic chemical vapor deposition process includes: The temperature of the cavity is set to 1000℃~1100℃, the pressure is set to 25Toor~30Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 45sccm~55sccm, the trimethylaluminum flow rate is set to 9sccm~11sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. An AlGaN layer with a thickness of 18nm~22nm is deposited on the upper surface of the channel layer to form the barrier layer. The step of depositing p-GaN on the surface of the barrier layer to form the support layer by metal-organic chemical vapor deposition includes: The temperature of the cavity is set to 1000℃~1050℃, the pressure is set to 25Toor~30Toor, the ammonia flow rate is set to 1900sccm~2100sccm, the trimethylgallium flow rate is set to 72sccm~88sccm, the magnesia-dicenocene flow rate is set to 0.09sccm~0.11sccm, and the carrier gas flow rate is set to 1900sccm~2100sccm. A 1.8um~2.2um thick layer of p-GaN is deposited on the upper surface of the barrier layer to form the support layer.

5. The method for manufacturing a double heterojunction nitrogen polar surface gallium nitride transistor as described in claim 1, characterized in that, The steps of forming an ohmic contact region on the upper surface of the passivation layer, etching the barrier layer and the passivation layer at the ohmic contact region, and fabricating a drain electrode and a source electrode within the ohmic contact region include: A layer of photoresist is deposited on the upper surface of the passivation layer; Etching removes the photoresist at the first preset location to form the ohmic contact area; Etch the barrier layer and the passivation layer at the ohmic contact area to expose the corresponding channel layer; 9 nm Ti, 100 nm Al, 30 nm Ni and 50 nm Au are sequentially deposited in the ohmic contact region by vacuum evaporation process. Annealing at 750℃~850℃ for 25s~35s in an annealing furnace forms the drain electrode and the source electrode.

6. The method for manufacturing a double heterojunction nitrogen polar surface gallium nitride transistor as described in claim 1, characterized in that, The steps of forming a Schottky contact region on the upper surface of the passivation layer, etching the passivation layer at the Schottky contact region, and fabricating a gate electrode within the Schottky contact region include: A layer of photoresist is deposited on the passivation layer; Etching removes the photoresist at the second preset location to form the Schottky contact area; Etch the passivation layer at the corresponding Schottky contact area to expose the corresponding barrier layer; Ni of 18 nm to 22 nm and Au of 90 nm to 110 nm are sequentially deposited in the Schottky contact region by vacuum evaporation process. The gate electrode is formed by annealing at 650℃~750℃ for 25s~35s in an annealing furnace.

7. A double heterojunction nitrogen polar surface gallium nitride transistor, characterized in that, The dual heterojunction nitrogen-polarized gallium nitride transistor is manufactured by any one of claims 1 to 6, comprising, from bottom to top, a substrate layer, a bonding layer, a support layer, a barrier layer, a channel layer made of GaN, and a barrier layer made of AlGaN, wherein the support layer is made of p-GaN, the nitrogen-polarized surface of the channel layer faces upward, and a gate electrode and a source electrode and a drain electrode forming an ohmic contact with the channel layer are disposed above the channel layer, the source electrode and the drain electrode are respectively located on opposite sides of the channel layer, the two sides of the barrier layer are respectively connected to the source electrode and the drain electrode, the gate electrode is located between the source electrode and the drain electrode and is disposed on the barrier layer, a Schottky contact is formed between the gate electrode and the barrier layer, and a passivation layer made of SiN is formed between the gate electrode and the source electrode and between the gate electrode and the drain electrode, the passivation layer being stacked above the barrier layer.

8. The double heterojunction nitrogen polar surface gallium nitride transistor as described in claim 7, characterized in that, The substrate layer is made of Si, Al2O3, or SiC; and / or, The bonding layer is made of SnIn; and / or, The barrier layer is made of AlGaN.

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