GaAs device structure based on electron beam direct writing T-type gate and its preparation method and GaAs device

Abstract

The invention discloses a GaAs device structure based on electron beam direct writing T-type gate, a preparation method thereof and a GaAs device, the structure comprises a GaAs substrate and a T-type gate, a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer, an n-AlGaN charge layer and a silicon-doped GaAs cap layer are sequentially grown on the GaAs substrate from bottom to top, a window is opened in the silicon-doped GaAs cap layer, and the T-type gate is arranged on the n-AlGaN charge layer through the window. The preparation method comprises preparing the above-mentioned film layers and the T-type gate on a GaAs substrate. In the present invention, the work function of each film layer is well matched with the substrate, which is conducive to reducing capacitance, improving carrier mobility and radio frequency characteristics, and can effectively realize the high-frequency properties of GaAs-based devices. The preparation method has the advantages of simple process, easy operation, precise and controllable graphic size, etc., and is compatible with traditional processes.

Description

Technical Field

[0001] The invention belongs to the field of micro-nano processing of semiconductor devices, and relates to a GaAs device structure based on electron beam direct writing T-type gate, a preparation method thereof and a GaAs device. Background Art

[0002] Gallium-source semiconductor devices represented by T-type gate have very strong application value in the fields of high electron mobility transistor devices, photodetectors, laser generators, infrared detectors, high-frequency microwave devices, etc. due to their high preparation precision, few sidewall defects, higher carrier mobility and lower permittivity.

[0003] For GaAs-based devices, due to the difference in lattice constants between GaAs and InGaAs, the interface damage and work function mismatch caused by the growth of each film layer on the interface will lead to lattice mismatch and large dislocation density of the interface layer, and the surface film layer quality is not high. In addition, the InGaAs layer is subjected to a certain tensile stress of the GaAs layer. If the growth film thickness exceeds a certain range, surface defects or Ga element desorption will occur. Therefore, it is very necessary to obtain a GaAs device structure with the required film thickness for high carrier mobility devices and a good match between the work function of each film layer and the substrate, and there is great difficulty. For the GaAs device structure with a T-type gate structure, obtaining a T-type gate with a small gate line width, low sidewall roughness, and good gate film thickness uniformity is the key to obtaining high-performance GaAs-based devices. However, the existing GaAs device structure still has defects such as large T-type gate line width, poor process stability, and many sidewall particles, so it is difficult to improve the performance of GaAs devices, which is not conducive to widespread application in high-frequency devices. In addition, in order to obtain a T-type gate with a smaller line width, photolithography is an indispensable process. However, the minimum line width that can be achieved by traditional photolithography is about 1μm, which cannot meet the requirements of high-frequency devices. Usually, for high-frequency devices, the gate foot size of the T-type gate is generally below 250nm. In addition, unlike optical lithography, although the electron beam spot used by the electron beam lithography machine as a light source can minimize the optical diffraction effect to obtain a smaller gate foot, the existing electron beam direct writing process usually uses a smaller electron beam current (less than 40pA), and it is difficult to obtain a T-type gate with a smaller line width. At the same time, the T-type gate prepared in the existing electron beam direct writing process still has defects such as poor side wall thickness uniformity, high surface roughness and high interface defect density. As a result, it is difficult to effectively reduce leakage loss and obtain a larger carrier mobility. Therefore, obtaining a GaAs device structure with small line width, good sidewall thickness uniformity, low surface roughness, and low defect density and a matching preparation method are of great significance for reducing the capacitance of GaAs devices, improving the carrier mobility and radio frequency characteristics of GaAs devices, and realizing the high-frequency properties of GaAs devices. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a GaAs device structure based on electron beam direct writing T-gate with small line width, good side wall thickness uniformity, low surface roughness and low defect density, a preparation method thereof and a GaAs device.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions.

[0006] A GaAs device structure based on electron beam direct writing T-type gate comprises a GaAs substrate and a T-type gate; a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer, an n-AlGaN charge layer and a silicon-doped GaAs cap layer are sequentially grown on the GaAs substrate from bottom to top; a window is opened in the silicon-doped GaAs cap layer, and the T-type gate is arranged on the n-AlGaN charge layer through the window.

[0007] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved in that the GaAs substrate has a (111) crystal orientation or a (100) crystal orientation; and the diameter of the GaAs substrate is 4 inches to 8 inches.

[0008] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, wherein the thickness of the GaAs buffer layer is 400nm to 650nm; the defect density of the GaAs buffer layer is less than 150 / cm 2 ; The surface roughness of the GaAs buffer layer is less than 15nm.

[0009] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, the thickness of the AlGaAs two-dimensional electron gas layer is 5nm to 8nm; the defect density of the AlGaAs two-dimensional electron gas layer is less than 100 / cm 2 ; The surface roughness of the AlGaAs two-dimensional electron gas layer is less than 2nm.

[0010] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved in that the thickness of the AlGaAs spacer layer is 6nm-10nm; and the surface roughness of the AlGaAs spacer layer is less than 2nm.

[0011] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, wherein the thickness of the n-AlGaN charge layer is 30nm to 50nm; the carrier mobility of the n-AlGaN charge layer is 6×10 17 / cm 3 ~5×10 18 / cm 3; The surface roughness of the n-AlGaN charge layer is less than 4nm.

[0012] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, wherein the thickness of the silicon-doped GaAs cap layer is 45nm-70nm; the carrier mobility of the silicon-doped GaAs cap layer is 5×10 16 / cm 3 ~9×10 17 / cm 3 ; The surface roughness of the silicon-doped GaAs cap layer is less than 6nm.

[0013] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, wherein the T-gate is a Ti / Ni / Au electrode; the Ti / Ni / Au electrode is a titanium layer, a nickel layer, and a gold layer from bottom to top; the thickness of the titanium layer is 90nm to 110nm; the thickness of the nickel layer is 195nm to 205nm; the thickness of the gold layer is 0.9μm to 1.2μm.

[0014] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, wherein the GaAs device structure also includes a source and a drain; the source and the drain are arranged on the silicon-doped GaAs cap layer; the source is AlSiCu with a thickness of 5μm; the drain is AlSiCu with a thickness of 5μm.

[0015] As a general technical concept, the present invention also provides a GaAs device structure based on electron beam direct writing T-type gate, including a GaAs substrate and a T-type gate; a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer and a silicon-doped GaAs cap layer are grown on the GaAs substrate from bottom to top; and the T-type gate is arranged on the silicon-doped GaAs cap layer.

[0016] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved in that the GaAs substrate has a (111) crystal orientation or a (100) crystal orientation; and the diameter of the GaAs substrate is 4 inches to 8 inches.

[0017] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, wherein the thickness of the GaAs buffer layer is 400nm to 650nm; the defect density of the GaAs buffer layer is less than 150 / cm 2 ; The surface roughness of the GaAs buffer layer is less than 15nm.

[0018] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, the thickness of the AlGaAs two-dimensional electron gas layer is 5nm to 8nm; the defect density of the AlGaAs two-dimensional electron gas layer is less than 100 / cm 2 ; The surface roughness of the AlGaAs two-dimensional electron gas layer is less than 2nm.

[0019] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved in that the thickness of the AlGaAs spacer layer is 6nm-10nm; and the surface roughness of the AlGaAs spacer layer is less than 2nm.

[0020] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, wherein the thickness of the silicon-doped GaAs cap layer is 45nm-70nm; the carrier mobility of the silicon-doped GaAs cap layer is 5×10 16 / cm 3 ~9×10 17 / cm 3 ; The surface roughness of the silicon-doped GaAs cap layer is less than 6nm.

[0021] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, wherein the T-gate is a Ti / Ni / Au electrode; the Ti / Ni / Au electrode is a titanium layer, a nickel layer, and a gold layer from bottom to top; the thickness of the titanium layer is 90nm to 110nm; the thickness of the nickel layer is 195nm to 205nm; the thickness of the gold layer is 0.9μm to 1.2μm.

[0022] The above-mentioned GaAs device structure based on electron beam direct writing T-gate is further improved, wherein the GaAs device structure also includes a source and a drain; the source and the drain are arranged on the silicon-doped GaAs cap layer; the source is AlSiCu with a thickness of 5μm; the drain is AlSiCu with a thickness of 5μm.

[0023] As a general technical concept, the present invention also provides a method for preparing a GaAs device structure based on electron beam direct writing of a T-gate, comprising the following steps:

[0024] S1. growing a GaAs buffer layer on a GaAs substrate;

[0025] S2, growing an AlGaAs two-dimensional electron gas layer on the GaAs buffer layer;

[0026] S3, growing an AlGaAs spacer layer on the AlGaAs two-dimensional electron gas layer;

[0027] S4, growing an n-AlGaN charge layer on the AlGaAs spacer layer;

[0028] S5, growing a silicon-doped GaAs cap layer on the n-AlGaN charge layer;

[0029] S6, coating a photoresist on the silicon-doped GaAs cap layer;

[0030] S7, directly writing the photoresist by electron beam exposure to form a T-shaped structure on the n-AlGaN charge layer;

[0031] S8. Prepare a T-type gate in the T-type structure on the n-AlGaN charge layer to complete the preparation of the GaAs device structure. The above preparation method is further improved. In step S1, a GaAs buffer layer is grown on a GaAs substrate by molecular beam epitaxy or metal organic chemical vapor deposition. The preparation process of the GaAs buffer layer is as follows: the GaAs substrate is placed in a vacuum reaction chamber, heated to 420°C to 440°C, the As beam source furnace baffle is opened and the baffle opening angle is maintained at 47° to 50°, the temperature is raised to 750°C to 770°C, the Ga beam source furnace is opened and the baffle opening angle is maintained at 57° to 60°, and the temperature is maintained for 30min to 42min to obtain a GaAs buffer layer. The GaAs substrate also includes the following treatment before use: the surface of the GaAs substrate is cleaned in a He atmosphere to remove surface moisture, impurities and particles.

[0032] The above preparation method is further improved, in step S2, an AlGaAs two-dimensional electron gas layer is grown on a GaAs buffer layer by molecular beam epitaxy; the preparation process of the AlGaAs two-dimensional electron gas layer is as follows: a GaAs substrate on which a GaAs buffer layer is grown is placed in a vacuum reaction chamber, the temperature is raised to 600°C to 620°C, the As beam source furnace baffle is opened and the baffle opening angle is maintained at 35°, the temperature is raised to 690°C to 710°C, the Ga beam source furnace is opened and the baffle opening angle is maintained at 30° to 35°, the Al beam source furnace is opened and the baffle opening angle is maintained at 25° to 30°, and the temperature is maintained for 3min to 5min to obtain the AlGaAs two-dimensional electron gas layer.

[0033] The above preparation method is further improved, in step S3, an AlGaAs spacer layer is grown on the AlGaAs two-dimensional electron gas layer by molecular beam epitaxy; the preparation process of the AlGaAs spacer layer is as follows: a GaAs substrate on which an AlGaAs two-dimensional electron gas layer is grown is placed in a vacuum reaction chamber, the temperature is raised to 580°C to 600°C, the As beam source furnace baffle is opened and the baffle opening angle is maintained at 30°, the temperature is continuously raised to 670°C to 690°C, the Ga beam source furnace is opened and the baffle opening angle is maintained at 30°, the Al beam source furnace is opened and the baffle opening angle is maintained at 25°, and the temperature is maintained for 5min to 8min to obtain the AlGaAs spacer layer.

[0034] The above preparation method is further improved, in step S4, a molecular beam epitaxy method is used to grow an n-AlGaN charge layer on the AlGaAs spacer layer; the preparation process of the n-AlGaN charge layer is: placing a GaAs substrate on which an AlGaAs spacer layer is grown in a vacuum reaction chamber, heating to 580°C to 600°C, opening the N beam source furnace baffle and keeping the baffle opening angle at 30°, heating to 670°C to 690°C, opening the Ga beam source furnace and keeping the baffle opening angle at 30°, opening the Al beam source furnace and keeping the baffle opening angle at 25°, keeping for 7min to 11min, and obtaining the n-AlGaN charge layer.

[0035] The above preparation method is further improved, in step S5, a silicon-doped GaAs cap layer is grown on the n-AlGaN charge layer by molecular beam epitaxy; the preparation process of the silicon-doped GaAs cap layer is as follows: a GaAs substrate with an n-AlGaN charge layer grown thereon is placed in a vacuum reaction chamber, the temperature is raised to 420° C. to 440° C., the As beam source furnace baffle is opened and the baffle opening angle is maintained at 50°, the temperature is raised to 750° C. to 770° C., the Ga beam source furnace is opened and the baffle opening angle is maintained at 60°, the Si beam source furnace is opened and the baffle opening angle is maintained at 48°, and the temperature is maintained for 9 min to 15 min to obtain a silicon-doped GaAs cap layer.

[0036] The above preparation method is further improved, in step S6, a photoresist is coated on the window area on the silicon-doped GaAs cap layer by a spin coating method; the preparation process of the photoresist is: a GaAs substrate grown with a silicon-doped GaAs cap layer is placed in a coating machine, a bottom layer photoresist is prepared on the silicon-doped GaAs cap layer at a rotation speed of 4000 rpm to 6000 rpm, an upper layer photoresist is prepared on the bottom layer photoresist at a rotation speed of 4000 rpm to 5200 rpm, and baked at 140° C. to 150° C. for 75s to 90s; the thickness of the bottom layer photoresist is 80nm to 120nm; the bottom layer photoresist is PMMA or polyisoprene; the thickness of the upper layer photoresist is 0.95μm to 1.08μm; the upper layer photoresist is PMMA or polyisoprene.

[0037] The above preparation method is further improved. In step S7, the process parameters of the direct writing are: the electron beam current is 80pA to 140pA, the acceleration voltage is 40kV to 80kV, and the dose is 280uC / cm 2 ~360uC / cm 2 .

[0038] The above-mentioned preparation method is further improved. In step S8, a titanium layer, a nickel layer, and a gold layer are sequentially deposited in a T-shaped structure on the n-AlGaN charge layer by electron beam evaporation or resistance wire evaporation; the deposition process parameters of the metal titanium layer are: an evaporation rate of 3.5A / s to 4.2A / s, and a time of 4min to 5min; the deposition process parameters of the metal nickel layer are: an evaporation rate of 2.5A / s to 3.5A / s, and a time of 11min to 13min; the deposition process parameters of the metal gold layer are: an evaporation rate of 7.5A / s to 8.5A / s, and a time of 20min to 24min; the thickness of the titanium layer is 90nm to 110nm; the thickness of the nickel layer is 195nm to 205nm; the thickness of the gold layer is 0.9μm to 1.2μm; after the preparation of the gold layer is completed, the following treatment is also included: the GaAs substrate with the gold layer deposited thereon is cleaned to remove residual metal and the coating layer to form a T-shaped gate.

[0039] The above preparation method is further improved, and the method also includes the following steps: preparing a drain electrode and a source electrode on the silicon-doped GaAs cap layer.

[0040] The above-mentioned preparation method is further improved, wherein the GaAs device structure comprises a GaAs substrate and a T-type gate; a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer, an n-AlGaN charge layer and a silicon-doped GaAs cap layer are sequentially grown on the GaAs substrate from bottom to top; a window is opened in the silicon-doped GaAs cap layer, and the T-type gate is arranged on the n-AlGaN charge layer through the window;

[0041] The GaAs substrate has a (111) crystal orientation or a (100) crystal orientation; the diameter of the GaAs substrate is 4 inches to 8 inches;

[0042] The thickness of the GaAs buffer layer is 400nm to 650nm; the defect density of the GaAs buffer layer is less than 150 / cm 2 ; The surface roughness of the GaAs buffer layer is less than 15nm;

[0043] The thickness of the AlGaAs two-dimensional electron gas layer is 5nm to 8nm; the defect density of the AlGaAs two-dimensional electron gas layer is less than 100 / cm 2 ; The surface roughness of the AlGaAs two-dimensional electron gas layer is less than 2nm;

[0044] The thickness of the AlGaAs spacer layer is 6nm to 10nm; the surface roughness of the AlGaAs spacer layer is less than 2nm;

[0045] The thickness of the n-AlGaN charge layer is 30nm to 50nm; the carrier mobility of the n-AlGaN charge layer is 6×10 17 / cm 3 ~5×10 18 / cm 3 ; The surface roughness of the n-AlGaN charge layer is less than 4 nm;

[0046] The thickness of the silicon-doped GaAs cap layer is 45nm to 70nm; the carrier mobility of the silicon-doped GaAs cap layer is 5×10 16 / cm 3 ~9×10 17 / cm 3 ; The surface roughness of the silicon-doped GaAs cap layer is less than 6nm;

[0047] The source electrode is AlSiCu with a thickness of 5 μm; the drain electrode is AlSiCu with a thickness of 5 μm.

[0048] As a general technical concept, the present invention also provides a method for preparing a GaAs device structure based on electron beam direct writing of a T-gate, comprising the following steps:

[0049] (1) growing a GaAs buffer layer on a GaAs substrate;

[0050] (2) growing an AlGaAs two-dimensional electron gas layer on a GaAs buffer layer;

[0051] (3) growing an AlGaAs spacer layer on the AlGaAs two-dimensional electron gas layer;

[0052] (4) growing a silicon-doped GaAs cap layer on the AlGaAs spacer layer;

[0053] (5) coating a photoresist on the silicon-doped GaAs cap layer;

[0054] (6) direct writing the photoresist by electron beam exposure to form a T-shaped structure on the silicon-doped GaAs cap layer;

[0055] (7) A T-type gate is prepared in the T-type structure on the silicon-doped GaAs cap layer to complete the preparation of the GaAs device structure.

[0056] The above preparation method is further improved, in step (1), a GaAs buffer layer is grown on a GaAs substrate by molecular beam epitaxy or metal organic chemical vapor deposition; the preparation process of the GaAs buffer layer is as follows: the GaAs substrate is placed in a vacuum reaction chamber, the temperature is raised to 420°C to 440°C, the As beam source furnace baffle is opened and the baffle opening angle is maintained at 47° to 50°, the temperature is raised to 750°C to 770°C, the Ga beam source furnace is opened and the baffle opening angle is maintained at 57° to 60°, and the temperature is maintained for 30min to 42min to obtain the GaAs buffer layer; the GaAs substrate also includes the following treatment before use: the surface of the GaAs substrate is cleaned in a He atmosphere to remove surface moisture, impurities and particles.

[0057] The above preparation method is further improved, in step (2), an AlGaAs two-dimensional electron gas layer is grown on a GaAs buffer layer by molecular beam epitaxy; the preparation process of the AlGaAs two-dimensional electron gas layer is as follows: placing a GaAs substrate on which a GaAs buffer layer is grown in a vacuum reaction chamber, heating the temperature to 600°C to 620°C, opening the baffle of the As beam source furnace and keeping the baffle opening angle at 35°, heating the temperature to 690°C to 710°C, opening the Ga beam source furnace and keeping the baffle opening angle at 30° to 35°, opening the Al beam source furnace and keeping the baffle opening angle at 25° to 30°, and keeping for 3min to 5min to obtain the AlGaAs two-dimensional electron gas layer.

[0058] The above preparation method is further improved, in step (3), an AlGaAs spacer layer is grown on the AlGaAs two-dimensional electron gas layer by molecular beam epitaxy; the preparation process of the AlGaAs spacer layer is as follows: placing a GaAs substrate on which an AlGaAs two-dimensional electron gas layer is grown in a vacuum reaction chamber, heating the temperature to 580°C to 600°C, opening the baffle of the As beam source furnace and keeping the baffle opening angle at 30°, continuously heating the temperature to 670°C to 690°C, opening the Ga beam source furnace and keeping the baffle opening angle at 30°, opening the Al beam source furnace and keeping the baffle opening angle at 25°, and keeping the temperature for 5min to 8min to obtain the AlGaAs spacer layer.

[0059] The above preparation method is further improved, in which in step (4), a silicon-doped GaAs cap layer is grown on the AlGaAs spacer layer by molecular beam epitaxy; the preparation process of the silicon-doped GaAs cap layer is as follows: a GaAs substrate on which the AlGaAs spacer layer is grown is placed in a vacuum reaction chamber, the temperature is raised to 420° C. to 440° C., the baffle of the As beam source furnace is opened and the baffle opening angle is maintained at 50°, the temperature is raised to 750° C. to 770° C., the Ga beam source furnace is opened and the baffle opening angle is maintained at 60°, and the temperature is maintained for 9 min to 15 min to obtain the silicon-doped GaAs cap layer.

[0060] The above preparation method is further improved, in step (5), a photoresist is coated on the silicon-doped GaAs cap layer by a spin coating method; the preparation process of the photoresist is as follows: a GaAs substrate grown with a silicon-doped GaAs cap layer is placed in a spin coating machine, a bottom layer photoresist is prepared on the silicon-doped GaAs cap layer at a rotation speed of 4000 rpm to 6000 rpm, an upper layer photoresist is prepared on the bottom layer photoresist at a rotation speed of 4000 rpm to 5200 rpm, and baked at 140° C. to 150° C. for 75 s to 90 s; the thickness of the bottom layer photoresist is 80 nm to 120 nm; the bottom layer photoresist is PMMA or polyisoprene; the thickness of the upper layer photoresist is 0.95 μm to 1.08 μm; the upper layer photoresist is PMMA or polyisoprene.

[0061] The above preparation method is further improved, in step (6), the process parameters of the direct writing are: electron beam current size is 80pA ~ 140pA, acceleration voltage is 40kV ~ 80kV, dose is 280uC / cm 2 ~360uC / cm 2 .

[0062] The above preparation method is further improved, in step (7), a titanium layer, a nickel layer and a gold layer are sequentially deposited in the T-shaped structure on the silicon-doped GaAs cap layer by electron beam evaporation or resistance wire evaporation; the deposition process parameters of the metal titanium layer are: evaporation rate of 3.5A / s~4.2A / s, time of 4min~5min; the deposition process parameters of the metal nickel layer are: evaporation rate of 2.5A / s~3.5A / s, time of 11min~13min; the deposition process parameters of the metal gold layer are: evaporation rate of 7.5A / s~8.5A / s, time of 20min~24min; the thickness of the titanium layer is 90nm~110nm; the thickness of the nickel layer is 195nm~230nm; the thickness of the gold layer is 0.9μm~1.2μm; after the preparation of the gold layer is completed, the following treatment is also included: the GaAs substrate with the gold layer deposited is cleaned to remove residual metal and coating layer to form a T-shaped gate.

[0063] The above preparation method is further improved, and the method also includes the following steps: preparing a drain electrode and a source electrode on the silicon-doped GaAs cap layer.

[0064] The above preparation method is further improved, wherein the GaAs device structure comprises a GaAs substrate and a T-type gate; a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer and a silicon-doped GaAs cap layer are sequentially grown on the GaAs substrate from bottom to top; and the T-type gate is arranged on the silicon-doped GaAs cap layer;

[0065] The GaAs substrate has a (111) crystal orientation or a (100) crystal orientation; the diameter of the GaAs substrate is 4 inches to 8 inches;

[0066] The thickness of the GaAs buffer layer is 400nm to 650nm; the defect density of the GaAs buffer layer is less than 150 / cm 2 ; The surface roughness of the GaAs buffer layer is less than 15nm;

[0067] The thickness of the AlGaAs two-dimensional electron gas layer is 5nm to 8nm; the defect density of the AlGaAs two-dimensional electron gas layer is less than 100 / cm 2 ; The surface roughness of the AlGaAs two-dimensional electron gas layer is less than 2nm;

[0068] The thickness of the AlGaAs spacer layer is 6nm to 10nm; the surface roughness of the AlGaAs spacer layer is less than 2nm;

[0069] The thickness of the silicon-doped GaAs cap layer is 45nm to 70nm; the carrier mobility of the silicon-doped GaAs cap layer is 5×10 16 / cm 3 ~9×10 17 / cm 3 ; The surface roughness of the silicon-doped GaAs cap layer is less than 6nm;

[0070] The source electrode is AlSiCu with a thickness of 5 μm; the drain electrode is AlSiCu with a thickness of 5 μm.

[0071] As a general technical concept, the present invention also provides a GaAs device, which includes the above-mentioned GaAs device structure; the GaAs device is a T-gate photodetector, a trench T-gate high electron mobility transistor or a T-gate laser generator.

[0072] Compared with the prior art, the advantages of the present invention are:

[0073] (1) In view of the defects of the GaAs device structure, such as the poor matching between the work function of each film layer and the substrate, the present invention creatively proposes a GaAs device structure based on electron beam direct writing T-type gate, including a GaAs substrate and a T-type gate, wherein a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer, an n-AlGaN charge layer and a silicon-doped GaAs cap layer are grown on the GaAs substrate from bottom to top, a window is opened in the silicon-doped GaAs cap layer, and the T-type gate is arranged on the n-AlGaN charge layer through the window. In the present invention, a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer, an n-AlGaN charge layer and a silicon-doped GaAs cap layer are sequentially grown on a GaAs substrate from bottom to top, wherein the GaAs buffer layer has the characteristic of high resistivity and can reduce the substrate carrier concentration to reduce the drain current collapse caused by the buffer layer trap effect; the AlGaAs two-dimensional electron gas layer can be used as a channel to increase the electron concentration and improve the DC efficiency; the AlGaAs spacer layer is used to isolate the supply layer from the buffer layer and reduce the influence of the charge layer ion scattering on the charge mobility and concentration of the two-dimensional electron gas layer channel; the n-AlGaN charge ... drain current collapse caused by the buffer layer trap effect; the AlGaAs two-dimensional electron gas layer can be used as a channel to increase the electron concentration and improve the DC efficiency; the AlGaAs spacer layer is used to isolate the supply layer from the buffer layer and reduce the influence of the charge layer ion scattering on the charge mobility and concentration of the two-dimensional electron gas layer channel; the n-AlGaN charge layer has the characteristic of high resistivity and can reduce the drain current collapse caused by the buffer layer trap effect; the AlGaAs two-dimensional electron gas layer can be used as a channel to increase the electron concentration and improve the DC efficiency; the AlGaAs spacer layer is used to isolate the supply layer from the buffer layer and reduce the influence of the charge layer ion scattering on the charge mobility and concentration of the two-dimensional electron gas layer channel; the n-AlGaN charge layer has the characteristic of high resistivity and high resistivity; the n- The charge layer can also increase the electron concentration of the two-dimensional electron gas layer and improve the DC characteristics. The silicon-doped GaAs cap layer can reduce the collapse of the drain current, maintain the polarization characteristics, and also reduce the gate leakage current and enhance the breakdown voltage. At the same time, the T-type gate is set on the n-AlGaN charge layer through the window, which brings the following benefits: the T-type gate can be closely compounded with the n-AlGaN charge layer and the silicon-doped GaAs cap layer, thereby reducing the interface defects between the T-type gate and the n-AlGaN charge layer and the silicon-doped GaAs cap layer, thereby helping to reduce the problem of device gate leakage and playing the role of gate efficient charge conduction. In the GaAs device structure of the present invention, the work function of each film layer is well matched with the substrate, so the T-type gate is set on the n-AlGaN charge layer through the window, which is conducive to reducing capacitance, improving carrier mobility and radio frequency characteristics, and can effectively realize the high-frequency properties of GaAs-based devices.

[0074] (2) In view of the defects existing in the GaAs device structure, such as the poor matching between the work function of each film layer and the substrate, the present invention creatively proposes a GaAs device structure based on electron beam direct writing of a T-type gate, comprising a GaAs substrate and a T-type gate, wherein a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer and a silicon-doped GaAs cap layer are grown on the GaAs substrate from bottom to top, and the T-type gate is arranged on the GaAs cap layer. In the present invention, a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer and a silicon-doped GaAs cap layer are sequentially grown on a GaAs substrate from bottom to top, wherein the GaAs buffer layer has the characteristic of high resistivity and can reduce the substrate carrier concentration to reduce the drain current collapse caused by the buffer layer trap effect; the AlGaAs two-dimensional electron gas layer as a channel can increase the electron concentration and improve the DC efficiency; the AlGaAs spacer layer is used to isolate the supply layer and the buffer layer and reduce the influence of the charge mobility and concentration of the two-dimensional electron gas layer channel caused by the charge layer ion scattering; the silicon-doped GaAs cap layer can reduce the drain current collapse and maintain the polarization characteristics, and can also reduce the gate leakage current and enhance the breakdown voltage; on this basis, a T-type gate is arranged on the silicon-doped GaAs cap layer, which brings the following benefits: the T-type gate and the silicon-doped GaAs cap layer can be closely compounded together, thereby reducing the interface defects between the T-type gate and the silicon-doped GaAs cap layer, thereby facilitating the reduction of the device gate leakage problem and playing the role of gate efficient charge conduction. In the GaAs device structure of the present invention, the work function of each film layer matches the substrate well, so the T-type gate is arranged on the silicon-doped GaAs cap layer, which is conducive to reducing capacitance, improving carrier mobility and radio frequency characteristics, and can effectively realize the high-frequency properties of the GaAs device. In addition, the GaAs device structure of the present invention is simpler, so it is more conducive to obtaining a GaAs-based device with a simple structure and excellent performance.

[0075] (3) In view of the defects that it is difficult to obtain a GaAs device structure with a small line width, good sidewall thickness uniformity, low surface roughness, and low defect density in the preparation method of the GaAs device structure, the present invention creatively proposes a preparation method of a GaAs device structure based on electron beam direct writing T-type gate, firstly growing a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer, an n-AlGaN charge layer, and a silicon-doped GaAs cap layer on a GaAs substrate from bottom to top, thereby improving the matching of the work function of each film layer with the substrate, and on this basis, exposing the photoresist on the silicon-doped GaAs cap layer by electron beam exposure, thereby forming a T-type structure on the n-AlGaN charge layer with the advantages of small line width, low surface roughness, etc., and further, a T-type gate is formed in the T-type structure on the n-AlGaN charge layer, thereby preparing a GaAs device structure with a small line width, good sidewall thickness uniformity, low surface roughness, and few interface defects. In addition, the preparation method of the present invention has the advantages of simple process, easy operation, precise and controllable graphic size, etc. At the same time, the preparation method of the present invention is compatible with the traditional planar Si-based device process, so the existing production line can be effectively utilized to complete production, which is conducive to further reducing the preparation cost and is more suitable for promotion and application.

[0076] (4) In view of the defects that it is difficult to obtain a GaAs device structure with a small line width, good sidewall thickness uniformity, low surface roughness, and low defect density in the preparation method of the GaAs device structure, the present invention creatively proposes a preparation method of a GaAs device structure based on electron beam direct writing of a T-type gate. First, a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer, and a silicon-doped GaAs cap layer are sequentially grown on a GaAs substrate from bottom to top, thereby improving the matching of the work function of each film layer with the substrate. On this basis, an electron beam exposure method is used to expose the photoresist on the silicon-doped GaAs cap layer, thereby forming a T-type structure on the silicon-doped GaAs cap layer with the advantages of small line width and low surface roughness. Furthermore, a T-type gate is formed in the T-type structure on the silicon-doped GaAs cap layer, thereby preparing a GaAs device structure with a small line width, good sidewall thickness uniformity, low surface roughness, and few interface defects. In addition, the preparation method of the present invention has the advantages of simple process, easy operation, precise and controllable graphic size, etc. At the same time, the preparation method of the present invention is compatible with the traditional planar Si-based device process, so the existing production line can be effectively utilized to complete production, which is conducive to further reducing the preparation cost and is more suitable for promotion and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] In order to make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0078] Figure 1 Schematic diagram of the structure of a GaAs device based on electron beam direct writing of a T-gate in Example 1 of the present invention.

[0079] Figure 2 Schematic diagram of the process flow for preparing a GaAs device structure based on electron beam direct writing of a T-gate in Example 1 of the present invention.

[0080] Figure 3a-3b This is a comparison diagram of the T-type gate structure line width at different electron beam currents in Example 1 of the present invention.

[0081] Figure 4a-4b This is a comparison chart of the roughness of the T-type gate structure at different electron beam current sizes in Example 1 of the present invention.

[0082] Figure 5a-5b This is a comparison chart of the defect density of the T-type gate structure at different electron beam current sizes in Example 1 of the present invention.

[0083] Figure 6 Schematic diagram of the structure of a GaAs device based on electron beam direct writing of a T-gate in Example 2 of the present invention.

[0084] Legend:

[0085] 1. GaAs substrate; 2. GaAs buffer layer; 3. AlGaAs two-dimensional electron gas layer; 4. AlGaAs spacer layer; 5. n-AlGaN charge layer; 6. Silicon-doped GaAs cap layer; 7. T-type gate; 8. Source; 9. Drain. DETAILED DESCRIPTION

[0086] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0087] The materials and instruments used in the following examples are all commercially available.

[0088] Embodiment 1:

[0089] like Figure 1 As shown, a GaAs device structure based on electron beam direct writing T-type gate includes a GaAs substrate 1 and a T-type gate 7. A GaAs buffer layer 2, an AlGaAs two-dimensional electron gas layer 3, an AlGaAs spacer layer 4, an n-AlGaN charge layer 5 and a silicon-doped GaAs cap layer 6 are sequentially grown on the surface of the GaAs substrate 1 from bottom to top. A window is opened in the silicon-doped GaAs cap layer 6, and the T-type gate 7 is arranged on the n-AlGaN charge layer 5 through the window.

[0090] In this embodiment, the GaAs substrate 1 used has a (100) crystal orientation and a diameter of 6 inches.

[0091] In this embodiment, the thickness of the GaAs buffer layer 2 used is 455 nm, and the defect density is 140 / cm 2 , the surface roughness is 12nm; in the present invention, by optimizing the thickness, defect density and surface roughness of the GaAs buffer layer, the lattice mismatch problem can be reduced and the interface tension caused by the mismatch can be reduced.

[0092] In this embodiment, the thickness of the AlGaAs two-dimensional electron gas layer 3 used is 7 nm, and the defect density is 95 / cm 2 , the surface roughness is 1.5nm, and the carrier concentration is 5×10 17 / cm 3 In the present invention, by optimizing the thickness, defect density, and surface roughness of the AlGaAs two-dimensional electron gas layer, dislocations and stress defects can be reduced, and the DC efficiency can be improved.

[0093] In this embodiment, the thickness of the AlGaAs spacer layer 4 used is 9 nm, and the surface roughness is 1.5 nm. In the present invention, by optimizing the thickness and surface roughness of the AlGaAs spacer layer, the influence of defects on the uniformity of channel concentration can be effectively reduced.

[0094] In this embodiment, the thickness of the n-AlGaN charge layer 5 used is 45 nm, and the carrier mobility is 8×10 17 / cm 3 , and the surface roughness is 3.5nm; in the present invention, the uniformity of the DC characteristics can be improved by optimizing the thickness, carrier mobility, and surface roughness of the n-AlGaN charge layer.

[0095] In this embodiment, the thickness of the silicon-doped GaAs cap layer 6 is 57 nm, and the carrier mobility is 8.5×10 16 / cm 3 , the surface roughness is 5.5nm; in the present invention, by optimizing the thickness, carrier mobility and surface roughness of the silicon-doped GaAs cap layer, the leakage current is reduced and the average value of the breakdown voltage is increased.

[0096] In this embodiment, the T-type gate 7 used is a Ti / Ni / Au electrode, and the Ti / Ni / Au electrode is composed of a titanium layer, a nickel layer, and a gold layer from bottom to top, wherein the thickness of the titanium (Ti) layer is 105nm, the thickness of the nickel (Ni) layer is 195nm, and the thickness of the gold (Au) layer is 0.9μm; in the present invention, by optimizing the thickness of the metal layer in the Ti / Ni / Au electrode, the work function matching advantage is made more obvious, and the gate leakage current is effectively suppressed.

[0097] In this embodiment, the GaAs device structure further includes a source 8 and a drain 9, which are arranged on the silicon-doped GaAs cap layer 6, wherein the source 8 is AlSiCu with a thickness of 5 μm, and the drain 9 is AlSiCu with a thickness of 5 μm.

[0098] A method for preparing the GaAs device structure in the present embodiment, the preparation process flow chart is as follows: Figure 2 As shown, the specific example is a 6-inch <100> The GaAs substrate with 3 mm edge removal is prepared by molecular beam epitaxy, electron beam exposure and electron beam evaporation, including the following steps:

[0099] (1) The GaAs substrate substrate after edge removal was transferred to the molecular beam epitaxy buffer chamber in vacuum, and the secondary surface cleaning was performed for 5 min in a He atmosphere to remove surface moisture, impurities and particles. After the cleaning was completed, it was transferred to the molecular beam epitaxy vacuum reaction chamber by a non-destructive semi-automatic method. The chamber was heated from room temperature to 430 °C, and the vacuum degree reached 5×10 -8 After Pa, the As beam source furnace baffle was opened and the baffle opening angle was maintained at 50°, and the temperature was continuously raised to 750°C. The Ga beam source furnace was opened and the baffle opening angle was maintained at 60°. After the process was continued for 35 minutes, a GaAs buffer layer with a thickness of 455nm was obtained. The As and Ga beam source furnace baffles were closed, and the reaction chamber temperature was reduced to 360°C.

[0100] (2) The vacuum reaction chamber was heated to 620°C, the baffle of the As beam source furnace was opened and the baffle opening angle was maintained at 35°, and the temperature was continuously raised to 690°C. The Ga beam source furnace was opened and the baffle opening angle was maintained at 35°, and the Al beam source furnace was opened and the baffle opening angle was maintained at 25°. The process was continued for 4 min to obtain an AlGaAs two-dimensional electron gas layer with a thickness of 7 nm and a carrier concentration of 5×10 17 / cm 3 , close the As, Ga, and Al beam source furnace baffles and lower the reaction chamber temperature to 360°C.

[0101] (3) The vacuum reaction chamber was heated to 600°C, the baffle of the As beam source furnace was opened and the baffle opening angle was maintained at 30°, and the temperature was continuously raised to 680°C. The Ga beam source furnace was opened and the baffle opening angle was maintained at 30°. The Al beam source furnace was opened and the baffle opening angle was maintained at 25°. The process was continued for 7 minutes to obtain an AlGaAs spacer layer with a thickness of 9 nm. The baffles of the N, Ga, and Al beam source furnaces were closed.

[0102] (4) The temperature of the vacuum reaction chamber was lowered to 585°C, the damper of the N beam source furnace was opened and the damper opening angle was maintained at 30°, and the temperature was continuously raised to 675°C. The Ga beam source furnace was opened and the damper opening angle was maintained at 30°. The Al beam source furnace was opened and the damper opening angle was maintained at 25°. The process was continued for 10 minutes to obtain an AlGaN charge layer with a thickness of 45 nm. The dampers of the N, Ga, and Al beam source furnaces were closed, and the temperature of the reaction chamber was lowered to 350°C.

[0103] (5) The vacuum reaction chamber was heated from 350°C to 440°C, the As beam source furnace baffle was opened and the baffle opening angle was maintained at 50°, and the temperature was continuously raised to 765°C. The Ga beam source furnace was opened and the baffle opening angle was maintained at 60°. The process was continued for 12 minutes to obtain a doped GaAs cap layer with a thickness of 57 nm. The As and Ga beam source furnace baffles were closed, and the reaction chamber temperature was reduced to 350°C.

[0104] (6) Take out the substrate after the above epitaxial step, put it into a special electron beam direct writing coating machine, adjust the coating speed to 4500 rpm, the spin coating time to 20 seconds, prepare a bottom layer photoresist with a thickness of 100 nm on the silicon-doped GaAs cap layer, adjust the coating speed to 4200 rpm, the spin coating time to 180 seconds, prepare an upper layer photoresist with a thickness of 0.95 μm on the bottom layer photoresist; the photoresist material is PMMA. Put the substrate after spin coating on a hot plate at 150°C and bake for 90 seconds.

[0105] (7) Place the substrate after coating in an electron beam exposure machine with an electron beam current of 120 pA, an acceleration voltage of 60 kV, and a dose of 300 uC / cm 2 , directly write the photoresist to form a T-shaped structure on the n-AlGaN charge layer, and the minimum line width of the T-shaped structure is 30nm. In this step, the maximum output can reach 10 pieces / hour. The conventional process has a maximum output of 6 pieces / hour.

[0106] (8) Placing the substrate after electron beam exposure and development in an electron beam evaporation device, and sequentially depositing a titanium layer, a nickel layer, and a gold layer in a T-shaped structure on the n-AlGaN charge layer, wherein the evaporation rate of the deposited metal Ti is controlled at 3.5A / s, the time is 5 minutes, and the thickness is 105nm; the evaporation rate of Ni is controlled at 2.5A / s, the time is 13 minutes, and the thickness is 195nm; the evaporation rate of Au is controlled at 7.5A / s, the time is 20 minutes, and the thickness is 0.9μm. After the preparation of the gold layer is completed, the following treatment is also included: cleaning the GaAs substrate substrate with the gold layer deposited, removing the residual metal and the coating layer, and forming a T-shaped gate on the n-AlGaN charge layer.

[0107] (9) The drain and source are prepared on the silicon-doped GaAs cap layer by PVD sputtering, wherein the source is AlSiCu with a thickness of 5 μm, and the drain is AlSiCu with a thickness of 5 μm.

[0108] After testing, the minimum line width of the T-type gate structure prepared in this embodiment is 30nm, the uniformity of the side wall film thickness is about 5%, the surface roughness is 4nm, and the surface defect density before metal deposition is 90 / cm 2 , the sample has no jagged cracks or hole defects on the side wall before filling the metal electrode, and the surface is smooth.

[0109] A GaAs device, specifically a GaAs high electron mobility transistor including the GaAs device structure in the present embodiment. After testing, the noise coefficient of the GaAs high electron mobility transistor is at least 0.7dB (under 20GHZ) and the maximum source-gate leakage current is 50uA, while the noise coefficient of the existing conventional GaAs high electron mobility transistor is at least 1dB (under 20GHZ) and the maximum source-gate leakage current is 80uA. The reason is that the conventional GaAs high electron mobility transistor cannot reduce parasitic effects as in the present application, improve the depth-to-width ratio of the device gate structure in the vertical direction, reduce the generation of short channel effects and leakage current, and improve radio frequency characteristics.

[0110] In this embodiment, the influence of different electron beam current magnitudes on the T-type gate structure is also investigated. Except for the different electron beam current magnitudes, other conditions are the same as those in Embodiment 1. The results are shown in FIGS. 3-5 .

[0111] FIG3 is a graph showing the comparison of the line width of the T-type gate structure with different electron beam currents in Example 1 of the present invention. Figure 3a It can be seen that when the electron beam current is 95pA, the average line width of the prepared T-type gate structure is 40nm, and the uniformity is good; Figure 3b It can be seen that when the electron beam current is 35pA, the average line width of the prepared T-type gate structure is 70nm, and the uniformity is poor, which shows that increasing the electron beam current is conducive to obtaining a T-type gate structure with a smaller line width.

[0112] FIG4 is a comparison diagram of the roughness of the T-type grid structure with different electron beam currents in Example 1 of the present invention. Figure 4a It can be seen that when the electron beam current is 95pA, the surface roughness of the prepared T-type gate structure is less than 3nm; Figure 4b It can be seen that when the electron beam current is 35 pA, the surface roughness of the prepared T-type gate structure is less than 100 nm, which shows that increasing the electron beam current is conducive to obtaining a T-type gate structure with lower surface roughness.

[0113] FIG5 is a comparison chart of the defect density of the T-type gate structure with different electron beam currents in Example 1 of the present invention. Figure 5a It can be seen that when the electron beam current is 95pA, the number of defects in the prepared T-type gate structure is 74 / cm 2 ; and by Figure 5b It can be seen that when the electron beam current is 35pA, the number of defects in the prepared T-type gate structure is 349 / cm 2 This shows that increasing the electron beam current is more conducive to obtaining a T-type gate structure with fewer defects.

[0114] It can be seen from the above results that in the GaAs device structure of the present invention, the work function of each film layer is well matched with the substrate, so setting the T-type gate through the window on the n-AlGaN charge layer is beneficial to reducing capacitance, improving carrier mobility and radio frequency characteristics, and can effectively realize the high-frequency properties of GaAs-based devices.

[0115] Embodiment 2:

[0116] like Figure 6 As shown, a GaAs device structure based on electron beam direct writing T-type gate includes a GaAs substrate 1 and a T-type gate 7. A GaAs buffer layer 2, an AlGaAs two-dimensional electron gas layer 3, an AlGaAs spacer layer 4 and a silicon-doped GaAs cap layer 6 are grown in sequence from bottom to top on the surface of the GaAs substrate 1, and the T-type gate 7 is arranged on the silicon-doped GaAs cap layer 6.

[0117] In this embodiment, the GaAs substrate 1 used has a (100) crystal orientation and a diameter of 4 inches.

[0118] In this embodiment, the thickness of the GaAs buffer layer 2 used is 4575 nm, and the defect density is 130 / cm 2 , the surface roughness is 11nm.

[0119] In this embodiment, the thickness of the AlGaAs two-dimensional electron gas layer 3 used is 8 nm, and the defect density is less than 86 / cm 2 , the surface roughness is less than 1.8nm.

[0120] In this embodiment, the thickness of the AlGaAs spacer layer 4 used is 10 nm, and the surface roughness is less than 1.9 nm.

[0121] In this embodiment, the thickness of the silicon-doped GaAs cap layer 6 is 50 nm, and the carrier mobility is 9.5×10 16 / cm 3 , the surface roughness is less than 5.7nm.

[0122] In this embodiment, the T-type gate 7 used is a Ti / Ni / Au electrode, which is composed of a titanium layer, a nickel layer, and a gold layer from bottom to top, wherein the thickness of the titanium (Ti) layer is 96nm, the thickness of the nickel (Ni) layer is 230nm, and the thickness of the gold (Au) layer is 0.9μm.

[0123] In this embodiment, the GaAs device structure further includes a source 8 and a drain 9, which are arranged on the silicon-doped GaAs cap layer 6, wherein the source 8 is AlSiCu with a thickness of 5 μm, and the drain 9 is AlSiCu with a thickness of 5 μm.

[0124] A method for preparing the GaAs device structure in the present embodiment, specifically using a 4-inch <100> The GaAs substrate is prepared by molecular beam epitaxy, electron beam exposure and electron beam evaporation, including the following steps:

[0125] (1) The GaAs substrate substrate after edge removal was transferred to the molecular beam epitaxy buffer chamber in vacuum, and the secondary surface cleaning was performed for 5 min in a He atmosphere to remove surface moisture, impurities and particles. After the cleaning was completed, the substrate substrate was transferred to the molecular beam epitaxy vacuum reaction chamber by a semi-automatic method. The chamber was heated from room temperature to 440°C, and the vacuum degree was 3×10 -8 Pa, open the As beam source furnace baffle and keep the baffle opening angle at 48°, continue to heat up to 770°C, open the Ga beam source furnace and keep the baffle opening angle at 58°, continue the process for 40 minutes, obtain a GaAs buffer layer with a thickness of 575nm, close the As and Ga beam source furnace baffles, and reduce the reaction chamber temperature to 350°C.

[0126] (2) The vacuum reaction chamber was heated to 620°C, the baffle of the As beam source furnace was opened and the baffle opening angle was maintained at 35°, and the temperature was continuously raised to 690°C. The Ga beam source furnace was opened and the baffle opening angle was maintained at 35°. The Al beam source furnace was opened and the baffle opening angle was maintained at 30°. The process was continued for 5 minutes to obtain an AlGaAs two-dimensional electron gas layer with a thickness of 8 nm. The baffles of the As, Ga, and Al beam source furnaces were closed, and the temperature of the reaction chamber was reduced to 370°C.

[0127] (3) The vacuum reaction chamber was heated to 580°C, the N beam source furnace baffle was opened and the baffle opening angle was maintained at 30°, and the temperature was continuously raised to 690°C. The Ga beam source furnace was opened and the baffle opening angle was maintained at 30°. The Al beam source furnace was opened and the baffle opening angle was maintained at 25°. The process was continued for 8 minutes to obtain an AlGaN spacer layer with a thickness of 10 nm. The N, Ga, and Al beam source furnace baffles were closed, and the reaction chamber temperature was reduced to 350°C.

[0128] (4) The vacuum reaction chamber was heated from 350°C to 440°C, the As beam source furnace baffle was opened and the baffle opening angle was maintained at 50°, and the temperature was continuously raised to 770°C. The Ga beam source furnace was opened and the baffle opening angle was maintained at 60°. The process was continued for 9 minutes to obtain a doped GaAs cap layer with a thickness of 50 nm. The As and Ga beam source furnace baffles were closed, and the reaction chamber temperature was reduced to 350°C.

[0129] (5) Take out the substrate that has completed all the epitaxial steps, put it into a special electron beam direct writing coating machine, adjust the coating speed to 4500 rpm, the spin coating time to 20 seconds, and prepare a bottom layer photoresist with a thickness of 100 nm on the silicon-doped GaAs cap layer; adjust the coating speed to 4000 rpm, the spin coating time to 180 seconds, and prepare an upper layer photoresist with a thickness of 0.95 um on the bottom layer photoresist; the photoresist material is polyisoprene. Put the substrate after spin coating on a hot plate at 140°C and bake for 75 seconds.

[0130] (6) Place the substrate after coating in an electron beam exposure machine with an electron beam current of 120 pA, an acceleration voltage of 50 kV, and a dose of 320 uC / cm 2 , directly write the photoresist to form a T-shaped structure on the silicon-doped GaAs cap layer, and the minimum line width of the T-shaped structure is 50nm. In this step, the maximum output can reach 10 pieces / hour.

[0131] (7) Placing the substrate after electron beam exposure and development in an electron beam evaporation device, depositing a titanium layer, a nickel layer, and a gold layer in the T-shaped structure on the silicon-doped GaAs cap layer in sequence, wherein the deposition rate of metal Ti is controlled at 4A / s, the time is 4 minutes, and the thickness is 96nm; the Ni evaporation rate is controlled at 3.5A / s, the time is 11 minutes, and the thickness is 230nm; the Au evaporation rate is controlled at 7.5A / s, the time is 20 minutes, and the thickness is 0.9μm. In this step, after the preparation of the gold layer is completed, the following treatment is also included: cleaning the GaAs substrate with the gold layer deposited, removing the residual metal and the coating layer, and forming a T-shaped gate on the silicon-doped GaAs cap layer.

[0132] (8) The drain and source are prepared on the silicon-doped GaAs cap layer by PVD sputtering, wherein the source is AlSiCu with a thickness of 5 μm, and the drain is AlSiCu with a thickness of 5 μm.

[0133] After testing, the minimum line width of the T-type gate structure prepared in this embodiment is 50nm, the side wall film thickness uniformity is 4.5%, the surface roughness is 5nm, and the surface defect density before metal deposition is 95 / cm 2 .

[0134] A GaAs device, specifically a GaAs radio frequency device including the GaAs device structure in the above-mentioned embodiment. After testing, the radio frequency frequency of the GaAs high electron mobility transistor is increased from the original 2.4GHz (under 0.35dB) to 4GHz (under 0.35dB). The reason is that the existing conventional GaAs high electron mobility transistor cannot effectively reduce parasitic effects like the present application, improve the depth-to-width ratio of the device gate structure in the vertical direction, reduce the short channel effect and the generation of leakage current, and improve the radio frequency characteristics. Therefore, in the GaAs device structure of the present invention, the work function of each film layer is well matched with the substrate, so the T-type gate is set on the silicon-doped GaAs cap layer, which is beneficial to reduce capacitance, improve carrier mobility and radio frequency characteristics, and can effectively realize the high-frequency properties of the GaAs device. In addition, the GaAs device structure of the present invention is simpler, and thus it is more conducive to obtaining a GaAs-based device with a simple structure and excellent performance.

[0135] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as above in the preferred embodiment, it is not used to limit the present invention. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent replacement, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention, still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A GaAs device structure based on electron beam direct writing T-gate, characterized in that: The invention comprises a GaAs substrate and a T-type gate; a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer, an n-AlGaN charge layer and a silicon-doped GaAs cap layer are sequentially grown on the GaAs substrate from bottom to top; a window is opened in the silicon-doped GaAs cap layer, and the T-type gate is arranged on the n-AlGaN charge layer through the window; the thickness of the n-AlGaN charge layer is 30nm to 50nm; the carrier mobility of the n-AlGaN charge layer is 6×10 17 / cm 3 ~5×10 18 / cm 3 The surface roughness of the n-AlGaN charge layer is less than 4 nm; the thickness of the silicon-doped GaAs cap layer is 45 nm to 70 nm; the carrier mobility of the silicon-doped GaAs cap layer is 5×10 16 / cm 3 ~9×10 17 / cm 3 ; The surface roughness of the silicon-doped GaAs cap layer is less than 6nm.

2. A GaAs device structure based on electron beam direct writing T-gate, characterized in that: The invention comprises a GaAs substrate and a T-type gate; a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer and a silicon-doped GaAs cap layer are sequentially grown on the GaAs substrate from bottom to top; the T-type gate is arranged on the silicon-doped GaAs cap layer; the thickness of the silicon-doped GaAs cap layer is 45nm to 70nm; the carrier mobility of the silicon-doped GaAs cap layer is 5×10 16 / cm 3 ~9×10 17 / cm 3 ; The surface roughness of the silicon-doped GaAs cap layer is less than 6nm.

3. The GaAs device structure based on electron beam direct writing T-gate according to claim 1 or 2, characterized in that: The GaAs substrate has a (111) crystal orientation or a (100) crystal orientation; the diameter of the GaAs substrate is 4 inches to 8 inches; The thickness of the GaAs buffer layer is 400nm to 650nm; the defect density of the GaAs buffer layer is less than 150 / cm 2 ; The surface roughness of the GaAs buffer layer is less than 15nm; The thickness of the AlGaAs two-dimensional electron gas layer is 5nm to 8nm; the defect density of the AlGaAs two-dimensional electron gas layer is less than 100 / cm 2 ; The surface roughness of the AlGaAs two-dimensional electron gas layer is less than 2nm; The thickness of the AlGaAs spacer layer is 6nm to 10nm; the surface roughness of the AlGaAs spacer layer is less than 2nm; The T-shaped gate is a Ti / Ni / Au electrode; the Ti / Ni / Au electrode is a titanium layer, a nickel layer, and a gold layer from bottom to top; the thickness of the titanium layer is 90 nm to 110 nm; the thickness of the nickel layer is 195 nm to 205 nm; the thickness of the gold layer is 0.9 μm to 1.2 μm; The GaAs device structure further includes a source and a drain; the source and the drain are arranged on the silicon-doped GaAs cap layer; the source is AlSiCu with a thickness of 5 μm; the drain is AlSiCu with a thickness of 5 μm.

4. A method for preparing a GaAs device structure based on electron beam direct writing of a T-gate, characterized in that: The following steps are involved: S1. growing a GaAs buffer layer on a GaAs substrate; S2, growing an AlGaAs two-dimensional electron gas layer on the GaAs buffer layer; S3, growing an AlGaAs spacer layer on the AlGaAs two-dimensional electron gas layer; S4, using molecular beam epitaxy to grow an n-AlGaN charge layer on the AlGaAs spacer layer; the preparation process of the n-AlGaN charge layer is: placing a GaAs substrate with an AlGaAs spacer layer in a vacuum reaction chamber, heating to 580°C to 600°C, opening the N beam source furnace baffle and keeping the baffle opening angle at 30°, heating to 670°C to 690°C, opening the Ga beam source furnace and keeping the baffle opening angle at 30°, opening the Al beam source furnace and keeping the baffle opening angle at 25°, and keeping for 7 min to 11 min to obtain the n-AlGaN charge layer; S5. Growing a silicon-doped GaAs cap layer on the n-AlGaN charge layer by molecular beam epitaxy; the preparation process of the silicon-doped GaAs cap layer is as follows: placing a GaAs substrate with an n-AlGaN charge layer in a vacuum reaction chamber, heating to 420°C to 440°C, opening the baffle of the As beam source furnace and keeping the baffle opening angle at 50°, heating to 750°C to 770°C, opening the Ga beam source furnace and keeping the baffle opening angle at 60°, opening the Si beam source furnace and keeping the baffle opening angle at 48°, and keeping for 9 min to 15 min to obtain a silicon-doped GaAs cap layer; S6, coating a photoresist on the silicon-doped GaAs cap layer; S7, directly writing the photoresist by electron beam exposure to form a T-shaped structure on the n-AlGaN charge layer; S8. Prepare a T-type gate in the T-type structure on the n-AlGaN charge layer to complete the preparation of the GaAs device structure.

5. The preparation method according to claim 4, characterized in that: In step S1, a GaAs buffer layer is grown on a GaAs substrate by molecular beam epitaxy or metal organic chemical vapor deposition. The preparation process of the GaAs buffer layer is as follows: a GaAs substrate is placed in a vacuum reaction chamber, heated to 420°C to 440°C, an As beam source furnace baffle is opened and the baffle opening angle is maintained at 47° to 50°, heated to 750°C to 770°C, a Ga beam source furnace is opened and the baffle opening angle is maintained at 57° to 60°, and maintained for 30min to 42min to obtain a GaAs buffer layer. The GaAs substrate also includes the following treatments before use: the surface of the GaAs substrate is cleaned in a He atmosphere to remove surface moisture, impurities and particles; In step S2, an AlGaAs two-dimensional electron gas layer is grown on a GaAs buffer layer by molecular beam epitaxy; the preparation process of the AlGaAs two-dimensional electron gas layer is as follows: a GaAs substrate on which a GaAs buffer layer is grown is placed in a vacuum reaction chamber, the temperature is raised to 600° C. to 620° C., the As beam source furnace baffle is opened and the baffle opening angle is maintained at 35°, the temperature is raised to 690° C. to 710° C., the Ga beam source furnace is opened and the baffle opening angle is maintained at 30° to 35°, the Al beam source furnace is opened and the baffle opening angle is maintained at 25° to 30°, and the temperature is maintained for 3 min to 5 min to obtain an AlGaAs two-dimensional electron gas layer; In step S3, an AlGaAs spacer layer is grown on the AlGaAs two-dimensional electron gas layer by molecular beam epitaxy; the preparation process of the AlGaAs spacer layer is as follows: placing a GaAs substrate on which an AlGaAs two-dimensional electron gas layer is grown in a vacuum reaction chamber, heating the temperature to 580°C to 600°C, opening the baffle of the As beam source furnace and keeping the baffle opening angle at 30°, continuously heating the temperature to 670°C to 690°C, opening the Ga beam source furnace and keeping the baffle opening angle at 30°, opening the Al beam source furnace and keeping the baffle opening angle at 25°, and keeping for 5 min to 8 min to obtain the AlGaAs spacer layer; In step S6, a photoresist is coated on the window area on the silicon-doped GaAs cap layer by a spin coating method; the preparation process of the photoresist is as follows: a GaAs substrate on which a silicon-doped GaAs cap layer is grown is placed in a coating machine, a bottom layer photoresist is prepared on the silicon-doped GaAs cap layer at a rotation speed of 4000 rpm to 6000 rpm, an upper layer photoresist is prepared on the bottom layer photoresist at a rotation speed of 4000 rpm to 5200 rpm, and the top layer photoresist is baked at 140° C. to 150° C. for 75 s to 90 s; the thickness of the bottom layer photoresist is 80 nm to 120 nm; the bottom layer photoresist is PMMA or polyisoprene; the thickness of the top layer photoresist is 0.95 μm to 1.08 μm; the top layer photoresist is PMMA or polyisoprene; In step S7, the process parameters of the direct writing are: electron beam current of 80 pA to 140 pA, acceleration voltage of 40 kV to 80 kV, and dose of 280 uC / cm 2 ~360 uC / cm 2 ; In step S8, a titanium layer, a nickel layer, and a gold layer are sequentially deposited in a T-shaped structure on the n-AlGaN charge layer by electron beam evaporation or resistance wire evaporation; the deposition process parameters of the titanium layer are: the evaporation rate is 3.5 A / s to 4.2 A / s, and the time is 4 min to 5 min; the deposition process parameters of the nickel layer are: the evaporation rate is 2.5 A / s to 3.5 A / s, and the time is 11 min to 13 min; the deposition process parameters of the gold layer are: the evaporation rate is 7.5 A / s to 8.5 A / s, and the time is 20 min to 24 min; the thickness of the titanium layer is 90 nm to 110 nm; the thickness of the nickel layer is 195 nm to 205 nm; the thickness of the gold layer is 0.9 μm to 1.2 μm; after the preparation of the gold layer is completed, the following treatment is also included: the GaAs substrate with the gold layer deposited is cleaned to remove residual metal and the coating layer to form a T-shaped gate; The method further comprises the following steps: preparing a drain electrode and a source electrode on the silicon-doped GaAs cap layer.

6. The preparation method according to claim 5, characterized in that The GaAs device structure comprises a GaAs substrate and a T-type gate; a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer, an n-AlGaN charge layer and a silicon-doped GaAs cap layer are sequentially grown on the GaAs substrate from bottom to top; a window is opened in the silicon-doped GaAs cap layer, and the T-type gate is arranged on the n-AlGaN charge layer through the window; The GaAs substrate has a (111) crystal orientation or a (100) crystal orientation; the diameter of the GaAs substrate is 4 inches to 8 inches; The thickness of the GaAs buffer layer is 400nm to 650nm; the defect density of the GaAs buffer layer is less than 150 / cm 2 ; The surface roughness of the GaAs buffer layer is less than 15nm; The thickness of the AlGaAs two-dimensional electron gas layer is 5nm to 8nm; the defect density of the AlGaAs two-dimensional electron gas layer is less than 100 / cm 2 ; The surface roughness of the AlGaAs two-dimensional electron gas layer is less than 2nm; The thickness of the AlGaAs spacer layer is 6nm to 10nm; the surface roughness of the AlGaAs spacer layer is less than 2nm; The thickness of the n-AlGaN charge layer is 30nm to 50nm; the carrier mobility of the n-AlGaN charge layer is 6×10 17 / cm 3 ~5×10 18 / cm 3 ; The surface roughness of the n-AlGaN charge layer is less than 4 nm; The thickness of the silicon-doped GaAs cap layer is 45nm-70nm; the carrier mobility of the silicon-doped GaAs cap layer is 5×10 16 / cm 3 ~9×10 17 / cm 3 ; The surface roughness of the silicon-doped GaAs cap layer is less than 6nm; The source electrode is AlSiCu with a thickness of 5 μm; the drain electrode is AlSiCu with a thickness of 5 μm.

7. A method for preparing a GaAs device structure based on electron beam direct writing of a T-gate, characterized in that: The following steps are involved: (1) Growing a GaAs buffer layer on a GaAs substrate; (2) Growing an AlGaAs two-dimensional electron gas layer on a GaAs buffer layer; (3) growing an AlGaAs spacer layer on the AlGaAs two-dimensional electron gas layer; (4) Growing a silicon-doped GaAs cap layer on the AlGaAs spacer layer by molecular beam epitaxy; the preparation process of the silicon-doped GaAs cap layer is as follows: placing the GaAs substrate on which the AlGaAs spacer layer is grown in a vacuum reaction chamber, heating it to 420°C to 440°C, opening the baffle of the As beam source furnace and keeping the baffle opening angle at 50°, heating it to 750°C to 770°C, opening the Ga beam source furnace and keeping the baffle opening angle at 60°, and keeping it for 9 min to 15 min to obtain a silicon-doped GaAs cap layer; (5) Coating a photoresist on the silicon-doped GaAs cap layer; (6) Direct writing of photoresist by electron beam exposure to form a T-shaped structure on the silicon-doped GaAs cap layer; (7) A T-type gate is prepared in the T-type structure on the silicon-doped GaAs cap layer to complete the preparation of the GaAs device structure.

8. The preparation method according to claim 7, characterized in that: In step (1), a GaAs buffer layer is grown on a GaAs substrate by molecular beam epitaxy or metal organic chemical vapor deposition. The preparation process of the GaAs buffer layer is as follows: placing the GaAs substrate into a vacuum reaction chamber, heating it to 420°C to 440°C, opening the baffle of the As beam source furnace and maintaining the baffle opening angle at 47° to 50°, heating it to 750°C to 770°C, opening the Ga beam source furnace and maintaining the baffle opening angle at 57° to 60°, and maintaining it for 30 minutes to 42 minutes to obtain the GaAs buffer layer. The GaAs substrate also includes the following treatments before use: cleaning the surface of the GaAs substrate in a He atmosphere to remove surface moisture, impurities and particles; In step (2), an AlGaAs two-dimensional electron gas layer is grown on a GaAs buffer layer by molecular beam epitaxy. The preparation process of the AlGaAs two-dimensional electron gas layer is as follows: placing a GaAs substrate on which a GaAs buffer layer is grown in a vacuum reaction chamber, heating the chamber to 600°C to 620°C, opening the baffle of the As beam source furnace and maintaining the baffle opening angle at 35°, heating the chamber to 690°C to 710°C, opening the Ga beam source furnace and maintaining the baffle opening angle at 30°C to 35°, opening the Al beam source furnace and maintaining the baffle opening angle at 25°C to 30°, and maintaining the temperature for 3 min to 5 min to obtain an AlGaAs two-dimensional electron gas layer. In step (3), an AlGaAs spacer layer is grown on the AlGaAs two-dimensional electron gas layer by molecular beam epitaxy. The preparation process of the AlGaAs spacer layer is as follows: placing a GaAs substrate on which an AlGaAs two-dimensional electron gas layer is grown in a vacuum reaction chamber, heating the chamber to 580°C to 600°C, opening the baffle of the As beam source furnace and maintaining the baffle opening angle at 30°, continuously heating the chamber to 670°C to 690°C, opening the Ga beam source furnace and maintaining the baffle opening angle at 30°, opening the Al beam source furnace and maintaining the baffle opening angle at 25°, and maintaining the temperature for 5 min to 8 min to obtain the AlGaAs spacer layer. In step (5), a photoresist is coated on the silicon-doped GaAs cap layer by spin coating. The preparation process of the photoresist is as follows: a GaAs substrate on which a silicon-doped GaAs cap layer is grown is placed in a spin coating machine, a bottom layer photoresist is prepared on the silicon-doped GaAs cap layer at a rotation speed of 4000 rpm to 6000 rpm, an upper layer photoresist is prepared on the bottom layer photoresist at a rotation speed of 4000 rpm to 5200 rpm, and the top layer photoresist is baked at 140° C. to 150° C. for 75 s to 90 s. The thickness of the bottom layer photoresist is 80 nm to 120 nm. The bottom layer photoresist is PMMA or polyisoprene. The thickness of the upper layer photoresist is 0.95 μm to 1.08 μm. The upper layer photoresist is PMMA or polyisoprene. In step (6), the process parameters of the direct writing are: electron beam current of 80 pA to 140 pA, acceleration voltage of 40 kV to 80 kV, and dose of 280 uC / cm 2 ~360 uC / cm 2 ; In step (7), a titanium layer, a nickel layer, and a gold layer are sequentially deposited in a T-shaped structure on a silicon-doped GaAs cap layer by electron beam evaporation or resistance wire evaporation. The deposition process parameters of the titanium layer are as follows: a deposition rate of 3.5 A / s to 4.2 A / s, and a time of 4 min to 5 min; the deposition process parameters of the nickel layer are as follows: a deposition rate of 2.5 A / s to 3.5 A / s, and a time of 11 min to 13 min; the deposition process parameters of the gold layer are as follows: a deposition rate of 7.5 A / s to 8.5 A / s, and a time of 20 min to 24 min; the thickness of the titanium layer is 90 nm to 110 nm; the thickness of the nickel layer is 195 nm to 230 nm; the thickness of the gold layer is 0.9 μm to 1.2 μm; after the preparation of the gold layer is completed, the following treatments are also included: The GaAs substrate with the gold layer deposited thereon is cleaned to remove the residual metal and the coating layer to form a T-type gate; The method further comprises the following steps: preparing a drain electrode and a source electrode on the silicon-doped GaAs cap layer.

9. The preparation method according to claim 8, characterized in that The GaAs device structure comprises a GaAs substrate and a T-type gate; a GaAs buffer layer, an AlGaAs two-dimensional electron gas layer, an AlGaAs spacer layer and a silicon-doped GaAs cap layer are sequentially grown on the GaAs substrate from bottom to top; the T-type gate is arranged on the silicon-doped GaAs cap layer; The GaAs substrate has a (111) crystal orientation or a (100) crystal orientation; the diameter of the GaAs substrate is 4 inches to 8 inches; The thickness of the GaAs buffer layer is 400nm to 650nm; the defect density of the GaAs buffer layer is less than 150 / cm 2 ; The surface roughness of the GaAs buffer layer is less than 15nm; The thickness of the AlGaAs two-dimensional electron gas layer is 5nm to 8nm; the defect density of the AlGaAs two-dimensional electron gas layer is less than 100 / cm 2 ; The surface roughness of the AlGaAs two-dimensional electron gas layer is less than 2nm; The thickness of the AlGaAs spacer layer is 6nm to 10nm; the surface roughness of the AlGaAs spacer layer is less than 2nm; The thickness of the silicon-doped GaAs cap layer is 45nm-70nm; the carrier mobility of the silicon-doped GaAs cap layer is 5×10 16 / cm 3 ~9×10 17 / cm 3 ; The surface roughness of the silicon-doped GaAs cap layer is less than 6nm; The source electrode is AlSiCu with a thickness of 5 μm; the drain electrode is AlSiCu with a thickness of 5 μm.

10. A GaAs device, characterized in that: The GaAs device comprises the GaAs device structure of any one of claims 1 to 9; the GaAs device is a T-gate photodetector, a trench T-gate high electron mobility transistor or a T-gate laser generator.

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