Multi-stage trench heterojunction enhanced IGBT device and fabrication method

Abstract

The application discloses a multistage trench heterojunction enhanced IGBT device, which comprises a gallium oxide substrate and a gallium oxide epitaxial layer on one side of the gallium oxide substrate, a first trench is arranged on the other side of the gallium oxide substrate, the first trench is a multistage trench, a P-type oxide is deposited on the surface of the first trench, a metal layer is deposited on the surface of the P-type oxide, a collector for filling the first trench and covering the gallium oxide substrate is deposited on the surface of the metal layer, the gallium oxide epitaxial layer is provided with a second trench for constituting a trench type insulated gate bipolar transistor structure, and the first trench and the second trench are staggered in the horizontal direction. The multistage trench heterojunction enhanced IGBT device structure can further reduce the electric field at the device surface, reduce the dependence of the device on the thickness of the gate dielectric material and improve the influence of temperature on the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a multi-level trench heterojunction enhancement IGBT device and its fabrication method. Background Technology

[0002] In recent years, ultra-wide bandgap semiconductor materials with band gaps larger than SiC and GaN have been considered an exciting and challenging new research field due to their superior optical and electrical properties. The larger band gap allows devices to be used in many extreme environments: in geothermal energy production and oil and gas extraction, they enable higher drilling speeds and lower failure rates; in high-temperature environments, they allow for higher operating temperatures in aluminum plants, steel mills, and coal-fired and gas-fired power plants controlled by electronic sensors, thereby improving the energy efficiency of these industrial processes. Among wide bandgap semiconductor materials, Ga2O3 has a bandgap of 4.8 eV, an ideal breakdown electric field strength of 8 MV / cm, and a BFOM value as high as 3400, approximately four times that of GaN and ten times that of SiC. Therefore, in today's power electronics applications with higher power density and lower power consumption requirements, Ga2O3 materials have greater research significance and broader market application prospects. In contrast to the ease of n-type doping, there are currently no reports of successful p-type doping in Ga2O3, which limits the application of Ga2O3 in bipolar power devices compared to materials that can be bipolar-doped.

[0003] Because gallium oxide (GaO) lacks an effective P-type semiconductor, it cannot be fabricated into conventional MOSFET structures like SiC and GaN. Instead, it can only be used to create heterojunction JFETs or MISFETs where the drain, source, and drift region are all N-type conductive. In GaO MISFETs and JFETs, a work function difference exists between the gate metal, polysilicon, and P-type semiconductor and the GaO epitaxial layer, resulting in a depletion layer in the conductive path, affecting the device's operating characteristics. In planar GaO MISFETs, the conductive path is only partially depleted at 0V, not completely depleted, making it a depletion-type device under forward bias. When the device is reverse biased, the gate electrode can shield some of the electric field, but because the depletion region on the GaO epitaxial surface is insufficient, the electric field shielding ability is limited, and the electric field at the metal-semiconductor interface remains strong. With increasing reverse voltage, more and more electrons flow from the source to the drain, resulting in a large reverse leakage current and deteriorating device reliability. On the other hand, when devices operate under high current conditions, they generate a large amount of heat. Since gallium oxide itself has low thermal conductivity, this causes the device temperature to rise, reducing carrier mobility and consequently decreasing the output current. Therefore, there is a need to further develop junction enhancement-mode devices that are less affected by temperature.

[0004] To achieve enhancement-mode devices, reduce the electric field at the metal-semiconductor interface, and mitigate the impact of temperature on the device, a layer of p-type NiO was sputtered onto a Ga2O3 substrate, followed by etching a gallium oxide epitaxial layer to form grooves on the surface. Insulating media such as SiO2 and Al2O3 were then deposited into these grooves to form the insulating gate dielectric of the IGBT device, thus fabricating an enhancement-mode IGBT (EIGBT). Compared to planar MISFET devices, EIGBTs exhibit normally-off characteristics because the metal or polysilicon gate can completely deplete the conductive channels. Furthermore, the gate electrode has a certain depth, which can effectively shield part of the electric field during reverse bias, resulting in a certain degree of reduction in the surface electric field. surf,EIGBT <E surf,plane MISFET This reduces leakage current. Furthermore, the EIGBT drift region is bipolar carrier-conducting, thus exhibiting a conductivity modulation effect, which significantly reduces on-resistance. At high temperatures, the enhanced carrier injection effect compensates for the decreased carrier mobility, thereby improving the device's high-temperature characteristics. However, due to the characteristics of gallium oxide, achieving deep gate dielectric deposition cannot be achieved through thermal oxidation; instead, deep trenches must be formed in the gallium oxide material, followed by gate dielectric deposition on the surface of these trenches. However, the significant depth of these trenches leads to uneven thickness of the gate dielectric layer within the trenches, affecting the uniformity of the device's threshold voltage. Although the EIGBT effectively reduces the surface electric field during reverse operation, the limited trench depth means the peak electric field is close to the surface, allowing some field lines to still penetrate the gate and reach the source. This results in a still strong electric field at the metal-semiconductor interface, leading to significant leakage current and impacting device reliability. More importantly, the gate dielectric material typically chosen to achieve enhancement-mode devices is very thin. When the electric field peak shifts from the surface to the bulk trench, the gate dielectric can only withstand a very small voltage, making the device more prone to breakdown at the gate dielectric. Therefore, the breakdown voltage and forward conduction characteristics of EIGBT devices are affected by the gate dielectric thickness, and the high breakdown field strength of gallium oxide cannot be fully utilized. Furthermore, when this structure is forward-turned on, it needs to overcome the heterojunction barrier between the substrate and the sputtered P-type NiO, increasing the device's turn-on voltage and hindering its operation. Additionally, this device lacks reverse conduction capability, requiring an additional FRD device for reverse freewheeling in inductive load circuits, thus increasing the operating cost. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a multi-level trench heterojunction enhanced IGBT device unit structure, which further reduces the electric field at the device surface, reduces the device's dependence on the thickness of the gate dielectric material, and improves the effect of temperature on the device, so as to fabricate high-voltage and high-reliability gallium oxide IGBT devices.

[0006] To achieve the above objectives, the present invention adopts the following technical solution.

[0007] The present invention provides a multi-level trench heterojunction enhancement-type IGBT device, comprising: a gallium oxide substrate and a gallium oxide epitaxial layer located on one side of the gallium oxide substrate, a first trench provided on the other side of the gallium oxide substrate, the first trench being a multi-level trench, a P-type oxide deposited on the surface of the first trench, a metal layer deposited on the surface of the P-type oxide, a collector electrode deposited on the surface of the metal layer filling the first trench and covering the gallium oxide substrate, and a second trench forming a trench-type insulated gate bipolar transistor structure on the gallium oxide epitaxial layer, wherein the first trench and the second trench are staggered in the horizontal direction.

[0008] In some embodiments, the P-type oxide is one of NiO and Cu2O.

[0009] In some embodiments, the metal layer is made of one of Ni, Au, or Pt.

[0010] In some embodiments, the second trench is a multi-level trench.

[0011] In some embodiments, the surface of the epitaxial layer near the opening of the second trench and the sidewalls and part of the bottom surface of the first trench are covered with a gate dielectric layer, the sidewalls and bottom of the trenches other than the first trench are covered with an insulating dielectric layer, a gate electrode is deposited on the surface of the gate dielectric layer and the insulating dielectric layer, and an interlayer dielectric layer is covered between the gate electrode and the emitter.

[0012] In some embodiments, the material of the gate dielectric layer is selected from p-type oxide and Al2O3.

[0013] In some embodiments, the material of the insulating dielectric layer is selected from at least one of SiO2, LPTEOS, ALD-Al2O3, and Si3N4.

[0014] In some embodiments, the gate electrode is made of metal or doped polycrystalline silicon.

[0015] The present invention also provides a method for fabricating the above-mentioned multi-level trench heterojunction enhanced IGBT device, comprising the following steps:

[0016] S1. A first trench is formed by etching on a gallium oxide substrate including a gallium oxide epitaxial layer;

[0017] S2. Deposit a P-type oxide on the surface of the first trench;

[0018] S3. Deposit a metal layer on the surface of the P-type oxide;

[0019] S4. Deposit current collector metal on the surface of the metal layer and the gallium oxide substrate;

[0020] S5. A second trench is formed by etching on the gallium oxide epitaxial layer;

[0021] S6. Deposit an insulating dielectric layer and a gate dielectric layer on the surface of the second trench;

[0022] S7. Deposit a gate electrode on the surfaces of the insulating dielectric layer and the gate dielectric layer;

[0023] S8. Cover the surface of the gate electrode with an interlayer dielectric layer;

[0024] S9. Deposit emitter metal on the interlayer dielectric layer and the gallium oxide epitaxial layer.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] This invention employs a multi-level trench structure in the epitaxial layer, which extends the gate dielectric and field plate deep into the drift region. When the gate electrode is at 0V, the work function difference between the gate electrode and the semiconductor can deplete the conductive channel, achieving an enhancement-mode device. When the device is reverse-biased, the field plate formed by the multi-level trenches and the gate dielectric in the first-level trench can disperse the electric field, avoiding electric field concentration and premature breakdown of the gate dielectric, reducing dependence on the thickness of the gate dielectric material, and lowering the surface electric field and leakage current. The multi-level trench substrate can reduce the heterojunction turn-on voltage without changing the device's turn-on voltage, thereby entering a bipolar conduction mode and reducing on-resistance. Furthermore, the device has reverse conduction capability; when the emitter potential is higher than the collector potential, electrons can travel from the collector to the emitter, realizing current transfer from the emitter to the collector. Therefore, when this device is operating, there is no need to connect an additional FRD device in parallel as a freewheeling diode, saving circuit costs. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of the multi-level trench heterojunction enhancement IGBT device in Example 1;

[0028] Figure 2 This is a schematic diagram of the fabrication process of the multi-level trench heterojunction enhanced IGBT device in Example 1.

[0029] Figure 3This is a schematic diagram of the electric field and current distribution of the multi-level trench heterojunction enhancement IGBT device in Example 1;

[0030] Figure 4 This is a schematic diagram showing the gate dielectric layer thickness and current distribution of a single-stage trench enhancement-type IGBT device.

[0031] Figure 5 Schematic diagram of current distribution of the multi-level trench heterojunction enhancement IGBT device in Example 1 under different modes;

[0032] Figure 6 This is a schematic diagram of the structure of the multi-level trench heterojunction enhanced IGBT device in Example 2. Detailed Implementation

[0033] The present invention will be further described in detail below with reference to specific embodiments, so that those skilled in the art can more clearly understand the present invention. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention. In the embodiments of the present invention, unless otherwise specified, all raw material components are commercially available products well known to those skilled in the art; unless specifically specified, the technical means used are all conventional means well known to those skilled in the art.

[0034] An embodiment of the present invention provides a multi-level trench heterojunction enhancement-type IGBT device, comprising: a gallium oxide substrate and a gallium oxide epitaxial layer located on one side of the gallium oxide substrate, a first trench provided on the other side of the gallium oxide substrate, the first trench being a multi-level trench, a P-type oxide deposited on the surface of the first trench, a metal layer deposited on the surface of the P-type oxide, a collector electrode deposited on the surface of the metal layer filling the first trench and covering the gallium oxide substrate, and a second trench provided in the gallium oxide epitaxial layer constituting a trench-type insulated gate bipolar transistor structure, the first trench and the second trench being staggered in the horizontal direction.

[0035] In some embodiments, the p-type oxide is one of NiO and Cu2O.

[0036] In some embodiments, the metal layer is made of one of Ni, Au, or Pt.

[0037] In some implementations, the second trench is a multi-level trench.

[0038] In some embodiments, the surface of the epitaxial layer near the opening of the second trench and the sidewalls and part of the bottom surface of the first trench are covered with a gate dielectric layer, the sidewalls and bottom of the trenches other than the first trench are covered with an insulating dielectric layer, a gate electrode is deposited on the surface of the gate dielectric layer and the insulating dielectric layer, and an interlayer dielectric layer is covered between the gate electrode and the emitter.

[0039] In some embodiments, the material of the gate dielectric layer is selected from p-type oxide and Al2O3.

[0040] In some embodiments, the material of the insulating dielectric layer is selected from at least one of SiO2, LPTEOS, ALD-Al2O3, and Si3N4.

[0041] In some implementations, the gate electrode is made of metal or doped polycrystalline silicon.

[0042] This invention also provides a method for fabricating the above-mentioned multi-level trench heterojunction enhanced IGBT device, comprising the following steps:

[0043] S1. A first trench is formed by etching on a gallium oxide substrate including a gallium oxide epitaxial layer;

[0044] S2. Deposit P-type oxide on the surface of the first trench;

[0045] S3. Deposit a metal layer on the surface of a P-type oxide;

[0046] S4. Deposit collector metal on the surface of the metal layer and on the gallium oxide substrate;

[0047] S5. Etch a second trench on the gallium oxide epitaxial layer;

[0048] S6. Deposit an insulating dielectric layer and a gate dielectric layer on the surface of the second trench;

[0049] S7. Deposit a gate electrode on the surfaces of the insulating dielectric layer and the gate dielectric layer;

[0050] S8. Cover the gate electrode surface with an interlayer dielectric layer;

[0051] S9. Deposit emitter metal on the interlayer dielectric layer and the gallium oxide epitaxial layer.

[0052] Example 1

[0053] This embodiment provides a multi-level trench heterojunction enhanced IGBT device structure, as follows: Figure 1 As shown, a first secondary trench is provided on one side of the bottom of the gallium oxide substrate 1. A P-type NiO layer 3 is deposited on the surface of the first secondary trench. A metallic Ni layer 4 is deposited on the surface of the P-type NiO layer 3. A collector electrode 4 that fills the first secondary trench and covers the gallium oxide substrate 1 is deposited on the surface of the metallic Ni layer 4. A second secondary trench is provided on the upper part of the gallium oxide epitaxial layer 2. An Al2O3 gate dielectric layer 6 is covered on the surface of the epitaxial layer near the opening of the second secondary trench, the sidewalls of the first secondary trench, and part of the bottom surface. An SiO2 insulating dielectric layer 7 is covered on the sidewalls and bottom of the second secondary trench, and part of the bottom surface of the first secondary trench. A doped polycrystalline silicon gate electrode 8 is deposited on the surface of the gate dielectric layer 6 and the insulating dielectric layer 7. An SiO2 interlayer dielectric layer 9 is covered between the gate electrode 8 and the emitter 10.

[0054] The specific fabrication process of the multi-level trench heterojunction enhanced IGBT device provided in this embodiment is as follows: Figure 2 As shown, firstly, a first secondary trench is formed by etching on a gallium oxide substrate including a gallium oxide epitaxial layer; then, P-type NiO is deposited and patterned on the surface of the first secondary trench; metallic Ni is deposited and patterned on the surface of the P-type NiO layer, forming an ohmic contact between Ni and NiO; finally, Ti / Au metal is deposited on the surface of the metallic Ni layer and on the gallium oxide substrate, and tempered to form a collector, forming an ohmic contact between Ti and Ga2O3; then, a second secondary trench is formed by etching on the gallium oxide epitaxial layer; finally, SiO2 insulating dielectric is deposited on the surface of the second secondary trench, and after patterning, except for the sidewalls of the first secondary trench... The bottom and sidewalls of the remaining trenches are covered with deposited insulating dielectric layers; an Al2O3 insulating layer is deposited and patterned to form a gate dielectric layer on the epitaxial surface near the sidewalls, part of the bottom, and trench opening of the first-level trench; doped polysilicon is deposited and patterned to form a gate on the surface of the gate dielectric layer, and the polysilicon covering the insulating dielectric layer constitutes the field plate in the cell region; SiO2 dielectric is deposited and patterned to form an interlayer dielectric layer to achieve isolation between layers; Ti / Al / Pt metal is deposited and patterned as an emitter to form an ohmic contact with the gallium oxide on the surface.

[0055] Figure 3 This diagram illustrates the electric field and current distribution of the multi-level trench heterojunction enhancement-type IGBT device in this embodiment. It shows that, under reverse blocking conditions, the breakdown field strength of the insulating dielectric at the bottom and sidewalls of the multi-level trench used in this embodiment is higher than that of gallium oxide. Furthermore, the presence of a gate electrode on the insulating dielectric disperses the electric field near the gate dielectric, thus preventing the bottom gate dielectric from being the first to break down and reducing dependence on the thickness of the gate dielectric material. Due to the shielding effect of the gate dielectric and the field plate on the electric field, the electric field strength on the gallium oxide surface can be further reduced. surf,MTEMISFET <E surf,EMISFET <E surf,plane MISFET . Figure 4 The diagram shows the gate dielectric layer thickness and current distribution of a single-level trench enhancement-type IGBT device. It can be seen that, compared with a single-level trench of the same depth, the gate dielectric thickness deposited on the sidewalls of a multi-level trench is more uniform, preventing premature breakdown at the thinner part of the gate dielectric (point O in the figure). The device has a higher breakdown voltage and better threshold voltage uniformity. At the same time, when the device is forward-biased, the downward current path is larger, the JFET effect is weakened, the series resistance is reduced, and the forward characteristics are better. Figure 5The diagram illustrates the current distribution of the multi-level trench heterojunction enhancement-type IGBT device in this embodiment under different modes. It can be seen that because the first and second trenches are staggered horizontally, and their openings are not on a vertical line, the current conduction path during forward turn-on is increased. Point A on the substrate surface and point B at the bottom of the substrate trench have a larger potential difference. When this potential difference can overcome the heterojunction barrier of the substrate, the heterojunction barrier can be turned on, and the device enters a bipolar conduction mode. Furthermore, the device has reverse conduction capability. When the emitter potential is higher than the collector potential, electrons can travel from the collector to the emitter, generating a current from the emitter to the collector. Therefore, when this device is operating, there is no need to connect an additional FRD device in parallel as a freewheeling diode, saving circuit costs.

[0056] Example 2

[0057] This embodiment provides a multi-level trench heterojunction enhanced IGBT device structure, as follows: Figure 6 As shown, the difference from Example 1 is that the insulating dielectric layer 6 is a composite dielectric layer, the first dielectric layer 601 is LPTEOS, and the second dielectric layer 602 is Si3N4.

[0058] Example 3

[0059] This embodiment provides a multi-level trench heterojunction enhanced IGBT device structure, which differs from Embodiment 1 in that the gate dielectric layer material is P-type NiO, the gate electrode material is metallic Ni, and the gate electrode and the gate dielectric layer form an ohmic contact.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-level trench heterojunction enhanced IGBT device, characterized in that, include: The system comprises a gallium oxide substrate and a gallium oxide epitaxial layer located on one side of the gallium oxide substrate. A first trench is provided on the other side of the gallium oxide substrate. The first trench is a multi-level trench. A P-type oxide is deposited on the surface of the first trench. A metal layer is deposited on the surface of the P-type oxide. A collector electrode is deposited on the surface of the metal layer, which fills the first trench and covers the gallium oxide substrate. A second trench is provided on the gallium oxide epitaxial layer, which constitutes a trench-type insulated gate bipolar transistor structure. The first trench and the second trench are staggered in the horizontal direction.

2. The multi-level trench heterojunction enhanced IGBT device according to claim 1, characterized in that, The p-type oxide is one of NiO and Cu2O.

3. The multi-level trench heterojunction enhanced IGBT device according to claim 1, characterized in that, The metal layer is made of one of Ni, Au, or Pt.

4. The multi-level trench heterojunction enhanced IGBT device according to claim 1, characterized in that, The second trench is a multi-level trench.

5. The multi-level trench heterojunction enhanced IGBT device according to claim 4, characterized in that, The epitaxial layer surface near the opening of the second trench and the sidewalls and part of the bottom surface of the first trench are covered with a gate dielectric layer. The sidewalls and bottom of the trenches other than the first trench are covered with an insulating dielectric layer. A gate electrode is deposited on the surface of the gate dielectric layer and the insulating dielectric layer. An interlayer dielectric layer is covered between the gate electrode and the emitter.

6. The multi-level trench heterojunction enhanced IGBT device according to claim 5, characterized in that, The material of the gate dielectric layer is selected from either P-type oxide or Al2O3.

7. The multi-level trench heterojunction enhanced IGBT device according to claim 5, characterized in that, The material of the insulating dielectric layer is selected from at least one of SiO2, LPTEOS, ALD-Al2O3, and Si3N4.

8. The multi-level trench heterojunction enhancement IGBT device according to claim 5, characterized in that, The gate electrode is made of metal or doped polycrystalline silicon.

9. A method for fabricating a multi-level trench heterojunction enhanced IGBT device according to any one of claims 1 to 8, characterized in that, Includes the following steps: S1. A first trench is formed by etching on a gallium oxide substrate including a gallium oxide epitaxial layer; S2. Deposit a P-type oxide on the surface of the first trench; S3. Deposit a metal layer on the surface of the P-type oxide; S4. Deposit current collector metal on the surface of the metal layer and the gallium oxide substrate; S5. A second trench is formed by etching on the gallium oxide epitaxial layer; S6. Deposit an insulating dielectric layer and a gate dielectric layer on the surface of the second trench; S7. Deposit a gate electrode on the surfaces of the insulating dielectric layer and the gate dielectric layer; S8. Cover the surface of the gate electrode with an interlayer dielectric layer; S9. Deposit emitter metal on the interlayer dielectric layer and the gallium oxide epitaxial layer.

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