Pgan-enhanced hent device structure based on gan substrate and preparation method thereof

Abstract

This invention provides a pGaN-enhanced HEMT device structure based on a GaN substrate and its fabrication method. The device structure includes: a substrate structure comprising a first substrate and a buffer layer and a GaN layer sequentially formed on the first substrate in a direction away from the first substrate; and a Schottky barrier diode comprising a pGaN layer formed within the GaN layer. + Doped regions and formed in the p + n in the doped region + The doped region, the p + The doped region and the n + The doped regions form a PN junction to constitute the Schottky barrier diode; an isolation layer is formed on the GaN layer and covers the p-junction. + The doped region and the n + Doped region; pGaN enhancement-mode HEMT device, formed on a portion of the isolation layer; wherein, the p + Doped regions and the n + The doped regions are electrically connected to the anode and cathode, respectively, and the anode is electrically connected to the source of the pGaN enhancement-mode HEMT device; the cathode is electrically connected to the drain of the pGaN enhancement-mode HEMT device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and in particular to a pGaN enhancement mode HEMT device structure based on a GaN substrate and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) has high application value in the field of power electronics due to its high electron mobility, large band gap, high breakdown voltage, and small dielectric constant. High electron mobility transistors (HEMTs) based on AlGaN / GaN heterostructures can have very low on-resistance and very small leakage current. The two-dimensional electron gas (2DEG) channel generated by the AlGaN / GaN heterojunction naturally exists without gate bias voltage, and the high-concentration two-dimensional electron gas in the channel cannot be depleted by the Schottky gate at zero bias, which undoubtedly increases the complexity of circuit design and greatly increases power consumption. Compared with traditional HEMTs, the enhancement mode HEMT based on a pGaN gate structure can adjust the threshold voltage and has better stability, and is widely used.

[0003] However, the pGaN enhancement mode HEMT device will inevitably be in a reverse conduction state during operation, and the voltage drop between the source and the drain is affected by the gate voltage, the reverse conduction current is larger, and there is a problem of substrate leakage, which will cause higher loss. Therefore, improving the reverse conduction capability of the pGaN enhancement mode HEMT device is crucial to reducing the power consumption of the device. SUMMARY

[0004] The present application provides a pGaN enhancement mode HEMT device structure based on a GaN substrate and a preparation method thereof to solve the problem of reverse conduction leakage caused by structural defects of the pGaN enhancement mode HEMT device.

[0005] According to a first aspect of the present application, a pGaN enhancement mode HEMT device structure based on a GaN substrate is provided, comprising:

[0006] a substrate structure, the substrate structure comprising a first substrate and a buffer layer, a GaN layer formed in sequence on the first substrate in a direction away from the first substrate;

[0007] a Schottky barrier diode, the Schottky barrier diode comprising a p + doped region formed in the GaN layer and an n + doped region formed in the p + doped region, the p + doped region and the n + doped region contact to form a PN junction to constitute the Schottky barrier diode;

[0008] an isolation layer formed on the GaN layer and covering the p + doped region and the n + doped region;

[0009] a pGaN enhanced HEMT device formed on part of the isolation layer;

[0010] wherein the p + doped region and the n + doped region are electrically connected with an anode and a cathode respectively, and the anode is electrically connected with a source of the pGaN enhanced HEMT device; the cathode is electrically connected with a drain of the pGaN enhanced HEMT device.

[0011] Optionally, the pGaN enhanced HEMT device comprises:

[0012] a first nucleation layer, a channel layer and a barrier layer formed on the isolation layer in sequence in a direction away from the isolation layer;

[0013] a source, a gate and a drain formed on the barrier layer; and the gate comprises a pGaN layer and a gate metal layer formed on a top end of the pGaN layer;

[0014] a passivation layer formed on the barrier layer and filling a gap between the source, the gate and the drain.

[0015] Optionally, the pGaN enhanced HEMT device further comprises:

[0016] a gate field plate formed on the gate metal layer and electrically connected with the gate metal layer.

[0017] Optionally, a position of the drain corresponds to a position of the n + doped region in a vertical direction, and an area of the n + doped region along a horizontal direction is greater than an area of the drain along the horizontal direction.

[0018] Optionally, a material of the first substrate is Si, a material of the buffer layer is AlGaN, a material of the isolation layer is Al2O3, a material of the first nucleation layer is AlN, a material of the channel layer is GaN, and a material of the barrier layer is AlGaN.

[0019] According to a second aspect of the present application, a preparation method of a pGaN enhanced HEMT device structure based on a GaN substrate is provided, comprising:

[0020] providing a first substrate, and forming a buffer layer and a GaN layer on the first substrate in sequence in a direction away from the first substrate;

[0021] forming a p + doped region in the GaN layer, and forming an n + doped region in the p + doped region, the p + doped region and the n + doped region contact to form a PN junction to constitute a Schottky barrier diode;

[0022] forming an isolation layer on the GaN layer, and the isolation layer covers the p + doped region and the n + doped region;

[0023] forming a pGaN enhancement mode HEMT device formed on part of the isolation layer;

[0024] forming an anode and a cathode, wherein the anode and the cathode are electrically connected with the p + doped region and the n + doped region respectively, and the anode is electrically connected with a source of the pGaN enhancement mode HEMT device, and the cathode is electrically connected with a drain of the pGaN enhancement mode HEMT device.

[0025] Optionally, the forming a p + doped region in the GaN layer specifically comprises:

[0026] performing p + ion implantation on a first region of the GaN layer;

[0027] performing rapid thermal annealing activation or laser annealing activation on the implanted p + ions to form the p + doped region.

[0028] Optionally, the forming an n + doped region in the p + doped region specifically comprises:

[0029] performing n + ion implantation on a first region of the p + doped region;

[0030] performing rapid thermal annealing activation or laser annealing activation on the implanted n + ions to form the n + doped region.

[0031] Optionally, the forming a pGaN enhancement mode HEMT device specifically comprises:

[0032] forming a first nucleation layer, a channel layer, and a barrier layer in sequence on the isolation layer in a direction away from the isolation layer;

[0033] forming an isolation mesa, wherein the isolation mesa comprises a first isolation mesa located at both ends of the buffer layer along the first direction and a second isolation mesa located at both ends of the isolation layer along the first direction;

[0034] etching the pGaN layer so that the etched pGaN layer only covers part of the barrier layer;

[0035] forming a source and a drain on the barrier layer on both sides of the pGaN layer along the first direction;

[0036] forming a gate metal layer on the etched pGaN layer, and the etched pGaN layer and the gate metal layer constitute a gate.

[0037] Optionally, after forming the gate, it further comprises:

[0038] forming a gate field plate on the top end of the gate metal layer.

[0039] Optionally, the forming of the anode and the cathode, wherein the anode and the cathode are electrically connected to the p + doped region and the n + doped region are electrically connected respectively, and the anode is electrically connected to the source of the pGaN enhancement mode HEMT device, and the cathode is electrically connected to the drain of the pGaN enhancement mode HEMT device, and specifically comprises:

[0040] depositing a passivation layer covering the first isolation mesa, the second isolation mesa, the source, the drain and the gate;

[0041] forming a plurality of openings in the passivation layer, and the plurality of openings respectively penetrate to the p + doped region, the source, the gate, the drain and the n + doped region;

[0042] depositing an electrode metal layer, and the electrode metal layer fills the plurality of through holes, wherein the electrode metal layer electrically connected to the p + doped region constitutes the anode, and the electrode metal layer electrically connected to the n + doped region constitutes the cathode, and the anode is electrically connected to the source; the cathode is electrically connected to the drain; and the electrode metal layer electrically connected to the gate constitutes the gate field plate.

[0043] Optionally, the forming of the isolation mesa specifically comprises:

[0044] The pGaN layer, barrier layer, channel layer and first nucleation layer are etched at both ends along the first direction to form a second isolation mesa at both ends of the isolation layer;

[0045] The isolation layer and GaN layer are etched at both ends along the first direction to form a first isolation mesa at both ends of the buffer layer.

[0046] According to a third aspect of the present invention, an electronic device is provided, comprising the pGaN-enhanced HEMT device structure based on a GaN substrate as described in any of the first aspects of the present invention.

[0047] According to a fourth aspect of the present invention, a method for fabricating an electronic device is provided, comprising the method for fabricating a pGaN-enhanced HEMT device structure based on a GaN substrate as described in any of the second aspects of the present invention.

[0048] This invention provides a pGaN-enhanced HEMT device structure based on a GaN substrate, which is achieved by forming pGaN in the substrate structure. + Doped region and n + The doped region makes p + Doped region and n + The doped regions form a PN junction to constitute a Schottky barrier diode. The anode and cathode of the Schottky barrier diode are electrically connected to the source and drain of the pGaN enhancement-mode HEMT device, respectively. Therefore, the reverse current generated when the device is turned off establishes a current loop through the source, anode, Schottky barrier diode, cathode, and drain, preventing it from flowing through the interior of the pGaN enhancement-mode HEMT device. This avoids the pGaN enhancement-mode HEMT device being affected by reverse current. Furthermore, the presence of this Schottky barrier diode suppresses reverse leakage current in the pGaN enhancement-mode HEMT device.

[0049] Furthermore, in a preferred embodiment, by using n + The doped region is located at the lower end of the drain of the pGaN enhancement-mode HEMT device, and n + The doped region along the horizontal direction is larger than the drain region along the horizontal direction, so that the leakage current can be almost entirely borne by the Schottky barrier diode. Therefore, the leakage current of the pGaN enhancement-mode HEMT device can be almost completely suppressed, thus improving the reliability of the device. Attached Figure Description

[0050] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only need to be some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0051] Figure 1 is a flowchart of a preparation method of a pGaN enhanced HEMT device structure based on a GaN substrate according to an embodiment of the present application;

[0052] Figure 2 is a device structure schematic of different process stages of a preparation method of a pGaN enhanced HEMT device structure based on a GaN substrate according to an embodiment of the present application Figure 1 ;

[0053] Figure 3 is a device structure schematic of different process stages of a preparation method of a pGaN enhanced HEMT device structure based on a GaN substrate according to an embodiment of the present application Figure 2 ;

[0054] Figure 4 is a device structure schematic of different process stages of a preparation method of a pGaN enhanced HEMT device structure based on a GaN substrate according to an embodiment of the present application Figure 3 ;

[0055] Figure 5 is a device structure schematic of different process stages of a preparation method of a pGaN enhanced HEMT device structure based on a GaN substrate according to an embodiment of the present application Figure 4 ;

[0056] Figure 6 is a device structure schematic of different process stages of a preparation method of a pGaN enhanced HEMT device structure based on a GaN substrate according to an embodiment of the present application Figure 5 ;

[0057] Figure 7 is a device structure schematic of different process stages of a preparation method of a pGaN enhanced HEMT device structure based on a GaN substrate according to an embodiment of the present application Figure 6 ;

[0058] Figure 8 is a device structure schematic of different process stages of a preparation method of a pGaN enhanced HEMT device structure based on a GaN substrate according to an embodiment of the present application Figure 7 ;

[0059] Figure 9 This is a schematic diagram of the device structure at different process stages according to the fabrication method of pGaN enhancement-mode HEMT device structure based on GaN substrate provided in an embodiment of the present invention. Figure 8 ;

[0060] Figure 10 This is a schematic diagram of the device structure at different process stages according to the fabrication method of pGaN enhancement-mode HEMT device structure based on GaN substrate provided in an embodiment of the present invention. Figure 9 ;

[0061] Figure 11 This is a schematic diagram of the device structure at different process stages according to the fabrication method of pGaN enhancement-mode HEMT device structure based on GaN substrate provided in an embodiment of the present invention. Figure 10 .

[0062] Explanation of reference numerals in the attached figures:

[0063] 1-First substrate;

[0064] 2-Buffer layer;

[0065] 3-GaN layer;

[0066] 31-p + Doped regions;

[0067] 32-n + Doped regions;

[0068] 4-Isolation layer;

[0069] 5-First nucleation layer;

[0070] 6-Channel layer;

[0071] 7-Barrier layer;

[0072] 8-pGaN layer;

[0073] 9 - First isolation platform;

[0074] 10 - Second isolation surface;

[0075] 11-Source;

[0076] 12-Drain;

[0077] 13-Gate metal layer;

[0078] 14-Passivation layer;

[0079] 15-Through hole;

[0080] 16-Anode;

[0081] 17-Cathode;

[0082] 18-gate field plate. DETAILED DESCRIPTION

[0083] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work belong to the protection scope of the present application.

[0084] The terms "first", "second", "third", "fourth" and the like in the description, claims, and drawings of the present application, and the above-mentioned drawings (if any), are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0085] The pGaN enhancement type HEMT device can improve the utilization of the HEMT device by increasing the pGaN layer to control the depletion or generation of the two-dimensional electron gas, but the pGaN enhancement type HEMT device lacks a body diode, the voltage drop between the source and the drain is affected by the gate voltage, the reverse conduction current is larger, and higher power loss is caused.

[0086] In view of the above problems existing in the traditional pGaN enhancement type HEMT device structure, the present application proposes a new pGaN enhancement type HEMT device structure based on a GaN substrate, by forming a p + The doping region and the n + The doping region, so that the p + The doping region and the n + The doping region contacts to form a PN junction to constitute a Schottky barrier diode, and the anode and the cathode of the Schottky barrier diode are electrically connected with the source and the drain of the pGaN enhancement type HEMT device respectively, therefore, the reverse conduction current generated when the device is turned off will form a current loop of the source, the anode, the Schottky barrier diode, the cathode, and the drain, and will not flow through the inside of the pGaN enhancement type HEMT device, so that the pGaN enhancement type HEMT device can be prevented from being affected by the reverse conduction current. In addition, due to the presence of the Schottky barrier diode, the reverse leakage current of the pGaN enhancement type HEMT device can also be suppressed.

[0087] In addition, in the preferred embodiment, by setting n + The doped region is arranged at the lower end of the drain of the pGaN enhancement mode HEMT device, and n + The area of the doped region in the horizontal direction is greater than the area of the drain in the horizontal direction, so that the leakage current can be substantially completely suppressed by the Schottky barrier diode, thereby improving the reliability of the device.

[0088] The technical solutions of the present application will be described in detail below with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes may not be described in detail in some examples.

[0089] Please refer to Figure 1 According to an embodiment of the present application, a pGaN enhancement mode HEMT device structure based on a GaN substrate is provided, comprising a substrate structure, a Schottky barrier diode, an isolation layer 4, and a pGaN enhancement mode HEMT device; wherein:

[0090] The substrate structure comprises a first substrate 1 and a buffer layer 2, a GaN layer 3 formed in turn on the first substrate 1 in a direction away from the first substrate 1;

[0091] The Schottky barrier diode comprises a p + doped region 31 formed in the GaN layer 3 and an n + doped region 32 formed in the p + doped region 31; + doped region 31 and the n + doped region 32 form a PN junction to constitute the Schottky barrier diode;

[0092] The isolation layer 4 is formed on the GaN layer 3 and covers the p + doped region 31 and the n + doped region 32;

[0093] The pGaN enhancement mode HEMT device is formed on part of the isolation layer 4;

[0094] The p + doped region 31 and the n + doped region 32 are respectively electrically connected to an anode 16 and a cathode 17, and the anode 16 is electrically connected to the source 11 of the pGaN enhancement mode HEMT device; the cathode 17 is electrically connected to the drain 12 of the pGaN enhancement mode HEMT device.

[0095] The pGaN enhancement-mode HEMT device structure provided by this invention forms a PN structure as a Schottky diode in the substrate structure, giving the pGaN enhancement-mode HEMT device a body diode. The source 11 and drain 12 of the pGaN enhancement-mode HEMT device are electrically connected to the anode 16 and cathode 17 of the Schottky diode. Therefore, the reverse conduction current generated when the device is turned off will flow from the source 11 to the anode 16, thereby solving the problem of large reverse conduction current and high power consumption in traditional pGaN enhancement-mode HEMT devices, and achieving the effect of reducing the loss of pGaN enhancement-mode HEMT devices.

[0096] In one embodiment, the pGaN enhancement-mode HEMT device includes: a first nucleation layer 5, a channel layer 6, and a barrier layer 7 sequentially formed on the isolation layer 4 in a direction away from the isolation layer 4;

[0097] A source 11, a gate, and a drain 12 are formed on the barrier layer 7; and the gate includes a pGaN layer 8 and a gate metal layer 13 formed on the top of the pGaN layer 8;

[0098] A passivation layer 14 is formed on the barrier layer 7 and fills the gap between the source 11, the gate and the drain 12.

[0099] In one specific embodiment, the first substrate 1 is made of Si, the buffer layer 2 is made of AlGaN, the isolation layer 4 is made of Al2O3, the first nucleation layer 5 is made of AlN, the channel layer 6 is made of GaN, the barrier layer 7 is made of AlGaN, and the passivation layer 14 is made of Al2O3. Of course, the aforementioned structural layers can also be made of other materials. This invention is not limited to these materials, and any implementation of the corresponding structural layer materials is within the protection scope of this invention.

[0100] In one embodiment, the pGaN enhancement-mode HEMT device further includes:

[0101] A gate field plate 18 is formed on the gate metal layer 13 and electrically connected to the gate metal layer 13.

[0102] In one embodiment, the position of the drain 12 is relative to the n + The positions of the doped regions 32 are vertically corresponding, and the n + The doped region 32 is larger in the horizontal direction than the drain 12.

[0103] As a preferred implementation, n + The doped region 32 is larger in the horizontal direction than the drain region 12, and the n+ The doped region 32 is arranged in the p + doped region 31, so as to block the drain current from leaking to the GaN layer 3, and thus, when the pGaN enhanced HEMT device is turned on, the doped region 32 can prevent the device from leaking.

[0104] Secondly, referring to Figures 2-11 and combining Figure 2 , the embodiment of the present application further provides a preparation method of the pGaN enhanced HEMT device structure based on the GaN substrate, which comprises S1-S6 and is specifically as follows.

[0105] S1: providing a first substrate 1, as shown in Figure 3 .

[0106] S2: sequentially forming a buffer layer 2 and a GaN layer 3 on the first substrate 1 in a direction away from the first substrate 1, as shown in Figure 4 .

[0107] S3: forming a p + doped region 31 in the GaN layer 3, and forming an n + doped region 32 in the p + doped region 31, wherein the p + doped region 31 and the n + doped region 32 form a PN junction to constitute a Schottky barrier diode, as shown in Figure 5 .

[0108] As an example, S3 can specifically comprise the following steps S31-S32.

[0109] S31: performing p + ion implantation on a first region of the GaN layer 3; here, the first region can be the whole GaN layer 3 or a selected region in the GaN layer 3;

[0110] performing rapid thermal annealing activation or laser annealing activation on the implanted p + ions to form the p + doped region 31; here, the p + ions are Mg ions, and of course, other elements can also be selected, and the present application is not limited in this way.

[0111] S32: performing n + ion implantation on the first region of the p + doped region 31;

[0112] performing rapid thermal annealing activation or laser annealing activation on the implanted n + ions to form the n +Doped region 32, here n + The ion is Si ion, of course, it can also be other elements, the present application is not limited thereto.

[0113] S4: Forming an isolation layer 4 on the GaN layer 3, and the isolation layer 4 covers the p + Doped region 31 and the n + Doped region 32, such as Figure 5 As shown.

[0114] S5: Forming a pGaN enhancement mode HEMT device, the pGaN enhancement mode HEMT device is formed on part of the isolation layer 4, as shown. Figure 5 As shown.

[0115] As an example, S5 can include the following steps S51-S53:

[0116] S51: Forming a first nucleation layer 5, a channel layer 6, and a barrier layer 7 on the isolation layer 4 in a direction away from the isolation layer 4, as shown. Figure 6 As shown.

[0117] Forming an isolation mesa, wherein the isolation mesa includes a first isolation mesa 9 located at both ends of the buffer layer 2 along the first direction and a second isolation mesa 10 located at both ends of the isolation layer 4 along the first direction, as shown. Figure 7 As shown.

[0118] Etching the pGaN layer 8 so that the etched pGaN layer 8 only covers part of the barrier layer 7, as shown. Figure 8 As shown.

[0119] Forming a source 11 and a drain 12, the source 11 and the drain 12 are formed on the barrier layer 7 on both sides of the pGaN layer 8 along the first direction, as shown. Figure 8 As shown.

[0120] Forming a gate metal layer 13 on the etched pGaN layer 8, the etched pGaN layer 8 and the gate metal layer 13 constitute a gate, as shown. Figure 8 As shown.

[0121] S52: Etching the pGaN layer 8, barrier layer 7, channel layer 6 and first nucleation layer 5 along both ends of the first direction to form a second isolation mesa 10 at both ends of the isolation layer 4, as shown. Figure 8 As shown.

[0122] Etching the isolation layer 4 and the GaN layer 3 along both ends of the first direction to form a first isolation mesa 9 at both ends of the buffer layer 2, as shown. Figure 11 As shown.

[0123] S53: forming a gate field plate 18 on the top of the gate metal layer 13, as shown in Figure 11 .

[0124] S6: forming an anode 16 and a cathode 17, wherein the anode 16 and the cathode 17 are electrically connected with the p + doped region 31 and the n + doped region 32 respectively, and the anode 16 is electrically connected with the source 11 of the pGaN enhancement mode HEMT device; the cathode 17 is electrically connected with the drain 12 of the pGaN enhancement mode HEMT device, as shown in Figure 9 .

[0125] As an example, S6 can specifically include the following step S61:

[0126] S61: depositing a passivation layer 14 on the first isolation mesa 9, the second isolation mesa 10, the source 11, the drain 12 and the gate, as shown in Figure 10 .

[0127] forming a plurality of openings in the passivation layer 14, wherein the plurality of openings respectively pass through the p + doped region 31, the source 11, the gate, the drain 12 and the n + doped region 32, as shown in Figure 11 .

[0128] depositing an electrode metal layer, wherein the electrode metal layer fills the plurality of through holes 15, and the electrode metal layer electrically connected with the p + doped region 31 constitutes the anode 16, the electrode metal layer electrically connected with the n + doped region 32 constitutes the cathode 17, and the anode 16 is electrically connected with the source 11; the cathode 17 is electrically connected with the drain 12; the electrode metal layer electrically connected with the gate constitutes the gate field plate 18, as shown in ​ .

[0129] Again, according to another embodiment of the present application, an electronic device is also provided, which comprises the pGaN enhancement mode HEMT device structure based on GaN substrate according to any one of the first aspect of the present application.

[0130] According to other embodiments of the present application, a method for manufacturing an electronic device is also provided, which comprises the method for manufacturing the pGaN enhancement mode HEMT device structure based on GaN substrate according to any one of the second aspect of the present application.

[0131] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pGaN-enhanced HEMT device structure based on a GaN substrate, characterized in that, include: A substrate structure, the substrate structure comprising a first substrate and a buffer layer and a GaN layer sequentially formed on the first substrate in a direction away from the first substrate; Schottky barrier diode, the Schottky barrier diode comprising p formed within the GaN layer + Doped regions and formed in the p + n in the doped region + The doped region, the p + The doped region and the n + The doped regions are contacted to form a PN junction to constitute the Schottky barrier diode; An isolation layer is formed on the GaN layer and covers the p + The doped region and the n + Doped regions; pGaN enhancement-mode HEMT devices are formed on a portion of the isolation layer; Wherein, p + Doped regions and the n + The doped regions are electrically connected to the anode and cathode, respectively, and the anode is electrically connected to the source of the pGaN enhancement-mode HEMT device; the cathode is electrically connected to the drain of the pGaN enhancement-mode HEMT device.

2. The pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 1, characterized in that, The pGaN enhancement-mode HEMT device includes: A first nucleation layer, a channel layer, and a barrier layer are sequentially formed on the isolation layer in a direction away from the isolation layer; A source, a gate, and a drain are formed on the barrier layer; and the gate includes a pGaN layer and a gate metal layer formed on top of the pGaN layer; A passivation layer formed on the barrier layer and filling the gap between the source, the gate and the drain.

3. The pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 2, characterized in that, The pGaN-enhanced HEMT device also includes: A gate field plate is formed on the gate metal layer and electrically connected to the gate metal layer.

4. The pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 3, characterized in that, The position of the drain electrode and n + The positions of the doped regions are vertically corresponding, and the n + The doped region along the horizontal direction is larger than the drain region along the horizontal direction.

5. The pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 4, characterized in that, The first substrate is made of Si, the buffer layer is made of AlGaN, the isolation layer is made of Al2O3, the first nucleation layer is made of AlN, the channel layer is made of GaN, and the barrier layer is made of AlGaN.

6. A method for fabricating a pGaN-enhanced HEMT device structure based on a GaN substrate, characterized in that, include: A first substrate is provided, and a buffer layer and a GaN layer are sequentially formed on the first substrate in a direction away from the first substrate; p is formed within the GaN layer + Doped regions, and in the p + n is formed in the doped region + The doped region, the p + The doped region and the n + Doped regions are contacted to form a PN junction to constitute a Schottky barrier diode; An isolation layer is formed on the GaN layer, and the isolation layer covers the p + The doped region and the n + Doped regions; A pGaN enhancement-mode HEMT device is formed on a portion of the isolation layer; Forming an anode and a cathode, wherein the anode and cathode are related to the p + Doped regions and the n + The doped regions are electrically connected, and the anode is electrically connected to the source of the pGaN enhancement-mode HEMT device; the cathode is electrically connected to the drain of the pGaN enhancement-mode HEMT device.

7. The method for fabricating a pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 6, characterized in that, p is formed within the GaN layer + The doped regions specifically include: p + Ion implantation; For the injected p + Ions are activated by rapid thermal annealing or laser annealing to form the p. + Doped region.

8. The method for fabricating a pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 7, characterized in that, The p + n is formed in the doped region + The doped regions specifically include: For the p + The first region of the doped region is subjected to n + Ion implantation; For the injected n + Ions are activated by rapid thermal annealing or laser annealing to form the n. + Doped region.

9. The method for fabricating a pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 8, characterized in that, The formation of pGaN enhancement-mode HEMT devices specifically includes: A first nucleation layer, a channel layer, and a barrier layer are sequentially formed on the isolation layer along a direction away from the isolation layer. An isolation platform is formed, wherein the isolation platform includes a first isolation platform located at both ends of the buffer layer along a first direction and a second isolation platform located at both ends of the isolation layer along a first direction. The pGaN layer is etched so that the etched pGaN layer only covers a portion of the barrier layer; A source and a drain are formed on the barrier layers on both sides of the pGaN layer along the first direction; A gate metal layer is formed on the etched pGaN layer, and the etched pGaN layer and the gate metal layer together constitute a gate.

10. The method for fabricating a pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 9, characterized in that, After the gate is formed, the following is also included: A gate field plate is formed at the top of the gate metal layer.

11. The method for fabricating a pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 10, characterized in that, The anode and cathode are formed, wherein the anode and cathode are related to p. + Doped regions and the n + The doped regions are electrically connected, and the anode is electrically connected to the source of the pGaN enhancement-mode HEMT device; the cathode is electrically connected to the drain of the pGaN enhancement-mode HEMT device, specifically including: A passivation layer is deposited, which covers the first isolation mesa, the second isolation mesa, the source, the drain, and the gate. A plurality of openings are formed in the passivation layer, and the plurality of openings respectively penetrate to the p + The doped region, the source, the gate, the drain, and the n + Doped regions; A deposited electrode metal layer is formed, the electrode metal layer filling the plurality of openings, wherein, with respect to p + The electrode metal layer electrically connected to the doped region constitutes the anode, and is connected to the n + The electrode metal layer electrically connected to the doped region constitutes the cathode, and the anode is electrically connected to the source; the cathode is electrically connected to the drain; and the electrode metal layer electrically connected to the gate constitutes the gate field plate.

12. The method for fabricating a pGaN-enhanced HEMT device structure based on a GaN substrate according to claim 11, characterized in that, The formation of the isolation platform specifically includes: The pGaN layer, barrier layer, channel layer and first nucleation layer are etched at both ends along the first direction to form a second isolation mesa at both ends of the isolation layer; The isolation layer and GaN layer are etched at both ends along the first direction to form a first isolation mesa at both ends of the buffer layer.

13. An electronic device, characterized in that, Includes the pGaN-enhanced HEMT device structure based on a GaN substrate as described in any one of claims 1-5.

14. A method for manufacturing an electronic device, characterized in that, The method for fabricating a pGaN-enhanced HEMT device structure based on a GaN substrate as described in any one of claims 6 to 12.

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