Enhanced Gallium Nitride Power Device, Its Preparation Method, and Electronic Device

Abstract

The present invention provides an enhanced gallium nitride power device, in which a gate dielectric layer is provided between the p-GaN layer and the gate metal layer. Since the conduction band offset of the gate dielectric layer and the p-GaN layer can raise the potential trap position at the AlGaN / GaN heterojunction, making it further away from the Fermi level, the threshold voltage can be effectively increased. At the same time, the introduction of the gate dielectric can improve the gate leakage of the enhanced gallium nitride power device and solve the problem of the small gate voltage swing of the existing enhanced gallium nitride power devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular, to an enhancement-mode gallium nitride power device, a preparation method thereof, and an electronic device. Background Art

[0002] Due to its excellent material properties, such as high breakdown field strength and high electron mobility, gallium nitride high electron mobility transistors (AlGaN / GaN HEMTs) have extremely broad application prospects in the radio frequency and power fields. The strong polarization effect causes a large amount of two-dimensional electron gas to be generated in the AlGaN / GaN heterojunction. Therefore, conventional AlGaN / GaN HEMTs are depletion-mode devices with a negative threshold voltage. Considering simplifying the circuit design and improving the system reliability at the same time, power conversion circuits usually require high-performance enhancement-mode (or normally-closed type) transistors, that is, the device can be turned on only when the gate voltage is positive.

[0003] Among the existing several schemes for realizing normally-closed devices, p-type gate gallium nitride high mobility transistors (p-GaN Gate HEMTs) have relatively comprehensive electrical properties and thus have been increasingly applied.

[0004] However, for p-GaN Gate HEMTs, due to the very low hole activation concentration in the p-GaN layer, its threshold voltage is not high (<2V), which easily causes mis-turn-on of the device. In addition, when the forward gate voltage increases, the PN junction under the gate is turned on, and the gate-drain current will increase rapidly. Therefore, the gate voltage swing is also small (<8V), which not only increases the circuit design cost but also severely limits its application scenarios.

[0005] Therefore, it is necessary to improve p-GaN Gate HEMTs. Summary of the Invention

[0006] The present invention provides an enhancement-mode gallium nitride power device, a preparation method thereof, and an electronic device to increase the threshold voltage of the enhancement-mode gallium nitride power device.

[0007] According to a first aspect of the present invention, there is provided an enhancement-mode gallium nitride power device, comprising:

[0008] a substrate;

[0009] an epitaxial structure, the epitaxial structure including a stacked AlN nucleation layer, a buffer layer, a GaN channel layer, an AlN insertion layer, and an AlGaN barrier layer formed on the substrate in sequence along a direction away from the substrate;

[0010] a p-GaN layer formed on a first region of the AlGaN barrier layer;

[0011] A gate dielectric layer covering the p-GaN layer and other regions of the AlGaN barrier layer; the other regions are the AlGaN barrier layer except for the first region;

[0012] A source ohmic contact electrode and a drain ohmic contact electrode, which penetrate the gate dielectric layer and contact the AlGaN barrier layer, and the source ohmic contact electrode and the drain ohmic contact electrode are respectively located on both sides of the p-GaN layer;

[0013] A gate metal layer formed on the gate dielectric layer, located directly above the p-GaN layer and matching the p-GaN layer;

[0014] A passivation layer covering the gate metal layer, the source ohmic contact electrode, the drain ohmic contact electrode, and the gate dielectric layer;

[0015] A metal interconnection layer including a source metal interconnection layer, a drain metal interconnection layer, and a gate metal interconnection layer. The source metal interconnection layer, the drain metal interconnection layer, and the gate metal interconnection layer penetrate the passivation layer and are electrically connected to the source ohmic contact electrode, the drain ohmic contact electrode, and the gate metal layer respectively.

[0016] Optionally, the material of the gate dielectric layer is Al 2 O 3 , AlN, SiO 2 , HfO 2 , SiN x or any one of their laminated combinations.

[0017] Optionally, the laminated combination includes AlN / SiO 2 .

[0018] Optionally, the thickness of the gate dielectric layer is 2 - 10 nm.

[0019] Optionally, the source ohmic contact electrode and the drain ohmic contact electrode extend into the AlGaN barrier layer, and the distance from the bottom of the source ohmic contact electrode and the drain ohmic contact electrode to the bottom of the AlGaN barrier layer is 2 - 4 nm.

[0020] Optionally, the materials of the source ohmic contact electrode and the drain ohmic contact electrode are Ti / Al / Ni / Au laminated metal.

[0021] Optionally, in the Ti / Al / Ni / Au laminated metal, the thickness of the Ti metal is 20 nm, the thickness of the Al metal is 120 nm, the thickness of the Ni metal is 50 nm, and the thickness of the Au metal is 100 nm.

[0022] Optionally, the material of the gate metal layer is Ni / Au laminated metal.

[0023] Optionally, the thickness of the Ni metal in the Ni / Au laminated metal is 40 nm, and the thickness of the Au metal is 60 nm.

[0024] Optionally, the passivation layer is a SiN layer with a thickness of 40 - 80 nm.

[0025] According to the second aspect of the present invention, a method for manufacturing an enhanced gallium nitride power device is provided, which is used to manufacture the enhanced gallium nitride power device involved in the first aspect and the optional solutions. The method includes:

[0026] Provide a substrate;

[0027] Form an epitaxial structure, which includes a stacked AlN nucleation layer, a buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-GaN layer formed on the substrate in sequence along the direction away from the substrate.

[0028] Perform active region isolation to form isolation layers on both sides of the p-GaN layer, the AlGaN barrier layer, the AlN insertion layer, and the GaN channel layer.

[0029] Etch the p-GaN layer so that it only covers the first region of the AlGaN barrier layer.

[0030] Form a gate dielectric layer, which is formed on the p-GaN layer and other regions of the AlGaN barrier layer; the other regions are the AlGaN barrier layer except the first region.

[0031] Form a source ohmic contact electrode and a drain ohmic contact electrode. The source ohmic contact electrode and the drain ohmic contact electrode penetrate the gate dielectric layer and then contact the AlGaN barrier layer, and the source ohmic contact electrode and the drain ohmic contact electrode are respectively located on both sides of the p-GaN layer.

[0032] Form a gate metal layer, which is formed on the gate dielectric layer, directly above the p-GaN layer and matches the p-GaN layer.

[0033] Form a passivation layer, which covers the gate metal layer, the source ohmic contact electrode, the drain ohmic contact electrode, and the gate dielectric layer.

[0034] A metal interconnect layer is formed. The metal interconnect layer includes a source metal interconnect layer, a drain metal interconnect layer, and a gate metal interconnect layer. After passing through the passivation layer, the source metal interconnect layer, the drain metal interconnect layer, and the gate metal interconnect layer are electrically connected to the source ohmic contact electrode, the drain ohmic contact electrode, and the gate metal layer, respectively.

[0035] Optionally, before forming the p-GaN layer and after forming the epitaxial structure, the method further includes:

[0036] Performing active region isolation to form isolation layers in the AlGaN barrier layer, the AlN insertion layer, and the GaN channel layer.

[0037] According to the third aspect of the present invention, an electronic device is provided, including the enhanced gallium nitride power device involved in the first aspect and the optional solutions.

[0038] In the enhanced gallium nitride power device provided by the present invention, a gate dielectric layer is provided between the p-GaN layer and the gate metal layer. Since the conduction band offset between the gate dielectric layer and the p-GaN layer can raise the potential well position at the AlGaN / GaN heterojunction, making it further away from the Fermi level, the threshold voltage can be effectively increased. At the same time, the introduction of the gate dielectric can improve the gate leakage of the enhanced gallium nitride power device and solve the problem of the small gate voltage swing of the existing enhanced gallium nitride power devices. Description of the Drawings

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0040] Figure 1 It is a schematic cross-sectional structure diagram of an enhanced gallium nitride power device provided by an embodiment of the present invention;

[0041] Figure 2 It is a schematic flowchart of a preparation method of an enhanced gallium nitride power device provided by an embodiment of the present invention;

[0042] Figures 3A - 3I It is a schematic cross-sectional structure diagram of a device at different process stages according to the preparation method of an enhanced gallium nitride power device provided by an embodiment of the present invention;

[0043] Figures 4A - 4C It is a schematic diagram of the measurement results of device characteristics provided by an embodiment of the present invention.

[0044] Description of the Reference Numerals:

[0045] 201 - Substrate;

[0046] 202 - AlN Nucleation Layer;

[0047] 203 - Buffer Layer;

[0048] 204 - GaN Channel Layer;

[0049] 205 - AlN Insertion Layer;

[0050] 206 - AlGaN Barrier Layer;

[0051] 207 - p - GaN Layer;

[0052] 208 - Isolation Layer;

[0053] 209 - Gate Dielectric Layer;

[0054] 210 - Source Ohmic Contact Electrode;

[0055] 211 - Drain Ohmic Contact Electrode;

[0056] 212 - Gate Metal Layer;

[0057] 213 - Passivation Layer;

[0058] 214 - Source Metal Interconnection Layer;

[0059] 215 - Drain Metal Interconnection Layer;

[0060] 216 - Gate Metal Interconnection Layer. Detailed Embodiment

[0061] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0062] In the description, claims, and above-mentioned drawings of the present invention, terms such as "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or devices.

[0063] Due to its advantages such as wide bandgap, high electron mobility, and large breakdown electric field, gallium nitride, a third-generation semiconductor material, has extremely broad application prospects in commercial application fields such as high-frequency power amplifiers and power switching devices.

[0064] For a traditional p-type gate gallium nitride high electron mobility transistor, a gate metal layer is directly covered on its p-GaN layer and then led out through a gate metal interconnection layer. Since the hole activation concentration in the p-GaN layer is very low, its threshold voltage is not high (<2V), which easily causes misturn-on of the device. In addition, when the forward gate voltage increases, the PN junction under the gate is turned on, and the gate leakage current will increase rapidly. Therefore, the gate voltage swing is also small (<8V), which not only increases the circuit design cost but also severely limits its application scenarios.

[0065] In view of this, the inventors have found through repeated design and experiments that setting a gate dielectric layer between the p-GaN layer and the gate metal layer can increase the threshold voltage of the device, thereby improving the gate leakage of the enhancement-mode gallium nitride power device, and thus solving the problem of the small gate voltage swing of the existing enhancement-mode gallium nitride power device.

[0066] The technical solution of the present invention will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0067] Please refer to Figure 1 , according to an embodiment of the present invention, there is provided an enhancement-mode gallium nitride power device, including:

[0068] A substrate 201;

[0069] An epitaxial structure, which includes a stacked AlN nucleation layer 202, a buffer layer 203, a GaN channel layer 204, an AlN insertion layer 205, and an AlGaN barrier layer 206 formed on the substrate 201 in sequence along the direction away from the substrate 201;

[0070] The p-GaN layer 207 is formed on the first region of the AlGaN barrier layer 206; wherein, the first region is generally the relatively central region of the AlGaN barrier layer 206;

[0071] The gate dielectric layer 209 covers the p-GaN layer 207 and other regions of the AlGaN barrier layer 206; the other regions are the AlGaN barrier layer except the first region;

[0072] The source ohmic contact electrode 210 and the drain ohmic contact electrode 211 penetrate through the gate dielectric layer 209 and then contact with the AlGaN barrier layer 206, and the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 are respectively located on both sides of the p-GaN layer 207;

[0073] The gate metal layer 212 is formed on the gate dielectric layer 209, located directly above the p-GaN layer 207 and matching the p-GaN layer 207; wherein, the matching here refers to size matching, that is, the length and width of the gate metal layer 212 match the length and width of the p-GaN layer 207;

[0074] The passivation layer 213 covers the gate metal layer 212, the source ohmic contact electrode 210, the drain ohmic contact electrode 211 and the gate dielectric layer 209;

[0075] The metal interconnection layer includes a source metal interconnection layer 214, a drain metal interconnection layer 215 and a gate metal interconnection layer 216. The source metal interconnection layer 214, the drain metal interconnection layer 215 and the gate metal interconnection layer 216 penetrate through the passivation layer 213 and are respectively electrically connected to the source ohmic contact electrode 210, the drain ohmic contact electrode 211 and the gate metal layer 212.

[0076] In an embodiment of the present invention, the material of the gate dielectric layer 209 is Al 2 O 3 、AlN、SiO 2 、HfO 2 、SiN x Any one of them and their stacked combinations. As a preferred embodiment, the stacked combination includes AlN / SiO 2 . Of course, it should be realized that the present invention is not limited thereto, and the materials of other gate dielectric layers are also within the protection scope of the present invention.

[0077] As an implementation manner, the thickness of the gate dielectric layer 209 is 2 - 10 nm. Of course, it should be realized that the present invention is not limited thereto, and other thickness values of the gate dielectric layer are also within the protection scope of the present invention.

[0078] As an implementation manner, the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 extend into the AlGaN barrier layer 206, and the distance from the bottom of the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 to the bottom of the AlGaN barrier layer 206 is 2 - 4 nm. Of course, it should be realized that this distance is only an example, and the present invention is not limited thereto, and other distance values are also within the protection scope of the present invention.

[0079] As an implementation manner, the materials of the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 are Ti / Al / Ni / Au stacked metals. In an example, the thickness of the Ti metal in the Ti / Al / Ni / Au stacked metals is 20 nm, the thickness of the Al metal is 120 nm, the thickness of the Ni metal is 50 nm, and the thickness of the Au metal is 100 nm. Of course, it should be realized that the materials and thicknesses of the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 should not be construed as limitations on the present invention, and other materials and thicknesses are also within the protection scope of the present invention.

[0080] As an implementation manner, the material of the gate metal layer 212 is Ni / Au stacked metals. In an example, the thickness of the Ni metal in the Ni / Au stacked metals is 40 nm, and the thickness of the Au metal is 60 nm. Of course, it should be realized that the materials and thicknesses of the gate metal layer 212 should not be construed as limitations on the present invention, and other materials and thicknesses are also within the protection scope of the present invention.

[0081] As an implementation manner, the passivation layer 213 is a SiN layer, and its thickness is 40 - 80 nm. Of course, it should be realized that the materials and thicknesses of the passivation layer 213 should not be construed as limitations on the present invention, and other materials and thicknesses are also within the protection scope of the present invention.

[0082] For the enhanced gallium nitride power device provided by the present invention, a gate dielectric layer is disposed between the p-GaN layer and the gate metal layer. Since the conduction band offset between the gate dielectric layer and the p-GaN layer can raise the potential well position at the AlGaN / GaN heterojunction, making it further away from the channel, the threshold can be increased. At the same time, the introduction of the gate dielectric can improve the gate leakage of the enhanced gallium nitride power device and solve the problem of the small gate voltage swing of the existing enhanced gallium nitride power devices.

[0083] Specifically, in practical applications, for example, the original threshold voltage of 1-2V can be increased to 3-4V. Of course, the specific value of the threshold voltage is related to the dielectric thickness and interface quality.

[0084] Please continue to refer to Figure 2 and Figures 3A - 3I , the embodiment of the present invention also provides a method for manufacturing an enhanced gallium nitride power device for manufacturing the aforementioned enhanced gallium nitride power device, the method comprising:

[0085] S1: Provide a substrate 201, as Figure 3A shown.

[0086] S2: Form an epitaxial structure, the epitaxial structure comprising a stacked AlN nucleation layer 202, a buffer layer 203, a GaN channel layer 204, an AlN insertion layer 205, an AlGaN barrier layer 206, and a p-GaN layer 207 formed in sequence on the substrate in a direction away from the substrate 201; as Figure 3B shown.

[0087] S3: Perform active region isolation, and form isolation layers on both sides of the p-GaN layer 207, the AlGaN barrier layer 206, the AlN insertion layer 205, and the GaN channel layer 204; to isolate the active region. The schematic diagram of the device structure after this step is as Figure 3C shown.

[0088] As a specific implementation, for example, the regions on both sides of the p-GaN layer 207, the AlGaN barrier layer 206, the AlN insertion layer 205, and the GaN channel layer 204 can be implanted with ions of elements such as N and F to form isolation layers; or the regions on both sides of the p-GaN layer 207, the AlGaN barrier layer 206, the AlN insertion layer 205, and the GaN channel layer 204 can be etched with a Cl-based gas and then filled with isolation layers. Of course, it should be realized that the present invention is not limited thereto, and other methods for forming mesa isolation are also within the protection scope of the present invention.

[0089] S4: Etch the p-GaN layer 207 so that it only covers the first region of the AlGaN barrier layer 206. The schematic diagram of the device structure after this step is as Figure 3D shown.

[0090] Wherein, the first region is the gate region.

[0091] Among them, in one example, Cl 2 / O 2 or BCl 3 / SF 6The gas combination is used to selectively etch the p-GaN layer 207; of course, the etching gas is not limited to these forms, and the use of other etching gases is also within the protection scope of the present invention.

[0092] S5: Form a gate dielectric layer 209, and the gate dielectric layer 209 is formed on other regions of the p-GaN layer 207 and the AlGaN barrier layer 206; the other regions are the AlGaN barrier layers except the first region; the schematic diagram of the device structure after this step is as Figure 3E shown.

[0093] In one example, the gate dielectric layer 209 can be formed by atomic layer deposition (ALD). Specifically, for example, 10 nm of AlN or 10 nm of Al 2 O 3 or 2 nm of AlN / 8 nm of Al 2 O 3 is used as the gate dielectric layer 209.

[0094] In one example, after depositing the gate dielectric layer 209, an annealing treatment is also performed on the gate dielectric layer 209. Specifically, for example, annealing is performed at 500 °C for 60 seconds. Of course, the annealing temperature and annealing time can be adjusted according to the actual situation.

[0095] S6: Form a source ohmic contact electrode 210 and a drain ohmic contact electrode 211. The source ohmic contact electrode 210 and the drain ohmic contact electrode 211 penetrate through the gate dielectric layer 209 and then contact the AlGaN barrier layer 206, and the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 are respectively located on both sides of the p-GaN layer 207; the schematic diagram of the device structure after this step is as Figure 3F shown.

[0096] In one example, forming the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 specifically includes: etching the AlGaN barrier layer 206 in the corresponding region until 2 - 4 nm remains, and then depositing a Ti / Al / Ni / Au stacked metal in the corresponding region.

[0097] In one example, the thickness of the Ti metal in the Ti / Al / Ni / Au stacked metal is 20 nm, the thickness of the Al metal is 120 nm, the thickness of the Ni metal is 50 nm, and the thickness of the Au metal is 100 nm. Of course, it should be realized that the specific materials of the source ohmic contact electrode 210 and the drain ohmic contact electrode 211 are not limited to this, and their thicknesses can also be adjusted according to actual needs.

[0098] In one example, after depositing the Ti / Al / Ni / Au stacked metal, the Ti / Al / Ni / Au stacked metal is also annealed at a low temperature. As a specific implementation, the conditions for the low-temperature annealing are, for example: annealing at a temperature of 550 °C for 30 seconds in an N 2 gas atmosphere. Of course, the annealing conditions are only an example and should not be construed as a limitation of the present invention, and can be adjusted according to actual needs.

[0099] S7: Form a gate metal layer 212, the gate metal layer 212 is formed on the gate dielectric layer 209, directly above the p-GaN layer 207 and matches the p-GaN layer 207; the schematic diagram of the device structure after this step is as Figure 3G shown. Among them, being matched can be understood as being matched in size, for example, the length and width are equal.

[0100] In one example, the Ni / Au stacked metal can be deposited by ALD as the gate metal layer 212. In one example, the thickness of the Ni metal in the Ni / Au stacked metal is 40 nm, and the thickness of the Au metal is 60 nm. Of course, it should be realized that the material and thickness of the gate metal layer 212 should not be construed as a limitation of the present invention, and other materials and thicknesses are also within the protection scope of the present invention.

[0101] S8: Form a passivation layer 213, the passivation layer 213 covers the gate metal layer 212, the source ohmic contact electrode 210, the drain ohmic contact electrode 211, and the gate dielectric layer 209; the schematic diagram of the device structure after this step is as Figure 3H shown.

[0102] In one example, for example, SiN can be deposited by PECVD as the passivation layer 213. In one example, the thickness of the SiN passivation layer is 60 nm. Of course, it should be realized that the material and thickness of the passivation layer 213 should not be construed as a limitation of the present invention, and other materials and thicknesses are also within the protection scope of the present invention.

[0103] S9: Form a metal interconnection layer, the metal interconnection layer includes a source metal interconnection layer 214, a drain metal interconnection layer 215, and a gate metal interconnection layer 216. The source metal interconnection layer 214, the drain metal interconnection layer 215, and the gate metal interconnection layer 216 penetrate through the passivation layer 213 and are respectively electrically connected to the source ohmic contact electrode 210, the drain ohmic contact electrode 211, and the gate metal layer 212. The schematic diagram of the device structure after this step is as Figure 3I shown.

[0104] Regarding the performance of the enhanced gallium nitride power device of the present invention, please refer to Figures 4A - 4C , whereFigure 4A is the output curve of the enhanced gallium nitride power device, where the abscissa (V DS ) is the drive voltage of the source-drain, and the ordinate I DS (mA / mm)) is the output current of the enhanced gallium nitride power device; the four curves respectively represent the change curves of the output current of the enhanced gallium nitride power device with the drive voltage of the source-drain when the gate voltage is increased from 0V to 15V with a step of 3V; from Figure 4A it can be obtained that the enhanced gallium nitride power device provided by the present invention has good output performance and a strong current output ability.

[0105] Figure 4B is the transfer curve diagram of the enhanced gallium nitride power device provided by the present invention, where the abscissa (V GS ) is the gate voltage, and the ordinate I DS (mA / mm)) is the source-drain conduction current; from Figure 4B it can be seen that the switching ratio of the enhanced gallium nitride power device provided by the present invention can reach 10 7 or more, and the threshold voltage is greater than 2V, which is significantly higher than the threshold voltage of the traditional p-GaN GateHEMT device.

[0106] Figure 4C is the transfer curve diagram of the enhanced gallium nitride power device provided by the present invention, where the abscissa (V GS ) is the gate voltage, and the ordinate I GS (mA / mm)) is the gate-source current. It can be seen that the gate voltage swing of the enhanced gallium nitride power device provided by the present invention can reach 15V or more.

[0107] It can be seen that the enhanced gallium nitride power device provided by the present invention has excellent performance.

[0108] In addition, the present invention also provides an electronic device, including the enhanced gallium nitride power device involved in the above embodiments.

[0109] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An enhanced gallium nitride power device, characterized in that, it includes: a substrate; an epitaxial structure, which includes a stacked AlN nucleation layer, a buffer layer, a GaN channel layer, an AlN insertion layer, and an AlGaN barrier layer formed on the substrate in sequence along the direction away from the substrate; a p-GaN layer formed on a first region of the AlGaN barrier layer; a gate dielectric layer covering the p-GaN layer and other regions of the AlGaN barrier layer; the other regions are the AlGaN barrier layer except the first region; a source ohmic contact electrode and a drain ohmic contact electrode, which penetrate the gate dielectric layer and then contact the AlGaN barrier layer, and the source ohmic contact electrode and the drain ohmic contact electrode are respectively located on both sides of the p-GaN layer; a gate metal layer formed on the gate dielectric layer, located directly above the p-GaN layer and matching the p-GaN layer; a passivation layer covering the gate metal layer, the source ohmic contact electrode, the drain ohmic contact electrode, and the gate dielectric layer; a metal interconnection layer, including a source metal interconnection layer, a drain metal interconnection layer, and a gate metal interconnection layer, and the source metal interconnection layer, the drain metal interconnection layer, and the gate metal interconnection layer penetrate the passivation layer and are respectively electrically connected to the source ohmic contact electrode, the drain ohmic contact electrode, and the gate metal layer.

2. The enhanced gallium nitride power device according to claim 1, characterized in that, The material of the gate dielectric layer is Al 2 O 3 , AlN, SiO 2 , HfO 2 , SiN x or any one of their laminated combinations.

3. The enhanced gallium nitride power device according to claim 2, characterized in that, The laminated combination includes AlN / SiO 2 .

4. The enhanced gallium nitride power device according to claim 2, characterized in that, the thickness of the gate dielectric layer is 2 - 10 nm.

5. The enhanced gallium nitride power device according to claim 1, characterized in that, the source ohmic contact electrode and the drain ohmic contact electrode extend into the AlGaN barrier layer, and the distance from the bottom of the source ohmic contact electrode and the drain ohmic contact electrode to the bottom of the AlGaN barrier layer is 2 - 4 nm.

6. The enhanced gallium nitride power device according to claim 5, characterized in that, the materials of the source ohmic contact electrode and the drain ohmic contact electrode are Ti / Al / Ni / Au laminated metal.

7. The enhanced gallium nitride power device according to claim 6, characterized in that, in the Ti / Al / Ni / Au laminated metal, the thickness of the Ti metal is 20 nm, the thickness of the Al metal is 120 nm, the thickness of the Ni metal is 50 nm, and the thickness of the Au metal is 100 nm.

8. The enhanced gallium nitride power device according to claim 1, characterized in that, the material of the gate metal layer is Ni / Au laminated metal.

9. The enhanced gallium nitride power device according to claim 8, characterized in that, in the Ni / Au laminated metal, the thickness of the Ni metal is 40 nm, and the thickness of the Au metal is 60 nm.

10. The enhanced gallium nitride power device according to claim 1, characterized in that, The passivation layer is a SiN layer with a thickness of 40 - 80 nm.

11. A method for manufacturing an enhanced gallium nitride power device, which is used to manufacture the enhanced gallium nitride power device according to any one of claims 1 - 10, characterized in that, the method comprises: providing a substrate; forming an epitaxial structure, which includes a stacked AlN nucleation layer, a buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-GaN layer formed on the substrate in sequence along the direction away from the substrate; performing active region isolation to form isolation layers on both sides of the p-GaN layer, the AlGaN barrier layer, the AlN insertion layer, and the GaN channel layer; etching the p-GaN layer so that it only covers a first region of the AlGaN barrier layer; forming a gate dielectric layer, which is formed on the p-GaN layer and other regions of the AlGaN barrier layer; the other regions are the AlGaN barrier layer except the first region; forming a source ohmic contact electrode and a drain ohmic contact electrode, the source ohmic contact electrode and the drain ohmic contact electrode penetrate through the gate dielectric layer and then contact the AlGaN barrier layer, and the source ohmic contact electrode and the drain ohmic contact electrode are respectively located on both sides of the p-GaN layer; forming a gate metal layer, which is formed on the gate dielectric layer, directly above the p-GaN layer and matches the p-GaN layer; forming a passivation layer, which covers the gate metal layer, the source ohmic contact electrode, the drain ohmic contact electrode, and the gate dielectric layer; forming a metal interconnection layer, which includes a source metal interconnection layer, a drain metal interconnection layer, and a gate metal interconnection layer, the source metal interconnection layer, the drain metal interconnection layer, and the gate metal interconnection layer penetrate through the passivation layer and are respectively electrically connected to the source ohmic contact electrode, the drain ohmic contact electrode, and the gate metal layer.

12. The method for manufacturing an enhanced gallium nitride power device according to claim 11, characterized in that, before forming the p-GaN layer and after forming the epitaxial structure, the method further comprises: performing active region isolation to form isolation layers in the AlGaN barrier layer, the AlN insertion layer, and the GaN channel layer.

13. An electronic device, characterized in that, it includes the enhanced gallium nitride power device according to any one of claims 1 - 10.

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