Semiconductor device and method of manufacturing the same

Abstract

This invention discloses a semiconductor device and its fabrication method, wherein the semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source / drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed within the semiconductor substrate. The first source / drain region is disposed within the first drift region. At least a portion of a first portion of the gate oxide layer is disposed vertically between the gate structure and the semiconductor substrate. A second portion of the gate oxide layer is disposed horizontally between the first portion and the first source / drain region. The second portion includes a bottom extending downwards and a first recessed upper surface located above the bottom. A portion of the first drift region is located below the first and second portions of the gate oxide layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device with a gate oxide layer and a method for manufacturing the same. Background Technology

[0002] In power devices with high-voltage handling capabilities, double-diffused MOS (DMOS) transistors continue to receive significant attention. Common DMOS transistors include vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors. LDMOS transistors, due to their high operating bandwidth and efficiency, as well as their planar structure that facilitates integration with other integrated circuits, are now widely used in high-voltage operating environments, such as CPU power supplies, power management systems, AC / DC converters, and high-power or high-frequency power amplifiers. A key characteristic of LDMOS transistors is the use of a large-area lateral diffusion drift region with low doping concentration to mitigate the high voltage between the source and drain terminals, thus enabling them to achieve a high breakdown voltage. However, as product requirements become increasingly stringent, improving the electrical performance and / or density of high-voltage semiconductor devices through structural and / or fabrication process design adjustments remains a continuous area of ​​research for those in the field. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method thereof, which utilizes a gate oxide layer having a downwardly extending bottom and a corresponding recessed upper surface, and a drift region partially disposed below the gate oxide layer to improve the relevant electrical performance of the semiconductor device and / or reduce the area occupied by the semiconductor device.

[0004] An embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a gate structure, a first drift region, a first source / drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate and located on one side of the gate structure. The first source / drain region is disposed in the first drift region. The gate oxide layer includes a first portion and a second portion. At least a portion of the first portion is disposed in a vertical direction between the gate structure and the semiconductor substrate. The second portion is disposed in a horizontal direction between the first portion of the gate oxide layer and the first source / drain region. The second portion of the gate oxide layer includes a bottom extending downward and a first recessed upper surface located above the bottom in a vertical direction. A portion of the first drift region is located in a vertical direction below the first and second portions of the gate oxide layer.

[0005] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: forming a first drift region in a semiconductor substrate; forming a gate oxide layer on the semiconductor substrate; forming a gate structure on the gate oxide layer, wherein the first drift region is located on one side of the gate structure; forming a first source / drain region in the first drift region; the gate oxide layer comprising a first portion and a second portion; at least a portion of the first portion being disposed in a vertical direction between the gate structure and the semiconductor substrate; the second portion being disposed in a horizontal direction between the first portion of the gate oxide layer and the first source / drain region; the second portion of the gate oxide layer comprising a bottom extending downward and a first recessed upper surface located above the bottom in a vertical direction; a portion of the first drift region being located below the first portion and the second portion of the gate oxide layer in a vertical direction. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a semiconductor device according to a first embodiment of the present invention;

[0007] Figures 2 to 7 This is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein...

[0008] Figure 3 for Figure 2 A diagram illustrating the subsequent situation;

[0009] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0010] Figure 5 for Figure 4 A diagram illustrating the subsequent situation;

[0011] Figure 6 for Figure 5 A diagram illustrating the subsequent situation;

[0012] Figure 7 for Figure 6 A diagram illustrating the subsequent situation.

[0013] Figure 8 This is a schematic diagram of a semiconductor device according to a second embodiment of the present invention;

[0014] Figure 9 and Figure 10 This is a schematic diagram of a method for fabricating a semiconductor device according to a second embodiment of the present invention, wherein... Figure 10 for Figure 9 A diagram illustrating the subsequent situation.

[0015] Explanation of main component symbols

[0016] 10 Semiconductor substrate

[0017] 10C Ditch Area

[0018] 12 Patterned Mask Layers

[0019] 14 Patterned Mask Layer

[0020] 22 First Drift Zone

[0021] 22A Part 1

[0022] 22B Part 2

[0023] 24 Second Drift Zone

[0024] 24A Part 1

[0025] 24B Part Two

[0026] 26 Patterned Mask Layers

[0027] 30 Gate oxide layer

[0028] 40 Gate Structure

[0029] 42 First gap wall

[0030] 44 Second spacer wall

[0031] 52 First source / drain region

[0032] 54 Second source / drain region

[0033] 62 First silicide layer

[0034] 64 Second silicide layer

[0035] 91 Doping process

[0036] 92 Oxidation Process

[0037] 101 Semiconductor Device

[0038] 102 Semiconductor Device

[0039] AX axis

[0040] BM1 bottom

[0041] BM2 bottom

[0042] BM3 bottom

[0043] BM4 bottom

[0044] BM5 bottom

[0045] D1 Vertical direction

[0046] D2 Horizontal direction

[0047] DS distance

[0048] P1 Part 1

[0049] Part 2, Page 2

[0050] Part 3, Page 3

[0051] S1 upper surface

[0052] S2 bottom surface

[0053] SP gap wall structure

[0054] TK Thickness

[0055] TR1 First Trench

[0056] TR2 Second Trench

[0057] TS1 upper surface

[0058] TS2 upper surface

[0059] TS3 upper surface

[0060] TS4 upper surface

[0061] TS5 top surface Detailed Implementation

[0062] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0063] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0064] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0065] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0066] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term that includes etching.

[0067] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0068] Please see Figure 1 . Figure 1 The illustration shows a schematic diagram of a semiconductor device 101 according to a first embodiment of the present invention. Figure 1 As shown, the semiconductor device 101 includes a semiconductor substrate 10, a gate structure 40, a first drift region 22, a first source / drain region 52, and a gate oxide layer 30. The gate structure 40 and the gate oxide layer 30 are disposed on the semiconductor substrate 10. The first drift region 22 is disposed in the semiconductor substrate 10 and located on one side of the gate structure 40. The first source / drain region 52 is disposed in the first drift region 22. The gate oxide layer 30 includes a first portion P1 and a second portion P2. At least a portion of the first portion P1 is in a vertical direction (e.g., Figure 1The second part P2 is disposed between the gate structure 40 and the semiconductor substrate 10 in a vertical direction D1 (or / other directions parallel to the vertical direction D1). Figure 1 The gate oxide layer 30 is disposed between the first portion P1 and the first source / drain region 52 in the horizontal direction D2 (or / other directions parallel to the horizontal direction D2). The second portion P2 of the gate oxide layer 30 includes a bottom BM3 extending downward and a first recessed upper surface (e.g., ...). Figure 1 The upper surface TS3 shown is located above the bottom BM3 in the vertical direction D1. A portion of the first drift region 22 is located below the first portion P1 and the second portion P2 of the gate oxide layer 30 in the vertical direction D1. By utilizing the second portion P2 of the gate oxide layer 30 with the downwardly extending bottom BM3 and the corresponding recessed upper surface, the current path in the first drift region 22 located below the gate oxide layer 30 can be extended downward in the vertical direction D1. Therefore, the electrical performance of the semiconductor device 101 can be improved by increasing the current path (e.g., reducing the edge electric field, improving the ability to withstand hot carrier injection, etc., but not limited thereto) and / or the area occupied by the first drift region 22 and the semiconductor device 101 can be relatively reduced under certain current path specifications, which helps to increase the number and / or density of semiconductor devices 101.

[0069] In some embodiments, the aforementioned vertical direction D1 can be considered as the thickness direction of the semiconductor substrate 10, and the semiconductor substrate 10 may have an opposing upper surface in the vertical direction D1. Figure 1 (Not shown) and a bottom surface S2. In some embodiments, the gate structure 40 and the gate oxide layer 30 may be disposed on the upper surface of the semiconductor substrate 10, and the bottom BM3 of the second portion P2 of the gate oxide layer 30 may be considered to protrude and extend toward the bottom surface S2. In addition, horizontal directions that are substantially orthogonal to the vertical direction D1 (e.g., horizontal direction D2 and other directions orthogonal to the vertical direction D1) may be substantially parallel to the upper surface and / or the bottom surface S2 of the semiconductor substrate 10, but are not limited thereto. In this document, the distance in the vertical direction D1 between a relatively high position or / and a component and the bottom surface S2 of the semiconductor substrate 10 may be greater than the distance in the vertical direction D1 between a relatively low position or / and a component and the bottom surface S2 of the semiconductor substrate 10. The lower part or bottom of each component may be closer to the bottom surface S2 of the semiconductor substrate 10 in the vertical direction D1 than the upper part or top of the component. Another component above a component may be considered to be relatively far away from the bottom surface S2 of the semiconductor substrate 10 in the vertical direction D1, while another component below a component may be considered to be relatively close to the bottom surface S2 of the semiconductor substrate 10 in the vertical direction D1.

[0070] Further, in some embodiments, the first drift region 22 may include a first portion 22A and a second portion 22B, which may be directly connected. The second portion 22B may be located between the gate structure 40 and the first portion 22A in the horizontal direction D2. Furthermore, a first source / drain region 52 may be disposed in the first portion 22A, and the second portion P2 of the gate oxide layer 30 may be disposed on the second portion 22B of the first drift region 22. In some embodiments, the second portion 22B of the first drift region 22 may include a bottom BM1 protruding and extending toward the bottom surface S2. Therefore, the bottom BM1 of the second portion 22B may be lower than the bottom surface and / or the bottommost surface of the first portion 22A in the vertical direction D1, and the bottom BM3 of the second portion P2 of the gate oxide layer 30 may be correspondingly disposed with the bottom BM1 of the second portion 22B of the first drift region 22 in the vertical direction D1 and substantially overlap with each other, but this is not a limitation. In some embodiments, the second portion 22B of the first drift region 22 may be disposed below the first portion P1 and the second portion P2 of the gate oxide layer 30 in the vertical direction D1, and the second portion 22B of the first drift region 22 may surround the bottom BM3 of the second portion P2 of the gate oxide layer 30 in the horizontal direction D2. Furthermore, the cross-sectional shape of the second portion 22B of the first drift region 22 may be substantially similar to the cross-sectional shape of the second portion P2 of the gate oxide layer 30 (e.g., both are U-shaped or V-shaped structures), but is not limited thereto.

[0071] In some embodiments, the semiconductor device 101 may further include a second drift region 24 and a second source / drain region 54. The second drift region 24 may be disposed in the semiconductor substrate 10, and the first drift region 22 and the second drift region 24 may be respectively located on the semiconductor substrate 10 disposed below the gate structure 40 (e.g., but not limited to...). Figure 1 The channel region 10C shown is separated from each other on two opposite sides in the horizontal direction D2. A second source / drain region 54 may be disposed in the second drift region 24, and the first source / drain region 52 and the second source / drain region 54 may be located on two opposite sides of the gate structure 40 in the horizontal direction D2. Furthermore, the gate oxide layer 30 may also include a third portion P3, which may be disposed in the horizontal direction D2 between the first portion P1 of the gate oxide layer 30 and the second source / drain region 54. In some embodiments, the third portion P3 of the gate oxide layer 30 may include a bottom BM4 extending downwards and a second recessed upper surface (e.g., Figure 1 The upper surface TS4 shown is located above the bottom BM4 of the third portion P3 in the vertical direction D1, and a portion of the second drift region 24 may be located below the first portion P1 and the third portion P3 of the gate oxide layer 30 in the vertical direction D1.

[0072] In some embodiments, the second drift region 24 may include a first portion 24A and a second portion 24B, which may be directly connected, and the second portion 24B may be located between the gate structure 40 and the first portion 24A in the horizontal direction D2. Furthermore, a second source / drain region 54 may be disposed in the first portion 24A, and a third portion P3 of the gate oxide layer 30 may be disposed on the second portion 24B of the second drift region 24. In some embodiments, the second portion 24B of the second drift region 24 may include a bottom BM2 protruding and extending toward the bottom surface S2, so that the bottom BM2 of the second portion 24B may be lower than the bottom surface and / or the bottommost surface of the first portion 24A in the vertical direction D1, and the bottom BM4 of the third portion P3 of the gate oxide layer 30 may be correspondingly disposed with the bottom BM2 of the second portion 24B of the second drift region 24 in the vertical direction D1 and substantially overlap with each other, but this is not a limitation. In some embodiments, the second portion 24B of the second drift region 24 may be disposed below the first portion P1 and the third portion P3 of the gate oxide layer 30 in the vertical direction D1, and the second portion 24B of the second drift region 24 may surround the bottom BM4 of the third portion P3 of the gate oxide layer 30 in the horizontal direction D2. Furthermore, the cross-sectional shape of the second portion 24B of the second drift region 24 may be substantially similar to the cross-sectional shape of the third portion P3 of the gate oxide layer 30 (e.g., both are U-shaped or V-shaped structures), but is not limited thereto.

[0073] In some embodiments, the second portion P2 and the third portion P3 of the gate oxide layer 30 may be located on opposite sides of the first portion P1 in the horizontal direction D2, and the first portion P1 may be directly connected to the second portion P2 and the third portion P3, respectively. In some embodiments, the second portion P2 of the gate oxide layer 30 may be conformally disposed on the second portion 22B of the first drift region 22, and the third portion P3 of the gate oxide layer 30 may be conformally disposed on the second portion 24B of the second drift region 24. Furthermore, the bottom BM5 of the first portion P1 of the gate oxide layer 30 may be higher than the bottom BM3 of the second portion P2 and the bottom BM4 of the third portion P3 in the vertical direction D1, and the upper surface TS5 of the first portion P1 may be higher than the recessed upper surface (e.g., upper surface TS3) of the second portion P2 and the recessed upper surface (e.g., upper surface TS4) of the third portion P3 in the vertical direction D1, and the cross-sectional shape of the gate oxide layer 30 may be generally W-shaped, but is not limited thereto. In some embodiments, the thickness TK of the first portion P1 of the gate oxide layer 30 may be generally between 200 angstroms and 300 angstroms, and the distance DS between the upper surface TS5 of the first portion P1 and the bottom BM3 of the second portion P2 in the vertical direction D1 may be between 400 angstroms and 600 angstroms, but is not limited thereto.

[0074] In some embodiments, the cross-sectional shape of the semiconductor device 101 can be considered as a generally symmetrical structure. Therefore, the cross-sectional shapes of the first drift region 22 and the second drift region 24 can be similar to each other and symmetrical (e.g., mirror symmetry with respect to the axis AX passing through the gate structure 40 in the vertical direction D1 as the central axis, but not limited thereto). Similarly, the cross-sectional shapes of the second portion P2 and the third portion P3 of the gate oxide layer 30 can be similar to each other and symmetrical thereto, but not limited thereto. Furthermore, the two source / drain regions in the semiconductor device 101 can be a source region and a drain region, respectively (e.g., the first source / drain region 52 can be a drain region and the second source / drain region 54 can be a source region, or the first source / drain region 52 can be a source region and the second source / drain region 54 can be a drain region). The semiconductor device 101 can be considered as a double diffused drain MOS (DDDMOS) structure, but not limited thereto.

[0075] In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable semiconductor materials. Furthermore, the first drift region 22 and the second drift region 24 may include doped regions formed using a doping fabrication process (e.g., implantation process) on the semiconductor substrate 10. The semiconductor substrate 10 may be a semiconductor substrate having a first conductivity type or a region including the first conductivity type (e.g., a doped well region having the first conductivity type, not shown), while the first drift region 22 and the second drift region 24 may have a second conductivity type, and the second conductivity type may be complementary to the first conductivity type. For example, in this embodiment, the first conductivity type may be p-type, and the second conductivity type may be n-type, but this is not a limitation. In other words, in some embodiments, the semiconductor substrate 10 may be a p-type semiconductor substrate or a semiconductor substrate with a p-type well region, and the first drift region 22 and the second drift region 24 may each be an n-type doped region; or the semiconductor substrate 10 may be an n-type semiconductor substrate or a semiconductor substrate with an n-type well region, and the first drift region 22 and the second drift region 24 may each be a p-type doped region. In some embodiments, the first source / drain region 52 and the second source / drain region 54 may include doped regions formed in the semiconductor substrate 10 using a doping fabrication process (e.g., implantation fabrication process). In some embodiments, the conductivity of the first source / drain region 52 and the second source / drain region 54 may be the same as that of the first drift region 22 and the second drift region 24, but the doping concentration of the first source / drain region 52 and the second source / drain region 54 may be higher than that of the first drift region 22 and the second drift region 24. For example, the first source / drain region 52 and the second source / drain region 54 may be n-type heavily doped regions, but this is not a limitation.

[0076] In some embodiments, the gate oxide layer 30 may include silicon oxide or other suitable oxide dielectric materials. In some embodiments, the first portion P1, the second portion P2, and the third portion P3 of the gate oxide layer 30 may be formed by oxidizing different portions of the semiconductor substrate 10, the first drift region 22, and / or the second drift region 24, and the material composition of the first portion P1, the second portion P2, and the third portion P3 may be substantially the same, but is not limited thereto. Furthermore, the gate structure 40 may include a gate dielectric layer (not shown) and a gate material layer (not shown) disposed on the gate dielectric layer. The gate dielectric layer may include a high-k dielectric material or other suitable dielectric material, and the gate material layer may include a non-metallic conductive material (e.g., doped polysilicon) or a metallic conductive material, such as a metal gate structure formed by stacking a work function layer and a low resistance layer, but is not limited thereto.

[0077] In some embodiments, the semiconductor device 101 may further include a spacer structure SP disposed on the sidewall of the gate structure 40, and the spacer structure SP may be disposed on the first portion P1, the second portion P2, and the third portion P3 of the gate oxide layer 30 in the vertical direction D1. The spacer structure SP may include a single layer or multiple layers of dielectric material, such as silicon nitride, silicon oxynitride, or other suitable dielectric materials. For example, the spacer structure SP may include a first spacer 42 and a second spacer 44, the first spacer 42 may be disposed between the second spacer 44 and the gate structure 40, and the material composition of the first spacer 42 may be different from the material composition of the second spacer 44, but is not limited thereto. In some embodiments, the gate structure 40 and the first spacer wall 42 may be disposed on the upper surface TS5 of the first portion P1 of the gate oxide layer 30 in the vertical direction D1. The second spacer wall 44 located between the gate structure 40 and the first source / drain region 52 in the horizontal direction D2 may be disposed on the upper surface TS5 of the first portion P1 of the gate oxide layer 30 and the first recessed upper surface (e.g., upper surface TS3) of the second portion P2 of the gate oxide layer 30 in the vertical direction D1. The second spacer wall 44 located between the gate structure 40 and the second source / drain region 54 in the horizontal direction D2 may be disposed on the upper surface TS5 of the first portion P1 of the gate oxide layer 30 and the second recessed upper surface (e.g., upper surface TS4) of the third portion P3 of the gate oxide layer 30 in the vertical direction D1, but is not limited thereto.

[0078] In some embodiments, the surface undulation design of the gate oxide layer 30 having the first portion P1, the second portion P2, and the third portion P3 described above (e.g., the W-shaped structure described above) can increase the support stability of the gate structure 40 and / or the spacer structure SP formed on the gate oxide layer 30, thereby positively contributing to the fabrication yield. Furthermore, in some embodiments, the semiconductor device 101 may also include a first silicide layer 62 and a second silicide layer 64 respectively disposed on the first source / drain region 52 and the second source / drain region 54. The first silicide layer 62 and the second silicide layer 64 may include silicide conductive materials such as metal silicide materials, but are not limited thereto. The aforementioned metal silicide may include cobalt-silicide, nickel-silicide, or other suitable metal silicides. In some embodiments, the first silicide layer 62 and the second silicide layer 64 may be directly connected to the second portion P2 and the third portion P3 of the gate oxide layer 30, respectively, but this is not a limitation.

[0079] Please see Figures 1 to 7 . Figures 2 to 7The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein... Figure 3 It is illustrated Figure 2 A diagram illustrating the subsequent situation. Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustrated Figure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 The following is a diagram illustrating the situation, and Figure 7 It is illustrated Figure 6 A schematic diagram of the subsequent situation. In some embodiments, Figure 1 It can be regarded as a drawing Figure 7 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 1 As shown, the method for fabricating the semiconductor device 101 in this embodiment may include the following steps. First, a first drift region 22 is formed in a semiconductor substrate 10. A gate oxide layer 30 is formed on the semiconductor substrate 10. A gate structure 40 is formed on the gate oxide layer 30, and the first drift region 22 is located on one side of the gate structure 40. A first source / drain region 52 is formed in the first drift region 22. The gate oxide layer 30 includes a first portion P1 and a second portion P2. At least a portion of the first portion P1 is disposed between the gate structure 40 and the semiconductor substrate 10 in the vertical direction D1. The second portion P2 is disposed between the first portion P1 and the first source / drain region 52 in the horizontal direction D2. The second portion P2 of the gate oxide layer 30 includes a bottom BM3 extending downward and a first recessed upper surface (e.g., upper surface TS3) located above the bottom BM3 in the vertical direction D1. A portion of the first drift region 22 is located below the first portion P1 and the second portion P2 of the gate oxide layer 30 in the vertical direction D1.

[0080] To further explain, the manufacturing method of this embodiment may include, but is not limited to, the following steps. For example... Figure 2 As shown, a patterned mask layer 12 can be formed on the upper surface S1 of the semiconductor substrate 10, and the patterned mask layer 12 can be used as an etching mask to perform an etching process on the semiconductor substrate 10 to form multiple trenches (e.g., a first trench TR1 and a second trench TR2) in the semiconductor substrate 10. The patterned mask layer 12 may include nitrides (e.g., silicon nitride) or other suitable mask materials. Figure 2 and Figure 3As shown, after forming the first trench TR1 and the second trench TR2, the patterned mask layer 12 can be removed, and a patterned mask layer 14 can be formed on the semiconductor substrate 10. The patterned mask layer 14 may include a photoresist material or other suitable mask material. Then, a doping fabrication process 91 can be performed on the semiconductor substrate 10 using the patterned mask layer 14 as a mask to form the first drift region 22 and the second drift region 24 in the semiconductor substrate 10. The doping fabrication process 91 may include an ion implantation process or other suitable doping methods. In some embodiments, a portion of the semiconductor substrate 10 located between the first trench TR1 and the second trench TR2 in the horizontal direction D2 may be covered by a patterned mask layer 14. After the first drift region 22 and the second drift region 24 are formed, at least a portion of the semiconductor substrate 10 located between the first drift region 22 and the second drift region 24 in the horizontal direction D2 may be regarded as the channel region 10C. Therefore, at least a portion of the channel region 10C may be regarded as the area of ​​the semiconductor substrate 10 covered by the patterned mask layer 14 in the doping fabrication process 91, but is not limited thereto.

[0081] In some embodiments, a portion of the first drift region 22 (e.g., first portion 22A) may be formed in the vertical direction D1 below the upper surface S1 of the semiconductor substrate 10, while another portion of the first drift region 22 (e.g., second portion 22B) may be formed in the vertical direction D1 below the first trench TR1 and on opposite sides of the first trench TR1 in the horizontal direction D2. Similarly, a portion of the second drift region 24 (e.g., first portion 24A) may be formed in the vertical direction D1 below the upper surface S1 of the semiconductor substrate 10, while another portion of the second drift region 24 (e.g., second portion 24B) may be formed in the vertical direction D1 below the second trench TR2 and on opposite sides of the second trench TR2 in the horizontal direction D2. In some embodiments, the regional distribution of the first drift region 22 and the second drift region 24 formed by the doping fabrication process 91 is affected by the first trench TR1 and the second trench TR2. For example, the shape of the bottom BM1 of the second portion 22B of the first drift region 22 may be similar to the shape of the first groove TR1, and the shape of the bottom BM2 of the second portion 24B of the second drift region 24 may be similar to the shape of the second groove TR2, but is not limited thereto. In some embodiments, the second portion 22B of the first drift region 22 may have a recessed upper surface (e.g., Figure 3 The upper surface TS1 shown can be the surface of the first groove TR1, and the upper surface TS1 can be correspondingly disposed in the vertical direction D1 with the bottom BM1 of the second part 22B of the first drift region 22 and substantially overlap with each other. Similarly, the second part 24B of the second drift region 24 can have a recessed upper surface (e.g., Figure 3The upper surface TS2 shown can be the surface of the second groove TR2, and the upper surface TS2 can be correspondingly set in the vertical direction D1 with the bottom BM2 of the second part 24B of the second drift region 24 and substantially overlap with each other.

[0082] like Figure 3 and Figure 4 As shown, after the first drift region 22 and the second drift region 24 are formed, the patterned mask layer 14 can be removed and a patterned mask layer 26 can be formed on the semiconductor substrate 10. The patterned mask layer 26 may include a nitride (e.g., silicon nitride) or other suitable mask material. In some embodiments, the patterned mask layer 26 may cover the first portion 22A of the first drift region 22 and the first portion 24A of the second drift region 24 in the vertical direction D1, while the second portion 22B of the first drift region 22, the second portion 24B of the second drift region 24, and the channel region 10C may be exposed without being covered by the patterned mask layer 26. Then, as Figure 4 and Figure 5 As shown, after the patterned mask layer 26 is formed, an oxidation process 92 can be performed to form the gate oxide layer 30. The oxidation process 92 may include a thermal oxidation process or other suitable oxidation methods. In other words, the gate oxide layer 30 can be formed as described above. Figure 3 The doping fabrication process 91 shown is followed by an oxidation fabrication process 92, and the gate oxide layer 30 can be formed by oxidizing the second portion 22B of the first drift region 22 not covered by the patterned mask layer 26, the second portion 24B of the second drift region 24, and the channel region 10C by the oxidation fabrication process 92. For example, a portion of the channel region 10C of the semiconductor substrate 10, a portion of the first drift region 22 adjacent to the channel region 10C, and a portion of the second drift region 24 adjacent to the channel region 10C can be oxidized by the oxidation fabrication process 92 to become at least a portion of the first portion P1 of the gate oxide layer 30, a portion of the first drift region 22 located below the first trench TR1 can be oxidized by the oxidation fabrication process 92 to become at least a portion of the second portion P2 of the gate oxide layer 30, and a portion of the second drift region 24 located below the second trench TR2 can be oxidized by the oxidation fabrication process 92 to become at least a portion of the third portion P3 of the gate oxide layer 30, but is not limited thereto.

[0083] In some embodiments, due to differences in the oxidation rates of different portions, the thickness of the first portion P1 of the gate oxide layer 30 (e.g., the distance in the vertical direction D1 between the upper surface TS5 and the bottom BM5) may differ from the thickness of the second portion P2 (e.g., the distance or shortest distance in the vertical direction D1 between the upper surface TS3 and the bottom BM3) and / or the thickness of the third portion P3 (e.g., the distance or shortest distance in the vertical direction D1 between the upper surface TS4 and the bottom BM4), but this is not a limitation. For example, the thickness of the first portion P1 of the gate oxide layer 30 may be greater than the thickness of the second portion P2 and / or the thickness of the third portion P3. Furthermore, in some embodiments, due to the depth of the trench described above, the upper surface TS3 of the second portion P2 and / or the upper surface TS4 of the third portion P3 may be lower than the bottom BM5 of the first portion P1 in the vertical direction D1, but this is not a limitation. Figure 5 and Figure 6 As shown, after forming the gate oxide layer 30, the patterned mask layer 26 can be removed to expose the first portion 22A of the first drift region 22 and the first portion 24A of the second drift region 24. It is worth noting that, in this invention, the fabrication method for forming the first drift region 22, the second drift region 24, and the gate oxide layer 30 may include the methods described above. Figures 2 to 5 The steps shown are not limited to these. In other words, other suitable manufacturing methods can be used as needed for the design. Figure 6 and Figure 1 The first drift region 22, the second drift region 24, and the gate oxide layer 30 are shown in the figure.

[0084] Then, as Figure 7As shown, a gate structure 40 can be formed, and a spacer structure SP can be formed on the sidewalls of the gate structure 40. In some embodiments, the gate structure 40 can be formed on the upper surface TS5 of the first portion P1 of the gate oxide layer 30, while the spacer structure SP can be formed on the first portion P1, the second portion P2, and the third portion P3 of the gate oxide layer 30 in the vertical direction D1. For example, the first spacer 42 can be formed on the upper surface TS5 in the vertical direction D1, while the second spacer 44 can be partially formed on the upper surface TS5 and partially formed on the upper surfaces TS3 of the second portion P2 and TS4 of the third portion P3 of the gate oxide layer 30 in the vertical direction D1, but is not limited thereto. Furthermore, a portion of the second portion P2 of the gate oxide layer 30 may be disposed in the horizontal direction D2 between the first portion 22A of the first drift region 22 and the second spacer 44, thereby separating the spacer structure SP from the first portion 22A of the first drift region 22. A portion of the third portion P3 of the gate oxide layer 30 may be disposed in the horizontal direction D2 between the first portion 24A of the second drift region 24 and the second spacer 44, thereby separating the spacer structure SP from the first portion 24A of the second drift region 24.

[0085] like Figure 7 and Figure 1 As shown, a first source / drain region 52 and a second source / drain region 54 can be formed in the first portion 22A of the first drift region 22 and the first portion 24A of the second drift region 24, respectively, and a first silicide layer 62 and a second silicide layer 64 can be formed on the first source / drain region 52 and the second source / drain region 54, respectively. In some embodiments, the first silicide layer 62 and the second silicide layer 64 can be formed in a self-aligned manner, so the first silicide layer 62 can be directly connected to the second portion P2 of the gate oxide layer 30 and separated from the spacer structure SP, and the second silicide layer 64 can be directly connected to the third portion P3 of the gate oxide layer 30 and separated from the spacer structure SP, but this is not a limitation.

[0086] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0087] Please see Figure 8 . Figure 8 The illustration shows a schematic diagram of a semiconductor device 102 according to a second embodiment of the present invention. Figure 8As shown, in the semiconductor device 102, the gate oxide layer 30 may have a first portion P1 and a second portion P2 but not the third portion described in the first embodiment. Furthermore, the second drift region 24 may not have a downwardly extending bottom; therefore, the bottom of the second drift region 24 may be higher in the vertical direction D1 than the bottom BM1 of the second portion 22B of the first drift region 22 and / or the bottom BM3 of the second portion P2 of the gate oxide layer 30. In some embodiments, the first source / drain region 52 disposed in the first drift region 22 having a bottom BM1 protruding and extending toward the bottom surface S2 may be a drain region, while the second source / drain region 54 disposed in the second drift region 24 not having a bottom protruding and extending toward the bottom surface S2 may be a source region, but this is not a limitation. Furthermore, a portion of the second spacer wall 44 may be disposed in the horizontal direction D2 between the first portion P1 of the gate oxide layer 30 and the second silicide layer 64, and the second spacer wall 44 may directly contact the second silicide layer 64 and the second drift region 24, but this is not a limitation.

[0088] Please see Figures 8 to 10 . Figure 9 and Figure 10 The illustration shows a schematic diagram of a method for manufacturing a semiconductor device 102 according to a second embodiment of the present invention. Figure 10 It is illustrated Figure 9 A schematic diagram of the subsequent situation. In some embodiments, Figure 8 It can be regarded as a drawing Figure 10 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 9 As shown, in some embodiments, a first trench TR1 may be formed in the semiconductor substrate 10 before the doping fabrication process 91, without forming the second trench described in the first embodiment. Therefore, the second drift region 24 may not be formed below the trench. Then, as... Figure 9 and Figure 10 As shown, since the second drift region 24 is not formed below the trench, during the oxidation fabrication process 92, the patterned mask layer 26 can cover the first portion 22A of the first drift region 22 but not the second portion 22B of the first drift region 22, the channel region 10C, and the second drift region 24. The first portion P1 of the gate oxide layer 30 can be formed by oxidation of a portion of the channel region 10C not covered by the patterned mask layer 26, a portion of the second portion 22B of the first drift region 22, and a portion of the second drift region 24 by the oxidation fabrication process 92, but is not limited thereto. Then, as... Figure 10 and Figure 8As shown, a gate structure 40, a spacer structure SP, a first source / drain region 52, a second source / drain region 54, a first silicide layer 62, and a second silicide layer 64 can then be formed to form a semiconductor device 102. In some embodiments, a portion of the first portion P1 of the gate oxide layer 30 may be removed after the step of forming the first spacer 42, thereby allowing a portion of the second spacer 44 to be formed on the second drift region 24 and this portion of the second spacer 44 to be used as a mask to form the second source / drain region 54 and the second silicide layer 64, but this is not a limitation.

[0089] In summary, in the semiconductor device and its manufacturing method of the present invention, the gate oxide layer having a downwardly extending bottom and a corresponding recessed upper surface allows the current path in the drift region located below the gate oxide layer to extend downward in the vertical direction. Therefore, the electrical performance of the semiconductor device can be improved by increasing the current path (e.g., reducing the edge electric field, improving the ability to withstand hot carrier injection, etc.) and / or the drift region and the area occupied by the semiconductor device can be relatively reduced under certain current path specifications, which helps to increase the number and / or density of semiconductor devices.

[0090] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A gate structure is disposed on the semiconductor substrate; The first drift region is disposed in the semiconductor substrate and located on one side of the gate structure; The first source / drain region is located in the first drift region; as well as A gate oxide layer is disposed on the semiconductor substrate, wherein the gate oxide layer comprises: The first part, wherein at least a portion of the first part is disposed in the vertical direction between the gate structure and the semiconductor substrate; The second part is horizontally disposed between the first part of the gate oxide layer and the first source / drain region, wherein the second part of the gate oxide layer includes a bottom extending downward and a first recessed upper surface located above the bottom in the vertical direction; the bottom of the first part of the gate oxide layer is higher than the bottom of the second part in the vertical direction; neither the bottom of the second part nor the first recessed upper surface overlaps with the gate structure in the vertical direction; and a portion of the first drift region is located below the first and second parts of the gate oxide layer in the vertical direction. A gap wall structure is disposed on the sidewall of the gate structure, wherein the gap wall structure is disposed on the first portion and the second portion of the gate oxide layer in the vertical direction, and the gap wall structure directly contacts the first recessed upper surface of the second portion of the gate oxide layer.

2. The semiconductor device of claim 1, wherein the second portion of the gate oxide layer is directly connected to the first portion of the gate oxide layer.

3. The semiconductor device of claim 1, wherein the first drift region disposed below the second portion of the gate oxide layer surrounds the bottom of the second portion of the gate oxide layer in the horizontal direction.

4. The semiconductor device of claim 1, wherein the second portion of the gate oxide layer is conformally disposed on the first drift region.

5. The semiconductor device of claim 1, further comprising: A second drift region is disposed in the semiconductor substrate, wherein the first drift region and the second drift region are respectively located on two opposite sides of the semiconductor substrate disposed below the gate structure in the horizontal direction; and A second source / drain region is disposed in the second drift region, wherein the first source / drain region and the second source / drain region are respectively located on two opposite sides of the gate structure in the horizontal direction, and the gate oxide layer further includes: The third part is disposed in the horizontal direction between the first part of the gate oxide layer and the second source / drain region, wherein the third part of the gate oxide layer includes a bottom extending downward and a second recessed upper surface located above the bottom of the third part in the vertical direction, and a portion of the second drift region is located below the first part and the third part of the gate oxide layer in the vertical direction.

6. The semiconductor device of claim 5, wherein the third portion of the gate oxide layer is directly connected to the first portion of the gate oxide layer.

7. The semiconductor device of claim 5, wherein the bottom of the first portion of the gate oxide layer is higher than the bottom of the third portion of the gate oxide layer in the vertical direction.

8. A method for manufacturing a semiconductor device, comprising: A first drift region is formed in the semiconductor substrate; A gate oxide layer is formed on the semiconductor substrate; A gate structure is formed on the gate oxide layer, wherein the first drift region is located on one side of the gate structure; A first source / drain region is formed in the first drift region, wherein the gate oxide layer comprises: A first part, wherein at least a portion of the first part is disposed vertically between the gate structure and the semiconductor substrate; and The second part is horizontally disposed between the first part of the gate oxide layer and the first source / drain region, wherein the second part of the gate oxide layer includes a bottom extending downward and a first recessed upper surface located above the bottom in the vertical direction; the bottom of the first part of the gate oxide layer is higher than the bottom of the second part in the vertical direction; neither the bottom of the second part nor the first recessed upper surface overlaps with the gate structure in the vertical direction; and a portion of the first drift region is located below the first and second parts of the gate oxide layer in the vertical direction. A gap wall structure is formed on the sidewall of the gate structure, wherein the gap wall structure is formed in the vertical direction on the first portion and the second portion of the gate oxide layer, and the gap wall structure directly contacts the first recessed upper surface of the second portion of the gate oxide layer.

9. The method of fabricating a semiconductor device as claimed in claim 8, wherein the method of forming the first drift region comprises: A first trench is formed in the semiconductor substrate; as well as After the first trench is formed, a doping process is performed to form the first drift region in the semiconductor substrate, wherein a portion of the first drift region is formed in the vertical direction below the first trench and on two opposite sides of the first trench in the horizontal direction.

10. The method of fabricating a semiconductor device as claimed in claim 9, wherein the gate oxide layer is formed by an oxidation process after the doping process, and a portion of the first drift region located below the first trench is oxidized by the oxidation process to become at least a portion of the second portion of the gate oxide layer.

11. The method of fabricating a semiconductor device as claimed in claim 10, wherein a region of the semiconductor substrate is covered by a patterned mask layer in the doping fabrication process, and a portion of the region of the semiconductor substrate is oxidized by the oxidation fabrication process to become at least a portion of the first portion of the gate oxide layer.

12. The method of manufacturing a semiconductor device as claimed in claim 8, further comprising: A second drift region is formed in the semiconductor substrate, wherein the first drift region and the second drift region are respectively located on two opposite sides of the semiconductor substrate disposed below the gate structure in the horizontal direction; and A second source / drain region is formed in the second drift region, wherein the first source / drain region and the second source / drain region are respectively located on two opposite sides of the gate structure in the horizontal direction, and the gate oxide layer further includes: The third part is disposed in the horizontal direction between the first part of the gate oxide layer and the second source / drain region, wherein the third part of the gate oxide layer includes a bottom extending downward and a second recessed upper surface located above the bottom of the third part in the vertical direction, and a portion of the second drift region is located below the first part and the third part of the gate oxide layer in the vertical direction.

13. The method of fabricating a semiconductor device as claimed in claim 12, wherein the method of forming the first drift region and the second drift region comprises: A first trench and a second trench are formed in the semiconductor substrate; as well as After the first trench and the second trench are formed, a doping process is performed to form the first drift region and the second drift region in the semiconductor substrate. A portion of the first drift region is formed in the vertical direction below the first trench and on two opposite sides of the first trench in the horizontal direction, and a portion of the second drift region is formed in the vertical direction below the second trench and on two opposite sides of the second trench in the horizontal direction.

14. The method of fabricating a semiconductor device as claimed in claim 13, wherein the gate oxide layer is formed by an oxidation process after the doping process, a portion of the first drift region located below the first trench is oxidized by the oxidation process to become at least a portion of the second portion of the gate oxide layer, and a portion of the second drift region located below the second trench is oxidized by the oxidation process to become at least a portion of the third portion of the gate oxide layer.

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