A single-event hard SiC UMOSFET device

Abstract

The application relates to an anti-single-particle SiC UMOSFET device, which comprises a substrate, a drain arranged below the substrate, an N-drift region arranged above the substrate, a first P+ region arranged inside the N-drift region, a second P+ region arranged inside the N-drift region, a P-type base region arranged inside the N-drift region and between the first P+ region and the second P+ region, an N+ source region arranged on the upper surfaces of the first P+ region, the P-type base region and the second P+ region, a gate slot arranged through the N+ source region and adjacent to the P-type base region, a gate arranged inside the gate slot, a gate medium filled between the gate and the gate slot, a source arranged on the surface of the first source slot, the surface of the second source slot, the two side surfaces of the N+ source region and part of the upper surface of the N+ source region, and a gate electrode arranged on the gate. The gate slot of the application has a large thickness of the gate oxide layer at the bottom of the gate slot, the bottom of the gate slot is semi-enclosed, and the source slot is etched, so that the rapid extraction of excess holes is realized, and the single-particle reliability of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of power semiconductor devices, and particularly relates to a single-particle-resistant SiC UMOSFET device. BACKGROUND

[0002] The typical third-generation semiconductor material silicon carbide is widely used in high-voltage, high-power and radiation-resistant fields due to its excellent characteristics such as wide band gap, high breakdown field and high thermal conductivity. Compared with the traditional planar gate VDMOSFET (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor), the UMOSFET (Trench Gate Metal Oxide Semiconductor Field Effect Transistor) can better achieve a compromise between the on-state characteristics and the reverse characteristics due to the absence of the JFET region and the small on-state resistance, and the etching of the gate trench reduces the cell area. So far, UMOSFETs of various structures have been put into use and have shown excellent performance.

[0003] However, when applied to the field of aviation, the single event effect caused by the incidence of multiple high-energy particles will cause the performance of the device to decline or even fail. Single event gate rupture and single event burnout are two irreversible single event effects that can cause device failure. Single event effect often occurs in the blocking state of the device, which refers to the problem of strong electric field, large current or large power dissipation caused by the interaction between cosmic particles and the device and material after the cosmic particles enter the device, thereby causing the performance of the device to degrade or even fail. When cosmic particles enter the device, the atoms of the device material obtain energy and generate a large number of electron-hole pairs. A large number of holes move to the gate and drift region interface under the action of the drain voltage, so that a strong additional electric field is superimposed on the gate oxide layer. When the gate oxide electric field strength exceeds the bearing limit of the device, single event gate rupture occurs, and the gate oxide layer is broken down. In addition, after the single event incidence causes the inherent parasitic transistor in the device to open and form a positive feedback with the bottom high-low junction avalanche, the device current remains at a high level, causing the device temperature to rise to the melting point of the material, i.e., single event burnout occurs. This requires that the holes be extracted and discharged to reduce the emission junction voltage of the parasitic transistor, thereby inhibiting the establishment of the positive feedback of the parasitic transistor opening and the collision ionization at the high-low junction. The existing two types of UMOSFET devices, such as DTMOSFET (Double Trench MOSFET; double trench metal oxide semiconductor field effect transistor) and ATMOSFET (Asymmetric Trench MOSFET; asymmetric trench metal oxide semiconductor field effect transistor), have the following problems. The former has the problems that the holes accumulated in the initial stage of single event incidence are not easy to be extracted by the parasitic transistor, and the lateral distance between the single event gate rupture sensitive position and the second P+ region is long, which further increases the difficulty of hole extraction. The latter has the problems that the holes accumulated in the initial stage of single event incidence are also not easy to be extracted by the parasitic transistor, and the source metal coverage area is small, which further increases the hole discharge path. Therefore, the anti-single particle performance of both is poor. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the present application provides a single particle resistant SiC UMOSFET device. The technical problems to be solved by the present application are realized by the following technical solutions:

[0005] The present application provides a single particle resistant SiC UMOSFET device, comprising:

[0006] a substrate;

[0007] a drain electrode disposed below the substrate;

[0008] an N-drift region located above the substrate;

[0009] a first P+ region located inside the N-drift region;

[0010] a second P+ region, located inside the N-drift region and spaced apart from the first P+ region; the first P+ region forms a first source trench, and the second P+ region forms a second source trench;

[0011] a P-type base region, located inside the N-drift region, between the first P+ region and the second P+ region and adjacent to the first P+ region;

[0012] an N+ source region, located on the upper surface of the first P+ region, the P-type base region and the second P+ region;

[0013] a gate trench, passing through the N+ source region and adjacent to the P-type base region, the bottom of the gate trench being located inside the N-drift region and the second P+ region, the second P+ region semi-enclosing the gate trench;

[0014] a gate electrode, located inside the gate trench, the gate electrode being filled with gate dielectric between the gate electrode and the gate trench, the thickness of the gate dielectric below the gate electrode being greater than the thickness of the gate dielectric on both sides of the gate electrode;

[0015] a source electrode, located on the surface of the first source trench, the surface of the second source trench, and the upper surface and part of the side surface of the N+ source region;

[0016] the source electrode being in ohmic contact with the first P+ region, the second P+ region and the N+ source region;

[0017] a gate electrode, located above the gate electrode.

[0018] In an embodiment of the present application, the distance between the side wall of the gate trench away from the first P+ region and the side wall of the second P+ region inside close to the first P+ region is half of the width of the gate trench.

[0019] In an embodiment of the present application, the material of the substrate is N-type SiC, doped with phosphorus ions, the doping concentration being 5×10 18 -1×10 19 cm -3 .

[0020] In an embodiment of the present application, the material of the drain electrode is Ni, and the material of the source electrode is Ti / Al / Ni laminated metal.

[0021] In an embodiment of the present application, the material of the N-drift region is N-type SiC, doped with phosphorus ions, the thickness of the N-drift region being in the range of 10-30 μm, and the doping concentration being 3×10 15 -1×10 16 cm -3 .

[0022] In one embodiment of the present application, the material of the gate medium is SiO2, and the material of the gate is polysilicon.

[0023] In one embodiment of the present application, the bottom of the first source groove and the bottom of the second source groove are both level with the bottom of the gate groove.

[0024] In one embodiment of the present application, the thickness of the gate medium under the gate is in the range of 300-500 nm.

[0025] Compared with the prior art, the present application has the following advantages:

[0026] 1. The anti-single-particle SiC UMOSFET device of the present application has a gate oxide layer at the bottom of the gate groove with a thickness greater than that of the gate oxide layer at the sidewall, so that the holes accumulated due to single-particle incidence are more easily extracted by the parasitic transistor, effectively improving the anti-single-particle gate punch-through capability of the device; the lateral distance between the single-particle gate punch-through sensitive position and the second P+ region is shorter, and the excess holes can be discharged through this path, realizing rapid extraction of the excess holes and reducing the accumulation degree of the holes at the interface between the gate oxide layer and the N+ drift region, thereby effectively reducing the gate oxide electric field strength and improving the single-particle gate punch-through reliability of the device.

[0027] 2. The anti-single-particle SiC UMOSFET device of the present application, after etching the source groove and covering the source metal, the source metal coverage area increases and the hole extraction path becomes shorter, so that the excess holes are discharged faster through the source groove and less flow through the parasitic transistor; the potential change caused by the current flowing through the first P+ region due to the extraction of holes by the source groove is reduced, thereby reducing the emission junction voltage of the parasitic transistor, effectively suppressing the establishment of positive feedback of collision ionization at the opening and high-low junction of the parasitic transistor, effectively reducing the gate oxide electric field strength and the possibility of opening of the parasitic transistor, and improving the single-particle burnout reliability of the device.

[0028] 3. The anti-single-particle SiC UMOSFET device of the present application has an etching depth of the source groove consistent with that of the gate groove, and is formed simultaneously with the gate groove. Compared with the DTMOSFET, no additional etching process is added. In addition, compared with the ATMOSFET, the ion implantation depth on the left and right sides is significantly reduced, the process difficulty is reduced, and it is easier to implement.

[0029] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a structural schematic diagram of an existing DTMOSFET device;

[0031] Figure 2 is a structural schematic diagram of an existing ATMOSFET device;

[0032] Figure 3 is a structural schematic diagram of an anti-single-particle SiC UMOSFET device provided by an embodiment of the present application.

[0033] Figure: 1-substrate; 2-drain; 3-N-drift region; 4-first P+ region; 401-first P+ ohmic contact region; 402-second P+ ohmic contact region; 5-P-type base region; 6-N+ source region; 7-source; 8-gate slot; 801-gate dielectric; 802-gate; 9-gate electrode; 10-second P+ region; 101-third P+ ohmic contact region; 105-fourth P+ ohmic contact region; 11-second P-type base region. DETAILED DESCRIPTION

[0034] In order to further illustrate the technical means and effects taken by the present application to achieve the predetermined purposes, the following will be described in detail in combination with the drawings and specific embodiments, and an anti-single-particle SiC UMOSFET device according to the present application will be described in detail.

[0035] The foregoing and other technical contents, features and effects of the present application can be clearly presented in the following detailed description of specific embodiments in combination with the drawings. Through the description of specific embodiments, the technical means and effects taken by the present application to achieve the predetermined purposes can be more deeply and specifically understood. However, the attached drawings are provided for reference and illustration only, and are not used to limit the technical solutions of the present application.

[0036] Embodiment one

[0037] Please refer to Figure 3 , Figure 3 is a structural schematic diagram of an anti-single-particle SiC UMOSFET device provided by an embodiment of the present application.

[0038] As shown in the figure, the anti-single-particle SiC UMOSFET device of the embodiment of the present application comprises:

[0039] a substrate 1;

[0040] a drain 2 arranged below the substrate 1;

[0041] an N-drift region 3 located above the substrate 1;

[0042] a first P+ region 4 located inside the N-drift region 3;

[0043] The second P+ region 10 is located inside the N-drift region 3 and is spaced apart from the first P+ region 4.

[0044] The first P+ region 4 is provided with a first source trench, and the second P+ region 10 is provided with a second source trench.

[0045] The P-type base region 5 is located inside the N-drift region 3, between the first P+ region 4 and the second P+ region 10 and adjacent to the first P+ region 4.

[0046] The N+ source region 6 is located on the upper surface of the first P+ region 4, the P-type base region 5 and the second P+ region 10.

[0047] The gate trench 8 is located through the N+ source region 6 and adjacent to the P-type base region 5, the bottom of the gate trench 8 is located inside the N-drift region 3 and the second P+ region 10, and the second P+ region 10 semi-encloses the gate trench 8.

[0048] The gate electrode 802 is located inside the gate trench 8, and the gate dielectric 801 is filled between the gate electrode 802 and the gate trench 8, the thickness of the gate dielectric 801 located below the gate electrode 802 is greater than the thickness of the gate dielectric 801 located on both sides of the gate electrode 802.

[0049] The gate electrode 9 is located on the gate electrode 802.

[0050] In an optional embodiment, the thickness of the gate dielectric 801 located below the gate electrode 802 ranges from 300 nm to 500 nm.

[0051] In this embodiment, the material of the substrate 1 is N-type SiC, doped with phosphorus ions, and the doping concentration is 5×10 18 -1×10 19 cm -3 .

[0052] In this embodiment, the material of the drain 2 is Ni, and the material of the source 7 is Ti / Al / Ni laminated metal.

[0053] In this embodiment, the N-drift region 3 is made of N-type SiC, doped with phosphorus ions, and has a thickness of 10-30 μm, and the doping concentration is 3×10 15 -1×10 16 cm -3 .

[0054] In this embodiment, the first P+ region 4 is P-type doped, which can be boron ion doping, and the doping concentration is 5×10 18 -1×10 19 cm -3 .

[0055] In this embodiment, the second P+ region 10 is P-type doped, which can be boron ion doping, and the doping concentration is 5×10 18-1 x 10 19 cm -3 .

[0056] In an alternative embodiment, after etching the first P+ region 4 on the N- drift region 3 to form the first source trench, the first P+ ohmic contact region 401 and the second P+ ohmic contact region 402 are formed by boron ion implantation under the first source trench and on the right side of the first source trench, respectively. The second P+ ohmic contact region 402 is located on the right side of the first P+ ohmic contact region 401. The first P+ ohmic contact region 401 and the second P+ ohmic contact region 402 jointly form the first P+ region 4.

[0057] In an alternative embodiment, after etching the second P+ region 10 on the N- drift region 3 to form the second source trench, the third P+ ohmic contact region 101 and the fourth P+ ohmic contact region 102 are formed by boron ion implantation under the second source trench and on the left side of the second source trench, respectively. The fourth P+ ohmic contact region 102 is located on the left side of the third P+ ohmic contact region 101. The third P+ ohmic contact region 101 and the fourth P+ ohmic contact region 102 jointly form the second P+ region 10.

[0058] In this embodiment, the source electrode 7 is disposed on the surface of the first source trench, the surface of the second source trench, and the two side surfaces and part of the upper surface of the N+ source region 6. The source electrode 7 is in ohmic contact with the interfaces of the first P+ region 4, the second P+ region 10, and the N+ source region 6.

[0059] In this embodiment, the material of the gate dielectric 801 is SiO2, and the material of the gate electrode 802 is polysilicon.

[0060] In an alternative embodiment, the thickness of the gate oxide layer at the bottom of the gate dielectric 801 under the gate electrode 802 is greater than the thickness of the gate oxide layer at the sidewall of the gate dielectric 801. The corner position where the bottom and the sidewall of the gate dielectric 801 meet is a single-particle gate punch-through sensitive position. The holes accumulated at the initial stage of single-particle incidence are more easily extracted by the parasitic transistor, effectively improving the single-particle gate punch-through resistance of the device.

[0061] In an alternative embodiment, the distance between the sidewall of the gate trench 8 on the side away from the first P+ region 4 and the sidewall of the second P+ region 10 on the side close to the first P+ region 4 is half the width of the gate trench 8. The purpose is to avoid excess holes that cannot be discharged through the second source trench, thereby reducing the single-particle resistance of the device. In addition, the holes accumulated by the single-particle gate punch-through sensitive position are more easily extracted through the second source trench on the right side of the gate trench 8, effectively reducing the gate oxide electric field strength.

[0062] In the embodiment, the inner bottom of the first source trench and the inner bottom of the second source trench are both level with the inner bottom of the gate trench 8, so that the first source trench, the gate trench 8 and the second source trench can be formed simultaneously by one etching process, without increasing additional etching processes, and the ion implantation depth of the region is greatly reduced due to the source trench etching, so that the processing difficulty is reduced and the implementation is easier.

[0063] Further, the depth of the inner bottom of the first source trench 4 and the inner bottom of the second source trench 10 is adjusted according to the depth of the inner bottom of the gate trench 8, so as to control the gate oxide electric field of the device to be as low as possible when the device is in forward operation.

[0064] Referring to Figure 1 , Figure 1 is a structural schematic diagram of a DTMOSFET device.

[0065] As shown in the figure, compared with the DTMOSFET device, the thickness of the gate dielectric 801 under the gate 802 of the UMOSFET device of the application is greater than the thickness of the gate dielectric 801 on both sides of the gate 802; therefore, the thick gate oxide layer makes the holes accumulated at the single-particle gate punch-through sensitive position due to single-particle incidence more easily extracted by the parasitic transistor, effectively improving the single-particle gate punch-through resistance of the device; since the second source trench on the right side is closer to the sensitive position, it is easier to extract holes, so there is an additional hole discharge path on the right side compared with the DTMOSFET device.

[0066] Referring to Figure 2 , Figure 2 is a structural schematic diagram of an ATMOSFET device.

[0067] As shown in the figure, compared with the ATMOSFET device, the thickness of the gate dielectric 801 under the gate 802 of the UMOSFET device of the application is greater than the thickness of the gate dielectric 801 on both sides of the gate 802, and the source trench is not etched; therefore, the thick gate oxide layer makes the holes accumulated at the single-particle gate punch-through sensitive position due to single-particle incidence more easily extracted by the parasitic transistor, effectively improving the single-particle gate punch-through resistance of the device; since the first source trench and the second source trench are etched respectively, and the source 7 is covered thereon, the source metal coverage area is increased, the hole discharge path is shortened, and the holes can be discharged through the path on both sides of the gate trench 8, effectively improving the single-particle gate punch-through resistance of the device; in addition, the holes extracted by the first source trench and the second source trench reduce the potential change caused by the current flowing through the first P+ region 4, thereby reducing the emission junction voltage of the parasitic transistor, effectively suppressing the establishment of the positive feedback of collision ionization at the on and off junctions of the parasitic transistor, and improving the single-particle burnout reliability of the device.

[0068] The anti-single-particle SiC UMOSFET device of the embodiment of the application has the thickness of the gate oxide layer of the bottom of the gate slot greater than the thickness of the gate oxide layer of the sidewall, so that the holes accumulated due to single-particle incidence are more easily extracted by the parasitic transistor, effectively improving the single-particle gate punch-through resistance of the device; the lateral distance between the single-particle gate punch-through sensitive position and the second P+ region is shorter, and the excess holes can be discharged through the path, realizing rapid extraction of the excess holes, reducing the accumulation degree of the holes at the interface between the gate oxide layer and the N+ drift region, thereby effectively reducing the gate oxide electric field strength and improving the single-particle gate punch-through reliability of the device.

[0069] The anti-single-particle SiC UMOSFET device of the embodiment of the application has the source slot etched and the source metal covered, the source metal coverage area is increased and the hole extraction path is shortened, so that the excess holes are discharged through the source slot more quickly and less flow through the parasitic transistor; the source slot extracts the holes, so that the potential change caused by the current flowing through the first P+ region is reduced, thereby reducing the emission junction voltage of the parasitic transistor, effectively inhibiting the establishment of the positive feedback of the collision ionization at the high and low junctions of the parasitic transistor, effectively reducing the gate oxide electric field strength and the possibility of the parasitic transistor being turned on, and improving the single-particle burnout reliability of the device.

[0070] The anti-single-particle SiC UMOSFET device of the embodiment of the application has the etching depth of the source slot consistent with the gate slot and formed at the same time. Compared with the DTMOSFET, no additional etching process is added. In addition, compared with the ATMOSFET, the ion implantation on the left and right sides forms a deep P+ region, although the structure process adds a source slot etching, the ion implantation depth is significantly reduced, the process difficulty is reduced, and it is easier to realize.

[0071] It should be noted that, in this document, the terms such as first and second are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variant are intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the article or device including the element. The terms "connected" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The directions or positions indicated by "up", "down", "left", "right" and the like are based on the directions or positions shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and therefore cannot be understood as limiting or implying that the devices or elements referred to must have a particular direction, be constructed and operated in a particular direction, and therefore cannot be understood as limiting the application.

[0072] The above description is further detailed in connection with specific preferred embodiments of the application, and it is not to be construed that the specific implementation of the application is limited to these descriptions. For those skilled in the art of the present application, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all of them should be considered as falling within the protection scope of the present application.

Claims

1. A single event immune SiC UMOSFET device, characterized by, The application relates to a vertical power MOSFET, comprising: a substrate (1); a drain (2) arranged below the substrate (1); an N-drift region (3) arranged above the substrate (1); a first P+ region (4) arranged inside the N-drift region (3); a second P+ region (10) arranged inside the N-drift region (3) and spaced apart from the first P+ region (4); the first P+ region (4) forms a first source trench, and the second P+ region (10) forms a second source trench; a P-type base region (5) arranged inside the N-drift region (3) and arranged between the first P+ region (4) and the second P+ region (10) and adjacent to the first P+ region (4); an N+ source region (6) arranged on the upper surfaces of the first P+ region (4), the P-type base region (5) and the second P+ region (10); a gate trench (8) arranged through the N+ source region (6) and adjacent to the P-type base region (5), the bottom of the gate trench (8) being arranged inside the N-drift region (3) and the second P+ region (10), and the second P+ region (10) semi-enclosing the gate trench (8); a gate electrode (802) arranged inside the gate trench (8), and a gate dielectric (801) being filled between the gate electrode (802) and the gate trench (8), the thickness of the gate dielectric (801) arranged below the gate electrode (802) being greater than the thickness of the gate dielectric (801) arranged on both sides of the gate electrode (802); a source electrode (7) arranged on the surface of the first source trench, the surface of the second source trench, and the upper surface and part of the side surface of the N+ source region (6); the source electrode (7) being in ohmic contact with the first P+ region (4), the second P+ region (10) and the N+ source region (6); a gate electrode (9) arranged on the gate electrode (802); the distance between the side wall of the gate trench (8) away from the first P+ region (4) and the side wall of the second P+ region (10) close to the first P+ region (4) is half of the width of the gate trench (8); the inner bottom of the first source trench and the inner bottom of the second source trench are horizontally leveled with the inner bottom of the gate trench (8).

2. The anti-single event SiCUMOSFET device of claim 1, wherein, The material of the substrate (1) is N-type SiC, doped with phosphorus ions, with a doping concentration of 5x10 18 -1x10 19 cm -3 .

3. The anti-single event SiCUMOSFET device of claim 1, wherein, The material of the drain (2) is Ni, and the material of the source electrode (7) is a Ti / Al / Ni laminated metal.

4. The anti-single event SiC UMOSFET device of claim 1, wherein, The N-drift region (3) is made of N-type SiC, doped with phosphorus ions, with a thickness ranging from 10 to 30 μm and a doping concentration of 3 x 1015 cm-3. 15 -1 x 1014 cm-3. 16 cm-3. -3 ​ 5. The anti-single event SiCUMOSFET device of claim 1, wherein, The material of the gate dielectric (801) is SiO2, and the material of the gate electrode (802) is polysilicon.

6. The anti-single event SiC UMOSFET device of claim 1, wherein, The thickness of the gate dielectric (801) arranged below the gate electrode (802) ranges from 300 to 500 nm.

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