High-voltage TVS product and PN junction passivation process thereof

Abstract

The application discloses a high-voltage TVS product and a PN junction passivation process thereof. The application relates to a semiconductor device, in particular to a low-stress high-reliability high-voltage TVS product and a PN junction passivation process thereof. The application provides a high-voltage TVS product and a PN junction passivation process thereof, which are low in production cost, can effectively improve the reliability and stability of the device, and reduce the stress of the device. In the application, the SIPOS film passivation is combined with the Si3N4 and SiO2 film passivation in the high-voltage TVS manufacturing process. After the SIPOS film is deposited, a layer of Si3N4 and dense SiO2 film is continuously grown on the surface of the SIPOS film by using LPCVD. The impurity pollution at the PN junction caused by the glass melting process and the bonding stress between the glass and the silicon are reduced, the reverse leakage current is reduced, and the product reliability is improved. The application has the remarkable characteristics of simple structure and convenient manufacturing.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, in particular to a high-voltage TVS product with low stress and high reliability and a PN junction passivation process thereof. BACKGROUND

[0002] Transient voltage suppression diode (TVS) is a high-performance surge protection device. Due to its fast response time, large transient power, low leakage current, small breakdown voltage deviation, and easy-to-control clamping voltage, it has been widely used in various fields such as precision electronic components and communication equipment.

[0003] After the trench of the TVS tube is shaped, the PN junction is affected by the external environment (such as impurity pollution and stress), which can significantly change the performance of the device, thereby affecting the stability of the device and even causing the failure of the device application. At present, the TVS diode product usually uses SIPOS film + glass or pure SiO2 or glass as the PN junction passivation insulating layer. The above three passivation methods mainly have the following problems:

[0004] 1) When SIPOS film + glass passivation (or glass passivation alone) is used, the semi-insulating and electrically neutral SIPOS film can make the induced charge flow into the semi-insulating polysilicon under the external environment, thereby relieving the surface electric field of the potential barrier region and improving the PN junction voltage resistance, reliability and stability of the product. However, this process needs to be combined with glass passivation, which has high production cost and high stress during glass passivation, resulting in large IR of the device affected by stress and hidden cracks in the glass during cutting, which can easily cause reliability failure;

[0005] 2) When pure SiO2 insulating film is used for insulation passivation, the passivation layer will be disturbed by the external electric field and the movable charges on the surface of the PN junction, which cannot effectively prevent the accumulation of surface charges and metal ion contamination of the device. In addition, the carrier injection into the insulator of silicon dioxide can be stored and long-term residence, which changes the conductivity of the surface region of the device and degrades the reverse characteristics of the PN junction, ultimately affecting the overall voltage resistance, high-temperature characteristics and reliability of the high-voltage TVS tube, resulting in a decrease in product quality. In the vast application market of protective devices, improving the reliability and stability of the device and reducing the stress of the device has become an important research field of semiconductor devices. SUMMARY

[0006] In view of the above problems, the present application provides a high-voltage TVS product and a PN junction passivation process thereof, which can effectively improve the reliability and stability of the device and reduce the stress of the device at a low production cost.

[0007] The technical solution of the present application is: a PN junction passivation process of a high-voltage TVS product, comprising the following steps:

[0008] S100, diffusion

[0009] Depositing a layer of phosphorus and boron on the wafer surface to form a P+-N-N+ structure;

[0010] S200, selective lithography

[0011] Regionalizing the wafer into dies and exposing the areas to be etched on the die surface, and protecting other areas with photoresist;

[0012] S300, trench etching

[0013] Etching the areas exposed on the die surface to form etching grooves extending downward to the N layer substrate area and in an elliptical structure on the silicon surface;

[0014] S400, SIPOS;

[0015] S410, long SIPOS film

[0016] Through low pressure chemical vapor deposition, N2O / SIH4 is subjected to thermal decomposition reaction to deposit a SIPOS film on the product surface;

[0017] S420, densification

[0018] In the LPCVD process, through high temperature annealing, the interstitial oxygen atoms in the SIPOS film are freed from the silicon network and form more stable O-Si-O bonds with the oxidation of silicon outside the network;

[0019] S430, long MTO film

[0020] Through medium temperature oxidation, a long MTO film is deposited on the SIPOS film to increase the protection of the SIPOS film;

[0021] S500, SI3N4 deposition long SI3N4 film

[0022] Through low pressure chemical vapor deposition, a dense SI3N4 film is deposited on the surface of the SIPOS film, and the reaction formula is mainly: 3SiH2Cl2+7NH3→Si3N4↓+3NH4Cl+3HCl+6H2↑

[0023] S600, insulation passivation long SIO2 film

[0024] Through the LPCVD process, a dense SIO2 insulation passivation layer is formed on the surface of the SI3N4 film;

[0025] S700, selective lithography

[0026] The passivation layer in the die trench is protected with photoresist, and the mesa and cutting passivation film is exposed;

[0027] S800, electrode surface oxide film removal

[0028] The passivation film on the wafer surface is removed to prepare for subsequent metallization.

[0029] S900, metallization

[0030] An electrode metal layer is plated on the wafer surface, and the processing is completed.

[0031] Specifically, in step S300, since the PN junction reverse withstand voltage is required, the etching groove is dug through the P+ junction to the base region N+, and the etching depth is determined according to the depth of the P+ junction and the depth of the base region N+. Generally, the etching depth is 50-150um, and the width is 200-500um.

[0032] Specifically, in step S410, the N2O / SIH4 flow ratio is 0.1-0.5; the reaction pressure is (0.25-0.28) x 133.3 Pa; and the deposition temperature is 600±70℃.

[0033] Specifically, in S420, the high-temperature annealing temperature is 810±30℃, and the time is 40±20min.

[0034] Specifically, in S430, the medium-temperature oxidation deposition temperature is 700±50℃, the N2O / SIH4 flow ratio is 5-10, and the deposition time is 60±20min.

[0035] Specifically, in S500, the NH3 / SiH2Cl2 flow ratio is 1.2-1.7;

[0036] The reaction pressure is (0.25-0.28) x 133.3 Pa;

[0037] The deposition temperature is 800±50℃.

[0038] Specifically, in step S600, in the LPCVD process:

[0039] The SiO2 insulation passivation temperature is 850±50℃;

[0040] The SiH4 / O2 flow ratio is 0.8-0.95;

[0041] The time is 90±20min.

[0042] A high-voltage TVS product includes an N+ layer, an N layer, and a P+ layer connected in sequence from bottom to top;

[0043] The P+ layer is provided with an etching groove of an elliptical structure etched downward to the N layer;

[0044] The etching groove is provided with SIPOS film, SI3N4 film and SiO2 film connected in sequence from bottom to top, and the end thereof extends to the top surface of P+ layer respectively;

[0045] The top surface of the P+ layer is provided with an upper electrode metal layer connected with the SIPOS film, SI3N4 film and SiO2 film.

[0046] The bottom of the N+ layer is provided with a lower electrode metal layer.

[0047] The top surface of the upper electrode metal layer is higher than the top surface of the SI3N4 film.

[0048] In the working process of the application, the SIPOS film passivation is combined with the Si3N4 and SiO2 film passivation mode in the high-voltage TVS manufacturing process, after the deposition of the SIPOS film, a layer of Si3N4 and dense SiO2 film is continuously grown on the surface thereof by using LPCVD, which has the remarkable characteristics of simple structure and convenient manufacturing.

[0049] a. The passivation layer uses LPCVD technology throughout, and a layer of Si3N4 and dense SiO2 film is deposited on the surface of the SIPOS without damaging the structure of the SIPOS, which replaces the traditional glass passivation as an insulating layer with dense Si3N4 film, so that the product has good voltage resistance, high temperature characteristics and reliability, while reducing the production cost;

[0050] b. Without glass passivation, the impurity pollution at the PN junction caused by the glass melting process and the bonding stress between the glass and silicon are reduced, the reverse leakage current is reduced, and the product reliability is improved;

[0051] c. Without glass in the trench, it is beneficial for wafer cutting operation, avoiding the risk of damage to the glass in the trench during cutting, and reducing the potential risk of the product caused by glass problems;

[0052] d. Without glass on the mesa, the effective area of the wafer mesa is increased, which can avoid the problems of glass hidden cracking and less solder paste on the mesa during packaging, and improve the product capacity. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 is the structural schematic diagram of step S100 of the application,

[0054] Figure 2 is the structural schematic diagram of step S200 of the application,

[0055] Figure 3 is the structural schematic diagram of step S300 of the application,

[0056] Figure 4 is the structural schematic diagram of step S400 of the application,

[0057] Figure 5 This is a structural schematic diagram of step S500 of the present invention.

[0058] Figure 6 This is a structural schematic diagram of step S700 of the present invention.

[0059] Figure 7 This is a structural schematic diagram of step S800 of the present invention.

[0060] Figure 8 This is a structural schematic diagram of step S900 of the present invention.

[0061] In the figure, 100 is the SIPOS film, 200 is the SI3N4 film, 300 is the SiO2 film, 410 is the upper electrode metal layer, and 420 is the lower electrode metal layer. Detailed Implementation

[0062] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0063] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0064] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0065] The following is for reference. Figures 1-8 Describe the present invention;

[0066] A passivation process for the PN junction of a high-voltage TVS product includes the following steps:

[0067] S100, diffusion

[0068] Depositing a layer of phosphorus and boron on the wafer surface to form a P+-N-N+ structure; refer to Figure 1 ;

[0069] S200, selective lithography

[0070] Regionalizing the wafer into dies and exposing the areas to be etched on the die surface, and protecting other areas with photoresist; refer to Figure 2 ;

[0071] S300, trench etching

[0072] Etching the exposed areas on the die surface to form etching grooves on the silicon surface extending downward to the N layer substrate area and in an elliptical structure; and exposing the PN junction of the TVS product to form a voltage-resistant structure;

[0073] S400, SIPOS; refer to Figure 4 ;

[0074] S410, long SIPOS film 100

[0075] Through low pressure chemical vapor deposition (LPCVD), N2O / SIH4 is subjected to thermal decomposition reaction at 600±70℃, (0.25~0.28)×133.3 Pa, to deposit a SIPOS film on the product surface (mainly P / N junction); the reaction formula is mainly: SiH4+N2O→SiO X +N2+2H2↑

[0076] S420, densification

[0077] In the LPCVD process, through high-temperature annealing, the interstitial oxygen atoms in the SIPOS film are freed from the silicon network and form more stable O-Si-O bonds or other higher-valence silicon oxides with the oxidation outside the network; high-temperature annealing makes the film change from amorphous structure to polycrystalline, forming a recrystallization process, reducing the grain boundary density and increasing the densification and protection effect.

[0078] S430, long MTO film

[0079] Through medium-temperature oxidation, a long MTO film is deposited on the SIPOS film 100 to increase the protection of the SIPOS film 100;

[0080] S500, SI3N4 deposition long SI3N4 film 200, refer to Figure 5 ;

[0081] Through low pressure chemical vapor deposition (LPCVD), a dense SI3N4 film is deposited on the surface of the SIPOS film 100, with a film thickness of 700-1200 angstroms; the reaction formula is mainly:

[0082] 3SiH2Cl2+7NH3→Si3N4↓+3NH4Cl+3HCl+6H2↑

[0083] S600, forming a long SIO2 insulation passivation film 300

[0084] A dense SIO2 insulation passivation layer 300 is formed on the surface of the Si3N4 thin film by the LPCVD process at a temperature of 850±50℃, a SiH4 / O2 flow ratio of 0.8-0.95, and a time of 90±20min.

[0085] S700, selective lithography, refer to Figure 6 shown;

[0086] The passivation layer in the grain trench is protected by the photoresist through the method of selective lithography, and the mesa and the cutting path passivation film are exposed;

[0087] S800, electrode surface oxide film removal, refer to Figure 7 shown;

[0088] The passivation film on the surface of the grain mesa and the cutting path is removed by the method of wet etching or dry etching, preparing for subsequent metallization;

[0089] S900, metallization, refer to Figure 8 shown;

[0090] An electrode metal (TI / NI / AG or NI / Au) is plated on the surface of the wafer, and the processing is completed.

[0091] Further limitation, in step S300, due to the requirement of PN junction reverse voltage resistance, the etching groove is dug through the P+ junction to the base region N+ (the groove depth is about 30um deeper than the base region), so according to the depth of P+ junction and the depth of base region N+ junction, the etching depth is determined. Generally, the etching path depth is 50-150um, and the width is 200-500um.

[0092] Further limitation, in step S410, the N2O / SIH4 flow ratio is 0.1-0.5; the reaction pressure is (0.25-0.28)×133.3Pa; the deposition temperature is 600±70℃.

[0093] The deposition rate of the SIPOS film 100 is proportional to the temperature and the gas flow, and within this temperature and flow ratio range, the deposition rate is relatively stable; the deposition pressure will affect the uniformity of the SIPOS film 100 between single pieces, and the growth rate at the edge of the wafer is faster than the center, and the deposition pressure in this range can make the film thickness on each silicon wafer more uniform.

[0094] Further limitation, in S420, the high-temperature annealing temperature is 810±30℃, and the time is 40±20min.

[0095] Further limit, in S430, the deposition temperature of the medium temperature oxidation is 700±50℃, the flow ratio of N2O / SiH4 is 5-10; the deposition time is 60±20min.

[0096] Further limit, in S500, the flow ratio of NH3 / SiH2Cl2 is 1.2-1.7;

[0097] The reaction pressure is (0.25-0.28)×133.3Pa;

[0098] The deposition temperature is 800±50℃. Under this process condition, the uniformity of the silicon nitride film is good, the stress is small, and the corrosion resistance is good.

[0099] Further limit, in S600, in the LPCVD process:

[0100] The temperature of the SiO2 insulation passivation is 850±50℃;

[0101] The flow ratio of SiH4 / O2 is 0.8-0.95;

[0102] The time is 90±20min. This process condition can meet the SiO2 film thickness and ensure the film thickness uniformity.

[0103] A high-voltage TVS product includes an N+ layer, an N layer, and a P+ layer connected in sequence from bottom to top;

[0104] The P+ layer is provided with an etching groove of an elliptical structure etched downward to the N layer;

[0105] The etching groove is provided with a SIPOS film 100, a SI3N4 film 200, and a SiO2 film 300 connected in sequence from bottom to top, and the end portions of the SIPOS film, the SI3N4 film, and the SiO2 film respectively extend to the top surface of the P+ layer and are spaced apart from the edge of the device;

[0106] To prevent poor protection of the sharp corners of the etched groove, resulting in sharp corner discharge phenomenon when the product is reverse biased, the top ends of the three passivation films are required to respectively extend to the top surface of the P+ layer and are spaced apart from the edge of the device, generally 25-60um;

[0107] The top surface of the P+ layer is provided with an upper electrode metal layer 410 connected with the SIPOS film 100, the SI3N4 film 200, and the SiO2 film 300.

[0108] Further limit, the bottom of the N+ layer is provided with a lower electrode metal layer 420.

[0109] Further limit, the top surface of the upper electrode metal layer 410 is higher than the top surface of the SI3N4 film 200.

[0110] For the disclosed content, the following points need to be explained:

[0111] (1) The disclosed embodiment of the present case only involves the structure involved in the disclosed embodiment of the present case, and other structures can be referred to the usual design.

[0112] (2) In the case of no conflict, the disclosed embodiments and the features in the embodiments can be combined to obtain new embodiments;

[0113] The above is only a specific embodiment of the present case, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A PN junction passivation process for high voltage TVS products, characterized in that, Includes the following steps: S100, diffusion: A layer of phosphorus and boron is deposited on the wafer surface to form a P⁺-NN⁺ structure; S200, selective lithography: the wafer is divided into grains, and the area to be etched is exposed on the surface of the grains, while other areas are protected with photoresist; S300, trench etching: etching the area exposed on the surface of the grain to form an elliptical etching trench on the silicon surface that extends downward to the N-layer substrate region. The etching trench penetrates the P⁺ junction to the N⁺ base region and the trench depth is 30um deeper than the base region. The depth of the etching trench is 50-150um and the width is 200-500um. S400, SIPOS: S410, long SIPOS film: Through low-pressure chemical vapor deposition, N2O and SiH4 undergo thermal decomposition reaction under the conditions of flow ratio 0.1-0.5, reaction pressure (0.25~0.28)×133.3Pa, and deposition temperature 600±70℃, and a SIPOS film is deposited on the product surface. S420, densification: In the LPCVD process, high-temperature annealing at 810±30℃ for 40±20min causes interstitial oxygen atoms in the SIPOS film to be released outside the silicon network and form more stable O-Si-O bonds with the silicon oxide phase outside the network. S430, long MTO film: MTO film is deposited on SIPOS film by medium-temperature oxidation. The medium-temperature oxidation deposition temperature is 700±50℃, the N2O / SiH4 flow ratio is 5-10, and the deposition time is 60±20min. S500, Si3N4 deposition of long Si3N4 film: A dense Si3N4 film is deposited and grown on the surface of the SIPOS film by low-pressure chemical vapor deposition (LPCVD). The main reaction formula is 3SiH2Cl2 + 7NH3 → Si3N4↓ + 3NH4Cl + 3HCl + 6H2↑, where the NH3 / SiH2Cl2 flow ratio is 1.2-1.7, the reaction pressure is (0.25~0.28)×133.3Pa, the deposition temperature is 800±50℃, and the Si3N4 film thickness is 700-1200 angstroms. S600, Insulating and Passivating Long SiO2 Film: A dense SiO2 insulating and passivating layer is formed on the surface of a Si3N4 thin film by LPCVD process under the conditions of temperature 850±50℃, SiH4 to O2 flow ratio 0.8-0.95, and time 90±20min. S700, selective photolithography: the passivation layer in the grain trench is protected with photoresist, the passivation film of the mesa and the dicing channel is exposed, and the ends of the SIPOS film, Si3N4 film and SiO2 film extend to the top surface of the P⁺ layer, with a 25-60um gap reserved with the edge of the device. S800, electrode surface oxide film removal: Remove the passivation film on the grain mesa and dicing surface to prepare for subsequent metallization; S900, Metallization: A layer of electrode metal is deposited on the surface of the wafer, and the processing is completed; In the above steps, the deposition of the SIPOS film, the Si3N4 film and the SiO2 film all adopt the LPCVD technology, and no glass melting and glass passivation related process steps are involved.

2. A high voltage TVS product prepared by the PN junction passivation process of claim 1, characterized in that, The N+ layer, the N layer and the P+ layer are sequentially connected from bottom to top; The P+ layer is provided with an etching groove of an elliptical structure etched downward to the N layer; The etching groove is provided with a SIPOS film, a Si3N4 film and a SiO2 film sequentially connected from bottom to top, and the end portions of the SIPOS film, the Si3N4 film and the SiO2 film extend to the top surface of the P+ layer respectively; The top surface of the P+ layer is provided with an upper electrode metal layer connected with the SIPOS film, the Si3N4 film and the SiO2 film.

3. The high voltage TVS product of claim 2, wherein, The bottom of the N+ layer is provided with a lower electrode metal layer.

4. The high voltage TVS product of claim 2, wherein, The top surface of the upper electrode metal layer is higher than the top surface of the Si3N4 film.

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