A flexible direct current transmission converter valve control link architecture and its delay optimization method

Abstract

The present application relates to the technical field of flexible direct current transmission, and discloses a flexible direct current transmission converter valve control link architecture and a delay optimization method thereof, wherein a valve control uplink, a valve control downlink and a valve control protection link are formed in the valve control link architecture, the output end of the power module controller in the valve control uplink is sequentially connected to the converter control protector through a pulse distribution board, a switching board, an arm control board and a main control board, the output end of the switching board is also connected to a background link to form a data shunt structure, so that the valve control uplink is facilitated to be optimized in terms of delay; the valve control downlink is connected to the main control board through the output end of an FPGA processing module, the output end of a coding compression module is connected to the arm control board, and the output end of a decoding restoration module is connected to the pulse distribution board, so that the valve control downlink is facilitated to be optimized in terms of delay; the output end of a measurement unit is sequentially connected to a protection board and then to the arm control board, so that the information transmission time is reduced, and the valve control protection link is facilitated to be optimized in terms of delay.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flexible direct current transmission, in particular to a flexible direct current transmission converter valve control link architecture and a delay optimization method thereof. BACKGROUND

[0002] Flexible direct current transmission technology is a new type of direct current transmission technology based on full-controlled power electronic devices, voltage source converters and pulse width modulation technology. The flexibility of control of flexible direct current transmission makes it have broad application prospects in large-scale renewable energy such as wind power grid connection, power supply to passive networks, urban distribution network capacity expansion, asynchronous AC grid interconnection, etc. In addition, compared with traditional thyristor valves, flexible direct current valves do not require filters, and direct current buses do not require capacitors. The valve group adopts modular design and redundant control, which not only facilitates expansion and maintenance, but also has the advantages of multiple output voltage levels, low harmonic content, low switching loss, etc.

[0003] The flexible direct current transmission control and protection system is the "brain" of the flexible direct current transmission, responsible for controlling the smooth operation of the flexible direct current system and ensuring the rapid and accurate action of the protection device. The hierarchical architecture of the flexible direct current transmission control and protection system is shown in the following figure Figure 1 The system can be divided into four levels of system-level and station-level control (SSC), converter control protection (CCP, also known as pole control), valve control monitoring (VCM) and power module control (PMC). Among them, the valve control monitoring (VCM) can be divided into two levels of valve control interface device (VCMI) and valve group control (VGC). VCMI is also called valve control host screen, and VGC is also called pulse distribution screen. VCM belongs to the valve-level control and protection system in all control levels of the converter station, and mainly completes the pulse modulation of the converter valve, pulse distribution and related protection functions. VCM receives the control and protection commands issued by CCP, and feeds back part of the state information of the converter valve to CCP, at the same time, sends control commands to the lower layer pulse distribution screen, and receives the power module state and fault information received by the pulse distribution screen.

[0004] The flexible direct current transmission control protection system device is multiple, the communication data amount between the devices is large, and the flexible direct current transmission control protection system link delay needs to be optimized according to the extreme control (CCP) and the valve control (VCM) in stages. SUMMARY

[0005] In order to overcome the defects existing in the prior art, the purpose of the present application is to provide a flexible direct current transmission converter valve control link architecture and a delay optimization method thereof, so as to solve the technical problems that the flexible direct current transmission control protection system delay leads to poor dynamic response of the system, reduces the fault ride-through capability of the flexible direct current transmission system, and threatens the stability of the system.

[0006] The present application is realized by the following technical solutions:

[0007] A flexible direct current transmission converter valve control link architecture, an input end of the valve control link architecture is connected with a converter control protector and a measurement unit link; an output end of the valve control link architecture is connected with a power module controller and a background link; the valve control link architecture comprises a valve control host cabinet and a pulse distribution cabinet connected by links; wherein the valve control host cabinet comprises a main control board, a bridge arm control board, a protection board, an FPGA processing module and a coding compression module; the pulse distribution cabinet comprises a switching board, a pulse distribution board and a decoding restoration module; an output end of the power module controller sequentially passes through the pulse distribution board, the switching board, the bridge arm control board, the main control board to the converter control protector to form a valve control uplink, wherein an output end of the switching board is also connected with the background link; an output end of the converter control protector sequentially passes through the main control board, the bridge arm control board, the switching board and the pulse distribution board to the power module controller to form a valve control downlink; wherein an output end of the FPGA processing module is connected to the main control board, an output end of the coding compression module is connected to the bridge arm control board, and an output end of the decoding restoration module is connected to the pulse distribution board; an output end of the measurement unit sequentially passes through the protection board, the bridge arm control board, the switching board and the pulse distribution board to the power module controller to form a valve control protection link.

[0008] Preferably, the valve control uplink between the pulse distribution board and the switching board is divided into two branches, one of which is connected to the background through the switching board, and the other is connected to the converter control protector through the switching board, the bridge arm control board and the main control board in turn.

[0009] Preferably, the valve control downlink and the valve control protection link are in the same direction in the pulse distribution cabinet and are two independent channels, and the valve control uplink is opposite to the valve control downlink and the valve control protection link in the pulse distribution cabinet.

[0010] A delay optimization method of a flexible DC power transmission converter valve control link architecture, based on any one of claims 1-3, respectively optimizes the valve control uplink, the valve control downlink and the valve control protection link, and the specific process is as follows:

[0011] The optimization process of the valve control uplink is as follows:

[0012] After receiving the message data of the power module controller, the pulse distribution board divides the message data into control data and monitoring data, and sends the monitoring data to the background through the network port of the switching board after the switching board, reduces the occupation of the monitoring data on the control data link in communication, improves the communication period of the control data link, reduces the delay of the uplink control link, and the control data is sent to the converter control protector through the switching board, the bridge arm control board and the main control board in turn;

[0013] The optimization process of the valve control downlink is as follows:

[0014] The data issued by the converter control protector is sent to the bridge arm control board after being processed by the FPGA processing module, and the bridge arm control board needs to pre-process the module sorting, then waits for the difference value of the bridge arm input module number of the FPGA processing module, and after updating the value, refreshes the trigger pulse of this bridge arm, where the trigger pulse encodes data according to the sequence control state, so as to compress the length of the subsequent uplink data packet, improve the communication period, and reduce the subsequent link delay. The encoded trigger pulse is sent to the power module controller after being decoded by the data terminal pulse distribution board.

[0015] The optimization process of the valve control protection link is as follows:

[0016] The measurement unit sends data to the protection board, the protection board performs protection calculation, and sends the protection result in the form of frequency signal to the bridge arm control board in real time through the cabinet backplane. The bridge arm control board analyzes the frequency signal into a protection action result, and applies the result to the valve control sequence control state. At the same time, the bridge arm control board packs the protection result, and sends it to the switching board through the bridge arm control board. The switching board converts the sequence control state and the protection result into frequency signals again, and sends them to the power module controller through the pulse distribution board.

[0017] Preferably, the message information includes module voltage information, module type information, module temperature information, module detailed fault state information and bypass fault bit information determined after module failure; wherein the module voltage information, the module type information and the bypass fault bit information determined after module failure are control data; the module temperature information and the module detailed fault state information are monitoring data.

[0018] Preferably, in the optimization process of the valve control uplink, the valve control uplink between the pulse distribution board and the switching board includes a backplane monitoring data link and a backplane control data link, wherein the monitoring data is sent to the background along the backplane monitoring data link to the network port of the switching board; the control data is sent along the backplane control data link to the converter control protector through the switching board, the bridge arm control board and the main control board.

[0019] Preferably, in the optimization process of the valve control downlink, the FPGA processing module calculates the bridge arm input module number difference value through the modulation voltage, the circulating current suppression voltage, the input module voltage and the module average voltage.

[0020] Preferably, in the optimization process of the valve control protection link, when the link from the bridge arm control board to the switching board is occupied, the bridge arm control board executes the lockout protection through the sequence control state in the data after the bridge arm control board packs the protection result; when the link is idle and the protection result is valid, the protection result is sent to the switching board in real time, the gap when the link is idle is utilized, and the protection delay is reduced.

[0021] Preferably, in the optimization process of the valve control protection link, the switching board converts the sequence control state and the protection result into a frequency signal again and sends the frequency signal to the pulse distribution board in real time through the backplane, and the pulse distribution board analyzes the protection signal to lock the trigger pulse and send the trigger pulse to the power module controller.

[0022] Preferably, in the optimization process of the valve control protection link, the frequency signal includes a low frequency 1MHz representing that the protection result is invalid and a high frequency 10MHz representing that the protection result is valid; the bridge arm control board analyzes the frequency signal into a protection action result, and applies the result to the valve control sequence control state; when the protection result is invalid, the sequence control state is unchanged; when the protection result is valid, the sequence control state jumps to the lockout state to lock the converter valve.

[0023] Compared with the prior art, the present application has the following beneficial technical effects:

[0024] The application provides a flexible direct current transmission converter valve control link architecture, by forming a valve control uplink, a valve control downlink and a valve control protection link in the valve control link architecture, and by making the output end of the power module controller in the valve control uplink sequentially pass through a pulse distribution board, a switching board, an arm control board, a main control board and a converter control protector, and by making the output end of the switching board also connected with a background link to form a data shunting structure to facilitate delay optimization of the valve control uplink; in the valve control downlink, the output end of an FPGA processing module is connected to the main control board, the output end of an encoding compression module is connected to the arm control board, and the output end of a decoding restoration module is connected to the pulse distribution board, to facilitate delay optimization of the valve control downlink; the output end of a measurement unit is sequentially connected to a protection board and directly connected to the arm control board, to reduce information transmission time and facilitate delay optimization of the valve control protection link, after delay optimization of the three links, the system real-time performance is greatly improved, the dynamic response characteristics of the system are improved, the fault ride-through capability of the flexible direct current system is significantly enhanced, the system operation stability is improved, and power oscillation is avoided.

[0025] Further, the valve control uplink between the pulse distribution board and the switching board is divided into two branches, one branch is connected to the background through the switching board, and the other branch sequentially passes through the switching board, the arm control board, the main control board and the converter control protector, a data shunting strategy is adopted, so that the data do not occupy each other's data link, and delay optimization of the valve control uplink is facilitated.

[0026] The application also provides a delay optimization method of the flexible direct current transmission converter valve control link architecture, the uplink delay optimization adopts a control data and monitoring data shunting strategy, the monitoring data is directly sent to the local background and SCADA through the switching board network port after the switching board, without occupying the control data link, to facilitate delay optimization of the valve control uplink; the downlink delay optimization utilizes the strong parallel processing and calculation capability of the FPGA, calculates the number of bridge arm input modules and sorts the sub-module voltages, refreshes the trigger pulse after the two processes are completed, encodes the trigger pulse combined with the sequence control state, and compresses the downlink data packet length to optimize the delay. The protection link delay optimization utilizes the advantage of high-frequency square wave signals in real-time performance, and high-frequency square wave signals are used to transmit the protection results in the cabinet; when the link is occupied, the protection results are executed through the sequence control state in the data between the cabinets, and the protection results are sent in real time when the link is idle and the protection results change. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a traditional technology flexible direct current control protection hierarchical architecture schematic diagram;

[0028] Figure 2 It is a flexible direct current transmission converter valve control link architecture schematic diagram in the application;

[0029] Figure 3 For the valve control uplink delay optimization schematic in the present application;

[0030] Figure 4 For the valve control downlink delay optimization schematic in the present application;

[0031] Figure 5 For the valve control protection link delay optimization schematic in the present application.

[0032] In the figure: 1 - valve control host chassis; 2 - pulse distribution chassis; 3 - converter control protector; 4 - measurement unit; 5 - power module controller; 6 - background; 7 - valve control uplink; 8 - valve control downlink; 9 - valve control protection link; 11 - master control board; 12 - bridge arm control board; 13 - protection board; 14 - FPGA processing module; 15 - encoding compression module; 21 - switching board; 22 - pulse distribution board; 23 - decoding restoration module. DETAILED DESCRIPTION

[0033] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiment of the present application will be described clearly and completely in the following by combining the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, not all. Based on the embodiment in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application.

[0034] The present application will be further described in detail in the following by combining the drawings:

[0035] The purpose of the present application is to provide a flexible DC power transmission converter valve control link architecture and its delay optimization method, so as to solve the technical problems of poor dynamic response of the system, reduced fault ride-through capability of the flexible DC system and threatened system operation stability caused by the delay of the existing flexible DC control protection system.

[0036] According to Figure 2As shown, the input end of the flexible HVDC converter valve control link architecture is linked with the converter control protector 3 and the measurement unit 4; the output end of the valve control link architecture is linked with the power module controller 5 and the background 6; wherein the valve control link architecture comprises the valve control host cabinet 1 and the pulse distribution cabinet 2 which are linked; wherein the valve control host cabinet 1 comprises the main control board 11, the bridge arm control board 12, the protection board 13, the FPGA processing module 14 and the encoding compression module 15; the pulse distribution cabinet 2 comprises the switching board 21, the pulse distribution board 22 and the decoding restoration module 23; the output end of the power module controller 5 is sequentially linked with the pulse distribution board 22, the switching board 21, the bridge arm control board 12, the main control board 11 and the converter control protector 3 to form the valve control uplink 7, wherein the output end of the switching board 21 is also linked with the background 6; the output end of the converter control protector 3 is sequentially linked with the main control board 11, the bridge arm control board 12, the switching board 21 and the pulse distribution board 22 to form the valve control downlink 8; wherein the output end of the FPGA processing module 14 is connected to the main control board 11, the output end of the encoding compression module 15 is connected to the bridge arm control board 12, and the output end of the decoding restoration module 23 is connected to the pulse distribution board 22; the output end of the measurement unit 4 is sequentially linked with the protection board 13, the bridge arm control board 12, the switching board 21 and the pulse distribution board 22 to form the valve control protection link 9.

[0037] Specifically, the valve control uplink 7 between the pulse distribution board 22 and the switching board 21 is divided into two branches, one of which is connected to the background 6 through the switching board 21, and the other is sequentially connected to the converter control protector 3 through the switching board 21, the bridge arm control board 12 and the main control board 11.

[0038] Specifically, the valve control downlink 8 and the valve control protection link 9 are in the same direction within the pulse distribution cabinet 2 and are two independent channels, and the valve control uplink 7 is opposite to the valve control downlink 8 and the valve control protection link 9 within the pulse distribution cabinet 2.

[0039] The application also provides a delay optimization method of the flexible HVDC converter valve control link architecture, which is based on the above-mentioned flexible HVDC converter valve control link architecture, and the valve control uplink 7, the valve control downlink 8 and the valve control protection link 9 are optimized respectively, and the specific process is as follows:

[0040] According to Figure 3 As shown, the optimization process of the valve control uplink 7 is as follows:

[0041] After receiving the message data from the power module controller 5, the pulse distribution board 22 divides the message data into control data and monitoring data, the monitoring data is sent to the background 6 through the network port of the switching board 21, reducing the occupation of the control data link in communication by the monitoring data, improving the communication period of the control data link, reducing the uplink control link delay, and the control data is sequentially sent to the converter control protector 3 through the switching board 21, the bridge arm control board 12 and the main control board 11;

[0042] The message information includes module voltage information, module type information, module temperature information, module detailed fault state information and bypass fault bit information determined after module failure; wherein the module voltage information, the module type information and the bypass fault bit information determined after the module failure are control data, which is needed in the valve control and pressure equalization control; the module temperature information and the module detailed fault state information are monitoring data, which is only used in the background monitoring, fault recording and state evaluation, and these detailed information is not needed in the control module. Generally, the monitoring data is several times of the control data, so stripping the monitoring data can greatly reduce the data packet length and reduce the control link delay. At the same time, in order to increase the communication redundancy between the modules, the cross communication mode is generally used, which increases the communication message information between the valve control and the module by one time, so there is a large space for optimizing the uplink delay.

[0043] In the optimization process of the valve control uplink 7, the valve control uplink 7 between the pulse distribution board 22 and the switching board 21 includes a backboard monitoring data link and a backboard control data link, wherein the monitoring data is sent to the background 6 through the network port of the switching board 21 along the backboard monitoring data link; the control data is sent to the converter control protector 3 through the switching board 21, the bridge arm control board 12 and the main control board 11 along the backboard control data link.

[0044] The control data is communicated through the control link, and the monitoring data is communicated through the monitoring link, so as to reduce the occupation of the control link in communication by the monitoring data, improve the communication period of the control link and reduce the uplink control link delay; the switching board and the pulse distribution board in the valve control pulse distribution cabinet have point-to-point MLVDS channels and full-through MLVDS channels, wherein the point-to-point MLVDS is used as the control data link, and the full-through MLVDS channel is used as the monitoring data link.

[0045] The monitoring data is sent to the pulse distribution cabinet through the monitoring link, and then directly sent to the SCADA through the network port of the switching board, so that the monitoring data is no longer uploaded to the SCADA through the valve control main cabinet (VCMI), and only the control data is uploaded to the VCMI, thereby optimizing the uplink control link delay from the pulse distribution cabinet to the VCMI.

[0046] According to Figure 4As shown, the optimization process of the valve-controlled downlink 8 is as follows:

[0047] The data sent by the converter control protector 3 is processed by the FPGA processing module 14 and then sent to the bridge arm control board 12. The bridge arm control board 12 needs to pre-process the module sorting, and then waits for the difference value of the bridge arm input module number of the FPGA processing module 14. After the value is updated, the bridge arm trigger pulse is refreshed. The trigger pulse is encoded according to the sequence control state, so as to compress the subsequent uplink data packet length, improve the communication period, reduce the subsequent link delay, and compress the single module control word from 4 bits before data encoding to 2 bits after data encoding according to the sequence control state. The data packet length is compressed by one time, half of the transmission time is saved, the data transmission efficiency is improved, and the delay is reduced. The encoded trigger pulse is sent to the power module controller 5 through the data end pulse distribution board.

[0048] In the optimization process of the valve-controlled downlink 8, the FPGA processing module 14 calculates the bridge arm input module number difference value by modulating the voltage, circulating current suppression voltage, input module voltage and module average voltage, without CPU board PPC processing, and uses the parallel processing capability of FPGA to reduce the processing delay of PPC operation. The FPGA processing of the CPU board is sent to the bridge arm control board (ACB board) in real time.

[0049] According to Figure 5 As shown, the optimization process of the valve-controlled protection link 9 is as follows:

[0050] The measurement unit 4 sends data to the protection board 13. After the bridge arm current, DC voltage and DC current of the MU or measurement device are received by the protection board 1, protection calculation is performed in real time, and the protection result is sent to the bridge arm control board 12 in real time in the form of a frequency signal through the chassis backplane. The frequency signal can be divided into two types, one is a low frequency of 1MHz indicating that the protection result is invalid, and the other is a high frequency of 10MHz indicating that the protection result is valid. Other frequencies are protection channel faults. The bridge arm control board 12 analyzes the frequency signal into a protection action result, and applies the result to the valve-controlled sequence control state. When the protection result is invalid, the sequence control state remains unchanged, and when the protection result is valid, the sequence control state jumps to the lockout state to lock the converter valve. At the same time, the bridge arm control board 12 packs the protection result, such as 16-bit 16 hexadecimal 0x5555 indicating that the protection is invalid, and 16-bit 16 hexadecimal 0xaaaa indicating that the protection is valid. When the protection determination result changes and the link is idle, the protection result is sent to the pulse distribution chassis switching board in real time. After passing through the bridge arm control board 12 to the switching board 21, the switching board 21 converts the sequence control state and the protection result into a frequency signal again, which is sent to the power module controller 5 through the pulse distribution board 22.

[0051] In the optimization process of the valve control protection link 9, the bridge arm control board 12 packages the protection result, and when the link from the bridge arm control board 12 to the switching board 21 is occupied, the lockout protection is performed through the sequence control state in the data, and when the link is idle and the protection result is valid, the protection result is sent to the switching board 21 in real time, the gap when the link is idle is utilized, and the protection delay is reduced.

[0052] In the optimization process of the valve control protection link 9, the switching board 21 converts the sequence control state and the protection result into frequency signals again and sends them to the pulse distribution board 22 in real time through the backplane, and the pulse distribution board 22 analyzes the protection signal to lock the trigger pulse and send it to the power module controller 5.

[0053] In summary, the application provides a DC power transmission converter valve control link architecture and a delay optimization method, which greatly optimizes the uplink, downlink and protection link 3 link delays of the valve control. After the link delay of the valve control system is optimized, the real-time performance of the system is greatly improved, the dynamic response characteristics of the system are improved, the fault ride-through capability of the flexible DC system is significantly enhanced, the system operation stability is improved, and power oscillation is avoided.

[0054] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the application and not to limit it, although the application has been described in detail with reference to the above examples, those skilled in the art should understand that the specific embodiments of the application can be modified or replaced, and any modification or equivalent replacement without departing from the spirit and scope of the application should be covered within the protection scope of the claims of the application.

Claims

1. A flexible direct current transmission converter valve gate link architecture, characterized by, The input end of the valve control link architecture is linked with a converter control protector (3) and a measurement unit (4); the output end of the valve control link architecture is linked with a power module controller (5) and a background (6); the valve control link architecture comprises a valve control host cabinet (1) and a pulse distribution cabinet (2); the valve control host cabinet (1) comprises a main control board (11), an arm control board (12), a protection board (13), an FPGA processing module (14) and an encoding compression module (15); the pulse distribution cabinet (2) comprises a switching board (21), a pulse distribution board (22) and a decoding restoration module (23); the output end of the power module controller (5) forms a valve control uplink (7) through the pulse distribution board (22), the switching board (21), the arm control board (12), the main control board (11) and the converter control protector (3) in sequence, wherein the output end of the switching board (21) is also linked with the background (6); the output end of the converter control protector (3) forms a valve control downlink (8) through the main control board (11), the arm control board (12), the switching board (21), the pulse distribution board (22) and the power module controller (5) in sequence; the output end of the FPGA processing module (14) is connected to the main control board (11), the output end of the encoding compression module (15) is connected to the arm control board (12), and the output end of the decoding restoration module (23) is connected to the pulse distribution board (22); the output end of the measurement unit (4) forms a valve control protection link (9) through the protection board (13), the arm control board (12), the switching board (21), the pulse distribution board (22) and the power module controller (5) in sequence; The data transmission mode of the valve control uplink (7) comprises that the pulse distribution board (22) receives the message data of the power module controller (5), divides the message data into control data and monitoring data, sends the monitoring data to the background (6) through the network port of the switching board (21) after the switching board (21), reduces the occupation of the monitoring data on the control data link in communication, improves the communication period of the control data link, reduces the uplink control link delay, and the control data passes through the switching board (21), the arm control board (12) and the main control board (11) to the converter control protector (3) in sequence; The data transmission mode of the valve control downlink (8) comprises that the converter control protector (3) sends data to the arm control board (12) after processing by the FPGA processing module (14), the arm control board (12) needs to pre-process the module sorting, then waits for the difference value of the bridge arm input module number of the FPGA processing module (14), and after the value is updated, the bridge arm trigger pulse is refreshed, the trigger pulse is encoded according to the sequence control state, the length of the subsequent uplink data packet is compressed to improve the communication period to reduce the subsequent link delay, and the encoded trigger pulse is sent to the power module controller (5) after being decoded by the pulse distribution board at the data end. The data transmission mode of the valve control protection link (9) includes that the measurement unit (4) sends data to the protection board (13), the protection board (13) performs protection calculation, and sends the protection result in the form of a frequency signal to the bridge arm control board (12) in real time through the chassis backplane, the bridge arm control board (12) analyzes the frequency signal into a protection action result, and applies the result to the valve control sequence control state, and the bridge arm control board (12) further packs the protection result, and sends the protection result to the switching board (21) through the bridge arm control board (12), and the switching board (21) converts the sequence control state and the protection result into a frequency signal again, and sends the frequency signal to the power module controller (5) through the pulse distribution board (22).

2. A flexible HVDC converter valve control link architecture according to claim 1, wherein, The valve control uplink (7) between the pulse distribution board (22) and the switching board (21) is divided into two branches, one of which is connected to the background (6) through the switching board (21), and the other is connected to the converter control protector (3) through the switching board (21), the bridge arm control board (12), and the main control board (11) in sequence.

3. A flexible HVDC converter valve control link architecture according to claim 1, wherein, The valve control downlink (8) and the valve control protection link (9) have the same direction in the pulse distribution chassis (2) and are two independent channels, and the valve control uplink (7) has the opposite direction to the valve control downlink (8) and the valve control protection link (9) in the pulse distribution chassis (2).

4. A method for delay optimization of a flexible HVDC converter valve control link architecture according to any one of claims 1 to 3, characterized in that The valve control uplink (7), the valve control downlink (8), and the valve control protection link (9) are optimized respectively, and the specific process is as follows: The optimization process of the valve control uplink (7) is as follows: After receiving the message data of the power module controller (5), the pulse distribution board (22) divides the message data into control data and monitoring data, the monitoring data is sent to the background (6) through the network port of the switching board (21) after passing through the switching board (21), reduces the occupation of the monitoring data on the control data link in communication, improves the communication period of the control data link, reduces the uplink control link delay, and the control data is sent to the converter control protector (3) through the switching board (21), the bridge arm control board (12), and the main control board (11) in sequence; The optimization process of the valve control downlink (8) is as follows: The data sent by the converter control protector (3) is processed by the FPGA processing module (14) and then sent to the bridge arm control board (12), the bridge arm control board (12) needs to pre-process the module sorting, then waits for the difference value of the bridge arm input module number of the FPGA processing module (14), and after updating the value, the bridge arm trigger pulse is refreshed, the trigger pulse is encoded according to the sequence control state, the length of the subsequent uplink data packet is compressed, the communication period is improved, and the subsequent link delay is reduced, the encoded trigger pulse is sent to the power module controller (5) after being decoded by the pulse distribution board at the data end; The optimization process of the valve control protection link (9) is as follows: The measurement unit (4) sends data to the protection board (13), the protection board (13) performs protection calculation, and sends the protection result in the form of a frequency signal to the bridge arm control board (12) in real time through the backplane of the cabinet, the bridge arm control board (12) analyzes the frequency signal into a protection action result, and applies the result to the valve control sequence control state, and at the same time, the bridge arm control board (12) packs the protection result again, and sends the protection result to the switching board (21) through the bridge arm control board (12), and the switching board (21) converts the sequence control state and the protection result into a frequency signal again, and sends the frequency signal to the power module controller (5) through the pulse distribution board (22).

5. The method of Claim 4, wherein, The message information includes module voltage information, module type information, module temperature information, module detailed fault state information and bypass fault bit information determined after module failure; wherein the module voltage information, the module type information and the bypass fault bit information determined after the module failure are control data; and the module temperature information and the module detailed fault state information are monitoring data.

6. The method of Claim 4, wherein, In the optimization process of the valve control uplink (7), the valve control uplink (7) between the pulse distribution board (22) and the switching board (21) includes a backplane monitoring data link and a backplane control data link, wherein the monitoring data is sent to the background (6) through the network port of the switching board (21) along the backplane monitoring data link; and the control data is sent to the converter control protector (3) through the switching board (21), the bridge arm control board (12) and the main control board (11) along the backplane control data link.

7. The method of Claim 4, wherein the method further comprises: In the optimization process of the valve control downlink (8), the FPGA processing module (14) calculates the difference value of the number of bridge arm input modules through the modulation voltage, the circulating current suppression voltage, the input module voltage and the module average voltage.

8. The method of Claim 4, wherein, In the optimization process of the valve control protection link (9), when the link between the bridge arm control board (12) and the switching board (21) is occupied, the bridge arm control board (12) executes the lockout protection through the sequence control state in the data; when the link is idle and the protection result is valid, the protection result is sent to the switching board (21) in real time, so as to utilize the interval when the link is idle and reduce the protection delay.

9. The method of Claim 4, wherein the method further comprises: In the optimization process of the valve control protection link (9), the switching board (21) converts the sequence control state and the protection result into a frequency signal again, and sends the frequency signal to the pulse distribution board (22) in real time through the backplane, and the pulse distribution board (22) analyzes the protection signal to trigger the pulse and send the pulse to the power module controller (5).

10. The method of Claim 4, wherein, In the optimization process of the valve control protection link (9), the frequency signal includes a low frequency 1MHz indicating that the protection result is invalid and a high frequency 10MHz indicating that the protection result is valid; the bridge arm control board (12) analyzes the frequency signal into a protection action result, and applies the result to the valve control sequence control state, and when the protection result is invalid, the sequence control state remains unchanged, and when the protection result is valid, the sequence control state jumps to the lockout state to lock the converter valve.

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