Semiconductor circuit and intelligent power module

Abstract

The application provides a semiconductor circuit and an intelligent power module, comprising: an HVIC chip, a heating wire, a humidity sensor and a temperature and humidity detection control circuit; an under-voltage detection circuit is connected between a plurality of filters and a fault logic control circuit; a first end of an interlocking circuit is connected with a plurality of level conversion circuits respectively, a second end of the interlocking circuit is connected with a high-voltage area output circuit, a third end of the interlocking circuit is connected with the fault logic control circuit and a comparison circuit respectively, the fault logic control circuit is also connected with a gate of a fault output MOS tube, a source of the fault output MOS tube is grounded, and a drain of the fault output MOS tube is connected with an output end; the temperature and humidity detection control circuit is connected with the fault logic control circuit, and the temperature and humidity detection control circuit is connected with the humidity sensor and the heating wire respectively, and is used for detecting humidity data collected by the humidity sensor and temperature data of the heating wire respectively. The application is convenient to integrate, is convenient to drive away invading insects and surface moisture, and has high reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of intelligent power modules, and in particular to a semiconductor circuit and an intelligent power module. BACKGROUND

[0002] High voltage integrated circuit, namely HVIC, is an integrated circuit product for converting MCU signals into driving IGBT signals. The HVIC integrates PMOS tubes, NMOS tubes, transistors, diodes, voltage stabilizing tubes, resistors and capacitors together to form circuits such as a Smith circuit, a low-voltage LEVELSHIFT, a high-voltage LEVELSHIFT, a pulse generating circuit, a delay circuit, a filter circuit, an overcurrent protection circuit and an overheat protection circuit, an under-voltage protection circuit and a bootstrap circuit. The HVIC receives control signals of the MCU on one hand and drives subsequent IGBT or MOS to work, and sends system state detection signals back to the MCU on the other hand. The HVIC is a key chip inside an intelligent power module IPM.

[0003] The application environment of the existing intelligent power module is relatively harsh, and it is often used in high-temperature and high-humidity, severe cold, coastal and other places. In particular, the integration of the module is getting higher and higher, and the pin gap tends to be dense. If the module is started in a high-humidity environment, the moisture attached to the surface of the module has not been driven away because the module has not yet heated up, and there is a pin gap leakage. Since the module is a non-hermetically sealed structure, moisture enters the inside of the module, causing internal leakage and module failure. In addition, since the air conditioner is used in an external environment, the module is a heat source and is easy to attract insects that like warmth to attach to the surface of the module, causing high voltage to electrically injure them when the module is started again, and affecting the electrical clearance between the module pins.

[0004] Therefore, the above semiconductor circuit is troublesome to integrate, has poor heat control effect, low reliability and small adaptation range. SUMMARY

[0005] In view of the deficiencies of the above related technologies, the present application provides a semiconductor circuit which is convenient to integrate, controls the working state of the heating wire according to the temperature and humidity, works in a low-humidity environment on one hand, and self-heats before starting to drive away insects on the surface of the module on the other hand, and has high reliability.

[0006] To solve the above technical problems, in a first aspect, embodiments of the present application provide a semiconductor circuit, comprising: an HVIC chip, a heating wire, a humidity sensor, and a temperature and humidity detection control circuit; the HVIC chip comprises a plurality of Schmitt circuits, a plurality of filters, a plurality of level conversion circuits, an under-voltage detection circuit, an interlock circuit, a fault logic control circuit, a fault output MOS tube, and a high-voltage area output circuit; the plurality of Schmitt circuits are connected in sequence to the plurality of filters, the plurality of level conversion circuits, and the fault logic control circuit; the under-voltage detection circuit is connected between the plurality of filters and the fault logic control circuit; a first end of the interlock circuit is connected to the plurality of level conversion circuits, a second end of the interlock circuit is connected to the high-voltage area output circuit, and a third end of the interlock circuit is connected to the fault logic control circuit; the fault logic control circuit is further connected to a gate of the fault output MOS tube, a source of the fault output MOS tube is grounded, and a drain of the fault output MOS tube is connected to an output end; the temperature and humidity detection control circuit is connected to the fault logic control circuit, and is further connected to the humidity sensor and the heating wire, for detecting humidity data collected by the humidity sensor and temperature data of the heating wire, respectively.

[0007] Preferably, the temperature and humidity detection control circuit comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first voltage comparator, a second voltage comparator, a NOT gate, and an OR gate.

[0008] A first end of the humidity sensor is connected to a first end of the first resistor and a first end of the first capacitor, a second end of the humidity sensor is connected to a second end of the first capacitor and grounded, and a second end of the first resistor is connected to a power supply voltage.

[0009] A first end of the second resistor is connected to a second end of the first resistor, a second end of the second resistor is connected to a first end of the third resistor, a second end of the third resistor is connected to a second end of the first capacitor, a first end of the second capacitor is connected to a positive input end of the first voltage comparator, a second end of the second capacitor is connected to a second end of the third resistor, a negative input end of the first voltage comparator is connected to a first end of the first capacitor, an output end of the first voltage comparator is connected to a first end of the NOT gate, a second end of the NOT gate is connected to an output end of the second voltage comparator and a second end of the OR gate, a third end of the NOT gate is connected to the fault logic control circuit, the first end of the NOT gate is connected to a first end of the OR gate, and a third end of the OR gate is connected to an LO4 port.

[0010] The source of the first transistor, the source of the second transistor and the first end of the fifth resistor are connected to the power supply voltage, the drain of the first transistor is connected to the emitter of the third transistor, the drain of the second transistor is connected to the first end of the fourth resistor and the negative input end of the second voltage comparator, the second end of the fifth resistor is connected to the first end of the sixth resistor and the positive input end of the second voltage comparator, the second end of the fourth resistor is connected to the emitter of the fourth transistor, the base of the third transistor is connected to the base of the fourth transistor, the collector of the third transistor is connected to the collector of the fourth transistor and grounded, and the second end of the sixth resistor is connected to the collector of the fourth transistor.

[0011] Preferably, the plurality of Schmitt circuits comprises a first Schmitt circuit, a second Schmitt circuit, a third Schmitt circuit, a fourth Schmitt circuit and a fifth Schmitt circuit.

[0012] The plurality of filters comprises a first filter, a second filter, a third filter, a fourth filter and a fifth filter.

[0013] The plurality of level conversion circuits comprises a first level conversion circuit, a second level conversion circuit, a third level conversion circuit and a fourth level conversion circuit.

[0014] The first Schmitt circuit is connected to the first filter, the first level conversion circuit and the fault logic control circuit in sequence; the second Schmitt circuit is connected to the second filter, the second level conversion circuit and the fault logic control circuit in sequence; the third Schmitt circuit is connected to the third filter, the undervoltage detection circuit and the fault logic control circuit in sequence; the fourth Schmitt circuit is connected to the fourth filter, the third level conversion circuit and the interlock circuit in sequence; and the fifth Schmitt circuit is connected to the fifth filter, the fourth level conversion circuit and the interlock circuit in sequence.

[0015] Preferably, the semiconductor circuit further comprises a pulse circuit, and the two ends of the pulse circuit are connected to the interlock circuit and the high-voltage area output circuit respectively.

[0016] Preferably, the semiconductor circuit further comprises a delay circuit, and the delay circuit is connected to the interlock circuit.

[0017] In a second aspect, an embodiment of the present application provides an intelligent power module, comprising: an inverter part triode, a fast recovery diode, an insulation layer, a binding metal wire, a circuit layout, an aluminum substrate, a pin, a sealing resin and the above semiconductor circuit.

[0018] The HCIC chip, the inverter partial triode, the fast recovery diode and the circuit wiring of the semiconductor circuit are arranged on the aluminum substrate respectively, the heating wire and the humidity sensor are fixed on the insulating layer respectively, the inverter partial triode is connected with the fast recovery diode and the circuit wiring through the binding metal wire respectively; the humidity sensor is connected with the HCIC chip through the binding metal wire, and the pin is fixed on the aluminum substrate.

[0019] Preferably, the humidity sensor is fixedly connected with the insulating layer through the insulating adhesive.

[0020] Preferably, the aluminum substrate is a rectangular plate made of aluminum with a material of 1100 or 5052.

[0021] Compared with the related art, the application comprises the following technical scheme: the HCIC chip comprises multiple Schmidt circuits, multiple filters, multiple level conversion circuits, an under-voltage detection circuit, an interlocking circuit, a fault logic control circuit, a fault output MOS tube and a high-voltage area output circuit; the multiple Schmidt circuits are connected with the multiple filters, the multiple level conversion circuits and the fault logic control circuit in sequence; the under-voltage detection circuit is connected between the multiple filters and the fault logic control circuit; the first end of the interlocking circuit is connected with the multiple level conversion circuits respectively, the second end of the interlocking circuit is connected with the high-voltage area output circuit, the third end of the interlocking circuit is connected with the fault logic control circuit respectively, the fault logic control circuit is also connected with the gate of the fault output MOS tube, the source of the fault output MOS tube is grounded, and the drain of the fault output MOS tube is connected with an output end; the temperature and humidity detection control circuit is connected with the fault logic control circuit, and is connected with the humidity sensor and the heating wire respectively, and is used for detecting the humidity data collected by the humidity sensor and the temperature data of the heating wire respectively. Thus, the heating wire works when the module is in a low-temperature and high-humidity state, which not only removes the moisture on the surface of the module, but also drives away the foreign matters attached to the surface of the module, avoids the start of the module in a high-humidity environment or the attachment of foreign insects to the surface of the module, and solves the problems of insufficient electricity between strong and weak electricity. The temperature of the module caused by the heating of the heating wire is automatically controlled by the temperature and humidity, so as to avoid excessive heating. For insects that like warm temperature, the module has a large amount of heat, and the insects that like warm temperature are easily attracted to the module after the work of the module is completed, so that the insects are attached to the pins of the module when the module is started again, resulting in electric injury. The presence of insects at the pins of the module easily causes the problems of insufficient electricity between strong and weak electricity. The module is heated to a temperature of about 55℃ before the module is started, so that the insects are not scalded to death, the invading insects are driven away, and the high temperature generated can drive away the moisture on the surface of the module. BRIEF DESCRIPTION OF DRAWINGS

[0022] The present application will be described in detail below with reference to the drawings. The above and other aspects of the present application will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 is a circuit diagram of a semiconductor circuit of the present application;

[0024] Figure 2 is a circuit diagram of a temperature and humidity detection control circuit of the present application;

[0025] Figure 3 is a circuit schematic diagram of driving upper and lower bridge arms by an HVIC chip of the present application;

[0026] Figure 4 is a structural schematic diagram of an intelligent power module of the present application;

[0027] Figure 5 is an internal structural schematic diagram of an intelligent power module of the present application;

[0028] Figure 6 is a partial schematic diagram along the line X-X' of Figure 4 .

[0029] In the drawings, 100, a semiconductor circuit, 1, a plurality of Schmitt circuits, 2, a plurality of filters, 3, a plurality of level conversion circuits, 4, an under-voltage detection circuit, 5, an interlock circuit, 6, a fault logic control circuit, 7, a fault output MOS transistor, 8, a high-voltage area output circuit, 9, a temperature and humidity detection control circuit, 10, a pulse circuit, 11, a delay circuit, 12, an HVIC chip, 13, an inverter part triode, 14, a fast recovery diode, 15, an insulation layer, 16, a binding metal wire, 17, a circuit wiring, 18, an aluminum substrate, 19, a pin, 20, a sealing resin, 21, an insulation adhesive, 200, an intelligent power module. DETAILED DESCRIPTION

[0030] The specific embodiments of the present application will be described in detail below with reference to the drawings.

[0031] The specific embodiments / examples described herein are specific embodiments of the present application, which are used to illustrate the concept of the present application, and are explanatory and exemplary, and should not be interpreted as limiting the embodiments of the present application and the scope of the present application. In addition to the examples described herein, those skilled in the art can also employ other technical solutions that are obvious based on the disclosure of the claims and the specification of the present application, which include technical solutions that make any obvious substitutions and modifications to the examples described herein, and all of these technical solutions are within the protection scope of the present application.

[0032] Example 1

[0033] As Figures 1-3 The present application provides a semiconductor circuit 100, comprising: an HVIC chip 12, a heating wire RL, a humidity sensor MS and a temperature and humidity detection control circuit 9; the HVIC chip 12 comprises a plurality of Schmitt circuits 1, a plurality of filters 2, a plurality of level conversion circuits 3, an under-voltage detection circuit 4, an interlocking circuit 5, a fault logic control circuit 6, a fault output MOS tube 7 and a high-voltage area output circuit 8; the plurality of Schmitt circuits 1 are connected in sequence with the plurality of filters 2, the plurality of level conversion circuits 3 and the fault logic control circuit 6; the under-voltage detection circuit 4 is connected between the plurality of filters 2 and the fault logic control circuit 6; the first end of the interlocking circuit 5 is connected with the plurality of level conversion circuits 3 respectively, the second end of the interlocking circuit 5 is connected with the high-voltage area output circuit 8, the third end of the interlocking circuit 5 is connected with the fault logic control circuit 6 respectively, the fault logic control circuit 6 is also connected with the gate of the fault output MOS tube 7, the source of the fault output MOS tube 7 is grounded, and the drain of the fault output MOS tube 7 is connected with an output end; the temperature and humidity detection control circuit 9 is connected with the fault logic control circuit 6, and the temperature and humidity detection control circuit 9 is connected with the humidity sensor MS and the heating wire RL respectively, for detecting humidity data collected by the humidity sensor MS and temperature data of the heating wire RL respectively.

[0034] The temperature and humidity detection control circuit 9 is designed, CADENCE VIRTUOSO is used for layout design and MMSIM is used for DRC and LVS error checking; the temperature and humidity detection control circuit 9 is integrated into the HVIC, circuit function simulation of the complete circuit of the HVIC is carried out and MMSIM is used for DRC and LVS error checking; the layout of the temperature and humidity detection control circuit 9 is integrated into the layout of the HVIC, and the layout circuit connection is connected according to the circuit schematic diagram.

[0035] Specifically, by internally integrating the heating wire RL, when the module is detected to be in a low-temperature and high-humidity state before the module is started to work, the heating wire RL works, which not only removes the moisture on the surface of the module, but also chases away foreign objects attached to the surface of the module at high temperature, avoids the problem of insufficient electricity between strong and weak electricity when the module is started in a high-humidity environment or foreign insects are attached to the surface of the module. The temperature of the module due to the heating of the heating wire RL is automatically controlled by temperature and humidity, so as to avoid excessive heating. For insects that like warm temperature, the module has a large amount of heat, which is easy to attract insects that like warm temperature after the module stops working, so that the insects are attached to the pins of the module when the module is started again, causing electric injury. The presence of insects at the pins of the module is easy to cause the problem of insufficient electricity between strong and weak electricity. Before the module is started, the module is heated to a temperature of about 55℃, so as not to scald the insects to death, and the high temperature can drive away invading insects and remove the moisture on the surface of the module. The detected moisture and temperature are used to control the working state and the temperature of the module, to drive away invading insects and surface moisture, thereby improving the working reliability of the module.

[0036] In the embodiment, the temperature and humidity detection control circuit 9 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor, a first capacitor C1, a second capacitor C2, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first voltage comparator IC1, a second voltage comparator IC3, a NOT gate IC2, and an OR gate IC4. The first transistor Q1 and the second transistor Q2 are PMOS tubes, and the third transistor Q3 and the fourth transistor Q4 are PNP tubes. The first capacitor C1 and the second capacitor C2 are filter capacitors.

[0037] The first end of the humidity sensor MS is connected to the first end of the first resistor R1 and the first end of the first capacitor C1, respectively, the second end of the humidity sensor MS is connected to the second end of the first capacitor C1 and grounded, and the second end of the first resistor R1 is connected to a power supply voltage.

[0038] The first end of the second resistor R2 is connected to the second end of the first resistor R1, the second end of the second resistor R2 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the second end of the first capacitor C1, the first end of the second capacitor C2 is connected to the positive input end of the first voltage comparator IC1, the second end of the second capacitor C2 is connected to the second end of the third resistor R3, the first end of the first voltage comparator IC1 is connected to the first end of the first capacitor C1, the output end of the first voltage comparator IC1 is connected to the first end of the NAND gate IC2, the second end of the NAND gate IC2 is connected to the output end of the second voltage comparator IC3 and the second end of the OR gate IC4, the third end of the NAND gate IC2 is connected to the fault logic control circuit 6, the first end of the NAND gate IC2 is connected to the first end of the OR gate IC4, and the third end of the OR gate IC4 is connected to the LO4 port.

[0039] The source of the first transistor Q1, the source of the second transistor Q2 and the first end of the fifth resistor R5 are commonly connected to the power supply voltage, the drain of the first transistor Q1 is connected to the emitter of the third transistor Q3, the drain of the second transistor Q2 is connected to the first end of the fourth resistor R4 and the negative input end of the second voltage comparator IC3 respectively, the second end of the fifth resistor R5 is connected to the first end of the sixth resistor and the positive input end of the second voltage comparator IC3 respectively, the second end of the fourth resistor R4 is connected to the emitter of the fourth transistor Q4, the base of the third transistor Q3 and the base of the fourth transistor Q4 are connected, the collector of the third transistor Q3 and the collector of the fourth transistor Q4 are connected and grounded, and the second end of the sixth resistor is connected to the collector of the fourth transistor Q4.

[0040] Specifically, the second resistor R2 and the third resistor R3 form the reference voltage of the first voltage comparator IC1, which is connected to the positive end of the voltage comparator, and the first resistor R1 and the humidity sensor MS form the detection voltage, which is connected to the negative end of the voltage comparator. When the humidity sensor MS is affected by the external humidity, its resistance will change. The first capacitor C1 and the second capacitor C2 play a role in filtering circuit noise to avoid affecting the stability of the circuit. When the resistance of the humidity sensor MS is lower than a certain value, the negative end of the voltage comparator is lower than the positive end of the voltage comparator, the voltage comparator outputs a high level, and the NAND gate IC2 outputs a low level, triggering the EN detection circuit fault. The fault logic control receives the EN low level signal, outputs the Enable high level signal and the FAULT_G high level signal, and the Enable high level signal controls the switch of each channel. When Enable is high, the upper and lower bridge drive signals are locked regardless of whether they are at high or low level, and the corresponding signal output end outputs a low level signal.

[0041] The first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4 and the fourth resistor R4 form a current mirror, as the temperature rises, the second voltage comparator IC3 C end voltage rises, when the C end voltage is higher than the second voltage comparator IC3 D end voltage, the second voltage comparator IC3 outputs low level, the non gate IC2 outputs high level, and the fault logic circuit trigger protection action is not triggered, when the temperature is lower than a certain value, the second voltage comparator IC3 C end voltage decreases, when the C end voltage is lower than the second voltage comparator IC3 D end voltage, the second voltage comparator IC3 outputs high level, the non gate IC2 outputs low level, and the fault logic circuit trigger protection action is triggered.

[0042] The or gate IC4 is connected with the output end of the first voltage comparator IC1 and the output end of the second voltage comparator IC3, that is, when the humidity is lower than a certain value, the first voltage comparator IC1 outputs low voltage, and when the temperature is higher than a certain value, the second voltage comparator IC3 outputs low level, the or gate IC4 outputs low level, and the LO4 outputs low level. When the first voltage comparator IC1 and the second voltage comparator IC3 output high level, the or gate IC4 outputs high level, and the LO4 outputs high level.

[0043] In the embodiment, the plurality of Schmitt circuits 1 includes a first Schmitt circuit, a second Schmitt circuit, a third Schmitt circuit, a fourth Schmitt circuit and a fifth Schmitt circuit.

[0044] The plurality of filters 2 includes a first filter, a second filter, a third filter, a fourth filter and a fifth filter.

[0045] The plurality of level conversion circuits 3 includes a first level conversion circuit, a second level conversion circuit, a third level conversion circuit and a fourth level conversion circuit.

[0046] The first Schmitt circuit is connected with the first filter, the first level conversion circuit and the fault logic control circuit 6 in sequence; the second Schmitt circuit is connected with the second filter, the second level conversion circuit and the fault logic control circuit 6 in sequence; the third Schmitt circuit is connected with the third filter, the under-voltage detection circuit 4 and the fault logic control circuit 6 in sequence; the fourth Schmitt circuit is connected with the fourth filter, the third level conversion circuit and the interlock circuit 5 in sequence; and the fifth Schmitt circuit is connected with the fifth filter, the fourth level conversion circuit and the interlock circuit 5 in sequence.

[0047] Specifically, the filter is an RC filter circuit, full name resistor-capacitance circuit (English: Resistor-Capacitance circuit), RC circuit is a passive anti-interference strong filter circuit composed of a resistor and a capacitor. Used to remove unnecessary high-frequency components in the input signal, remove high-frequency interference.

[0048] The Schmidt circuit is a Schmidt trigger (SCHMITT). By making PWM IN, ITRIP, TVC, and EN input signals pass through the Schmidt trigger first, filtering the level noise of the input circuit, the maximum value of logic 0 is 0.8V, and the minimum value of logic 1 is 2.9V.

[0049] The VREG-VCC level conversion circuit (VREG 2VCC LEVEL SHIFT) is used to convert the voltage from VREG to VCC.

[0050] Specifically, the fault logic control circuit 6 receives an EN low-level signal, outputs an Enable high-level signal and a FAULT_G high-level signal, and the Enable high-level signal controls the switch of each channel. When Enable is high, the upper and lower bridge drive signals are locked regardless of the high or low level, and the corresponding signal output end outputs a low-level signal. At the same time, the FAULT_G high-level signal drives the fault output MOS tube to open, and the external MCU detects the FAULT low-level signal and triggers the fault protection at the same time, and the drive signal of each channel is set to low level for fault protection.

[0051] When the temperature and humidity sensor MS detects that the humidity is higher than the set value of the temperature and humidity detection circuit, the temperature and humidity detection control circuit 9 is connected to the EN circuit in one way, outputs a low level, and the fault logic control receives an EN low-level signal, outputs an Enable high-level signal and a FAULT_G high-level signal, and the Enable high-level signal controls the switch of each channel. When Enable is high, the upper and lower bridge drive signals are locked regardless of the high or low level, and the corresponding signal output end outputs a low-level signal; the other way is connected to LO4, and outputs a high level.

[0052] When the temperature and humidity sensor MS detects that the humidity is lower than the set value of the temperature and humidity detection circuit, the temperature and humidity detection control circuit 9 is connected to the EN circuit in one way, outputs a high level, and the fault logic control receives an EN low-level signal, and when Enable is low, the upper and lower bridge drive signals are not locked regardless of the high or low level; the other way is connected to LO4, and outputs a low level.

[0053] In the embodiment, the semiconductor circuit 100 further comprises a pulse circuit 10, two ends of the pulse circuit 10 are connected with the interlocking circuit 5 and the high-voltage area output circuit 8 respectively. The pulse circuit 10 is used to generate a pulse at the rising edge and the falling edge of the HIN signal respectively, to make the high-voltage DMOS transiently conduct, and to record the signal of the transient conduction by using an RS flip-flop, to control the HO to be synchronized with the HIN. The reason why the DMOS conduction cannot be controlled by using the continuous high-low signal of the HIN is that when the VS is 600V-650V, the level of the VB is 615V-675V, the VB is a voltage formed by a voltage pump, and has limited energy, and generally does not have the ability to continuously pass the current of the conducted DMOS to the ground; if a continuous current loop is generated between the VB and the ground, the VB will be rapidly reduced, enters the low-voltage protection area, and makes the driving IC unable to work normally. Therefore, the introduction of the PLUSE GEN circuit is very necessary, and the PLUSE GEN signals commonly used in the driving IC include an ONESHOT circuit (generating a pulse) and a DOUBLE PLUSE circuit (generating two pulses). Generally, the ONESHOT circuit is enough for the commonly used occasions; for the circuit in which the VS will be pulled lower (generally, the subsequent circuit has a large inductance), the DOUBLE PLUSE circuit is used.

[0054] In the embodiment, the semiconductor circuit 100 further comprises a delay circuit 11, the delay circuit 11 is connected with the interlocking circuit 5. The delay circuit 11 is used to make a delay for the LO signal output, so that the HO output signal is consistent with the LO output signal.

[0055] In the embodiment, the HVIC chip 12 is used to drive the upper and lower bridge arm triodes to be turned on and off, and is internally integrated with a bootstrap circuit, an enable EN circuit, an overcurrent detection ITRIP circuit, and a fault output FAULT circuit.

[0056] Among them, Q1 is the U-phase upper bridge triode; Q2 is the V-phase upper bridge triode; Q3 is the W-phase upper bridge triode; Q4 is the U-phase lower bridge triode; Q5 is the V-phase lower bridge triode; Q6 is the W-phase lower bridge triode; and Q7 is a triode.

[0057] D1 is a fast recovery diode in parallel with the upper bridge transistor Q1 of the U phase; D2 is a fast recovery diode in parallel with the upper bridge transistor Q2 of the V phase; D3 is a fast recovery diode in parallel with the upper bridge transistor Q3 of the W phase; D4 is a fast recovery diode in parallel with the lower bridge transistor Q4 of the U phase; D5 is a fast recovery diode in parallel with the lower bridge transistor Q5 of the V phase; D6 is a fast recovery diode in parallel with the lower bridge transistor Q6 of the W phase; R1 is a bootstrap resistor in the bootstrap circuit; D7 is a bootstrap diode at the VB1 end; D8 is a bootstrap diode at the VB2 end; D9 is a bootstrap diode at the VB3 end; R1, D7, D8, and D9 form a bootstrap circuit.

[0058] Specifically, the inverter part includes three groups of inverter circuits, each group of inverter module includes two triodes, wherein Q1 and Q4 are a group, Q2 and Q5 are a group, Q3 and Q6 are a group, and each group of two triodes is divided into an upper bridge arm and a lower bridge arm, wherein the triode Q1 is the upper bridge arm, the triode Q4 is the lower bridge arm, the triode Q2 is the upper bridge arm, the triode Q5 is the lower bridge arm, the triode Q3 is the upper bridge arm, and the triode Q6 is the lower bridge arm. The drain of the triode Q1 of the upper bridge arm is connected with the high-voltage input end P of the module, the source of the triode Q1 of the upper bridge arm is connected with the drain of the triode Q4 of the lower bridge arm, the source of the triode Q4 of the lower bridge arm is connected with the U end of the external pin of the module, the gate of the triode Q2 is connected with the HVIC chip 12, and the gate of the triode Q5 is connected with the HVIC chip 12. The drain of the triode Q2 of the upper bridge arm is connected with the high-voltage input end P of the module, the source of the triode Q2 of the upper bridge arm is connected with the drain of the triode Q5 of the lower bridge arm, the source of the triode Q5 of the lower bridge arm is connected with the V end of the external pin of the module, the gate of the triode Q2 is connected with the HVIC chip 12, and the gate of the triode Q5 is connected with the HVIC chip 12. The drain of the triode Q3 of the upper bridge arm is connected with the high-voltage input end P of the module, the source of the triode Q3 of the upper bridge arm is connected with the drain of the triode Q6 of the lower bridge arm, the source of the triode Q6 of the lower bridge arm is connected with the W end of the external pin of the module, the gate of the triode Q3 is connected with the HVIC chip 12, and the gate of the triode Q6 is connected with the HVIC chip 12. The triode is one of an IGBT transistor, an inverse-IGBT transistor, or a MOSFET transistor.

[0059] When the module is powered on, the HVIC detects the temperature and humidity of the module, if the temperature is lower than the preset value or the humidity is higher than the preset value, the LO4 output high level is triggered, the Q7 is turned on, the heating wire RL is powered on to generate heat, and the module is heated to drive away the moisture and the invading insects.

[0060] Example two

[0061] As Figures 1-6 shown in the figure, the embodiment of the application provides a smart power module 200, comprising: an inverter part triode 13, a fast recovery diode 14, an insulation layer 15, a binding metal wire 16, a circuit wiring 17, an aluminum substrate 18, a pin 19, a sealing resin 20, and the semiconductor circuit 100 of the above-mentioned embodiment one.

[0062] The HCIC chip of the semiconductor circuit 100, the inverter part triode 13, the fast recovery diode 14, and the circuit wiring 17 are respectively arranged on the aluminum substrate 18, the heating wire RL and the humidity sensor MS are respectively fixed on the insulation layer 15, the inverter part triode 13 is connected with the fast recovery diode 14 and the circuit wiring 17 through the binding metal wire 16; the humidity sensor MS is connected with the HVIC chip 12 through the binding metal wire 16, and the pin 19 is fixed on the aluminum substrate 18.

[0063] In the embodiment, the humidity sensor MS is fixedly connected with the insulation layer 15 through an insulation adhesive 21. The humidity sensor MS is connected with the substrate insulation layer 15 through an insulation adhesive, and the sensor is not encapsulated by the plastic encapsulating material, which is convenient for detecting the humidity in the air.

[0064] In the embodiment, the aluminum substrate 18 is a rectangular plate made of aluminum with a material of 1100 or 5052.

[0065] Specifically, the HVIC chip 12, the inverter part triode 13, and the fast recovery diode 14 are fixed on the circuit wiring 17 to form a specified circuit. In addition, a heat sink made of copper or the like can be used to fix a power element and other elements with large heat generation on the aluminum substrate 18. Here, the active element and the like installed upward is connected with the circuit wiring 17 through the binding metal wire 16.

[0066] The binding metal wire 16 can be an aluminum wire, a gold wire, or a copper wire, and is used to establish an electrical connection relationship between the HVIC chip 12, the inverter part triode 13, and the fast recovery diode 14, between the circuit wiring 17, between the HVIC chip 12, the inverter part triode 13, and the fast recovery diode 14 and the circuit wiring 17, and sometimes is used to establish an electrical connection relationship between the pin 19 and the circuit wiring 17 or between the HVIC chip 12, the inverter part triode 13, and the fast recovery diode 14.

[0067] The insulating layer 15 covers at least one surface of the aluminum substrate 18 and is formed by filling a resin material such as epoxy resin with a high concentration of fillers such as aluminum oxide, silicon carbide aluminum, etc. to improve thermal conductivity. In order to improve thermal conductivity, the fillers can be in the shape of an angle, and in order to avoid the risk of damage to the surface of the HVIC chip 12, the inverter part triode transistor 13, and the fast recovery diode 14, the fillers can be in the shape of a ball or a mixture of an angle and a ball.

[0068] The heating wire RL is attached to the vacant position around the module HVIC to facilitate the drying of the moisture of the HVIC by the heating wire RL. Since the HVIC has a small volume and an internal high-voltage circuit, if the IC is damp, it is easy to cause electrical failure in the HVIC.

[0069] The pin 19 is fixed to the tail end of the circuit layout 17 provided on one edge of the aluminum substrate 18, and has the function of inputting and outputting to the outside. Here, a plurality of pins 19 are provided on one side, and the pins 19 and the tail end of the circuit layout 17 are soldered by a conductive adhesive such as solder. The pin 19 is generally made of copper or other metal, and a layer of nickel-tin alloy is formed on the surface of the copper by chemical plating and electroplating. The thickness of the alloy layer is generally 5 μm, and the plating layer can protect the copper from corrosion and oxidation, and can improve the weldability.

[0070] The sealing resin 20 can be molded using a thermosetting resin by a transfer mold method or using a thermoplastic resin by an injection mold method. Here, the sealing resin 20 completely seals all elements of the aluminum substrate 18 having the circuit layout 17 on one side except for the pins 19, and for the intelligent power module 200 which requires high heat dissipation, only the side of the aluminum substrate 18 having the elements is sealed by the sealing resin 20, and the other side is exposed.

[0071] Specifically, by internally integrating the heating wire RL, when the module is detected to be in a low-temperature and high-humidity state before the module starts to work, the heating wire RL works, which not only removes the moisture on the surface of the module, but also chases away foreign objects attached to the surface of the module at high temperature, avoiding the problem of insufficient electricity between strong and weak electricity when the module starts to work in a high-humidity environment or foreign insects are attached to the surface of the module. The temperature of the module due to the heating of the heating wire RL is automatically controlled by temperature and humidity to avoid excessive heat generation. For insects that like warmth, the module generates a large amount of heat, which easily attracts insects that like warmth after the module stops working, causing the insects to attach to the pins 19 of the module and causing electrical injury. The presence of insects at the pins 19 of the module easily leads to problems such as insufficient electricity between strong and weak electricity. Before the module starts to work, the module itself is heated to a temperature of about 55°C, which does not cause the insects to be scalded to death, and can drive away invading insects, and the high temperature generated can also drive away the moisture on the surface of the module.

[0072] The above merely provides the preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modified form, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of claims of the present application.

Claims

1. A semiconductor circuit, characterized in that, include: The system comprises an HVIC chip, a heating wire, a humidity sensor, and a temperature and humidity detection and control circuit. The HVIC chip includes multiple Schmitt trigger circuits, multiple filters, multiple level shifting circuits, an undervoltage detection circuit, an interlock circuit, a fault logic control circuit, a fault output MOSFET, and a high-voltage output circuit. The multiple Schmitt trigger circuits are sequentially connected to the multiple filters, the multiple level shifting circuits, and the fault logic control circuit. The undervoltage detection circuit is connected between the multiple filters and the fault logic control circuit. The first terminal of the interlock circuit is connected to the multiple level shifting circuits, and the second terminal of the interlock circuit is connected to the high-voltage output circuit. The semiconductor circuit also includes a delay circuit, and the third terminal of the interlock circuit is connected to the delay circuit. The fault logic control circuit is also connected to the gate of the fault output MOSFET, the source of the fault output MOSFET is grounded, and the drain of the fault output MOSFET is connected to the output terminal. The temperature and humidity detection and control circuit is connected to the fault logic control circuit and is also connected to the humidity sensor and the heating wire, respectively, to detect the humidity data collected by the humidity sensor and the temperature data of the heating wire. The plurality of Schmitt circuits include a first Schmitt circuit, a second Schmitt circuit, a third Schmitt circuit, a fourth Schmitt circuit, and a fifth Schmitt circuit; The plurality of filters includes a first filter, a second filter, a third filter, a fourth filter, and a fifth filter; The plurality of level conversion circuits include a first level conversion circuit, a second level conversion circuit, a third level conversion circuit, and a fourth level conversion circuit; The first Schmitt trigger circuit is connected in sequence to the first filter, the first level conversion circuit, and the fault logic control circuit; the second Schmitt trigger circuit is connected in sequence to the second filter, the second level conversion circuit, and the fault logic control circuit; the third Schmitt trigger circuit is connected in sequence to the third filter, the undervoltage detection circuit, and the fault logic control circuit; the fourth Schmitt trigger circuit is connected in sequence to the fourth filter, the third level conversion circuit, and the interlock circuit; and the fifth Schmitt trigger circuit is connected in sequence to the fifth filter, the fourth level conversion circuit, and the interlock circuit.

2. The semiconductor circuit as described in claim 1, characterized in that, The temperature and humidity detection and control circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first voltage comparator, a second voltage comparator, an NOT gate, and an OR gate; The first end of the humidity sensor is connected to the first end of the first resistor and the first end of the first capacitor respectively, the second end of the humidity sensor is connected to the second end of the first capacitor and grounded, and the second end of the first resistor is connected to the power supply voltage. The first end of the second resistor is connected to the second end of the first resistor; the second end of the second resistor is connected to the first end of the third resistor; the second end of the third resistor is connected to the second end of the first capacitor; the first end of the second capacitor is connected to the positive input terminal of the first voltage comparator; the second end of the second capacitor is connected to the second end of the third resistor; the negative input terminal of the first voltage comparator is connected to the first end of the first capacitor; the output terminal of the first voltage comparator is connected to the first end of the NOT gate; the second end of the NOT gate is connected to the output terminal of the second voltage comparator and the second end of the OR gate; the third end of the NOT gate is connected to the fault logic control circuit; the first end of the NOT gate is connected to the first end of the OR gate; the third end of the OR gate is connected to the LO4 port; the first end of the second capacitor is also connected to the second end of the second resistor. The source of the first transistor, the source of the second transistor, and the first terminal of the fifth resistor are connected together to the power supply voltage. The drain of the first transistor is connected to the emitter of the third transistor. The drain of the second transistor is connected to the first terminal of the fourth resistor and the negative input terminal of the second voltage comparator. The second terminal of the fifth resistor is connected to the first terminal of the sixth resistor and the positive input terminal of the second voltage comparator. The second terminal of the fourth resistor is connected to the emitter of the fourth transistor. The base of the third transistor is connected to the base of the fourth transistor. The collector of the third transistor is connected to the collector of the fourth transistor and grounded. The second terminal of the sixth resistor is connected to the collector of the fourth transistor.

3. The semiconductor circuit as described in claim 1, characterized in that, The semiconductor circuit also includes a pulse circuit, the two ends of which are connected to the interlock circuit and the high-voltage output circuit, respectively.

4. A smart power module, characterized in that, include: The inverter section comprises a transistor, a fast recovery diode, an insulating layer, bonding metal wires, circuit wiring, an aluminum substrate, pins, sealing resin, and a semiconductor circuit as described in any one of claims 1-3; The HVIC chip, the inverter transistor, the fast recovery diode, and the circuit wiring of the semiconductor circuit are respectively disposed on the aluminum substrate. The heating wire and the humidity sensor are respectively fixed on the insulating layer. The inverter transistor is connected to the fast recovery diode and the circuit wiring through the bonding metal wire. The humidity sensor is connected to the HVIC chip through the bonding metal wire, and the pin is fixed to the aluminum substrate.

5. The intelligent power module as described in claim 4, characterized in that, The humidity sensor is fixedly connected to the insulating layer by an insulating adhesive.

6. The intelligent power module as described in claim 4, characterized in that, The aluminum substrate is a rectangular plate made of aluminum of material 1100 or 5052.

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