Power supply driving circuit

Abstract

The application discloses a power supply driving circuit and relates to the field of switching power supplies. The power supply driving circuit comprises a tube M1, a tube M2, a tube M3, a tube M4, a driving circuit DRIVER1, a driving circuit DRIVER2, a diode D1, a diode D2, a capacitor C1, a capacitor C2, an inductor L, a high-voltage selection circuit, a first power compensation circuit, a second power compensation circuit, a first under-voltage detection circuit and a second under-voltage detection circuit. The highest voltage in the driving power supply is selected by the high-voltage selection circuit to supply power to all the driving circuits, and when any of the switching tubes needs to work at 100% duty cycle, an additional charge pump circuit is not needed; when one of the paths works in a switching mode and the other works at 100% duty cycle, the BOOT capacitor is compensated every cycle in the switching mode, and thus the corresponding voltage is always kept above the preset voltage, and an additional refreshing circuit is not needed, so that the real 100% duty cycle is realized.

Description

Technical Field

[0001] This invention relates to the field of switching power supply technology, and in particular to a power supply drive circuit. Background Technology

[0002] In modern switching power supplies, due to increasingly wider voltage ranges and higher integration levels, multiple power supplies (such as BUCK, BOOST, and BUCK-BOOST) are often integrated together. When the input and output are close, a shoot-through is required; therefore, the switch driver needs to achieve a 100% duty cycle.

[0003] To achieve 100% duty cycle, there are currently two main methods: 1) such as Figure 1 As shown, an additional charge pump is added to drive the circuit. The specific principle is to detect the duty cycle for each cycle. When the duty cycle increases to 100%, the charge pump is started to drive the upper transistor, thereby achieving a 100% duty cycle. The disadvantage of this approach is that an additional charge pump circuit is required, which will increase the chip area and power consumption. 2) Detect the voltage on the drive circuit. When the voltage on the drive capacitor is insufficient, the refresh circuit is started to replenish the capacitor. The main disadvantage of this method is that, since the capacitor needs to be replenished, the refresh circuit will work at a certain interval, which will result in the inability to achieve a 100% duty cycle and the ripple will increase. Summary of the Invention

[0004] To address the aforementioned issues, this invention proposes a power drive circuit that can achieve a true 100% duty cycle without requiring additional charge pump or refresh circuits.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A power supply drive circuit includes: transistors M1, M2, M3, and M4; drive circuit DRIVER1 and drive circuit DRIVER2; diode D1 and diode D2; capacitor C1 and capacitor C2; inductor L; high voltage selection circuit; first power supply circuit; second power supply circuit; first undervoltage detection circuit; and second undervoltage detection circuit.

[0007] The gate of transistor M1 is driven by the driving circuit DRIVER1; the connection node between the source of transistor M1 and the driving circuit DRIVER1 is node SW1; the drain of transistor M1 is connected to voltage VA; the anode of diode D1 is connected to voltage VCC; the connection node between the cathode of diode D1 and the driving circuit DRIVER1 is node BOOT1; the driving circuit DRIVER1 is also connected to pulse width modulation signal PWMH1; the gate of transistor M2 is connected to pulse width modulation signal PWML1; the drain of transistor M2 is connected to node SW1; the source of transistor M2 is grounded; one end of capacitor C1 is connected to node BOOT1; the other end of capacitor C1 is connected to node SW1.

[0008] The gate of transistor M4 is driven by the driving circuit DRIVER2; the connection node between the source of transistor M4 and the driving circuit DRIVER2 is node SW2; the drain of transistor M4 is connected to voltage VB; the anode of diode D2 is connected to voltage VCC; the connection node between the cathode of diode D2 and the driving circuit DRIVER2 is node BOOT2; the driving circuit DRIVER2 is also connected to pulse width modulation signal PWMH2; the gate of transistor M3 is connected to pulse width modulation signal PWML2; the drain of transistor M3 is connected to node SW2; the source of transistor M3 is grounded; one end of capacitor C2 is connected to node BOOT2; the other end of capacitor C2 is connected to node SW2.

[0009] One end of the inductor L is connected to node SW1; the other end of the inductor L is connected to node SW2; the high-voltage selection circuit is connected to nodes BOOT1 and BOOT2 respectively; the connection node between the high-voltage selection circuit and the first and second power supply circuits is node COM; the first power supply circuit is connected to nodes BOOT1 and SW1 respectively; the second power supply circuit is connected to nodes BOOT2 and SW2 respectively.

[0010] The first undervoltage detection circuit is connected to the node BOOT1, the node SW1 and the first power replenishment circuit respectively; the second undervoltage detection circuit is connected to the node BOOT2, the node SW2 and the second power replenishment circuit respectively.

[0011] Optionally, the high-voltage selection circuit includes transistors MP1 and MP2, diode DP1, and diode DP2; the gate of transistor MP1 is connected to node BOOT2; the drain of transistor MP1 is connected to node BOOT1; the source of transistor MP1 is connected to node COM; the anode of diode DP1 is connected to node BOOT1; the cathode of diode DP1 is connected to node COM; the gate of transistor MP2 is connected to node BOOT1; the drain of transistor MP2 is connected to node BOOT2; the source of transistor MP2 is connected to node COM; the anode of diode DP2 is connected to node BOOT2; and the cathode of diode DP2 is connected to node COM.

[0012] Optionally, the first power supply circuit and the second power supply circuit have a symmetrical structure; the first power supply circuit includes: transistors MB1~MB21, resistors RB1~RB4, capacitors CB1~CB4, current sources IB1~IB2, Zener diodes DB1, and undervoltage lockout module UVLO;

[0013] The source of transistor MB1, one end of resistor RB1, one end of capacitor CB1, one end of resistor RB2, the drain of transistor MB6, the source of transistor MB8, one end of capacitor CB2, the source of transistor MB9, the source of transistor MB10, one end of capacitor CB3, the source of transistor MB15, and one end of capacitor CB4 are all connected to node COM; the source of transistor MB2 is connected to the gate and drain of transistor MB1; the source of transistor MB3 is connected to the gate and drain of transistor MB2; one end of current source IB1 is connected to the gate and drain of transistor MB3; the other end of current source IB1 is grounded; The source of transistor MB4 is connected to the other end of resistor RB1; one end of resistor RB3 is connected to the other end of resistor RB2; the gate of transistor MB4 is connected to the gate of transistor MB3, the other end of capacitor CB1, the other end of resistor RB3, and the gate of transistor MB7; the drain of transistor MB4 is connected to the gate and drain of transistor MB5, one end of resistor RB4, and the gate of transistor MB6; the source of transistor MB5 is connected to the negative terminal of Zener diode DB1; the positive terminal of Zener diode DB1, the source of transistor MB20, and the source of transistor MB21 are all connected to node SW1; the other end of resistor RB4, the other end of transistor MB7, and the gate of transistor MB8 are connected to the gate of transistor MB3, the other end of capacitor CB1, the other end of resistor RB3, and the gate of transistor MB7 are connected to the gate of transistor MB8. The source of B6 and the drain of MB7 are both connected to node BOOT1; the drain of MB8 is connected to the source of MB7; the gate of MB8 is connected to the other end of capacitor CB2, the drain of MB9, the gate of MB10, the drain of MB11, the gate of MB12, and the source of MB13; the gate of MB9 is connected to the drain of MB10, the gate of MB11, the drain of MB12, and the source of MB14; the source of MB11 is connected to the source of MB12, the other end of capacitor CB3, the source of MB18, and the capacitor... The other end of CB4 is connected to the source of the transistor MB19; the source of the transistor MB16 is connected to the gate and drain of the transistor MB15; the source of the transistor MB17 is connected to the gate and drain of the transistor MB16; the drain of the transistor MB18 is connected to the gate and drain of the transistor MB15 and the gate of the transistor MB18; the gate of the transistor MB13 is connected to the gate of the transistor MB14 and the gate of the transistor MB19; the drain of the transistor MB13 is connected to the drain of the transistor MB20; the drain of the transistor MB14 is connected to the drain of the transistor MB21; one end of the current source IB2 is connected to the drain of the transistor MB19; the other end of the current source IB1 is grounded.

[0014] The gate of the transistor MB20 is connected to the signal BT_UVB; the gate of the transistor MB21 is connected to the signal BT_UVZ; the undervoltage lockout module UVLO is connected to the node BOOT1, the node SW1, the signal BT_UVB and the signal BT_UVZ respectively.

[0015] Optionally, the first undervoltage detection circuit and the second undervoltage detection circuit have a symmetrical structure; the first undervoltage detection circuit includes: transistors MQ1~MQ12, resistors RQ1~RQ3 and Schmitt trigger NB1;

[0016] The sources of transistors MQ1, MQ4, MQ7, and MQ9 are all connected to node BOOT1; the source of transistor MQ2 is connected to the gate and drain of transistor MQ1 and the gate of transistor MQ7; the source of transistor MQ3 is connected to the gate and drain of transistor MQ2; the drain of transistor MQ11 is connected to the gate and drain of transistor MQ3, the gate of transistor MQ4, and the gate of transistor MQ10; the drain of transistor MQ4 is connected to the source of transistor MQ5; the gate and drain of transistor MQ5 are connected to the source of transistor MQ6; the gate of transistor MQ6 is connected to the drain of transistor MQ6, the gate of transistor MQ8, and the resistor. One end of RQ3; the source of transistor MQ8 and the other end of resistor RQ3 are both connected to node SW1; the drain of transistor MQ7 is connected to the drain of transistor MQ8 and the gate of transistor MQ9; the drain of transistor MQ9 is connected to the source of transistor MQ10; the drain of transistor MQ10 is connected to the drain of transistor MQ12; the gate of transistor MQ11 is connected to the gate of transistor MQ12; the source of transistor MQ11 is connected to one end of resistor RQ1; the source of transistor MQ12 is connected to one end of resistor RQ2; the other ends of resistors RQ1 and RQ2 are both grounded; the source of transistor MQ12 also outputs the signal BOOTOK through Schmitt trigger NB1.

[0017] Optionally, the transistors M1, M2, M3 and M4 are all PMOS power MOSFETs.

[0018] Optionally, both MP1 and MP2 are NMOS power MOSFETs.

[0019] Optionally, transistors MB1, MB2, MB3, MB4, MB7, MB8, MB9, MB10, MB13, MB14, MB15, MB16, MB17, and MB19 are all NMOS power MOSFETs; while transistors MB5, MB6, MB11, MB12, MB18, MB20, and MB21 are all PMOS power MOSFETs.

[0020] Optionally, transistors MQ1, MQ2, MQ3, MQ4, MQ5, MQ6, MQ7, MQ9, and MQ10 are all NMOS power MOSFETs; and transistors MQ8, MQ11, and MQ12 are all PMOS power MOSFETs.

[0021] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0022] This invention provides a power supply drive circuit, including: transistors M1, M2, M3, and M4; drive circuits DRIVER1 and DRIVER2; diodes D1 and D2; capacitors C1 and C2; inductor L; a high-voltage selection circuit; a first power supply circuit; a second power supply circuit; a first undervoltage detection circuit; and a second undervoltage detection circuit. It can achieve a true 100% duty cycle without the need for additional charge pump circuits or refresh circuits. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of an existing circuit structure that achieves 100% duty cycle by adding an additional charge pump circuit;

[0025] Figure 2 A schematic diagram of a power drive circuit provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the high-voltage selection circuit in the power drive circuit provided in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the first power supply circuit in the power drive circuit provided in an embodiment of the present invention;

[0028] Figure 5This is a schematic diagram of the first undervoltage detection circuit in the power drive circuit provided in an embodiment of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] The purpose of this invention is to provide a power drive circuit that can achieve a true 100% duty cycle without adding an additional charge pump circuit or refresh circuit.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] Figure 1 This is a schematic diagram of an existing circuit structure that achieves 100% duty cycle by adding an additional charge pump circuit. (Example:) Figure 1 As shown, in some common application environments, in a BUCK-BOOST circuit with 4 transistors, it operates under BUCK or BOOST conditions most of the time. Under BUCK conditions, transistor M3 operates at 100% duty cycle, and under BOOST conditions, transistor M1 operates at 100% duty cycle. Figure 1 The 100% duty cycle implementation shown requires an additional charge pump circuit, which significantly increases area and power consumption. Another existing 100% duty cycle implementation requires a refresh circuit to recharge the BOOT capacitor corresponding to the 100% duty cycle, thus failing to truly achieve a 100% duty cycle.

[0033] To address the aforementioned shortcomings of existing 100% duty cycle implementation methods, this invention provides a power drive circuit, see [link to relevant documentation]. Figure 2 The power drive circuit includes: transistors M1, M2, M3, and M4; drive circuits DRIVER1 and DRIVER2; diodes D1 and D2; capacitors C1 and C2; inductor L; high-voltage selection circuit; first power supply circuit; second power supply circuit; first undervoltage detection circuit; and second undervoltage detection circuit.

[0034] In this configuration, the gate of transistor M1 is driven by the driving circuit DRIVER1; the connection node between the source of transistor M1 and the driving circuit DRIVER1 is node SW1; the drain of transistor M1 is connected to voltage VA; the anode of diode D1 is connected to voltage VCC; the connection node between the cathode of diode D1 and the driving circuit DRIVER1 is node BOOT1; the driving circuit DRIVER1 is also connected to pulse width modulation signal PWMH1; the gate of transistor M2 is connected to pulse width modulation signal PWML1; the drain of transistor M2 is connected to node SW1; the source of transistor M2 is grounded; one end of capacitor C1 is connected to node BOOT1; the other end of capacitor C1 is connected to node SW1.

[0035] The gate of transistor M4 is driven by the driving circuit DRIVER2; the connection node between the source of transistor M4 and the driving circuit DRIVER2 is node SW2; the drain of transistor M4 is connected to voltage VB; the anode of diode D2 is connected to voltage VCC; the connection node between the cathode of diode D2 and the driving circuit DRIVER2 is node BOOT2; the driving circuit DRIVER2 is also connected to pulse width modulation signal PWMH2; the gate of transistor M3 is connected to pulse width modulation signal PWML2; the drain of transistor M3 is connected to node SW2; the source of transistor M3 is grounded; one end of capacitor C2 is connected to node BOOT2; the other end of capacitor C2 is connected to node SW2.

[0036] The multiple drive power supplies refer to the functions of nodes BOOT1 and BOOT2 as drive power supplies. Voltages VA, VB, and VCC refer to the input / output voltage, output / input voltage, and drive voltage, respectively. The pulse width modulation signals PWMH1, PWMH2, PWML1, and PWML2 control the duty cycle under different input conditions to keep the output voltage constant.

[0037] One end of the inductor L is connected to node SW1; the other end of the inductor L is connected to node SW2; the high-voltage selection circuit is connected to nodes BOOT1 and BOOT2 respectively; the connection node between the high-voltage selection circuit and the first and second power supply circuits is node COM; the first power supply circuit is connected to nodes BOOT1 and SW1 respectively; the second power supply circuit is connected to nodes BOOT2 and SW2 respectively.

[0038] The first undervoltage detection circuit is connected to the node BOOT1, the node SW1 and the first power replenishment circuit respectively; the second undervoltage detection circuit is connected to the node BOOT2, the node SW2 and the second power replenishment circuit respectively.

[0039] See Figure 2 The working principle of the entire power drive circuit is described below. The main features of this power drive circuit are the addition of a high-voltage selection circuit, a power supply circuit, and an undervoltage detection circuit. The power supply circuit includes a symmetrically arranged first and second power supply circuits, and the undervoltage detection circuit includes a symmetrically arranged first and second undervoltage detection circuits. When the power drive circuit operates in BUCK mode, transistors M1 and M2 alternately operate periodically, transistor M3 is off, and transistor M4 is on. When transistor M1 is off, diode D1 supplies power to capacitor C1. When transistor M1 is on, the voltage V at node BOOT1... BOOT1 =V SW1 +VCC, where V SW1 This is the voltage at node SW1; to achieve a 100% duty cycle for transistor M4, the voltage across capacitor C2 powers the driver circuit DRIVER2. The high-voltage selection circuit ensures that the voltage V at node COM is... COM =V BOOT1 = V SW1 +VCC; If the voltage at node BOOT2 is V BOOT2 When the voltage is insufficient, the second power supply circuit is activated to charge capacitor C2, ensuring the normal operation of the driver circuit DRIVER2 for transistor M4. In BOOST mode, transistors M3 and M4 operate cyclically. When transistor M3 is off, VCC charges capacitor C2 through diode D2, and the voltage V at node BOOT2 is [value missing]. BOOT2 =V SW2 +VCC, where V SW2 The voltage at node SW2 is such that, to achieve a 100% duty cycle for transistor M1, the voltage across capacitor C1 powers the driver circuit DRIVER1. The high-voltage selection circuit then selects the voltage V at node COM. COM= V BOOT2 = V SW2 +VCC, if the voltage V at node BOOT1 BOOT1 If the current is insufficient, the first power supply circuit is activated to charge capacitor C1, ensuring that the drive circuit DRIVER1 of transistor M1 works normally.

[0040] therefore, Figure 1 The existing technology shown requires the addition of a charge pump circuit (including a charge pump and diodes) to power the corresponding boot when transistor M1 or M4 needs to operate at 100% duty cycle. According to... Figure 2The power supply drive circuit of this invention has symmetrical input and output. VA and VB can function as both inputs and outputs. When VA is the input, VB is the output, and vice versa. When the input voltage is greater than the output voltage, the power supply drive circuit operates in BUCK mode, with transistors M1 and M2 performing periodic switching operations, transistor M3 being off, and transistor M4 operating at 100% duty cycle. When the input voltage is much lower than the output voltage, the power supply drive circuit operates in BOOST mode, with transistor M2 off and transistor M1 operating at 100% duty cycle. When transistor M1 needs to operate at 100% duty cycle, the voltage V at node BOOT2... BOOT2 Node BOOT1 is powered by a high-voltage selection circuit; when transistor M4 is operating at 100% duty cycle, the voltage V on node BOOT1 is... BOOT1 BOOT2 is powered by a high-voltage selection circuit, eliminating the need for an additional charge pump circuit.

[0041] Figure 3 This is a schematic diagram of the high-voltage selection circuit in the power drive circuit provided in an embodiment of the present invention. See also... Figure 3 The high-voltage selection circuit includes transistors MP1 and MP2, diode DP1, and diode DP2. The gate of transistor MP1 is connected to node BOOT2; the drain of transistor MP1 is connected to node BOOT1; the source of transistor MP1 is connected to node COM; the anode of diode DP1 is connected to node BOOT1; the cathode of diode DP1 is connected to node COM; the gate of transistor MP2 is connected to node BOOT1; the drain of transistor MP2 is connected to node BOOT2; the source of transistor MP2 is connected to node COM; the anode of diode DP2 is connected to node BOOT2; and the cathode of diode DP2 is connected to node COM.

[0042] The working principle of the high voltage selection circuit is as follows: when the voltage V at node BOOT1 is... BOOT1 The voltage V at node BOOT2 is higher than BOOT2 At that time, tube MP1 is on and tube MP2 is off, and the voltage at node VCOM is V. COM =V BOOT1 When the voltage V at node BOOT1 BOOT1 The voltage V at node BOOT2 is lower than BOOT2 At that time, tube MP1 is off and tube MP2 is on, and the voltage at node VCOM is V. COM =V BOOT2 Thus, the voltage V at node VCOM is achieved. COM Always equal to V BOOT1 V BOOT2 The higher voltage in the middle. Voltage V at node VCOM. COM for Figure 2 The first and second power supply circuits shown are powered.

[0043] Figure 4 This is a schematic diagram of the first power supply circuit in the power drive circuit provided in an embodiment of the present invention. The first power supply circuit and the second power supply circuit have a symmetrical structure. The difference is that the first power supply circuit is connected to nodes BOOT1 and SW1, and correspondingly, the second power supply circuit is connected to nodes BOOT2 and SW2. The specific structure of the power supply circuit is described below using the first power supply circuit as an example.

[0044] See Figure 4 The first power supply circuit includes: transistors MB1~MB21, resistors RB1~RB4, capacitors CB1~CB4, current sources IB1~IB2, Zener diodes DB1, and undervoltage lockout module UVLO.

[0045] In this configuration, the source of transistor MB1, one end of resistor RB1, one end of capacitor CB1, one end of resistor RB2, the drain of transistor MB6, the source of transistor MB8, one end of capacitor CB2, the source of transistor MB9, the source of transistor MB10, one end of capacitor CB3, the source of transistor MB15, and one end of capacitor CB4 are all connected to node COM; the source of transistor MB2 is connected to the gate and drain of transistor MB1; the source of transistor MB3 is connected to the gate and drain of transistor MB2; one end of current source IB1 is connected to the gate and drain of transistor MB3; and the other end of current source IB1 is grounded. The source of transistor MB4 is connected to the other end of resistor RB1; one end of resistor RB3 is connected to the other end of resistor RB2; the gate of transistor MB4 is connected to the gate of transistor MB3, the other end of capacitor CB1, the other end of resistor RB3, and the gate of transistor MB7; the drain of transistor MB4 is connected to the gate and drain of transistor MB5, one end of resistor RB4, and the gate of transistor MB6; the source of transistor MB5 is connected to the negative terminal of Zener diode DB1; the positive terminal of Zener diode DB1, the source of transistor MB20, and the source of transistor MB21 are all connected to node SW1; the other end of resistor RB4, the transistor... The source of MB6 and the drain of MB7 are both connected to node BOOT1; the drain of MB8 is connected to the source of MB7; the gate of MB8 is connected to the other end of capacitor CB2, the drain of MB9, the gate of MB10, the drain of MB11, the gate of MB12, and the source of MB13; the gate of MB9 is connected to the drain of MB10, the gate of MB11, the drain of MB12, and the source of MB14; the source of MB11 is connected to the source of MB12, the other end of capacitor CB3, the source of MB18, and the... The other end of capacitor CB4 is connected to the source of transistor MB19; the source of transistor MB16 is connected to the gate and drain of transistor MB15 respectively; the source of transistor MB17 is connected to the gate and drain of transistor MB16 respectively; the drain of transistor MB18 is connected to the gate and drain of transistor MB15 and the gate of transistor MB18 respectively; the gate of transistor MB13 is connected to the gate of transistor MB14 and the gate of transistor MB19 respectively; the drain of transistor MB13 is connected to the drain of transistor MB20; the drain of transistor MB14 is connected to the drain of transistor MB21; one end of current source IB2 is connected to the drain of transistor MB19; the other end of current source IB1 is grounded.

[0046] Wherein, the gate of the transistor MB20 is connected to the signal BT_UVB; the gate of the transistor MB21 is connected to the signal BT_UVZ; the undervoltage lockout module UVLO is connected to the node BOOT1, the node SW1, the signal BT_UVB and the signal BT_UVZ respectively.

[0047] The undervoltage lockout module UVLO determines whether the voltage at node BOOT1 meets the circuit's minimum operating voltage. The signal BT_UVB indicates whether the voltage difference between BOOT (BOOT1 or BOOT2) and SW (SW1 or SW2) meets the minimum operating voltage, and the signal BT_UVZ indicates the inverse signal indicating whether the logic state between BOOT and SW is met. Figure 4 BT_COM_G and BT_COM_BIAS are the bias operating voltages provided for the circuit.

[0048] See Figure 4 The working principle of the first power replenishment circuit is as follows: When the undervoltage lockout module UVLO detects that the voltage difference between node BOOT1 and node SW1 is less than 4.5V, it turns on transistor M20, turns off transistor M21, turns on transistor M13, turns off transistor M14, and turns on transistor M8. Transistor M13 pulls down the gate of transistor M8, and transistors M8 and M7 replenish the voltage at node BOOT1, i.e., the voltage V at node VCOM is replenished. COM External BOOT capacitor C1 is charged through transistors M8 and M7. When the voltage difference between node BOOT1 and node SW1 is greater than 4.5V, transistor M21 is turned on, transistor M20 is turned off, transistor M14 is turned on, transistor M13 is turned off, and transistor M18 is turned off. Transistor M14 pulls down the gate of transistor M9, thus making the gate voltage of transistor M8 equal to V. COM Then pipe M8 is closed, thus stopping V. COM The second power supply circuit replenishes power to node BOOT1, i.e., stops charging the external BOOT capacitor C1. The working principle of the second power supply circuit is similar to that of the first power supply circuit, and will not be described in detail here.

[0049] Figure 5 This is a schematic diagram of the first undervoltage detection circuit in the power drive circuit provided in an embodiment of the present invention. The first undervoltage detection circuit and the second undervoltage detection circuit have a symmetrical structure. The difference is that the first undervoltage detection circuit is connected to nodes BOOT1 and SW1, and correspondingly, the second undervoltage detection circuit is connected to nodes BOOT2 and SW2. The specific structure of the undervoltage detection circuit will be described below using the first undervoltage detection circuit as an example.

[0050] See Figure 5 The first undervoltage detection circuit includes: transistors MQ1~MQ12, resistors RQ1~RQ3, and Schmitt trigger NB1.

[0051] In this configuration, the sources of transistors MQ1, MQ4, MQ7, and MQ9 are all connected to node BOOT1; the source of transistor MQ2 is connected to the gate and drain of transistor MQ1 and the gate of transistor MQ7; the source of transistor MQ3 is connected to the gate and drain of transistor MQ2; the drain of transistor MQ11 is connected to the gate and drain of transistor MQ3, the gate of transistor MQ4, and the gate of transistor MQ10; the drain of transistor MQ4 is connected to the source of transistor MQ5; the gate and drain of transistor MQ5 are connected to the source of transistor MQ6; the gate of transistor MQ6 is connected to the drain of transistor MQ6, the gate of transistor MQ8, and the gate of transistor MQ9. One end of resistor RQ3; the source of transistor MQ8 and the other end of resistor RQ3 are both connected to node SW1; the drain of transistor MQ7 is connected to the drain of transistor MQ8 and the gate of transistor MQ9; the drain of transistor MQ9 is connected to the source of transistor MQ10; the drain of transistor MQ10 is connected to the drain of transistor MQ12; the gate of transistor MQ11 is connected to the gate of transistor MQ12; the source of transistor MQ11 is connected to one end of resistor RQ1; the source of transistor MQ12 is connected to one end of resistor RQ2; the other ends of resistors RQ1 and RQ2 are both grounded; the source of transistor MQ12 also outputs a signal BOOTOK through Schmitt trigger NB1. The function of signal BOOTOK is to determine whether the voltage at node BOOT1 meets the minimum operating voltage. A high signal BOOTOK indicates that the minimum operating voltage is met, and a low signal indicates that the minimum operating voltage is not met.

[0052] Figure 5 The working principle of the first undervoltage detection circuit shown is as follows: When the voltage between node BOOT1 and node SW1 exceeds a certain value, the first undervoltage detection circuit sends a signal BOOTOK, the specific value of which is: , where R Q1 and R Q3 These represent the resistance values ​​of resistors RQ1 and RQ3, respectively; AVDD represents the operating voltage of the internal voltage; V GS V represents the gate-source voltage difference of a MOSFET; GS11 This represents the gate-source voltage difference when transistor MQ11 is operating. Typically, AVDD is a low voltage of 5V, therefore, the voltage difference is achieved by adjusting the ratio of resistors RQ1 and RQ3. BOOT1 and V SW1 The voltage between the two is determined. The working principle of the second undervoltage detection circuit is similar to that of the first undervoltage detection circuit, and will not be described in detail here.

[0053] in, Figure 2In the power drive circuit shown, transistors M1, M2, M3, and M4 are all PMOS power MOSFETs.

[0054] Figure 3 In the high-voltage selection circuit shown, both transistors MP1 and MP2 are NMOS power MOSFETs.

[0055] Figure 4 In the first power supply circuit shown, transistors MB1, MB2, MB3, MB4, MB7, MB8, MB9, MB10, MB13, MB14, MB15, MB16, MB17, and MB19 are all NMOS power MOSFETs; transistors MB5, MB6, MB11, MB12, MB18, MB20, and MB21 are all PMOS power MOSFETs.

[0056] Figure 5 In the first undervoltage detection circuit shown, transistors MQ1, MQ2, MQ3, MQ4, MQ5, MQ6, MQ7, MQ9, and MQ10 are all NMOS power MOSFETs; transistors MQ8, MQ11, and MQ12 are all PMOS power MOSFETs.

[0057] This invention is based on multiple driving power supplies. The highest voltage in the driving power supply is selected by a high voltage selection circuit to power all driving circuits. When any of the switching transistors needs to operate at 100% duty cycle, no additional charge pump circuit is required. When one circuit operates in switching mode and the other operates at 100% duty cycle, the BOOT capacitor is charged in each cycle of the switching mode. Therefore, the corresponding voltage is always kept at the driving voltage, and no additional refresh circuit is required, thus achieving a true 100% duty cycle.

[0058] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the control method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A power supply drive circuit, characterized in that, include: Tubes M1, M2, M3, and M4; Driver1 and Driver2; Diodes D1 and D2; Capacitors C1 and C2; Inductor L; High-voltage selection circuit; First power supply circuit; Second power supply circuit; First undervoltage detection circuit; and Second undervoltage detection circuit. The gate of transistor M1 is driven by the driving circuit DRIVER1; the connection node between the source of transistor M1 and the driving circuit DRIVER1 is node SW1; the drain of transistor M1 is connected to voltage VA; the anode of diode D1 is connected to voltage VCC; the connection node between the cathode of diode D1 and the driving circuit DRIVER1 is node BOOT1; the driving circuit DRIVER1 is also connected to pulse width modulation signal PWMH1; the gate of transistor M2 is connected to pulse width modulation signal PWML1; the drain of transistor M2 is connected to node SW1; the source of transistor M2 is grounded; one end of capacitor C1 is connected to node BOOT1; the other end of capacitor C1 is connected to node SW1. The gate of transistor M4 is driven by the driving circuit DRIVER2; the connection node between the source of transistor M4 and the driving circuit DRIVER2 is node SW2; the drain of transistor M4 is connected to voltage VB; the anode of diode D2 is connected to voltage VCC; the connection node between the cathode of diode D2 and the driving circuit DRIVER2 is node BOOT2; the driving circuit DRIVER2 is also connected to pulse width modulation signal PWMH2; the gate of transistor M3 is connected to pulse width modulation signal PWML2; the drain of transistor M3 is connected to node SW2; the source of transistor M3 is grounded; one end of capacitor C2 is connected to node BOOT2; the other end of capacitor C2 is connected to node SW2. One end of the inductor L is connected to node SW1; the other end of the inductor L is connected to node SW2; the high-voltage selection circuit is connected to nodes BOOT1 and BOOT2 respectively; the connection node between the high-voltage selection circuit and the first and second power supply circuits is node COM; the first power supply circuit is connected to nodes BOOT1 and SW1 respectively; the second power supply circuit is connected to nodes BOOT2 and SW2 respectively. The first undervoltage detection circuit is connected to node BOOT1, node SW1 and the first power replenishment circuit respectively; the second undervoltage detection circuit is connected to node BOOT2, node SW2 and the second power replenishment circuit respectively.

2. The power supply drive circuit according to claim 1, characterized in that, The high-voltage selection circuit includes transistors MP1 and MP2, diode DP1, and diode DP2. The gate of transistor MP1 is connected to node BOOT2; the drain of transistor MP1 is connected to node BOOT1; the source of transistor MP1 is connected to node COM; the anode of diode DP1 is connected to node BOOT1; the cathode of diode DP1 is connected to node COM; the gate of transistor MP2 is connected to node BOOT1; the drain of transistor MP2 is connected to node BOOT2; the source of transistor MP2 is connected to node COM; the anode of diode DP2 is connected to node BOOT2; and the cathode of diode DP2 is connected to node COM.

3. The power supply drive circuit according to claim 1, characterized in that, The first power supply circuit and the second power supply circuit have a symmetrical structure; the first power supply circuit includes: transistors MB1~MB21, resistors RB1~RB4, capacitors CB1~CB4, current sources IB1~IB2, Zener diodes DB1, and undervoltage lockout module UVLO; The source of transistor MB1, one end of resistor RB1, one end of capacitor CB1, one end of resistor RB2, the drain of transistor MB6, the source of transistor MB8, one end of capacitor CB2, the source of transistor MB9, the source of transistor MB10, one end of capacitor CB3, the source of transistor MB15, and one end of capacitor CB4 are all connected to node COM; the source of transistor MB2 is connected to the gate and drain of transistor MB1; the source of transistor MB3 is connected to the gate and drain of transistor MB2; one end of current source IB1 is connected to the gate and drain of transistor MB3; the other end of current source IB1 is grounded; The source of transistor MB4 is connected to the other end of resistor RB1; one end of resistor RB3 is connected to the other end of resistor RB2; the gate of transistor MB4 is connected to the gate of transistor MB3, the other end of capacitor CB1, the other end of resistor RB3, and the gate of transistor MB7; the drain of transistor MB4 is connected to the gate and drain of transistor MB5, one end of resistor RB4, and the gate of transistor MB6; the source of transistor MB5 is connected to the negative terminal of Zener diode DB1; the positive terminal of Zener diode DB1, the source of transistor MB20, and the source of transistor MB21 are all connected to node SW1; the other end of resistor RB4, the other end of transistor MB7, and the gate of transistor MB8 are connected to the gate of transistor MB3, the other end of capacitor CB1, the other end of resistor RB3, and the gate of transistor MB7 are connected to the gate of transistor MB8. The source of B6 and the drain of MB7 are both connected to node BOOT1; the drain of MB8 is connected to the source of MB7; the gate of MB8 is connected to the other end of capacitor CB2, the drain of MB9, the gate of MB10, the drain of MB11, the gate of MB12, and the source of MB13; the gate of MB9 is connected to the drain of MB10, the gate of MB11, the drain of MB12, and the source of MB14; the source of MB11 is connected to the source of MB12, the other end of capacitor CB3, the source of MB18, and the capacitor... The other end of CB4 is connected to the source of the transistor MB19; the source of the transistor MB16 is connected to the gate and drain of the transistor MB15; the source of the transistor MB17 is connected to the gate and drain of the transistor MB16; the drain of the transistor MB18 is connected to the gate and drain of the transistor MB15 and the gate of the transistor MB18; the gate of the transistor MB13 is connected to the gate of the transistor MB14 and the gate of the transistor MB19; the drain of the transistor MB13 is connected to the drain of the transistor MB20; the drain of the transistor MB14 is connected to the drain of the transistor MB21; one end of the current source IB2 is connected to the drain of the transistor MB19; the other end of the current source IB1 is grounded. The gate of the transistor MB20 is connected to the signal BT_UVB; the gate of the transistor MB21 is connected to the signal BT_UVZ; the undervoltage lockout module UVLO is connected to the node BOOT1, the node SW1, the signal BT_UVB and the signal BT_UVZ respectively.

4. The power supply drive circuit according to claim 1, characterized in that, The first undervoltage detection circuit and the second undervoltage detection circuit have a symmetrical structure; the first undervoltage detection circuit includes: transistors MQ1~MQ12, resistors RQ1~RQ3 and Schmitt trigger NB1; The sources of transistors MQ1, MQ4, MQ7, and MQ9 are all connected to node BOOT1; the source of transistor MQ2 is connected to the gate and drain of transistor MQ1 and the gate of transistor MQ7; the source of transistor MQ3 is connected to the gate and drain of transistor MQ2; the drain of transistor MQ11 is connected to the gate and drain of transistor MQ3, the gate of transistor MQ4, and the gate of transistor MQ10; the drain of transistor MQ4 is connected to the source of transistor MQ5; the gate and drain of transistor MQ5 are connected to the source of transistor MQ6; the gate of transistor MQ6 is connected to the drain of transistor MQ6, the gate of transistor MQ8, and the resistor. One end of RQ3; the source of transistor MQ8 and the other end of resistor RQ3 are both connected to node SW1; the drain of transistor MQ7 is connected to the drain of transistor MQ8 and the gate of transistor MQ9; the drain of transistor MQ9 is connected to the source of transistor MQ10; the drain of transistor MQ10 is connected to the drain of transistor MQ12; the gate of transistor MQ11 is connected to the gate of transistor MQ12; the source of transistor MQ11 is connected to one end of resistor RQ1; the source of transistor MQ12 is connected to one end of resistor RQ2; the other ends of resistors RQ1 and RQ2 are both grounded; the source of transistor MQ12 also outputs the signal BOOTOK through Schmitt trigger NB1.

5. The power supply drive circuit according to claim 1, characterized in that, The transistors M1, M2, M3 and M4 are all PMOS power MOSFETs.

6. The power drive circuit according to claim 2, characterized in that, Both MP1 and MP2 are NMOS power MOSFETs.

7. The power drive circuit according to claim 3, characterized in that, The transistors MB1, MB2, MB3, MB4, MB7, MB8, MB9, MB10, MB13, MB14, MB15, MB16, MB17, and MB19 are all NMOS power MOSFETs; the transistors MB5, MB6, MB11, MB12, MB18, MB20, and MB21 are all PMOS power MOSFETs.

8. The power drive circuit according to claim 4, characterized in that, The transistors MQ1, MQ2, MQ3, MQ4, MQ5, MQ6, MQ7, MQ9 and MQ10 are all NMOS power MOSFETs; the transistors MQ8, MQ11 and MQ12 are all PMOS power MOSFETs.

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