An all-integrated driving chip architecture based on voltage slope detection, electronic device

Abstract

The application provides a full-integrated driving chip architecture based on voltage slope detection, and an electronic device, which are used for driving a first power tube; a feedback capacitor is used for feeding back voltage slope change of source-drain voltage of the first power tube, and generating displacement current according to the feedback result; a control unit is used for outputting a control signal; a voltage slope detection circuit of an integrated driving unit is used for outputting a first turn-on level signal to a turn-on three-stage driving branch of the integrated driving unit according to the displacement current; the turn-on three-stage driving branch is used for forming a first driving current, a second driving current and a third driving current according to the first turn-on level signal and the control signal, and outputting to a gate of the first power tube, so as to sequentially control turn-on of the first power tube in different turn-on stages; and a turn-off driving branch of the integrated driving unit is used for outputting a constant fourth driving current to the gate of the first power tube according to the control signal, so as to control turn-off of the first power tube.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide driving, and more particularly to a fully integrated driving chip architecture and electronic device based on current slope detection. Background Technology

[0002] With the development of wide-bandgap devices, GaN HEMTs have seen rapid development and application in recent years due to their faster switching speeds and frequencies compared to Si MOSFETs, effectively improving power system efficiency. However, in applications with even faster switching speeds and frequencies, the EMI and switching losses of GaN HEMTs become more prominent. Traditional drive circuits struggle to simultaneously optimize both EMI and switching losses in GaN HEMTs. Therefore, a multi-stage drive circuit is needed to control the drive current at different stages of the Si MOSFET drive process. The drive current is reduced during stages where EMI issues occur and increased during other stages, thus optimizing both voltage and current spikes and switching losses during the GaN HEMT drive process.

[0003] Please refer to Figure 1 Existing multi-segment drive circuits consist of an off-chip FPGA and a digitally programmable driver chip. Since the programmable driver chip can control a large number of segments within a single switching cycle, the FPGA needs to generate control clock signals, segment number signals, and control switching signals for these multiple segments. Therefore, the overall control delay of existing multi-segment drive circuits is determined by the FPGA's control frequency, which is typically between 100 and 300 MHz. This makes existing technology unsuitable for GaN HEMTs with control delays in the tens of nanosecond range. Furthermore, to achieve multi-segment control, the digital control within the digitally programmable driver chip requires numerous level shifting circuits, multi-segment triggering circuits, and encoding / decoding circuits. Such large-scale digital circuitry leads to longer control delays and higher circuit costs, further hindering the reduction of control delays for GaN HEMTs. Summary of the Invention

[0004] This invention provides a fully integrated driver chip architecture and electronic device based on voltage slope detection, which simultaneously optimizes the EMI and switching loss problems of GaN HEMT through a low-latency and low-cost solution.

[0005] According to a first aspect of the present invention, a fully integrated driver chip architecture based on voltage slope detection is provided for driving a first power transistor, wherein a first terminal of the first power transistor is coupled to ground, and a second terminal of the first power transistor is connected to a power supply terminal through a load unit; the architecture includes:

[0006] A feedback capacitor; the first end of the feedback capacitor is coupled to the first end of the first power transistor; the feedback capacitor is used to detect the voltage slope of the first power transistor and generate a displacement current based on the detection result; wherein, the displacement current is used to characterize the change in the voltage slope of the first power transistor during the turn-on process;

[0007] A control unit, used to output a control signal based on an input level;

[0008] The integrated drive unit includes a three-stage turn-on drive branch and a turn-off drive branch; the three-stage turn-on drive branch includes a voltage slope detection circuit and a three-stage turn-on processing circuit; wherein:

[0009] The voltage slope detection circuit is coupled to the second terminal of the feedback capacitor, and is used to receive the displacement current and output a first turn-on level signal according to the displacement current.

[0010] The three-stage turn-on processing circuit is respectively coupled to the output terminal of the voltage slope detection circuit, the output terminal of the control unit, and the gate of the first power transistor; the three-stage turn-on processing circuit is used to receive the first turn-on level signal and the control signal, and to form a first drive current, a second drive current, and a third drive current to the gate of the first power transistor according to the first turn-on level signal and the control signal, wherein the first drive current, the second drive current, and the third drive current are used to sequentially control the turn-on of the first power transistor in different turn-on stages;

[0011] The shutdown drive branch is coupled to the output terminal of the control unit and the gate of the first power transistor respectively; the shutdown drive branch is used to receive the control signal and output a constant fourth drive current to the gate of the first power transistor according to the control signal, and the fourth drive current is used to control the shutdown of the first power transistor.

[0012] Furthermore, the three-stage drive branch for activation and the drive branch for deactivation are both integrated into the same chip.

[0013] Optionally, the three-stage activation processing circuit includes an activation logic control circuit and an activation three-stage push-pull circuit.

[0014] The turn-on logic control circuit is coupled to the output terminal of the voltage slope detection circuit and the output terminal of the control unit. It is used to receive the first turn-on level signal and the control signal, and to perform digital operations on the control signal, the first turn-on level signal, and the control signal respectively, and then output the first turn-on control signal and the second turn-on control signal.

[0015] The three-stage push-pull circuit is coupled to the output of the power-on logic control circuit and the gate of the first power transistor, respectively. It is used to receive the first power-on control signal and the second power-on control signal, and output the first drive current, the second drive current and the third drive current to the outside in sequence according to the first power-on control signal and the second power-on control signal.

[0016] Optionally, the shutdown drive branch includes a shutdown logic control circuit and a shutdown push-pull circuit;

[0017] The shutdown logic control circuit is coupled to the output terminal of the control unit. It is used to receive the control signal, perform digital calculations on the control signal, and output the first shutdown control signal to the outside.

[0018] The turn-off push-pull circuit is coupled to the output terminal of the turn-off logic control circuit and the gate of the first power transistor, respectively. It is used to receive the first turn-off control signal and output the fourth drive current according to the first turn-off control signal.

[0019] Optionally, the voltage slope detection circuit includes a first MOSFET, a first current source, a first inverter, and a second inverter;

[0020] The gate of the first MOS transistor is connected to its second terminal; its second terminal is connected to the second terminal of the first power supply terminal; wherein, the gate of the first MOS transistor also receives the displacement current;

[0021] The input terminal of the first inverter is connected to the second terminal of the first MOS transistor; the input terminal of the second inverter is connected to the output terminal of the first inverter; the output terminal of the second inverter is used to output the first turn-on level signal.

[0022] Optionally, the turn-on logic control circuit includes a third inverter, a fourth inverter, and a first AND gate;

[0023] The input terminal of the third inverter is coupled to the output terminal of the control unit, and its output terminal is connected to the input terminal of the fourth inverter; the third inverter is used to invert the control signal.

[0024] The output terminal of the fourth inverter serves as the output terminal of the turn-on logic control circuit, which is used to invert the inverted control signal again and output the second turn-on control signal.

[0025] The first input terminal and the second input terminal of the first AND gate are respectively coupled to the second terminal of the second MOS transistor and the output terminal of the control unit; the first AND gate is used to perform an AND operation on the first turn-on level signal and the control signal, and output the first turn-on control signal.

[0026] Optionally, the three-stage push-pull circuit includes a first-stage push-pull branch and a second-stage push-pull branch.

[0027] The first-stage push-pull branch includes a first-stage push-pull circuit and a first-stage turn-on MOSFET; the input terminal of the first-stage push-pull circuit is coupled to the output terminal of the first AND gate, and its output terminal is coupled to the gate of the first-stage turn-on MOSFET; the second terminal of the first-stage turn-on MOSFET is coupled to the gate of the first power transistor; the first-stage push-pull circuit is used to receive the first turn-on control signal, and output the first turn-on signal to the gate of the first-stage turn-on MOSFET after push-pull processing; the first-stage turn-on MOSFET is used to output a first current or not output current under the action of the first turn-on control signal after push-pull processing.

[0028] The second-stage turn-on push-pull branch includes a second-stage push-pull circuit and a second turn-on MOSFET; the input terminal of the second-stage push-pull circuit is coupled to the output terminal of the fourth inverter, and its output terminal is coupled to the gate of the second turn-on MOSFET; the second terminal of the second MOSFET is coupled to the gate of the first power transistor; the second-stage push-pull circuit receives the second turn-on control signal, and outputs the push-pull operation on the second turn-on control signal to the gate of the second turn-on MOSFET; the second turn-on MOSFET outputs the second current under the action of the push-pull second turn-on control signal; wherein:

[0029] The first driving current is composed of the first current and the second current; the second driving current is composed of the second current; the third driving current is composed of the first current and the second current.

[0030] Optionally, the shutdown logic control circuit includes a fifth inverter.

[0031] Optionally, the turn-off push-pull circuit includes a third-stage push-pull circuit and a first turn-off MOS transistor;

[0032] The input terminal of the third-stage push-pull circuit is coupled to the output terminal of the shutdown logic control circuit, and its input terminal is coupled to the gate of the first shutdown MOS transistor; the second terminal of the first shutdown MOS transistor is coupled to the gate of the first power transistor; the third-stage push-pull circuit is used to receive the first shutdown control signal, and output the first shutdown control signal to the gate of the first shutdown MOS transistor after push-pull operation; the first shutdown MOS transistor is used to output the fourth drive current under the action of the first shutdown control signal after push-pull operation.

[0033] Optionally, the first-stage push-pull circuit, the second-stage push-pull circuit, and the third-stage push-pull circuit are all composed of six inverters connected in series.

[0034] Optionally, both the first turn-on MOSFET and the second turn-on MOSFET are PLDMOS transistors.

[0035] Optionally, the first turn-off MOS transistor is an NLDMOS transistor.

[0036] Optionally, the load unit includes a second power transistor, a load inductor, a load capacitor, and a first constant voltage source;

[0037] The first terminal of the second power transistor is connected to the second terminal of the first power transistor and the second terminal of the load inductor, respectively.

[0038] The second terminal of the second power transistor, the first terminal of the load inductor, the first terminal of the load capacitor, and the first terminal of the first constant voltage source are all connected to the power supply terminal;

[0039] The second terminal of the load capacitor and the second terminal of the first constant voltage source are both grounded.

[0040] Optionally, the second power transistor may be an NMOS transistor.

[0041] Optionally, the first power transistor is a gallium nitride single transistor.

[0042] Optionally, the control unit includes a PWM controller.

[0043] According to a second aspect of the present invention, an electronic device is provided, comprising the fully integrated driver chip architecture based on voltage slope detection provided by the first aspect and alternative solutions of the present invention.

[0044] The fully integrated driver chip architecture based on current slope detection provided by this invention simulates and integrates the driving circuit composed of an off-chip FPGA and a digitally programmable driver chip in the prior art to form a fully integrated driver chip. The chip also integrates a detection circuit inside the chip and adds a feedback capacitor outside the chip to provide feedback on the voltage slope of the source-drain voltage of the first power transistor. This chip solves the delay and circuit complexity problems caused by the low control frequency of the off-chip FPGA and the large scale of the digital circuit inside the digitally programmable driver chip. At the same time, it can perform adaptive control according to the different operating states of the first power transistor, which has a better control effect than the open-loop control scheme of the prior art. Attached Figure Description

[0045] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0046] Figure 1 This is a schematic diagram of the structure of a multi-segment drive circuit in the prior art;

[0047] Figure 2This is the circuit structure block diagram of the fully integrated driver chip architecture based on voltage slope detection provided in the embodiments of the present invention. Figure 1 ;

[0048] Figure 3 This is a schematic diagram of the circuit structure of the voltage slope detection circuit provided in an embodiment of the present invention. Figure 1 ;

[0049] Figure 4 This is a schematic diagram of the circuit structure of the voltage slope detection circuit provided in an embodiment of the present invention. Figure 2 ;

[0050] Figure 5 This is the circuit structure block diagram of the fully integrated driver chip architecture based on voltage slope detection provided in the embodiments of the present invention. Figure 2 ;

[0051] Figure 6 This is a schematic diagram of the circuit structure of the turn-on logic control circuit provided in an embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of the circuit structure of the three-segment push-pull circuit provided in an embodiment of the present invention;

[0053] Figure 8 This is a schematic diagram of the circuit structure of the turn-off push-pull circuit provided in an embodiment of the present invention;

[0054] Figure 9 This is a schematic diagram of the circuit structure of the load unit provided in an embodiment of the present invention. Attached image description:

[0056] 10-Control unit;

[0057] 20 - Integrated drive unit;

[0058] 21- Open the three-stage drive branch;

[0059] 211-Voltage slope detection circuit;

[0060] 2111 - First inverter;

[0061] 2112 - Second inverter;

[0062] 212 - Activate the three-stage processing circuit;

[0063] 2121 - Turn-on logic control circuit;

[0064] 2122 - Enable the three-stage push-pull circuit;

[0065] 21221 - First-level opening of push-pull branch road;

[0066] 212211 - First-stage push-pull circuit;

[0067] 21222 - Second-level opening of push-pull branch road;

[0068] 212221 - Second-stage push-pull circuit;

[0069] 22-Shut down the drive branch;

[0070] 221 - Shutdown logic control circuit;

[0071] 222 - Turn off push-pull circuit;

[0072] 2221 - Third-stage push-pull circuit;

[0073] 30-Load Unit;

[0074] H1 - First power transistor;

[0075] Cs - Feedback capacitor;

[0076] M1 - First MOSFET;

[0077] Is - displacement current;

[0078] Q1 - First current source;

[0079] D1 - First diode;

[0080] D2 - Second diode;

[0081] CTR - First turn-on level signal;

[0082] VDC - Power supply terminal;

[0083] PWM - control signal;

[0084] Son2 - Second turn-on control signal;

[0085] Son1 - First turn-on control signal;

[0086] Soff - First shutdown control signal;

[0087] P1 - First MOSFET to be turned on;

[0088] P2 - Second turn-on MOSFET;

[0089] N1 - First turn-off MOSFET;

[0090] H2 - Second power transistor;

[0091] Lp - Load inductance;

[0092] CDC - Load capacitor;

[0093] V1 - First constant pressure source. Detailed Implementation

[0094] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0095] Before describing the embodiments of the present invention, the design concept of the present invention will be briefly introduced as follows:

[0096] The excessively fast switching speed and frequency of GaN HEMTs can lead to severe EMI problems during turn-on. This undoubtedly increases the voltage and current stress during GaN HEMT operation, reducing its reliability in long-term operation. Since most GaN HEMTs use DFN surface mount packages, their parasitic inductance and loop parasitic inductance are relatively small. Furthermore, according to the peak voltage formula:

[0097]

[0098] V os Used to characterize peak voltage; L DS Used to characterize the drain-source parasitic inductance of GaN HEMTs; i D Drain current used to characterize GaN HEM.

[0099] Therefore, voltage spikes and EMI issues during the turn-off process of GaN HEMTs are not the primary optimization target. However, overly conservative consideration of GaN HEMT operating stress would significantly limit the power rating of the GaN HEMT and increase turn-on losses. Therefore, it is necessary to optimize both EMI and turn-on losses during the turn-on process. Since EMI issues only occur in specific stages of the GaN HEMT turn-on process, it is necessary to differentiate between different stages. Slow turn-on should be used during stages with current and voltage spikes, while maintaining a fast turn-on speed in other stages. Furthermore, since the turn-on speed of GaN HEMTs is positively correlated with the drive current, a small drive current should be used during stages with EMI issues, while a large drive current should be maintained in other stages. This approach suppresses peak current levels during turn-on while maintaining low switching losses. To achieve this multi-stage driving, the feedback circuit and detection circuit need to be able to detect in a timely manner the stages during which current spikes appear and disappear during the turn-on process of the GaN HEMT. The subsequent logic control circuit and adjustment circuit should then adjust the output magnitude of the drive current accordingly. Therefore, reducing the feedback control delay is crucial. To reduce the feedback control delay, the detection circuit, logic control circuit, and subsequent adjustment circuit of this invention are all integrated into a single chip using analog circuitry, thereby minimizing the feedback control delay.

[0100] Please refer to Figure 2 Based on the above design concept, this embodiment of the invention provides a fully integrated driver chip architecture based on voltage slope detection for driving a first power transistor H1. The second terminal of the first power transistor H1 is connected to the power supply terminal VDC through a load unit 30. The architecture includes:

[0101] A feedback capacitor Cs is used; the first terminal of the feedback capacitor Cs is coupled to the first terminal of the first power transistor H1; the feedback capacitor Cs is used to provide feedback on the change in the voltage slope of the source-drain voltage of the first power transistor H1, and to generate a displacement current Is based on the change; wherein, the displacement current Is is used to characterize the change in the peak current caused by the change in the voltage slope of the source-drain voltage during the turn-on process of the first power transistor H1; the principle is as follows: the formula for the peak current generated by the first power transistor H1 during the turn-on process is:

[0102]

[0103] Among them, C oss Used to characterize the output capacitance of the first power transistor H1, v DS Used to characterize the source-drain voltage of the first power transistor H1.

[0104] The formula for the displacement current Is is:

[0105]

[0106] Wherein, Is is used to characterize the displacement current Is; Cs is used to characterize the feedback capacitor Cs.

[0107] As can be seen from the above formula, the peak current is related to the current slope of the first power transistor H1 during the turn-on process. Therefore, the change in the current slope of the source-drain voltage will change the magnitude of the peak current. Simultaneously, the change in the current slope of the source-drain voltage will also change the magnitude of the displacement current Is. Therefore, the displacement current Is can be used to characterize the change in the peak current caused by the change in the voltage slope of the source-drain voltage during the turn-on process of the first power transistor H1.

[0108] Control unit 10 is used to output a control signal Ps according to an input level;

[0109] The integrated drive unit 20 includes a three-stage turn-on drive branch 21 and a three-stage turn-off drive branch 22; the three-stage turn-on drive branch 21 includes a voltage slope detection circuit 211 and a three-stage turn-on processing circuit 212; wherein:

[0110] Please refer to Figure 3 The voltage slope detection circuit 211 is coupled to the second terminal of the feedback capacitor Cs, and is used to receive the displacement current Is and output a first turn-on level signal CTR according to the displacement current Is; specifically, the voltage slope detection circuit 211 includes a first MOS transistor M1, a first current source Q1, a first inverter 2111, and a second inverter 2112.

[0111] The gate of the first MOSFET M1 is connected to its second terminal; its second terminal is connected to the second terminal of the first power supply VDC; wherein, the gate of the first MOSFET M1 also receives the displacement current Is; the input terminal of the first inverter 2111 is connected to the second terminal of the first MOSFET M1; the input terminal of the second inverter 2112 is connected to the output terminal of the first inverter 2111; the output terminal of the second inverter 2112 is used to output the first turn-on level signal CTR. The specific working principle of the voltage slope detection circuit 211 is as follows: when the first power transistor H1 is initially turned on, its gate voltage gradually rises from zero, causing the current flowing through the first power transistor H1 to rise to the load current. During this process, the source-drain voltage of the first power transistor H1 remains essentially unchanged, and the displacement current Is is essentially zero. Therefore, the current flowing through the first MOSFET M1 is a small current from the first current source Q1, resulting in a very small voltage drop across the first MOSFET M1. This makes the drain voltage of the first MOSFET M1 high relative to the power supply VDC, causing the first turn-on level signal CTR output by the first inverter 2111 and the second inverter 2112 to be high. Specifically, the power supply VDC is 5V, and the drain voltage of the first MOSFET M1 is 4V-4.5V. Of course, this is only experimental data and is not a limitation. When the first power transistor H1 enters the Miller plateau, the source-drain voltage of the first power transistor H1 will drop rapidly, that is, the current slope of the source-drain voltage becomes negative. At this time, the displacement current Is also becomes negative according to the above formula, that is, it flows from the gate of the first MOSFET M1 to the drain of the first power transistor H1. Therefore, the current flowing through the first MOSFET M1 will increase to the current of the first current source Q1 plus the displacement current Is. Therefore, the voltage drop of the first MOSFET M1 is very large, making the drain voltage of the first MOSFET M1 low compared to the power supply terminal VDC, and making the first turn-on level signal CTR output by the first inverter 2111 and the second inverter 2112 low. When the source-drain voltage of the first power transistor H1 drops to 0, the voltage slope of the source-drain voltage of the first power transistor H1 becomes 0 again, and the first turn-on level returns to high level again as described above.

[0112] In one specific implementation, the first MOS transistor M1 is a PMOS transistor.

[0113] Please refer to Figure 4In a preferred embodiment, the voltage slope detection circuit 211 further includes a first diode D1 and a second diode D2; the forward terminal of the first diode D1 is connected to the gate of the first MOSFET M1, and its reverse terminal is connected to the source of the first MOSFET M1; the forward terminal of the second diode D2 is connected to the first terminal of the first current source Q1, and its reverse terminal is connected to the forward terminal of the first diode D1. The first diode D1 and the second diode D2 constitute a clamping circuit to clamp the voltage input to the voltage slope detection circuit 211.

[0114] Please refer to Figure 2 The three-stage turn-on processing circuit 212 is coupled to the output terminal of the voltage slope detection circuit 211, the output terminal of the control unit 10, and the gate of the first power transistor H1, respectively. The three-stage turn-on processing circuit 212 is used to receive the first turn-on level signal CTR and the control signal Ps, and to form a first drive current, a second drive current, and a third drive current to the gate of the first power transistor H1 according to the first turn-on level signal CTR and the control signal Ps. The first drive current, the second drive current, and the third drive current are used to sequentially control the turn-on of the first power transistor H1 in different turn-on stages.

[0115] Please refer to Figure 2 The shutdown drive branch 22 is coupled to the output terminal of the control unit 10 and the gate of the first power transistor H1, respectively. The shutdown drive branch 22 is used to receive the control signal Ps and output a constant fourth drive current to the gate of the first power transistor H1 according to the control signal Ps. The fourth drive current is used to control the shutdown of the first power transistor H1. As can be seen from the above description, the drain-source parasitic inductance of the first power transistor H1 is very small. According to the above peak voltage formula of the first power transistor H1, the fourth drive current is used as large as possible while ensuring that the current slope of the drain induced current of the first power transistor H1 does not exceed the first threshold. The first threshold can be adjusted according to actual needs and is not limited here.

[0116] Furthermore, the three-stage drive branch 21 for activation and the drive branch 22 for deactivation are both integrated into the same chip.

[0117] In one specific implementation, the first power transistor H1 is a gallium nitride single transistor.

[0118] In one specific implementation, the feedback capacitor Cs is an off-chip high-voltage capacitor.

[0119] In one specific implementation, the control unit 10 includes a PWM controller. Specifically, the control signal Ps is a PWM signal.

[0120] Please refer to Figure 5 In one specific implementation, the three-stage activation processing circuit 212 includes an activation logic control circuit 2121 and an activation three-stage push-pull circuit 2122.

[0121] Please refer to Figure 6 The turn-on logic control circuit 2121 is coupled to the output terminal of the voltage slope detection circuit 211 and the output terminal of the control unit 10. It receives the first turn-on level signal CTR and the control signal Ps, and performs digital operations on the control signal Ps, the first turn-on level signal CTR, and the control signal Ps respectively, then outputs the first turn-on control signal Son1 and the second turn-on control signal Son2. Specifically, the turn-on logic control circuit 2121 includes a third inverter, a fourth inverter, and a first AND gate. The input terminal of the third inverter is coupled to the output terminal of the control unit 10, and its output terminal is connected to the input terminal of the fourth inverter. The third inverter is used to invert the control signal Ps; the output of the fourth inverter serves as the output of the turn-on logic control circuit 2121, which inverts the inverted control signal Ps again and outputs the second turn-on control signal Son2; the advantage of using two inverters is that the control signal Ps is shaped to a standard level signal; the first and second inputs of the first AND gate are respectively coupled to the second terminal of the second MOS transistor and the output of the control unit 10; the first AND gate is used to perform an AND operation on the first turn-on level signal CTR and the control signal Ps, and outputs the first turn-on control signal Son1. The formulas for the first turn-on signal and the second turn-on control signal Son2 are:

[0122]

[0123] in, Used to characterize the first turn-on control signal Son1; The control signal Ps is used to characterize the second turn-on control signal Son2; PWM is used to characterize the control signal; CTR is used to characterize the first turn-on level signal. Specifically, during the turn-on phase of the first power transistor H1, the control signal Ps is always high, and the second turn-on control signal Son2 is always high; when the first turn-on level signal CTR is high, the first turn-on control signal Son1 is high; when the first turn-on level signal CTR is low, the first turn-on control signal Son1 is low.

[0124] Please refer to Figure 7The three-stage push-pull circuit 2122 is coupled to the output terminal of the turn-on logic control circuit 2121 and the gate of the first power transistor H1, respectively. It is used to receive the first turn-on control signal Son1 and the second turn-on control signal Son2, and output the first drive current, the second drive current and the third drive current to the outside in sequence according to the first turn-on control signal Son1 and the second turn-on control signal Son2. Specifically, the three-stage push-pull circuit 2122 includes a first-stage push-pull branch 21221 and a second-stage push-pull branch 21222. The first-stage push-pull branch 21221 includes a first-stage push-pull circuit 212211 and a first-stage turn-on MOSFET P1. The input terminal of the first-stage push-pull circuit 212211 is coupled to the output terminal of the first AND gate, and its output terminal is coupled to the gate of the first-stage turn-on MOSFET P1. The second terminal of the first-stage turn-on MOSFET P1 is coupled to the gate of the first power transistor H1. The first-stage push-pull circuit 212211 receives the first turn-on control signal Son1 and outputs it to the gate of the first-stage turn-on MOSFET P1 after push-pull processing. The first-stage turn-on MOSFET P1 outputs a first current or does not output current under the action of the first turn-on control signal Son1 after push-pull processing. The second-stage push-pull branch 212211 receives the first turn-on control signal Son1 and outputs it to the gate of the first-stage turn-on MOSFET P1. Circuit 21222 includes a second-stage push-pull circuit 212221 and a second turn-on MOSFET P2; the input terminal of the second-stage push-pull circuit 212221 is coupled to the output terminal of the fourth inverter, and its output terminal is coupled to the gate of the second turn-on MOSFET P2; the second terminal of the second MOSFET is coupled to the gate of the first power transistor H1; the second-stage push-pull circuit 212221 is used to receive the second turn-on control signal Son2, and outputs the second turn-on control signal Son2 to the gate of the second turn-on MOSFET P2 after push-pull operation; the second turn-on MOSFET P2 is used to output the second current under the action of the second turn-on control signal Son2 after push-pull operation; wherein: the first driving current is composed of the first current and the second current; the second driving current is composed of the second current; the third driving current is composed of the first current and the second current.

[0125] In one specific implementation, both the first turn-on MOS transistor P1 and the second turn-on MOS transistor P2 are PLDMOS transistors.

[0126] Please refer to Figure 5 In one specific implementation, the shutdown drive branch 22 includes a shutdown logic control circuit 221 and a shutdown push-pull circuit 222.

[0127] The shutdown logic control circuit 221 is coupled to the output terminal of the control unit 10. It is used to receive the control signal Ps, perform digital operations on the control signal Ps, and output the first shutdown control signal Soff. Specifically, the shutdown logic control circuit 221 is a fifth inverter.

[0128] Please refer to Figure 8 The turn-off push-pull circuit 222 is coupled to the output terminal of the turn-off logic control circuit 221 and the gate of the first power transistor H1, respectively. It receives the first turn-off control signal Soff and outputs the fourth drive current according to the first turn-off control signal Soff. Specifically, the turn-off push-pull circuit 222 includes a third-stage push-pull circuit 2221 and a first turn-off MOS transistor N1.

[0129] The input terminal of the third-stage push-pull circuit 2221 is coupled to the output terminal of the shutdown logic control circuit 221, and its input terminal is coupled to the gate of the first shutdown MOS transistor N1; the second terminal of the first shutdown MOS transistor N1 is coupled to the gate of the first power transistor H1; the third-stage push-pull circuit 2221 is used to receive the first shutdown control signal Soff, and output the first shutdown control signal Soff to the gate of the first shutdown MOS transistor N1 after push-pull operation; the first shutdown MOS transistor N1 is used to output the fourth drive current under the action of the first shutdown control signal Soff after push-pull operation.

[0130] In one specific implementation, the first turn-off MOS transistor N1 is an NLDMOS transistor.

[0131] Please refer to Figure 7 and Figure 8 In a preferred embodiment, the first-stage push-pull circuit 212211, the second-stage push-pull circuit 212221, and the third-stage push-pull circuit 2221 are all composed of six inverters connected in series. Each inverter is a CMOS inverter. The first-stage push-pull circuit 212211 to the sixth-stage push-pull circuit are used to improve the current driving capability. The principle is that the larger the size of the CMOS inverter, the greater its current driving capability. In this embodiment, the size of the CMOS inverter in each push-pull circuit increases progressively, so each time the CMOS inverter flips the input level, it improves the current driving capability.

[0132] Please refer to Figure 9 In one specific implementation, the load unit 30 includes a second power transistor H2, a load inductor Lp, a load capacitor CDC, and a first constant voltage source V1;

[0133] The first terminal of the second power transistor H2 is connected to the second terminal of the first power transistor H1 and the second terminal of the load inductor Lp, respectively.

[0134] The second terminal of the second power transistor H2, the first terminal of the load inductor Lp, the first terminal of the load capacitor CDC, and the first terminal of the first constant voltage source V1 are all connected to the power supply terminal VDC.

[0135] The second terminal of the load capacitor CDC and the second terminal of the first constant voltage source V1 are both grounded. Of course, the internal components of the load unit 30 can also be changed according to different actual circuits, and are not limited here.

[0136] In one specific implementation, the second power transistor H2 includes an NMOS transistor; wherein, since the second terminal, i.e. the negative terminal, of the first constant voltage source V1 is connected to the gate of the second power transistor H2, the second power transistor H2 remains normally closed, the purpose of which is to prevent the first power transistor H1 from being broken down by high voltage.

[0137] The fully integrated driver chip architecture based on voltage slope detection provided in this embodiment of the invention has the following advantages:

[0138] 1. Low latency: The fully integrated driver chip architecture based on current slope detection integrates the existing off-chip FPGA and digital programmable driver chip-based driving circuits to form a fully integrated driver chip. It also integrates a detection circuit within the chip and adds an external feedback unit to provide feedback on the leakage inductance voltage of the first power transistor H1. This solves the latency problems caused by the low control frequency of the off-chip FPGA and the large scale of the internal digital circuits of the digital programmable driver chip. The control latency of the first power transistor H1 in the prior art is generally between 30ns and 80ns, while the fully integrated driver chip architecture based on voltage slope detection provided in this embodiment can reduce it to about 10ns.

[0139] 2. Low cost: Similar to low latency, the analog integration of existing off-chip FPGAs and digital programmable driver chips into a fully integrated driver chip not only reduces control latency but also reduces circuit size and saves circuit costs.

[0140] 3. The operating state of the GaN HEMT can be adaptively controlled. By setting an off-chip high-voltage capacitor, the voltage slope of the GaN HEMT source-drain voltage is fed back in real time. When the voltage slope of the GaN HEMT source-drain voltage changes significantly, it can be fed back to the integrated driving unit 20 to change the driving current applied to the gate of the GaN HEMT, thereby reducing the turn-on speed of the GaN HEMT.

[0141] This invention also provides an electronic device, including the fully integrated driver chip architecture based on current slope detection.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fully integrated driver chip architecture based on voltage slope detection, used to drive a first power transistor, characterized in that, The first end of the first power transistor is coupled to ground, and the second end of the first power transistor is connected to the power supply through a load unit. The architecture includes: Feedback capacitor; the first end of the feedback capacitor is coupled to the first end of the first power transistor; the feedback capacitor is used to provide feedback on the change in the voltage slope of the source-drain voltage of the first power transistor, and generate a displacement current based on the change result; wherein, the displacement current is used to characterize the change in peak current caused by the change in the voltage slope of the source-drain voltage during the turn-on process of the first power transistor. A control unit, used to output a control signal based on an input level; The integrated drive unit includes a three-stage turn-on drive branch and a turn-off drive branch; the three-stage turn-on drive branch includes a voltage slope detection circuit and a three-stage turn-on processing circuit; wherein: The voltage slope detection circuit is coupled to the second terminal of the feedback capacitor, and is used to receive the displacement current and output a first turn-on level signal according to the displacement current. The three-stage turn-on processing circuit is respectively coupled to the output terminal of the voltage slope detection circuit, the output terminal of the control unit, and the gate of the first power transistor; the three-stage turn-on processing circuit is used to receive the first turn-on level signal and the control signal, and to form a first drive current, a second drive current, and a third drive current to the gate of the first power transistor according to the first turn-on level signal and the control signal, wherein the first drive current, the second drive current, and the third drive current are used to sequentially control the turn-on of the first power transistor in different turn-on stages; The shutdown drive branch is coupled to the output terminal of the control unit and the gate of the first power transistor respectively; the shutdown drive branch is used to receive the control signal and output a constant fourth drive current to the gate of the first power transistor according to the control signal, and the fourth drive current is used to control the shutdown of the first power transistor. Furthermore, the three-stage turn-on drive branch and the turn-off drive branch are both integrated into the same chip; The voltage slope detection circuit includes a first MOSFET, a first current source, a first inverter, and a second inverter; The gate of the first MOS transistor is connected to its second terminal; its second terminal is connected to the second terminal of the first current source; wherein, the gate of the first MOS transistor also receives the displacement current; The input terminal of the first inverter is connected to the second terminal of the first MOS transistor; the input terminal of the second inverter is connected to the output terminal of the first inverter; the output terminal of the second inverter is used to output the first turn-on level signal. The voltage slope detection circuit also includes a first diode and a second diode. The forward terminal of the first diode is connected to the gate of the first MOS transistor, and its reverse terminal is connected to the source of the first MOS transistor. The forward terminal of the second diode is connected to the first terminal of the first current source, and its reverse terminal is connected to the forward terminal of the first diode.

2. The fully integrated driver chip architecture based on voltage slope detection according to claim 1, characterized in that, The three-stage activation processing circuit includes an activation logic control circuit and an activation three-stage push-pull circuit. The turn-on logic control circuit is coupled to the output terminal of the voltage slope detection circuit and the output terminal of the control unit. It is used to receive the first turn-on level signal and the control signal, and to perform digital operations on the control signal, the first turn-on level signal, and the control signal respectively, and then output the first turn-on control signal and the second turn-on control signal. The three-stage push-pull circuit is coupled to the output of the power-on logic control circuit and the gate of the first power transistor, respectively. It is used to receive the first power-on control signal and the second power-on control signal, and output the first drive current, the second drive current and the third drive current to the outside in sequence according to the first power-on control signal and the second power-on control signal.

3. The fully integrated driver chip architecture based on voltage slope detection according to claim 2, characterized in that, The shutdown drive branch includes a shutdown logic control circuit and a shutdown push-pull circuit. The shutdown logic control circuit is coupled to the output terminal of the control unit. It is used to receive the control signal, perform digital calculations on the control signal, and output the first shutdown control signal to the outside. The turn-off push-pull circuit is coupled to the output terminal of the turn-off logic control circuit and the gate of the first power transistor, respectively. It is used to receive the first turn-off control signal and output the fourth drive current according to the first turn-off control signal.

4. The fully integrated driver chip architecture based on voltage slope detection according to claim 3, characterized in that, The activation logic control circuit includes a third inverter, a fourth inverter, and a first AND gate; The input terminal of the third inverter is coupled to the output terminal of the control unit, and its output terminal is connected to the input terminal of the fourth inverter; the third inverter is used to invert the control signal. The output terminal of the fourth inverter serves as the output terminal of the turn-on logic control circuit, which is used to invert the inverted control signal again and output the second turn-on control signal. The first input terminal and the second input terminal of the first AND gate are respectively coupled to the output terminal of the second inverter and the output terminal of the control unit; the first AND gate is used to perform an AND operation on the first turn-on level signal and the control signal, and output the first turn-on control signal.

5. The fully integrated driver chip architecture based on voltage slope detection according to claim 4, characterized in that, The three-stage push-pull circuit includes a first-stage push-pull branch and a second-stage push-pull branch. The first-stage turn-on push-pull branch includes a first-stage push-pull circuit and a first turn-on MOS transistor; the input terminal of the first-stage push-pull circuit is coupled to the output terminal of the first AND gate, and its output terminal is coupled to the gate of the first turn-on MOS transistor. The second terminal of the first turn-on MOS transistor is coupled to the gate of the first power transistor; The first-stage push-pull circuit is used to receive the first turn-on control signal, and output the first turn-on signal to the gate of the first turn-on MOS transistor after push-pull processing. The first turn-on MOSFET is used to output a first current or not output current under the action of the first turn-on control signal after push-pull; The second-stage turn-on push-pull branch includes a second-stage push-pull circuit and a second turn-on MOSFET; The input terminal of the second-stage push-pull circuit is coupled to the output terminal of the fourth inverter, and its output terminal is coupled to the gate of the second turn-on MOS transistor. The second terminal of the second turn-on MOS transistor is coupled to the gate of the first power transistor; The second-stage push-pull circuit is used to receive the second turn-on control signal, and output the second turn-on control signal to the gate of the second turn-on MOS transistor after push-pull processing. The second turn-on MOSFET is used to output a second current under the action of the second turn-on control signal after push-pull operation; wherein: The first driving current is composed of the first current and the second current; the second driving current is composed of the second current; the third driving current is composed of the first current and the second current.

6. The fully integrated driver chip architecture based on voltage slope detection according to claim 5, characterized in that, The shutdown logic control circuit includes a fifth inverter.

7. The fully integrated driver chip architecture based on voltage slope detection according to claim 6, characterized in that, The turn-off push-pull circuit includes a third-stage push-pull circuit and a first turn-off MOS transistor; The input terminal of the third-stage push-pull circuit is coupled to the output terminal of the shutdown logic control circuit, and its input terminal is coupled to the gate of the first shutdown MOS transistor. The second terminal of the first turn-off MOS transistor is coupled to the gate of the first power transistor; The third-stage push-pull circuit is used to receive the first turn-off control signal, and output the first turn-off control signal to the gate of the first turn-off MOS transistor after push-pull operation; the first turn-off MOS transistor is used to output the fourth drive current under the action of the first turn-off control signal after push-pull operation.

8. The fully integrated driver chip architecture based on voltage slope detection according to claim 7, characterized in that, The first-stage push-pull circuit, the second-stage push-pull circuit, and the third-stage push-pull circuit are all composed of six inverters connected in series.

9. The fully integrated driver chip architecture based on voltage slope detection according to claim 8, characterized in that, Both the first turn-on MOSFET and the second turn-on MOSFET are PLDMOS transistors.

10. The fully integrated driver chip architecture based on voltage slope detection according to claim 9, characterized in that, The first turn-off MOS transistor is an NLDMOS transistor.

11. The fully integrated driver chip architecture based on voltage slope detection according to claim 1, characterized in that, The load unit includes a second power transistor, a load inductor, a load capacitor, and a first constant voltage source; The first terminal of the second power transistor is connected to the second terminal of the first power transistor and the second terminal of the load inductor, respectively. The second terminal of the second power transistor, the first terminal of the load inductor, the first terminal of the load capacitor, and the first terminal of the first constant voltage source are all connected to the power supply terminal; The second terminal of the load capacitor and the second terminal of the first constant voltage source are both grounded.

12. The fully integrated driver chip architecture based on voltage slope detection according to claim 11, characterized in that, The second power transistor includes an NMOS transistor.

13. The fully integrated driver chip architecture based on voltage slope detection according to any one of claims 1 to 11, characterized in that, The first power transistor is a gallium nitride single transistor.

14. The fully integrated driver chip architecture based on voltage slope detection according to claim 13, characterized in that, The control unit includes a PWM controller.

15. An electronic device, characterized in that, Includes the fully integrated driver chip architecture based on voltage slope detection as described in any one of claims 1 to 14.

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