Commutation method and system based on ANPC topology for reducing voltage stress

Abstract

The application provides a commutation method based on an ANPC topology for reducing voltage stress, comprising generating a driving signal; controlling the turn-on and turn-off of a switch tube by using the driving signal; in a positive half cycle, keeping S2 always on, keeping S3 and S4 always off, and switching S1, S5 and S6 in the process of the voltage at the neutral end O changing from zero level to positive level or from positive level to zero level; in a negative half cycle, keeping S3 always on, keeping S1 and S2 always off, and switching S4, S6 and S5 in the process of the voltage at the neutral end O changing from zero level to negative level or from negative level to zero level. The stable state of the system in the whole modulation cycle is divided into P and O+ in the positive half cycle, and N and O- in the negative half cycle, and in normal operation, P and O+ in the positive half cycle are switched to each other, O+ and O- at zero level are switched to each other, and O- and N in the negative half cycle are switched to each other, so that the system state switching is smoother, and in particular, the voltage stress risk borne by the inner tube is greatly reduced when O+ is switched to P and O- is switched to N.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and more particularly to a commutation method and system based on an ANPC topology for reducing voltage stress. Background Art

[0002] As the installed capacity of energy storage products continues to grow, individual modules are also trending towards higher power. Due to insufficient IGBT production capacity, the traditional three-level NPC (Neutral Point Clamped) topology faces IGBT module shortages. The ANPC topology replaces the NPC topology with three two-level modules, addressing the IGBT shortage.

[0003] Figure 1 The single-phase NPC topology diagram shows a long commutation path due to the uncontrollable nature of D5 and D6. For example, when the system operates in inverter mode (i.e., when u > 0 and i > 0), the system switches between paths S1, S2 and D5, S2, creating a short commutation path. When the system operates in rectification mode (i.e., when u > 0 and i < 0), the system switches between paths D2, D1 and S3, D6, creating a short commutation path. In particular, when switching from path S3, D6 to path D2, D1, S3 experiences significant turn-off stress, posing a significant risk.

[0004] The ANPC (Active Neutral Point Clamped) topology is based on the NPC (Neutral point clamped) topology, replacing the original clamping diodes with two power switching devices with anti-parallel diodes. Due to the two additional degrees of freedom, the commutation control becomes more complicated. The existing technologies are all slightly modified based on the NPC topology commutation control, that is, when S2 and S3 are turned on at the same time, S5 and S6 are turned on, and when S2 and S3 are turned off at the same time, S5 and S6 are turned off. Therefore, although this commutation method is simple and can be slightly modified based on the original NPC commutation control program, it cannot maximize the advantages of the ANPC topology. There are many long commutation paths and the IGBT voltage stress is large.

[0005] Based on this, a new solution is needed. Summary of the Invention

[0006] According to one aspect of the present invention, a commutation method based on an ANPC topology for reducing voltage stress is provided. The ANPC converter includes six switching transistors S1 to S6, wherein each switching transistor is anti-parallel connected to a diode, the first switching transistor S1 and the fourth switching transistor S4 are respectively connected to the positive terminal P and the negative terminal N of a DC network, the connection point between the fifth switching transistor S5 and the sixth switching transistor S6 is connected to the neutral terminal O of the DC network, and the connection point between the second switching transistor S2 and the third switching transistor S3 is connected to the AC network. The modulation method includes:

[0007] generating a driving signal;

[0008] The driving signal is used to control the turn-off of each switch tube, wherein:

[0009] In the positive half cycle, the second switch tube S2 is kept normally on, and the third switch tube S3 and the fourth switch tube S4 are kept normally off. When the voltage at the neutral terminal O changes from zero level to positive level, the first switch tube S1 is turned on, the fifth switch tube S5 is turned off before the first switch tube S1 is turned on, and the sixth switch tube S6 is turned off before the fifth switch tube S5 is turned off and turned on after the first switch tube S1 is fully turned on. When the voltage at the neutral terminal O changes from positive level to zero level, the first switch tube S1 is turned off, and the fifth switch tube S5 is turned on after the first switch tube S1 is turned off.

[0010] In the negative half cycle, the third switch tube S3 is kept normally on, and the first switch tube S1 and the second switch tube S2 are normally off. When the voltage at the neutral terminal O changes from a zero level to a negative level, the fourth switch tube S4 is turned on, the sixth switch tube S6 is turned off before the fourth switch tube S4 is turned on, and the fifth switch tube S5 is turned off before the sixth switch tube S6 is turned off and turned on after the fourth switch tube S4 is completely turned on. When the voltage at the neutral terminal O changes from a negative level to a zero level, the fourth switch tube S4 is turned off, and the sixth switch tube S6 is turned on after the fourth switch tube S4 is turned off.

[0011] In the commutation method based on ANPC topology for reducing voltage stress provided by the present invention, the modulation method further includes:

[0012] When switching from the positive half cycle to the negative half cycle through the zero level, the third switch tube S3 is turned on, and the second switch tube S2 is turned off before the third switch tube S3 is turned on;

[0013] When switching from the negative half cycle to the positive half cycle through the zero level, the second switch tube S2 is turned on, and the third switch tube S3 is turned off before the second switch tube S2 is turned on.

[0014] In the commutation method based on ANPC topology for reducing voltage stress provided by the present invention, when the high-voltage side MOSFET current is less than a preset threshold, the comparison result signal is at a high level.

[0015] In the commutation method based on the ANPC topology for reducing voltage stress provided by the present invention, the step of generating the drive signal includes:

[0016] DSP outputs 3-way PWM signals to CPLD;

[0017] The CPLD outputs 18-channel PWM control signals to the driver board;

[0018] The driver board outputs 18 drive signals to control the shutdown of each switch tube.

[0019] In the commutation method based on ANPC topology for reducing voltage stress provided by the present invention, the step of outputting 18 PWM control signals from the CPLD to the driver board includes:

[0020] The CPLD contains three groups of modules, each of which expands the 1-channel PWM signal input from the DSP into 6-channel PWM temporary signals with dead zones;

[0021] After timing control, 6-channel PWM formal signals are generated;

[0022] Send the 6-way PWM official signal to the driver board to generate 6-way switch tube drive signals.

[0023] In the commutation method based on ANPC topology for reducing voltage stress provided by the present invention, the timing control includes a power-on timing and a power-off timing, wherein:

[0024] In the power-on sequence, the fifth switch S5 and the second switch S6 are turned on at the same time, then the second switch S2 or the third switch S3 is turned on, and finally the first switch S1 or the fourth switch S4 is turned on.

[0025] In the shutdown sequence, the first switch S1 and the fourth switch S4 are turned off simultaneously first, then the second switch S2 and the third switch S3 are turned off simultaneously, and finally the fifth switch S5 and the second switch S6 are turned off simultaneously.

[0026] According to another aspect of the present invention, a commutation system based on an ANPC topology for reducing voltage stress is further provided. The ANPC converter includes six switching transistors S1 to S6, wherein each switching transistor is anti-parallel connected to a diode, the first switching transistor S1 and the fourth switching transistor S4 are respectively connected to the positive terminal P and the negative terminal N of the DC network, the connection point between the fifth switching transistor S5 and the sixth switching transistor S6 is connected to the neutral terminal O of the DC network, and the connection point between the second switching transistor S2 and the third switching transistor S3 is connected to the AC network. The modulation system includes:

[0027] A driving signal generating module, used for generating a driving signal;

[0028] The modulation module is used to control the on and off of each switch tube using the driving signal, wherein:

[0029] In the positive half cycle, the second switch tube S2 is kept normally on, and the third switch tube S3 and the fourth switch tube S4 are kept normally off. When the voltage at the neutral terminal O changes from zero level to positive level, the first switch tube S1 is turned on, the fifth switch tube S5 is turned off before the first switch tube S1 is turned on, and the sixth switch tube S6 is turned off before the fifth switch tube S5 is turned off and turned on after the first switch tube S1 is fully turned on. When the voltage at the neutral terminal O changes from positive level to zero level, the first switch tube S1 is turned off, and the fifth switch tube S5 is turned on after the first switch tube S1 is turned off.

[0030] In the negative half cycle, the third switch tube S3 is kept normally on, and the first switch tube S1 and the second switch tube S2 are normally off. When the voltage at the neutral terminal O changes from a zero level to a negative level, the fourth switch tube S4 is turned on, the sixth switch tube S6 is turned off before the fourth switch tube S4 is turned on, and the fifth switch tube S5 is turned off before the sixth switch tube S6 is turned off and turned on after the fourth switch tube S4 is completely turned on. When the voltage at the neutral terminal O changes from a negative level to a zero level, the fourth switch tube S4 is turned off, and the sixth switch tube S6 is turned on after the fourth switch tube S4 is turned off.

[0031] In the ANPC topology-based commutation system for reducing voltage stress provided by the present invention, the modulation module is further used for:

[0032] When switching from the positive half cycle to the negative half cycle through the zero level, the third switch tube S3 is turned on, and the second switch tube S2 is turned off before the third switch tube S3 is turned on;

[0033] When switching from the negative half cycle to the positive half cycle through the zero level, the second switch tube S2 is turned on, and the third switch tube S3 is turned off before the second switch tube S2 is turned on.

[0034] In the ANPC topology-based commutation system for reducing voltage stress provided by the present invention, the drive signal generation module includes a DSP, a CPLD, and a driver board, wherein the DSP outputs three PWM signals to the CPLD; the CPLD outputs 18 PWM control signals to the driver board; and the driver board outputs 18 drive signals to control the on and off of each switch tube.

[0035] In the ANPC topology-based commutation system for reducing voltage stress provided by the present invention, the CPLD includes three groups of modules. Each group of modules expands one PWM signal input by the DSP into six temporary PWM signals with dead zones; generates six official PWM signals through timing control; and sends the six official PWM signals to a driver board to generate six switch tube drive signals.

[0036] In the ANPC topology-based commutation system for reducing voltage stress provided by the present invention, the second switch tube S2 and the third switch tube S3 are power frequency switch tubes.

[0037] The implementation of the ANPC topology-based commutation method for reducing voltage stress of the present invention has the following beneficial effects: the ANPC topology-based commutation method for reducing voltage stress provided by the present invention divides the state at zero level into two types, and divides the stable state of the system in the entire modulation cycle into P and O+ in the positive half cycle, and N and O- in the negative half cycle. In this way, during normal operation, in the positive half cycle, P and O+ switch with each other; at zero level, O+ and O- switch with each other; in the negative half cycle, O- and N switch with each other, making the system state switching smoother, especially when O+ switches to P and O- switches to N, and the voltage stress risk borne by the inner tube is greatly reduced; at the same time, by changing part of the long commutation to short commutation, the control logic is simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present invention. Those skilled in the art can also derive other drawings based on the provided drawings without inventive work.

[0039] Figure 1 Shown is the existing single-phase NPC topology diagram;

[0040] Figure 2 A single-phase circuit topology diagram of an ANPC converter in an embodiment of a commutation method based on an ANPC topology for reducing voltage stress provided by the present invention;

[0041] Figure 3 The figure shows the dead zone control logic block diagram of CPLD;

[0042] Figure 4 Shown are the power-on sequence control and power-off sequence control;

[0043] Figure 5 This is an enlarged waveform diagram of a commutation method based on ANPC topology for reducing voltage stress in the positive half cycle provided by the present invention;

[0044] Figure 6 This is an enlarged waveform diagram of the negative half cycle of a commutation method based on ANPC topology for reducing voltage stress provided by the present invention;

[0045] Figure 7 This is an enlarged waveform diagram of the full cycle of a commutation method based on ANPC topology for reducing voltage stress provided by the present invention. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0047] The embodiment provides a commutation method based on an ANPC topology for reducing voltage stress, wherein, as shown in the figure, Figure 2 The single-phase topology of the ANPC converter includes six switching tubes S1-S6, each of which is anti-parallel to a diode, the first switching tube S1 and the fourth switching tube S4 are connected to the positive terminal P and the negative terminal N of the DC network respectively, the connection point of the fifth switching tube S5 and the sixth switching tube S6 is connected to the neutral terminal O of the DC network, and the connection point of the second switching tube S2 and the third switching tube S3 is connected to the AC network; and wherein the first switching tube S1 and the fifth switching tube S5 are packaged in the same switching tube packaging module, the second switching tube S2 and the third switching tube S3 are packaged in the same switching tube packaging module, and the fourth switching tube S4 and the sixth switching tube S6 are packaged in the same switching tube packaging module; the second switching tube S2 and the third switching tube S3 select a power frequency IGBT module, the first switching tube S1 and the fifth switching tube S5 select a high-frequency IGBT module, and the fourth switching tube S4 and the sixth switching tube S6 select a high-frequency IGBT module, so that the hardware cost can be maximized.

[0048] The embodiment of the present application discloses a modulation method suitable for Figure 2 The modulation method of the ANPC converter includes:

[0049] Step S1: generating a driving signal;

[0050] Specifically, in an embodiment of the present application, three PWM signals are output by the DSP to the CPLD; then, eighteen PWM control signals are output by the CPLD to the driving board; finally, eighteen driving signals are output by the driving board to control the turn-off of each switching tube.

[0051] Specifically, in the embodiment, the core commutation control is realized by the CPLD, mainly including two parts: one is to realize dead-time control, and the other is to realize timing control. Figure 3For dead zone control logic block diagram, in CPLD there are three groups, corresponding to three-phase respectively. Each group will expand the DSP input 1 PWM signal to 6 PWM temporary signal with dead zone, respectively Pwm1Temp, Pwm2Temp, Pwm3Temp, Pwm4Temp, Pwm5Temp, Pwm6Temp. 6 PWM temporary signal, through timing control, generate 6 PWM formal signal PWM1, PWM2, PWM3, PWM4, PWM5, PWM6. 6 PWM formal signal is sent to the drive board to generate 6 switch tube drive signal. Timing control is divided into start-up timing control and shutdown timing control, as shown in Figure 4 The fifth switch tube S5 and the second switch tube S6 are turned on at the same time, then the second switch tube S2 or the third switch tube S3 is turned on, and finally the first switch tube S1 or the fourth switch tube S4 is turned on. In the shutdown timing, the first switch tube S1 and the fourth switch tube S4 are turned off at the same time, then the second switch tube S2 and the third switch tube S3 are turned off at the same time, and finally the fifth switch tube S5 and the second switch tube S6 are turned off at the same time. Therefore, the step of outputting 18 PWM control signals from the CPLD to the drive board comprises:

[0052] The CPLD comprises three groups of modules, each group of modules expands the 1 PWM signal input by the DSP into 6 PWM temporary signals with dead zone, generates 6 PWM formal signals through timing control, and sends the 6 PWM formal signals to the drive board to generate 6 switch tube drive signals.

[0053] In the present application, since the commutation control is realized by using DSP+CPLD together, only 3 PWM signals need to be input to expand 18 drive signals for driving.

[0054] In step S2, the drive signals are used to control the turn-off of each switch tube. In the positive half cycle, the second switch tube S2 is kept on, the third switch tube S3 and the fourth switch tube S4 are kept off, and the first switch tube S1, the fifth switch tube S5 and the sixth switch tube S6 are switched in the process that the voltage at the neutral end O changes from zero level to positive level or from positive level to zero level. In the negative half cycle, the third switch tube S3 is kept on, the first switch tube S1 and the second switch tube S2 are kept off, and the fourth switch tube S4, the sixth switch tube S6 and the fifth switch tube S5 are switched in the process that the voltage at the neutral end O changes from zero level to negative level or from negative level to zero level.

[0055] Specifically, in an embodiment of the present application, four stable states (P, O+, O-, N) are defined as shown in Table 1.

[0056] Table 1 Four stable states

[0057] State S1 S2 S3 S4 S5 S6 P 1 1 0 0 0 1 O+ 0 1 0 0 1 1 O- 0 0 1 0 1 1 N 0 0 1 1 1 0

[0058] As shown in Table 1, during the positive half-cycle (i.e., state P and state O+), the second switch S2 is kept normally on, the third and fourth switches S3 and S4 are kept normally off, and the first and fifth switches S1 and S5 complement each other at high frequency. In actual applications, due to differences in switch drive circuits and semiconductor devices themselves, the complementary switches may fail to turn off in time with the other switch turning on due to inconsistent on / off switching speeds. Therefore, in this embodiment, for the complementary first and fifth switches S1 and S5, when switching from state O+ to state P, the fifth switch S5 is turned off before the first switch S1 turns on. When switching from state P to state O+, the fifth switch S5 is turned on after the first switch S1 turns off. By inserting a dead time between the first and fifth switches S1 and S5, short circuits can be avoided. The length of the dead time is set according to the switching characteristics of the switches. Furthermore, when switching from state O+ to state P, in order to reduce the voltage stress risk borne by the inner tube, the sixth switch tube S6 is turned off before the fifth switch tube S5 is turned off and turned on after the first switch tube S1 is fully turned on. The turn-off time of the sixth switch tube S6 is set according to the switching characteristics of each switch tube. Therefore, if Figure 3 As shown, during the process of the voltage at the neutral terminal O transitioning from a zero level to a positive level (i.e., transitioning from state O+ to state P), the first switch tube S1 is turned on, the fifth switch tube S5 is turned off before the first switch tube S1 is turned on, and the sixth switch tube S6 is turned off before the fifth switch tube S5 is turned off and is turned on after the first switch tube S1 is completely turned on; during the process of the voltage at the neutral terminal O transitioning from a positive level to a zero level (i.e., transitioning from state P to state O+), the first switch tube S1 is turned off, and the fifth switch tube S5 is turned on after the first switch tube S1 is turned off.

[0059] As shown in Table 1, during the negative half-cycle (i.e., state N and state O-), the third switch S3 is kept normally on, the first switch S1 and the second switch S2 are normally off, and the fourth switch S4 and the sixth switch S6 are high-frequency complementary. In actual applications, due to differences in switch drive circuits and semiconductor devices themselves, the complementary switching transistors may fail to turn off in time with the other switch turning on due to inconsistent on / off switching speeds. Therefore, in this embodiment, for the complementary switching transistors S4 and S6, when switching from state O- to state N, the sixth switch S6 is turned off before the fourth switch S4 turns on. When switching from state N to state O-, the sixth switch S6 is turned on after the fourth switch S4 turns off. By inserting a dead time between the fourth switch S4 and the sixth switch S6, short circuits can be avoided. The length of the dead time is set according to the switching characteristics of the switches. Furthermore, when switching from state O- to state N, in order to reduce the voltage stress risk borne by the inner tube, the fifth switch tube S5 is turned off before the sixth switch tube S6 is turned off and turned on after the fourth switch tube S4 is fully turned on. The turn-off time of the fifth switch tube S5 is set according to the switching characteristics of each switch tube. Therefore, if Figure 4 As shown, when the voltage at the neutral terminal O changes from a zero level to a negative level, the fourth switch tube S4 is turned on, the sixth switch tube S6 is turned off before the fourth switch tube S4 is turned on, and the fifth switch tube S5 is turned off before the sixth switch tube S6 is turned off and is turned on after the fourth switch tube S4 is completely turned on; when the voltage at the neutral terminal O changes from a negative level to a zero level, the fourth switch tube S4 is turned off, and the sixth switch tube S6 is turned on after the fourth switch tube S4 is turned off.

[0060] Furthermore, in conventional control methods, when the system operates in a zero-level state, the second switch S2, the third switch S3, the fifth switch S5, and the sixth switch S6 are all turned on. In the present application, as shown in Table 1, the zero-level state is divided into two types: one is state O+, in which the second switch S2, the fifth switch S5, and the sixth switch S6 are all turned on, and the third switch S3 is turned off; the other is state O-, in which the third switch S3, the fifth switch S5, and the sixth switch S6 are all turned on, and the second switch S2 is turned off. In actual applications, due to differences in switch tube drive circuits and semiconductor devices themselves, the complementary switched-on switches may fail to turn off in time when the other switch tube turns on due to inconsistent on / off switching speeds. Therefore, in this embodiment, for the second switch tube S2 and the third switch tube S3 that are complementary switched-on in the zero state, when switching from state O- to state O+, the third switch tube S3 is turned off before the second switch tube S2 turns on, and when switching from state O+ to state O-, the second switch tube S2 is turned off before the third switch tube S3 turns on. By inserting a dead time between the second switch tube S2 and the third switch tube S3, a short circuit can be avoided, wherein the length of the dead time is set according to the switching characteristics of the switch tube. Therefore, if Figure 5 As shown, when switching from the positive half cycle to the negative half cycle through the zero level, the third switch tube S3 is turned on, and the second switch tube S2 is turned off before the third switch tube S3 is turned on; when switching from the negative half cycle to the positive half cycle through the zero level, the second switch tube S2 is turned on, and the third switch tube S3 is turned off before the second switch tube S2 is turned on.

[0061] The present application divides the state at zero level into two types, and divides the stable state of the system in the entire modulation cycle into P and O+ in the positive half cycle, and N and O- in the negative half cycle. In this way, during normal operation, in the positive half cycle, P and O+ switch with each other; at zero level, O+ and O- switch with each other; in the negative half cycle, O- and N switch with each other, making the system state switching smoother, especially when O+ switches to P and O- switches to N, the voltage stress risk borne by the inner tube is greatly reduced; at the same time, by changing part of the long commutation to short commutation, the control logic is simple and easy to implement.

[0062] Accordingly, the present invention also provides a method for Figure 2 The modulation system of the ANPC converter shown in FIG. 1 includes: a drive signal generation module for generating a drive signal; a modulation module for controlling the turn-off of each switch tube using the drive signal, wherein:

[0063] In the positive half cycle, the second switch tube S2 is kept normally on, and the third switch tube S3 and the fourth switch tube S4 are kept normally off. When the voltage at the neutral terminal O changes from zero level to positive level, the first switch tube S1 is turned on, the fifth switch tube S5 is turned off before the first switch tube S1 is turned on, and the sixth switch tube S6 is turned off before the fifth switch tube S5 is turned off and turned on after the first switch tube S1 is fully turned on. When the voltage at the neutral terminal O changes from positive level to zero level, the first switch tube S1 is turned off, and the fifth switch tube S5 is turned on after the first switch tube S1 is turned off.

[0064] In the negative half cycle, the third switch S3 is kept normally on, the first switch S1 and the second switch S2 are normally off, and when the voltage at the neutral terminal O changes from zero level to a negative level, the fourth switch S4 is turned on, the sixth switch S6 is turned off before the fourth switch S4 is turned on, and the fifth switch S5 is turned off before the sixth switch S6 is turned off and turned on after the fourth switch S4 is fully turned on; when the voltage at the neutral terminal O changes from a negative level to a zero level, the fourth switch S4 is turned off, and the sixth switch S6 is turned on after the fourth switch S4 is turned off;

[0065] When switching from the positive half cycle to the negative half cycle through the zero level, the third switch tube S3 is turned on, and the second switch tube S2 is turned off before the third switch tube S3 is turned on; when switching from the negative half cycle to the positive half cycle through the zero level, the second switch tube S2 is turned on, and the third switch tube S3 is turned off before the second switch tube S2 is turned on.

[0066] Furthermore, in one embodiment of the present invention, the drive signal generation module includes a DSP, a CPLD, and a driver board. The DSP outputs three PWM signals to the CPLD, which then outputs 18 PWM control signals to the driver board. The driver board then outputs 18 drive signals to control the on / off switching of each switch. The CPLD includes three modules, each of which expands the single PWM signal input from the DSP into six temporary PWM signals with dead zones. These signals are then processed through timing control to generate six official PWM signals. These signals are then fed into the driver board to generate six drive signals for the switch.

[0067] Certain specific embodiments of the present invention have been described above. Note that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. For example, unless the context clearly indicates otherwise, the singular forms "a / an," and "the" as used herein are intended to include the plural forms as well. It will also be understood that the word "comprising," when used in this specification, specifies the presence of stated features, components, steps, operations, units, and / or parts without excluding the presence or addition of one or more other features, components, steps, operations, units, parts, and / or combinations thereof.

[0068] Although several embodiments of the present invention have been described above with reference to the accompanying drawings, it should be understood that the invention is not limited to the specific embodiments disclosed. The present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A commutation method based on an ANPC topology for reducing voltage stress, wherein the ANPC topology includes three phases, each phase having six switches S1 to S6, wherein: Each switch tube is connected in anti-parallel with a diode. The first switch tube S1 and the fourth switch tube S4 are respectively connected to the positive terminal P and the negative terminal N of the DC network. The connection point of the fifth switch tube S5 and the sixth switch tube S6 is connected to the neutral terminal O of the DC network. The connection point of the second switch tube S2 and the third switch tube S3 is connected to the AC network. The commutation method includes: generating a driving signal; The driving signal is used to control the on and off of each switch tube, wherein: In the positive half cycle, the second switch tube S2 is kept normally on, and the third switch tube S3 and the fourth switch tube S4 are kept normally off. When the voltage at the neutral terminal O changes from zero level to positive level, the first switch tube S1 is turned on, the fifth switch tube S5 is turned off before the first switch tube S1 is turned on, and the sixth switch tube S6 is turned off before the fifth switch tube S5 is turned off and turned on after the first switch tube S1 is fully turned on. When the voltage at the neutral terminal O changes from positive level to zero level, the first switch tube S1 is turned off, and the fifth switch tube S5 is turned on after the first switch tube S1 is turned off. In the negative half cycle, the third switch tube S3 is kept normally on, and the first switch tube S1 and the second switch tube S2 are normally off. When the voltage at the neutral terminal O changes from a zero level to a negative level, the fourth switch tube S4 is turned on, the sixth switch tube S6 is turned off before the fourth switch tube S4 is turned on, and the fifth switch tube S5 is turned off before the sixth switch tube S6 is turned off and turned on after the fourth switch tube S4 is completely turned on. When the voltage at the neutral terminal O changes from a negative level to a zero level, the fourth switch tube S4 is turned off, and the sixth switch tube S6 is turned on after the fourth switch tube S4 is turned off.

2. The commutation method based on ANPC topology for reducing voltage stress according to claim 1, characterized in that: The commutation method further includes: When switching from the positive half cycle to the negative half cycle through the zero level, the third switch tube S3 is turned on, and the second switch tube S2 is turned off before the third switch tube S3 is turned on; When switching from the negative half cycle to the positive half cycle through the zero level, the second switch tube S2 is turned on, and the third switch tube S3 is turned off before the second switch tube S2 is turned on.

3. The commutation method based on ANPC topology for reducing voltage stress according to claim 1, characterized in that: The steps for generating the drive signal include: DSP outputs 3-way PWM signals to CPLD; The CPLD outputs 18-channel PWM control signals to the driver board; The driver board outputs 18 drive signals to control the shutdown of each switch tube.

4. The commutation method based on ANPC topology for reducing voltage stress according to claim 3, characterized in that: The steps for the CPLD to output 18 PWM control signals to the driver board include: The CPLD contains three groups of modules, each of which expands the 1-channel PWM signal input from the DSP into 6-channel PWM temporary signals with dead zones; After timing control, 6-channel PWM formal signals are generated; Send the 6-way PWM official signal to the driver board to generate 6-way switch tube drive signals.

5. The commutation method based on ANPC topology for reducing voltage stress according to claim 4, characterized in that: The timing control includes power-on timing and power-off timing, wherein: In the power-on sequence, the fifth switch S5 and the second switch S6 are turned on at the same time, then the second switch S2 or the third switch S3 is turned on, and finally the first switch S1 or the fourth switch S4 is turned on. In the shutdown sequence, the first switch S1 and the fourth switch S4 are turned off simultaneously first, then the second switch S2 and the third switch S3 are turned off simultaneously, and finally the fifth switch S5 and the second switch S6 are turned off simultaneously.

6. A commutation system based on an ANPC topology for reducing voltage stress, wherein the ANPC topology comprises three phases, each phase having six switches S1 to S6, wherein: Each switch tube is connected in anti-parallel with a diode. The first switch tube S1 and the fourth switch tube S4 are respectively connected to the positive terminal P and the negative terminal N of the DC network. The connection point of the fifth switch tube S5 and the sixth switch tube S6 is connected to the neutral terminal O of the DC network. The connection point of the second switch tube S2 and the third switch tube S3 is connected to the AC network. The commutation system includes: A driving signal generating module, used for generating a driving signal; The modulation module is used to control the on and off of each switch tube using the driving signal, wherein: In the positive half cycle, the second switch tube S2 is kept normally on, and the third switch tube S3 and the fourth switch tube S4 are kept normally off. When the voltage at the neutral terminal O changes from zero level to positive level, the first switch tube S1 is turned on, the fifth switch tube S5 is turned off before the first switch tube S1 is turned on, and the sixth switch tube S6 is turned off before the fifth switch tube S5 is turned off and turned on after the first switch tube S1 is fully turned on. When the voltage at the neutral terminal O changes from positive level to zero level, the first switch tube S1 is turned off, and the fifth switch tube S5 is turned on after the first switch tube S1 is turned off. In the negative half cycle, the third switch tube S3 is kept normally on, and the first switch tube S1 and the second switch tube S2 are normally off. When the voltage at the neutral terminal O changes from a zero level to a negative level, the fourth switch tube S4 is turned on, the sixth switch tube S6 is turned off before the fourth switch tube S4 is turned on, and the fifth switch tube S5 is turned off before the sixth switch tube S6 is turned off and turned on after the fourth switch tube S4 is completely turned on. When the voltage at the neutral terminal O changes from a negative level to a zero level, the fourth switch tube S4 is turned off, and the sixth switch tube S6 is turned on after the fourth switch tube S4 is turned off.

7. The ANPC topology-based commutation system for reducing voltage stress according to claim 6, characterized in that: The modulation module is further configured to: When switching from the positive half cycle to the negative half cycle through the zero level, the third switch tube S3 is turned on, and the second switch tube S2 is turned off before the third switch tube S3 is turned on; When switching from the negative half cycle to the positive half cycle through the zero level, the second switch tube S2 is turned on, and the third switch tube S3 is turned off before the second switch tube S2 is turned on.

8. The ANPC topology-based commutation system for reducing voltage stress according to claim 6, characterized in that: The driving signal generation module includes a DSP, a CPLD and a driving board, wherein the DSP outputs three PWM signals to the CPLD; the CPLD outputs 18 PWM control signals to the driving board; and the driving board outputs 18 driving signals to control the shutdown of each switch tube.

9. The ANPC topology-based commutation system for reducing voltage stress according to claim 8, characterized in that: Each group of CPLD expands one PWM signal input from the DSP into six temporary PWM signals with dead zones, and after timing control, generates the six temporary PWM signals into PWM control signals that are sent to the driver board.

10. The ANPC topology-based commutation system for reducing voltage stress according to claim 6, characterized in that: The second switch tube S2 and the third switch tube S3 are power frequency switch tubes.

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