Low power rc relaxation oscillator

Abstract

The application belongs to the technical field of electronic circuit, and particularly relates to a low-power RC relaxation oscillator. The low-power RC relaxation oscillator comprises a self-bias current source, a charge-discharge circuit, a positive threshold hysteresis comparator and a two-stage current-limiting inverter. The self-bias current source generates a current irrelevant to a power supply voltage. The charge-discharge circuit mirrors the current of the self-bias current source, is controlled by output signals QA and QB, and charges and discharges a capacitor. The voltages at both ends of the capacitor are respectively output voltages of the positive threshold hysteresis comparator. The output signal QA controls the capacitor during the charging and discharging process of the capacitor, and the number of input pairs is changed to change the flip threshold. The two-stage current-limiting inverter generates the output signals QA and QB, and limits the average current consumed by a direct path of the inverter during the charging and discharging process of the load capacitor through the current mirrored from the self-bias current source. The low-power RC relaxation oscillator has an output frequency of 30 KHz, a duty cycle of 50%, an average power consumption of 149 nA, and a frequency expression only related to resistance and capacitance.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic circuits, and particularly relates to a low-power consumption RC relaxation oscillator. BACKGROUND

[0002] With the continuous progress of semiconductor process level, various systems develop from discrete devices to single-chip integration, and the demand for on-chip integrable clock source is more and more urgent. Therefore, compared with external clock sources, oscillators as on-chip clock sources are favored by designers. At present, there are mainly three kinds of oscillators that can be integrated on-chip: LC oscillators, ring oscillators and RC relaxation oscillators. LC oscillators are mainly used in radio frequency circuits, and the working frequency is in the GHz level, and the phase noise performance is the best, but it needs to use on-chip inductors, which will greatly increase the area of the chip; the ring oscillator does not need to use passive devices, and the area is the smallest, and the working frequency is determined by the number of ring oscillators and the single-stage delay time, and is generally in the MHz level, but under the CMOS technology, the transistor delay is very sensitive to process, power voltage and temperature (PVT) and other factors, which greatly limits the working frequency accuracy of the ring oscillator. For the working frequency of KHz level, the industry generally selects RC relaxation oscillator, and an excellent circuit structure theoretically determines the working frequency only by RC.

[0003] However, the traditional RC relaxation oscillator structure needs two comparators and two capacitors to realize the oscillation of the circuit, and cannot meet the low-power consumption demand, and the layout area is large. SUMMARY

[0004] In view of the problems of the traditional RC relaxation oscillator in power consumption and layout area, the application provides a low-power consumption RC relaxation oscillator applied to an on-chip SOC system.

[0005] The technical scheme of the application is as follows:

[0006] A low-power consumption RC relaxation oscillator comprises a self-bias current source, a charging and discharging circuit, a positive threshold hysteresis comparator and a two-stage current-limiting inverter.

[0007] The self-bias current source comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3 and a first resistor R1.

[0008] The first PMOS tube MP1 gate, the first PMOS tube MP1 drain, the second PMOS tube MP2 gate, the third PMOS tube MP3 gate, the third PMOS tube MP3 source are commonly connected to the first NMOS tube MN1 gate, the first PMOS tube MP1 source, the second PMOS tube MP2 source, the third PMOS tube MP3 source, the fourth PMOS tube MP4 source are commonly connected to the power supply AVDD, the second PMOS tube MP2 drain, the fifth PMOS tube MP5 drain, the third NMOS tube MN3 gate, the third NMOS tube MN3 drain are commonly connected to the second NMOS tube MN2 gate, the third PMOS tube MP3 drain, the first NMOS tube MN1 source, the first NMOS tube MN1 drain, the third NMOS tube MN3 source, one end of the first resistor R1 are commonly connected to the reference ground AGND, the fourth PMOS tube MP4 gate, the fourth PMOS tube MP4 drain, the fifth PMOS tube MP5 gate are commonly connected to the second NMOS tube MN2 drain, the second NMOS tube source is connected to the other end of the first resistor R1. The gate voltage of the fourth PMOS tube MP4 is named as voltage Vbp, and the gate voltage of the third NMOS tube MN3 is named as voltage Vbn.

[0009] The charge and discharge circuit comprises a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a second resistor R2, a first capacitor C1 and a second capacitor C2.

[0010] The sixth PMOS tube MP6 gate is connected to the voltage Vbp, the source is connected to the power supply AVDD, and the drain is connected to the seventh PMOS tube MP7 source and the eighth PMOS tube MP8 source. The seventh PMOS tube MP7 gate is connected to the signal QB, the drain is connected to the fourth NMOS tube MN4 drain and one end of the first capacitor C1. The eighth PMOS tube MP8 gate is connected to the signal QA, the drain is connected to one end of the second resistor R2, the other end of the first capacitor C1 and one end of the second capacitor C2. The fourth NMOS tube MN4 gate is connected to the signal QB, the source is connected to the fifth NMOS tube MN5 drain. The fifth NMOS tube MN5 gate is connected to the voltage Vbn, the source is connected to the reference ground AGND. The sixth NMOS tube MN6 gate and the sixth NMOS tube MN6 drain are connected to the other end of the second resistor R2, and the source is commonly connected to the other end of the second capacitor C2 to the reference ground AGND. The voltage at one end of the first capacitor C1 connected to the seventh PMOS tube MP7 drain is named as Vn, and the voltage at the other end is named as Vp.

[0011] The positive threshold hysteresis comparator circuit comprises a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11 and a twelfth NMOS transistor MN12.

[0012] The source of the ninth PMOS transistor MP9, the source of the tenth PMOS transistor MP10 and the source of the eleventh PMOS transistor MP11 are commonly connected to a power supply AVDD, the gate of the ninth PMOS transistor MP9, the gate of the tenth PMOS transistor MP10 and the drain of the ninth PMOS transistor MP9 are commonly connected to the drain of the eighth NMOS transistor MN8, the drain of the tenth PMOS transistor MP10, the gate of the eleventh PMOS transistor MP11 and the drain of the eleventh NMOS transistor MN11 are commonly connected to the drain of the ninth NMOS transistor MN9, the drain of the eleventh PMOS transistor MP11 is connected to the drain of the twelfth NMOS transistor MN12, the gate of the eighth NMOS transistor MN8 is connected to a voltage Vn, the source of the eighth NMOS transistor MN8, the source of the ninth NMOS transistor MN9 and the source of the tenth NMOS transistor MN10 are commonly connected to the drain of the seventh NMOS transistor MN7, the gate of the ninth NMOS transistor MN9 and the gate of the tenth NMOS transistor MN10 are commonly connected to a voltage Vp, the drain of the tenth NMOS transistor MN10 is connected to the source of the eleventh NMOS transistor MN11, the gate of the eleventh NMOS transistor MN11 is connected to a signal QA, the gate of the seventh NMOS transistor MN7 and the gate of the twelfth NMOS transistor MN12 are commonly connected to a voltage Vbn, the source of the seventh NMOS transistor MN7 and the source of the twelfth NMOS transistor MN12 are commonly connected to a reference ground AGND. The voltage at the drain of the tenth NMOS transistor MN10 is named as V1, and the voltage at the drain of the eleventh PMOS transistor MP11 is named as V2.

[0013] The two-stage current-limiting inverter comprises a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first inverter INV1 and a second inverter INV2.

[0014] The gate of the twelfth PMOS transistor MP12 and the gate of the thirteenth PMOS transistor MP13 are commonly connected to a voltage Vbp, the source of the twelfth PMOS transistor MP12 and the source of the thirteenth PMOS transistor MP13 are commonly connected to a power supply AVDD, the drain of the twelfth PMOS transistor MP12 is connected to a V DD of the first inverter INV1, the drain of the thirteenth PMOS transistor MP13 is connected to a V DDThe gate of the thirteenth NMOS transistor MN13 and the gate of the fourteenth NMOS transistor MN14 are connected to a voltage Vbn, the source of the thirteenth NMOS transistor MN13 and the source of the fourteenth NMOS transistor MN14 are connected to a reference ground AGND, the drain of the thirteenth NMOS transistor MN13 is connected to the V SS The drain of the fourteenth NMOS transistor MN14 is connected to the V SS The input of the first inverter INV1 is connected to a voltage V2, and the output of the first inverter INV1 is connected to the input of the second inverter INV2. The output of the first inverter INV1 is named QB, and the output of the second inverter INV2 is named QA.

[0015] The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3 and the first NMOS transistor MN1 constitute a start-up circuit of the self-bias current source, which ensures that the circuit reaches a correct bias stable point from an original point. The third PMOS transistor MP3 and the fourth PMOS transistor MP4 constitute a PMOS current mirror with a size ratio of 1:1. The width-length ratio of the second NMOS transistor NM2 is equal to that of the third NMOS transistor NM3, but the number of the second NMOS transistor NM2 is N times that of the third NMOS transistor NM3 (N>1). By ignoring the substrate bias effect and the channel modulation effect, an expression of a bias current I generated by the circuit can be derived as follows:

[0016]

[0017] In the charge-discharge circuit, the sixth PMOS transistor MP6 and the fifth NMOS transistor MN5 mirror the current of the front self-bias current source, respectively, as a charge-discharge current source of the first capacitor C1. In order to ensure a duty cycle of 50%, the current of the two current sources is equal. The seventh PMOS transistor MP7, the eighth PMOS transistor MP8 and the fourth NMOS transistor MN4 are switch tubes controlled by the signals QA and QB. The sixth PMOS transistor MP6 flows through the second resistor R2 and the diode-connected sixth NMOS transistor MN6 in each half clock period, thereby generating an alternating voltage. After the alternating voltage is filtered by the second capacitor C2, a common-mode voltage of the positive threshold hysteresis comparator is obtained.

[0018] When the signal QA is at a high level and the signal QB is at a low level, the number ratio of the left input pair transistor to the right input pair transistor in the positive threshold hysteresis comparator is 1:N. When the charging time t1 of the first capacitor C1 satisfies the following condition, the output of the comparator flips:

[0019]

[0020] When the signal QA is low and QB is high, the number ratio of the left and right input pairs of the positive threshold hysteresis comparator is 1:1, when the first capacitor C1 discharges for a time t2, the comparator output flips over when the following condition is met:

[0021] t2 = R1C1

[0022] In the two-stage current-limiting inverter, the twelfth PMOS tube MP12, the thirteenth PMOS tube MP13 and the thirteenth NMOS tube MN13 and the fourteenth NMOS tube MN14 mirror the current of the preceding self-bias current source respectively to limit the average current consumed by the direct path of the inverter in the process of charging and discharging the load capacitor.

[0023] The low-power RC relaxation oscillator, the principle of starting process is as follows: (1) the initial first capacitor C1 has no stored charge, the voltage across the two ends is equal, that is, the output voltage Vn of the positive threshold hysteresis comparator is Vp; (2) at this time, the number ratio of the two input pairs of the positive threshold hysteresis comparator is 1:N, the first stage output of the positive threshold hysteresis comparator is low, the second stage output is high, the output QB of the first inverter INV1 is low, and the output QA of the second inverter INV2 is high. In the charging and discharging circuit, the seventh PMOS tube MP7 is turned on, the eighth PMOS tube MP8 and the fourth NMOS tube MN4 are turned off, and the current charges the first capacitor C1, and the Vn potential rises. (3) When Vn is charged to meet Vn-Vp=ΔVgs, the first stage output V1 of the positive threshold hysteresis comparator flips over to high, the second stage output V2 flips over to low, the output QB of the first inverter INV1 flips over to high, and the output QA of the second inverter INV2 flips over to low. (4) At this time, the number ratio of the two input pairs of the positive threshold hysteresis comparator becomes 1:1, and in the charging and discharging circuit, the seventh PMOS tube MP7 is turned off, the eighth PMOS tube MP8 and the fourth NMOS tube MN4 are turned on, and the current discharges the capacitor C1, and the Vn potential decreases. (5) When Vn is discharged to Vn=Vp, the first stage output V1 of the positive threshold hysteresis comparator, the second stage output V2, the output QB of the first inverter INV1 and the output QA of the second inverter INV2 flip over again. Thus the circuit works for a period. (6) Repeat the above (2)-(5), and the starting is completed.

[0024] The low-power RC relaxation oscillator, the frequency expression of the first inverter INV1 output QB and the second inverter INV2 output QA is:

[0025]

[0026] The beneficial effect of the application is that the circuit of the application comprises a self-bias current source, a charge-discharge circuit, a positive threshold hysteresis comparator and a two-stage current-limiting inverter, the self-bias current source generates a current independent of the power supply voltage, the charge-discharge circuit mirrors the current of the self-bias current source, is controlled by the output signal QA and the output signal QB, and charges and discharges the capacitor, the voltage across the capacitor is the output voltage of the positive threshold hysteresis comparator, and the output signal QA controls the charging and discharging of the capacitor, and the number of input pairs is changed to change the flip threshold value. The two-stage current-limiting inverter generates the output signal QA and the output signal QB, and limits the average current consumed by the direct path of the inverter during the charging and discharging of the load capacitor through the current mirrored from the self-bias current source; the low-power RC relaxation oscillator of the application has an output frequency of 30KHz, a duty cycle of 50%, an average power consumption of 149nA, and a frequency expression only related to resistance and capacitance BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 Fig. 1 shows the circuit structure schematic diagram of the low-power RC relaxation oscillator design in the embodiment.

[0028] Figure 2 Fig. 2 shows the output signal schematic diagram of the low-power RC relaxation oscillator. DETAILED DESCRIPTION

[0029] The technical solutions of the application will be described in detail below with reference to the drawings:

[0030] The low-power RC relaxation oscillator design of the application comprises a self-bias current source, a charge-discharge circuit, a positive threshold hysteresis comparator and a two-stage current-limiting inverter.

[0031] The self-bias current source in the application generates a current I independent of the power supply voltage, and provides the required voltage Vbp and the voltage Vbn for the circuit, such as Figure 1 Fig. 1 shows an implementation form of the self-bias current source, which comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2 and a third NMOS tube MN3, and a first resistor R1. The first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3 and the first NMOS tube MN1 form a start-up circuit of the self-bias current source, which ensures that the circuit reaches the correct bias stable point away from the origin. The third PMOS tube MP3 and the fourth PMOS tube MP4 form a PMOS current mirror with a size ratio of 1:1. The width-length ratio of the second NMOS tube MN2 is equal to that of the third NMOS tube MN3, but the number of the second NMOS tube MN2 is N times (N>1) that of the third NMOS tube MN3, and the self-bias generates a bias current I independent of the power supply voltage.

[0032] The charge-discharge circuit in the application comprises a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a second resistor R2, a first capacitor C1 and a second capacitor C2. The sixth PMOS transistor MP6 and the fifth NMOS transistor MN5 mirror the current of the self-bias current source respectively, as the charge-discharge current source of the first capacitor C1, so as to ensure 50% duty cycle, and the current of the two current sources is equal in size; the seventh PMOS transistor MP7, the eighth PMOS transistor MP8 and the fourth NMOS transistor MN4 are switch transistors controlled by signals QA and QB; the sixth PMOS transistor MP6 flows through the second resistor R2 and the sixth NMOS transistor MN6 in diode connection in each half clock cycle, thereby generating an alternating voltage, and the voltage becomes the common-mode voltage of the positive threshold hysteresis comparator after being filtered by the second capacitor C2.

[0033] The positive threshold hysteresis comparator in the application comprises a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10 and an eleventh NMOS transistor MN11. The ninth PMOS transistor MP9, the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11 are input pairs, the width-length ratio is equal, and the number ratio is 1:1:N-1. The twelfth NMOS transistor MN12 is a switch transistor. When the signal QA is high and the signal QB is low, the number ratio of the left and right input pairs in the positive threshold hysteresis comparator is 1:N; when the signal QA is low and the signal QB is high, the number ratio of the left and right input pairs in the positive threshold hysteresis comparator is 1:1. The change of the flip threshold is realized by changing the number of input pairs.

[0034] The two-stage current-limiting inverter in the application comprises a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first inverter INV1 and a second inverter INV2. The twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 mirror the current of the self-bias current source respectively, so as to limit the average current consumed by the direct path of the inverter in the process of charging and discharging the load capacitor.

[0035] The principle of the low-power RC relaxation oscillator of the application is as follows: (1) the initial first capacitor C1 has no stored charge, and the voltage across the capacitor is equal, that is, the output voltage Vn across the positive threshold hysteresis comparator is Vp; (2) at this time, the ratio of the number of input pairs of the positive threshold hysteresis comparator is 1:N, the first level output of the positive threshold hysteresis comparator is low, the second level output is high, the output QB of the first inverter INV1 is low, and the output QA of the second inverter INV2 is high. In the charging and discharging circuit, the seventh PMOS tube MP7 is turned on, the eighth PMOS tube MP8 and the fourth NMOS tube MN4 are turned off, the current charges the first capacitor C1, and the Vn potential rises. (3) When Vn is charged to satisfy Vn-Vp=ΔVgs, the first level output V1 of the positive threshold hysteresis comparator flips to high, the second level output V2 flips to low, the output QB of the first inverter INV1 flips to high, and the output QA of the second inverter INV2 flips to low. (4) At this time, the ratio of the number of input pairs of the positive threshold hysteresis comparator is changed to 1:1, and in the charging and discharging circuit, the seventh PMOS tube MP7 is turned off, the eighth PMOS tube MP8 and the fourth NMOS tube MN4 are turned on, the current discharges the capacitor C1, and the Vn potential decreases. (5) When Vn is discharged to Vn=Vp, the first level output V1, the second level output V2, the output QB of the first inverter INV1, and the output QA of the second inverter INV2 flip again. At this time, the circuit works for one period. (6) Repeat the above (2)-(5), and the start-up can be completed by repeating.

[0036] Figure 2 The output signal of the low-power RC relaxation oscillator is shown in the figure, the frequency of the output signal QA is 30KHz, the duty cycle is 50%, and the average power consumption is 149nA.

Claims

1. A low-power RC relaxation oscillator, characterized in that, It includes a self-biased current source, a charge-discharge circuit, a positive threshold hysteresis comparator, and a two-stage current-limiting inverter; The self-biased current source includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a first resistor R1; The gate, drain, gate, and source of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the third PMOS transistor MP3 are all connected to the gate of the first NMOS transistor MN1. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are all connected to the power supply AVDD. The drains of the second PMOS transistor MP2, the fifth PMOS transistor MP5, the gate, and the drain of the third NMOS transistor MN3 are all connected to the second NMOS transistor MN1. The gate of transistor MN2, the drain of the third PMOS transistor MP3, the source and drain of the first NMOS transistor MN1, the source of the third NMOS transistor MN3, and one end of the first resistor R1 are all connected to the reference ground AGND. The gate and drain of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP5 are all connected to the drain of the second NMOS transistor MN2. The source of the second NMOS transistor is connected to the other end of the first resistor R1. The gate voltage of the fourth PMOS transistor MP4 is defined as voltage Vbp, and the gate voltage of the third NMOS transistor MN3 is defined as voltage Vbn. The charging and discharging circuit includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a second resistor R2, a first capacitor C1, and a second capacitor C2. The gate of the sixth PMOS transistor MP6 is connected to voltage Vbp, its source is connected to power supply AVDD, and its drain is connected to the source of the seventh PMOS transistor MP7 and the source of the eighth PMOS transistor MP8. The gate of the seventh PMOS transistor MP7 is connected to signal QB, and its drain is connected to the drain of the fourth NMOS transistor MN4 and one end of the first capacitor C1. The gate of the eighth PMOS transistor MP8 is connected to signal QA, and its drain is connected to one end of the second resistor R2, the other end of the first capacitor C1, and one end of the second capacitor C2. The gate of the fourth NMOS transistor MN4 is connected to signal QB, and its source is connected to the drain of the fifth NMOS transistor MN5. The gate of the fifth NMOS transistor MN5 is connected to voltage Vbn, and its source is connected to reference ground AGND. The gate and drain of the sixth NMOS transistor MN6 are connected to the other end of the second resistor R2, and its source and the other end of the second capacitor C2 are connected to reference ground AGND. The voltage at one end of the first capacitor C1 connected to the drain of the seventh PMOS transistor MP7 is defined as Vn, and the voltage at the other end is defined as Vp. The positive threshold hysteresis comparator circuit includes a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12. The sources of the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, and the eleventh PMOS transistor MP11 are all connected to the power supply AVDD. The gates of the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, and the ninth PMOS transistor MP9 are all connected to the drain of the eighth NMOS transistor MN8. The drains of the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, and the eleventh NMOS transistor MN11 are all connected to the drain of the ninth NMOS transistor MN9. The drain of the eleventh PMOS transistor MP11 is connected to the drain of the twelfth NMOS transistor MN12. The gate of the eighth NMOS transistor MN8 is connected to the voltage Vn, and its source is connected to the source of the ninth NMOS transistor MN9. The source of the tenth NMOS transistor MN10 is connected to the drain of the seventh NMOS transistor MN7. The gates of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are connected to voltage Vp. The drain of the tenth NMOS transistor MN10 is connected to the source of the eleventh NMOS transistor MN11. The gate of the eleventh NMOS transistor MN11 is connected to signal QA. The gates of the seventh NMOS transistor MN7 and the twelfth NMOS transistor MN12 are connected to voltage Vbn. The sources of the seventh NMOS transistor MN7 and the twelfth NMOS transistor MN12 are connected to reference ground AGND. The drain voltage of the tenth NMOS transistor MN10 is defined as V1, and the drain voltage of the eleventh PMOS transistor MP11 is defined as V2. The two-stage current-limiting inverter includes a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first inverter INV1, and a second inverter INV2; The gates of the twelfth PMOS transistor MP12 and the thirteenth PMOS transistor MP13 are connected to the voltage Vbp. The sources of the twelfth PMOS transistor MP12 and the thirteenth PMOS transistor MP13 are connected to the power supply AVDD. The drain of the twelfth PMOS transistor MP12 is connected to the voltage Vbp of the first inverter INV1. DD Connected, the drain of the twelfth PMOS transistor MP13 is connected to the V of the second inverter INV2. DD The gates of the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 are connected to voltage Vbn. The sources of the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 are connected to reference ground AGND. The drain of the thirteenth NMOS transistor MN13 is connected to the voltage Vbn of the first inverter INV1. SS Connected, the drain of the fourteenth NMOS transistor MN14 is connected to the V of the second inverter INV2. SS Connected; the input terminal of the first inverter INV1 is connected to voltage V2, and the output terminal is connected to the input terminal of the second inverter INV2; the output of the first inverter INV1 is defined as QB, and the output of the second inverter INV2 is defined as QA.

2. The low-power RC relaxation oscillator according to claim 1, characterized in that, The first capacitor C1 is a MIM capacitor or a MOM capacitor, and the second capacitor C1 is a MOS capacitor, a MIM capacitor, or a MOM capacitor.

3. A low-power RC relaxation oscillator according to claim 1, characterized in that, The first resistor R1 and the second resistor R2 are P-type Poly resistors or trap resistors.

4. A low-power RC relaxation oscillator according to claim 1, characterized in that, The substrates of all NMOS transistors are grounded, and the substrates of all PMOS transistors are connected to the power supply.

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