W-band high-precision digital controlled phase shifter using gain compensation technique

Abstract

The application relates to a W-band high-precision digital control phase shifter adopting a gain compensation technology, which comprises a 90-degree polarity switching logic circuit, a radio frequency amplifier, an input balun, a quadrature signal generator, an analog adder, a double-path radio frequency amplifier and a 180-degree polarity switching logic circuit, wherein the 90-degree polarity switching logic circuit is used for generating a 90-degree state voltage; the radio frequency amplifier is connected with the 90-degree polarity switching logic circuit and the input balun respectively, and is used for phase-shifting a received radio frequency signal according to the 90-degree state voltage; the input balun, the quadrature signal generator and the analog adder are sequentially connected, and the radio frequency signal is twice phase-shifted through a received off-chip control signal; the double-path radio frequency amplifier is connected with the 180-degree polarity switching logic circuit, and the radio frequency signal is thrice phase-shifted through a received off-chip control signal to complete the phase-shifting of the radio frequency signal; the digital control phase shifter reduces the insertion loss and the gain error, and improves the phase precision of a synthesized signal of the digital control phase shifter.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency integrated circuits, and specifically relates to a W-band high-precision numerically controlled phase shifter using gain compensation technology. Background Technology

[0002] Beam scanning in modern array antennas almost exclusively employs phased arrays, which keep the antenna elements stationary while altering the phase of the electromagnetic waves transmitted by those elements. Signal propagation in any transmission medium introduces phase shift, but the phase shift introduced by conventional amplitude and spectrum processing circuits is often uncontrollable and impractical for phase scanning. Phase shifters, as phase adjustment circuits, are widely used in phased array radar, missile attitude control, millimeter-wave sensors, security and surveillance, and communications.

[0003] Traditional phase-shifting structures are mainly divided into passive phase shifters and active phase shifters. Passive phase shifters mainly include high-pass and low-pass filter circuit structure phase shifters, reflective phase shifters, and switched inductor-capacitor phase shifters. Their typical characteristics are no static power consumption, but relatively high insertion loss. Especially in the millimeter-wave band, the phase shifting accuracy and error, gain accuracy and error of passive phase shifters deteriorate severely. Active phase shifters are mainly implemented using vector synthesis. A typical structure of a traditional active phase shifter includes four parts: an input balun, a quadrature signal generator, an analog adder, and an output balun. The input balun converts the single-ended signal at the input terminal IN into a differential signal, and the output balun converts the synthesized differential signal back into a single-ended signal and outputs it from the OUT terminal. The quadrature signal generator converts the differential signal generated by the balun into four pairwise orthogonal signals. The analog adder performs vector synthesis on the quadrature signals and controls the I / Q gain by changing the current ratio injected into the analog adder through a current array, thus determining the phase of the synthesized signal. The current array generator is controlled by a combination of logic signals input from an externally sourced numerical control signal and output from a logic encoder, thus achieving numerical control. Besides its characteristic of consuming static power, the active phase shifter has certain advantages over the passive phase shifter in terms of area, gain, phase shifting accuracy, and error.

[0004] However, with the development of modern millimeter-wave communication systems, carrier application frequency bands have expanded to W and above, and the impact of the electromagnetic environment on circuit performance and even functionality is becoming increasingly severe. Traditional active phase shifter architectures experience significant performance degradation as the application frequency increases, primarily manifested in decreased phase shift accuracy, increased insertion loss, and exacerbated gain fluctuations. Low-frequency active phase shifter architectures are no longer able to perform well in the millimeter-wave band, making the design of high-precision phase shifters in W and above bands extremely difficult. Summary of the Invention

[0005] This invention provides a W-band high-precision numerically controlled phase shifter employing gain compensation technology, comprising a first phase shift module, a second phase shift module, and a third phase shift module connected in sequence, wherein...

[0006] The first phase shift module includes a 90° polarity switching logic circuit and an RF amplifier. The 90° polarity switching logic circuit receives an external first control signal and generates a 90° state voltage based on the first control signal. The input terminal of the RF amplifier is connected to the output terminal of the 90° polarity switching logic circuit. The RF amplifier receives an external RF signal and the 90° state voltage, performs phase shifting on the RF signal based on the 90° state voltage, and outputs the phase-shifted RF signal.

[0007] The second phase-shift module includes an input balun, a quadrature signal generator, and an analog adder. The input terminal of the input balun is connected to the output terminal of the RF amplifier to convert the phase-shifted RF signal into a pair of differential signals. The input terminal of the quadrature signal generator is connected to the output terminal of the input balun to convert the pair of differential signals into four pairs of pairwise orthogonal differential signals. The analog adder is connected to the output terminal of the quadrature signal generator to receive external second and third control signals, synthesize the four pairs of pairwise orthogonal differential signals into a pair of differential signals, and phase-shift the synthesized pair of differential signals according to the second and third control signals, and output the phase-shifted pair of differential signals.

[0008] The third phase shift module includes a 180° polarity switching logic circuit and a dual-channel RF amplifier. The output of the 180° polarity switching logic circuit is connected to the input of the dual-channel RF amplifier. The 180° polarity switching logic circuit is used to receive an external fourth control signal and generate a 180° state voltage based on the fourth control signal. The input of the dual-channel RF amplifier is connected to the output of the analog adder. The dual-channel RF amplifier is used to receive the 180° state voltage and perform a second phase shift on the phase-shifted pair of differential signals based on the 180° state voltage before outputting the signal.

[0009] In one embodiment of the present invention, the first control signal includes a preset first level signal and a preset second level signal, and the 90° state voltage includes a first 90° state voltage and a second 90° state voltage, wherein...

[0010] When the first control signal is the first level signal, the 90° polarity switching logic circuit generates the first 90° state voltage, and the RF amplifier realizes a 90° phase shift of the RF signal; when the first control signal is the second level signal, the 90° polarity switching logic circuit generates the second 90° state voltage, and the RF amplifier realizes a 0° phase shift of the RF signal.

[0011] In one embodiment of the present invention, the second control signal and the third control signal are preset with different voltage values, and the different voltage values ​​of the second control signal and the third control signal are used to control the analog adder to achieve different phase shift steps.

[0012] In one embodiment of the present invention, the fourth control signal includes the first level signal and the second level signal, and the 180° state voltage includes a first 180° state voltage and a second 180° state voltage, wherein,

[0013] When the fourth control signal is the first level signal, the 180° polarity switching logic circuit generates the first 180° state voltage, and the dual-channel RF amplifier performs a 180° phase shift on the received signal. When the fourth control signal is the second level signal, the 180° polarity switching logic circuit generates the second 180° state voltage, and the dual-channel RF amplifier performs a 0° phase shift on the received signal.

[0014] In one embodiment of the present invention, the 90° polarity switching logic circuit includes NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10; resistors R9, R10, R11, and R12; DC input terminals VB, VC, VP, and Sel90; and output terminals Vb90, Vc90, Vb0_90, and Vc0_90, wherein...

[0015] The gates of the PMOS transistor M9 and the NMOS transistor M10 are connected to the DC input terminal Sel90. The source and substrate of the PMOS transistor M9 are connected to the DC input terminal VP. The source and substrate of the NMOS transistor M10 are connected to the ground terminal. The drain of the PMOS transistor M9 is connected to the drain of the NMOS transistor M10.

[0016] The gate of NMOS transistor M1 is connected to the DC input terminal Sel90. The source of NMOS transistor M1 is connected to the first terminal of resistor R9 and the source of NMOS transistor M2. The drain of NMOS transistor M1 is connected to the DC input terminal VC. The gate of NMOS transistor M2 is connected to the drain of PMOS transistor M9. The drain of NMOS transistor M2 is grounded. The second terminal of resistor R9 is connected to the output terminal Vc90. The gate of NMOS transistor M3 is connected to the drain of PMOS transistor M9. The source of NMOS transistor M3 is connected to the first terminal of resistor R10 and the source of NMOS transistor M4. The drain of NMOS transistor M3 is connected to the DC input terminal VC. The gate of NMOS transistor M4 is connected to the DC input terminal Sel90. The drain of NMOS transistor M4 is grounded. The second terminal of resistor R10 is connected to the output terminal Vc0_90. The gate of NMOS transistor M5 is connected to the DC input terminal Sel90. The source of NMOS transistor M5 is connected to the first terminal of resistor R11 and the source of NMOS transistor M6. The drain of NMOS transistor M5 is connected to the DC input terminal VB. The gate of NMOS transistor M6 is connected to the drain of PMOS transistor M9. The drain of NMOS transistor M6 is grounded. The second terminal of resistor R11 is connected to the output terminal Vb90. The gate of NMOS transistor M7 is connected to the drain of PMOS transistor M9. The source of NMOS transistor M7 is connected to the first terminal of resistor R12 and the source of NMOS transistor M8. The drain of NMOS transistor M7 is connected to the DC input terminal VB. The gate of NMOS transistor M8 is connected to the DC input terminal Sel90. The drain of NMOS transistor M8 is grounded. The second terminal of resistor R12 is connected to the output terminal Vb0_90.

[0017] The DC input terminal Sel90 is used to receive the first control signal, and the DC input terminal VP is used to receive the first voltage from outside the chip as the power supply voltage for the 90° polarity switching logic circuit. The 90° polarity switching logic circuit provides voltage to the RF amplifier by receiving the second and third voltages from outside the chip through the DC input terminals VB and VC, respectively.

[0018] In one embodiment of the present invention, the radio frequency amplifier is a Cascode structure, including transmission lines TL1, TL2, TL3, and TL4; capacitors C1, C2, C3, C4, C5, and C6; resistors R1, R2, R3, and R4; transistors Q1, Q2, Q3, and Q4; inductors L1 and L2; a power input terminal VDD1; an input terminal IN; and an output terminal OUT1.

[0019] The first end of inductor L1 is connected to the input terminal IN, and the second end of inductor L1 is connected to the first end of capacitor C1, which is grounded. The first end of capacitor C2 is connected to the input terminal IN, and the second end of capacitor C2 is connected to the first end of resistor R1 and the base of transistor Q1. The second end of resistor R1 is connected to the output terminal Vb0_90 of the 90° polarity switching logic circuit. The emitter of transistor Q1 is grounded, and the collector of transistor Q1 is connected to the emitter of transistor Q2. The base of transistor Q2 is connected to the first end of resistor R2, and the second end of resistor R2 is connected to the output terminal Vc0_90 of the 90° polarity switching logic circuit. The collector of transistor Q2 is connected to the first end of transmission line TL2, and the second end of transmission line TL2 is connected to the first ends of transmission lines TL1, TL3, and TL4. The second end of transmission line TL1 is connected to the power input terminal VDD1. The second end of capacitor C3 is connected to the first end of capacitor C6. The second end of capacitor C6 is connected to the output terminal OUT1. The output terminal OUT1 is connected to one end of the primary coil in the input balun. The second end of transmission line TL4 is connected to the collector of transistor Q4. The base of transistor Q4 is connected to the first end of resistor R4. The second end of resistor R4 is connected to the output terminal Vc90 of the 90° polarity switching logic circuit. The first end of capacitor C3 is connected to the input terminal IN. The second end of capacitor C3 is connected to the first end of resistor R3 and the base of transistor Q3. The second end of resistor R3 is connected to the output terminal Vb90 of the 90° polarity switching logic circuit. The emitter of transistor Q3 is grounded. The collector of transistor Q3 is connected to the first end of inductor L2 and capacitor C4. The second end of capacitor C4 is grounded. The second end of inductor L2 is connected to the emitter of transistor Q4 and the first end of capacitor C5. The second end of capacitor C5 is grounded.

[0020] The input terminal IN is used to receive the radio frequency signal. Transistors Q2 and Q4 are common-base cascode transistors in the cascode structure of the radio frequency amplifier. The common-base cascode transistor receives the voltage from the 90° polarity switching logic circuit through the DC input terminal VC as a bias voltage. Transistors Q1 and Q3 are common-emitter amplifier transistors in the cascode structure of the radio frequency amplifier. The common-emitter amplifier receives the voltage from the 90° polarity switching logic circuit through the DC input terminal VB as a bias voltage. The power input terminal VDD1 is used to receive the first voltage from outside the chip as the power supply voltage of the radio frequency amplifier.

[0021] In one embodiment of the present invention, the analog adder includes capacitors C10, C11, C12, and C13; inductors L5, L6, L7, L8, L9, and L10; transistors Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16; NMOS transistors M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, and M32; DC signal input terminals VI and VQ; power input terminal VDD2; output terminal VON; and output terminal VOP.

[0022] The gate and drain of NMOS transistor M25 are shorted and connected to the gates of NMOS transistors M21 and M31, and then to the DC signal input terminal VI. The gate and drain of NMOS transistor M27 are shorted and connected to the gates of NMOS transistors M23 and M29, and then to the DC signal input terminal VQ. The gate and drain of NMOS transistor M26 are shorted and connected to the source of NMOS transistor M25, the gate of NMOS transistor M22, and the gate of NMOS transistor M32. The source of NMOS transistor M26 is grounded. The gate and drain of NMOS transistor M28 are shorted and connected to the source of NMOS transistor M27, the source of NMOS transistor M25, and M31, and then to the DC signal input terminal VQ. The gate of S-channel transistor M24 is connected to the gate of NMOS transistor M30, and the source of NMOS transistor M28 is grounded; all sources of NMOS transistors M22, M24, M30, and M32 are grounded; the drain of NMOS transistor M22 is connected to the source of NMOS transistor M21; the drain of NMOS transistor M21 is connected to the emitters of transistors Q9 and Q10; the drain of NMOS transistor M24 is connected to the source of NMOS transistor M23; the drain of NMOS transistor M23 is connected to the emitters of transistors Q11 and Q12; the drain of NMOS transistor M30 is connected to the source of NMOS transistor M24. The source of transistor M29 is connected to the source of transistor M31; the drain of transistor M29 is connected to the emitters of transistors Q13 and Q14; the drain of transistor M32 is connected to the source of transistor M31; the drain of transistor M31 is connected to the emitters of transistors Q15 and Q16; the base of transistor Q9 and the base of transistor Q13 are connected to the first output terminal I+ of the quadrature signal generator; the base of transistor Q10 and the base of transistor Q14 are connected to the second output terminal I- of the quadrature signal generator; the base of transistor Q11 and the base of transistor Q16 are connected to the third output terminal Q+ of the quadrature signal generator. The bases of transistors Q12 and Q15 are connected to the fourth output terminal Q- of the quadrature signal generator; the collectors of transistors Q9 and Q11, the first terminal of capacitor C10, and the first terminal of inductor L5 are connected; the collectors of transistors Q10 and Q12, the first terminal of capacitor C11, and the first terminal of inductor L6 are connected; the collectors of transistors Q13 and Q15, the first terminal of capacitor C12, and the first terminal of inductor L9 are connected; the collectors of transistors Q14 and Q16, the first terminal of capacitor C13, and the first terminal of inductor L10 are connected.The second terminals of all inductors L5, L6, L9, and L10 are connected to the power input terminal VDD2; the second terminal of capacitor C10 and the first terminal of inductor L8 are connected to the output terminal VON; the second terminal of capacitor C11 and the first terminal of inductor L7 are connected to the output terminal VOP; the second terminal of capacitor C12 is connected to the second terminal of inductor L7; and the second terminal of capacitor C13 is connected to the second terminal of inductor L8.

[0023] The power input terminal VDD2 is used to receive the first voltage from outside the chip as a power source. The DC signal input terminal VI is used to receive the second control signal. The DC signal input terminal VQ is used to receive the third control signal. The output terminals VON and VOP are used to output a pair of differential signals after phase shifting by the analog adder.

[0024] In one embodiment of the present invention, the dual-channel RF amplifier bit Cascode structure includes a power input terminal VDD3, an RF signal input terminal IN_N, an RF signal input terminal IN_P, an output terminal OUT2, transmission lines TL5, TL6, TL7, and TL8, a capacitor C7, resistors R5, R6, R7, and R8, and transistors Q5, Q6, Q7, and Q8, wherein...

[0025] The base of transistor Q5 is connected to the first terminal of resistor R5 and the RF signal input terminal IN_N. The RF signal input terminal IN_N is connected to the output terminal VON of the analog adder. The second terminal of resistor R5 is connected to the output terminal Vb0_180 of the 180° polarity switching logic circuit. The emitter of transistor Q5 is grounded, and the collector of transistor Q5 is connected to the emitter of transistor Q6. The base of transistor Q6 is connected to the first terminal of resistor R6. The second terminal of resistor R6 is connected to the output terminal Vc0_180 of the 180° polarity switching logic circuit. The collector of transistor Q6 is connected to the first terminal of transmission line TL6. The second terminal of transmission line TL6 is connected to the first terminals of transmission lines TL5, TL7, and TL8. The second terminal of transmission line TL5... The following connections are made: The first terminal of the transmission line TL7 is connected to the power input terminal VDD3; the second terminal of the transmission line TL7 is connected to the first terminal of the capacitor C7, and the second terminal of the capacitor C7 is connected to the output terminal OUT2; the second terminal of the transmission line TL8 is connected to the collector of the transistor Q8, the base of the transistor Q8 is connected to the first terminal of the resistor R8, and the second terminal of the resistor R8 is connected to the output terminal Vc180 of the 180° polarity switching logic circuit; the base of the transistor Q7 is connected to the first terminal of the resistor R7 and the RF signal input terminal IN_P, the RF signal input terminal IN_P is connected to the output terminal VOP of the analog adder, the second terminal of the resistor R7 is connected to the output terminal Vb180 of the 180° polarity switching logic circuit, the emitter of the transistor Q7 is grounded, and the collector of the transistor Q7 is connected to the emitter of the transistor Q8.

[0026] Transistors Q6 and Q8 are common-base cascode transistors in the cascode structure of the dual-channel RF amplifier. The common-base cascode transistor receives the voltage of the DC input terminal VC' in the 180° polarity switching logic circuit as a bias voltage. Transistors Q5 and Q7 are common-emitter amplifier transistors in the cascode structure of the dual-channel RF amplifier. The common-emitter amplifier receives the voltage output from the DC input terminal VB' in the 180° polarity switching logic circuit as a bias voltage. The power input terminal VDD3 is used to receive the first voltage from outside the chip as the power supply voltage of the dual-channel RF amplifier. The dual-channel RF amplifier is used to shift the signal from the analog adder and output it through the output terminal OUT2.

[0027] In one embodiment of the present invention, the 180° polarity switching logic circuit includes NMOS transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20; resistors R13, R14, R15, and R16; DC input terminals VB', VC', VP', and Sel180; and output terminals Vb180, Vb0_180, Vc180, and Vc0_180, wherein...

[0028] The gate of the PMOS transistor M19 and the gate of the NMOS transistor M20 are connected to the DC input terminal Sel180. The source and substrate of the PMOS transistor M19 are connected to the DC input terminal VP'. The source and substrate of the NMOS transistor M20 are connected and grounded. The drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20.

[0029] The gate of NMOS transistor M11 is connected to the DC input terminal Sel180. The source of NMOS transistor M11 is connected to the first terminal of resistor R13 and the source of NMOS transistor M12. The second terminal of resistor R13 is connected to the output terminal Vc180. The drain of NMOS transistor M11 is connected to the DC input terminal VC'. The gate of NMOS transistor M12 is connected to the drain of PMOS transistor M19, and the drain of NMOS transistor M12 is grounded. The gate of NMOS transistor M13 is connected to the drain of PMOS transistor M19. The source of NMOS transistor M13 is connected to the first terminal of resistor R14 and the source of NMOS transistor M14. The second terminal of resistor R14 is connected to the output terminal Vc0_180. The drain of NMOS transistor M13 is connected to the DC input terminal VC'. The gate of NMOS transistor M14 is connected to the DC input terminal Sel180, and the drain of NMOS transistor M14 is grounded. The gate of NMOS transistor M15 is connected to the DC input terminal Sel180. The source of NMOS transistor M15 is connected to the first terminal of resistor R15 and the source of NMOS transistor M16. The second terminal of resistor R15 is connected to the output terminal Vb180. The drain of NMOS transistor M15 is connected to the DC input terminal VB'. The gate of NMOS transistor M16 is connected to the drain of PMOS transistor M19. The drain of NMOS transistor M16 is grounded. The gate of NMOS transistor M17 is connected to the drain of PMOS transistor M19. The source of NMOS transistor M17 is connected to the first terminal of resistor R16 and the source of NMOS transistor M18. The second terminal of resistor R16 is connected to the output terminal Vb0_180. The drain of NMOS transistor M17 is connected to the DC input terminal VB'. The gate of NMOS transistor M18 is connected to the DC input terminal Sel180. The drain of NMOS transistor M18 is grounded.

[0030] The DC input terminal Sel180 is used to receive the fourth control signal, and the DC input terminal VP' is used to receive the first voltage from outside the chip as the power supply voltage of the 180° polarity switching logic circuit. The 180° polarity switching logic circuit receives the second voltage and the third voltage from outside the chip through the DC input terminal VB' and the DC input terminal VC' respectively to provide voltage for the dual-channel RF amplifier.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0032] 1. The high-precision numerically controlled phase shifter provided by this invention achieves sixty-four different phase shift states operating at 93–95 GHz using SiGe BiCMOS technology. By designing 90° polarity switching logic circuits and 180° polarity switching logic circuits to control the RF amplifier and dual-channel RF amplifier respectively, phase shift control is achieved. Different analog voltages are connected to the bases of different paths of the RF amplifier and the dual-channel RF amplifier, and a certain power supply voltage bias is applied to the RF amplifier and the dual-channel RF amplifier, thereby enabling the RF amplifier and the dual-channel RF amplifier to obtain gain compensation, reducing insertion loss, and providing a small amount of gain. This effectively reduces the insertion loss of the traditional switching phase shifter structure. While achieving 180° phase stepping through the 180° polarity switching logic circuit, it saves the output balun compared to the traditional phase shifter, thus reducing the area of ​​the phase shifter.

[0033] 2. The high-precision CNC phase shifter provided by the present invention is designed as a dual-injection Gilbert structure through analog adder design, which effectively reduces the range of impedance variation at the load end of the quadrature signal, reduces the amplitude and phase imbalance of the quadrature signal under different states, and improves the phase shifting accuracy.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a W-band high-precision numerically controlled phase shifter employing gain compensation technology, provided in an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of the circuit structure of a 90° polarity switching logic circuit provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the circuit structure of a radio frequency amplifier provided in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the circuit structure of an input balun and quadrature signal generator provided in an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of the circuit structure of an analog adder in a traditional phase shifter;

[0040] Figure 6 This is a schematic diagram of the circuit structure of the analog adder in the phase shifter provided in an embodiment of the present invention;

[0041] Figure 7 This is a schematic diagram of the circuit structure of a dual-channel radio frequency amplifier provided in an embodiment of the present invention;

[0042] Figure 8This is a schematic diagram of the circuit structure of a 180° polarity switching logic circuit provided in an embodiment of the present invention;

[0043] Figure 9 This is a simulation result diagram of the 64-phase state of a W-band high-precision numerically controlled phase shifter using gain compensation technology provided in an embodiment of the present invention;

[0044] Figure 10 This is a simulation result diagram of the root mean square error of the phase of the numerically controlled phase shifter provided in the embodiment of the present invention;

[0045] Figure 11 These are simulation results of 64 gain states of the numerically controlled phase shifter provided in this embodiment of the invention;

[0046] Figure 12 This is a simulation result diagram of the root mean square error of the gain of the numerically controlled phase shifter provided in the embodiment of the present invention;

[0047] Figure 13(a) shows the distribution of transistor input impedance in a conventional numerically controlled phase shifter under current scanning conditions;

[0048] Figure 13(b) is a diagram showing the distribution of transistor input impedance of the numerically controlled phase shifter provided in the embodiment of the present invention under the current scanning state provided in Figure 13(a). Detailed Implementation

[0049] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0050] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. References to terms such as "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0051] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0052] Please see Figure 1 , Figure 1 This is a schematic diagram of a W-band high-precision numerically controlled phase shifter employing gain compensation technology, provided by an embodiment of the present invention. This high-precision numerically controlled phase shifter receives off-chip radio frequency signals and outputs the signals after phase shifting according to actual needs. The high-precision numerically controlled phase shifter achieves a phase shift control range with a minimum relative phase shift of 5.625° and a maximum relative phase shift of 354.375°. The high-precision numerically controlled phase shifter is applied in the frequency range of 93–95 GHz, belonging to the W-band. The high-precision numerically controlled phase shifter includes three phase shift modules connected in series: a first phase shift module 10, a second phase shift module 20, and a third phase shift module 30.

[0053] The first phase shift module 10 includes a 90° polarity switching logic circuit and an RF amplifier. Specifically, the input terminal of the RF amplifier is connected to the output terminal of the 90° polarity switching logic circuit. The RF amplifier is used to receive external RF signals and a 90° state voltage from the 90° polarity switching logic circuit, and to phase-shift the RF signals according to the 90° state voltage, and output the phase-shifted RF signals. The 90° polarity switching logic circuit is used to receive an external first control signal, and to generate and output a 90° state voltage according to the first control signal. The first control signal includes a preset first level signal and a preset second level signal. Specifically, the preset voltage value of the first level signal is 2.5V, and the preset voltage value of the second level signal is 0V. The 90° state voltage includes a first 90° state voltage and a second 90° state voltage. When the first control signal is a preset first level signal, the 90° polarity switching logic circuit generates the first 90° state voltage, causing the RF amplifier to be in a phase-shifted state, and the RF amplifier realizes a 90° phase shift of the RF signal. When the first control signal is a preset second level signal, the 90° polarity switching logic circuit generates the second 90° state voltage, causing the RF amplifier to be in a reference state, and the RF amplifier realizes a 0° phase shift of the RF signal. Therefore, the first phase shift module 10 can realize two steps, 90° or 0°, so that the RF signal can achieve a 90° phase shift control range.

[0054] The second phase-shifting module 20 includes an input balun, a quadrature signal generator, and an analog adder. Specifically, the input terminal of the input balun is connected to the output terminal of the RF amplifier to convert the phase-shifted RF signal into a pair of differential signals. The input terminal of the quadrature signal generator is connected to the output terminal of the input balun to convert the pair of differential signals from the input balun into four pairwise orthogonal differential signals. The analog adder is connected to the output terminal of the quadrature signal generator to receive external second and third control signals, synthesize the four pairwise orthogonal signals into a pair of differential signals, phase-shift the synthesized pair of differential signals according to the second and third control signals, and output the phase-shifted pair of differential signals. Specifically, the second and third control signals are preset with sixteen different voltage values. These sixteen different voltage values ​​control the analog adder to achieve sixteen different steps from 5.625° to 90°. That is, the second phase shift module 20 can achieve sixteen steps of phase shift. Specifically, the first step is 5.625°, and the remaining steps are based on the previous step with an additional step of 5.625°, thereby achieving a phase shift control range of 5.625° to 90°.

[0055] The third phase shift module 30 includes a 180° polarity switching logic circuit and a dual-channel RF amplifier. The input of the dual-channel RF amplifier is connected to the output of the analog adder. The dual-channel RF amplifier receives a 180° state voltage from the 180° polarity switching logic circuit and, based on the 180° state voltage, further shifts the phase-shifted pair of differential signals before outputting the result. The output of the 180° polarity switching logic circuit is connected to the input of the dual-channel RF amplifier and receives an external fourth control signal, generating a 180° state voltage based on the fourth control signal. The fourth control signal includes a preset first-level signal and a preset second-level signal. Specifically, the voltage value of the preset first-level signal is 2.5V, and the voltage value of the preset second-level signal is 0V. The 180° state voltage includes a first 180° state voltage and a second 180° state voltage. When the fourth control signal is a preset first level signal, the 180° polarity switching logic circuit generates the first 180° state voltage, causing the dual-channel RF amplifier to be in a phase-shifted state, and the dual-channel RF amplifier performs a 180° phase shift on the received signal. When the fourth control signal is a preset second level signal, the 180° polarity switching logic circuit generates the second 180° state voltage, causing the dual-channel RF amplifier to be in a reference state, and the dual-channel RF amplifier performs a 0° phase shift on the received signal. Therefore, the third phase shift module 30 can achieve two phase shift steps of 180° or 0° and a 180° phase shift control range.

[0056] The high-precision CNC phase shifter provided in this embodiment can achieve a phase shift step of 5.625°, with a minimum relative phase shift of 5.625° and a maximum relative phase shift of 354.375°. The first phase shift module 10 can achieve two phase shift steps, the second phase shift module 20 can achieve sixteen phase shift steps, and the third phase shift module 30 can achieve two phase shift steps. Each phase shift step corresponds to a different working state. Therefore, this high-precision CNC phase shifter can achieve sixty-four different working states. Since the port impedance of the cascaded modules changes when the phase shifter switches between different working states, it is necessary to try to maintain the impedance value of each port in different states. In addition, the cascade order of the phase shift modules also affects the performance of the entire phase shifter. This invention optimizes the arrangement of the three phase shift modules to provide a small gain, thereby reducing the noise of the input balun and quadrature signal generator.

[0057] like Figure 2 As shown, the 90° polarity switching logic circuit includes NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10; resistors R9, R10, R11, and R12; DC input terminals VB, VC, VP, and Sel90; and output terminals Vb90, Vc90, Vb0_90, and Vc0_90.

[0058] Specifically, PMOS transistor M9 and NMOS transistor M10 constitute inverter circuit INV1, which is connected to the DC input terminal Sel90. Specifically, the gates of PMOS transistor M9 and NMOS transistor M10 are connected to the DC input terminal Sel90. The source and substrate of PMOS transistor M9 are connected to the DC input terminal VP. The source and substrate of NMOS transistor M10 are connected to ground. The drain of PMOS transistor M9 and the drain of NMOS transistor M10 are connected as the output terminal of the inverted level of the first control signal. For ease of description of subsequent circuit connections, this output terminal of the inverted level of the first control signal is labeled as... The DC input terminal Sel90 is used to receive the first control signal, and the inverter circuit INV1 is used to generate and output the inverted level of the first control signal. Specifically, when the first control signal received by the DC input terminal Sel90 is a second-level signal, that is, when the first control signal is a low level of 0V, the inverter circuit INV1 obtains an inverted level of 2.5V for the first control signal; when the first control signal is a first-level signal, that is, when the first control signal is a high level of 2.5V, the inverter circuit INV1 obtains an inverted level of 0V for the first control signal.

[0059] The gate of NMOS transistor M1 is connected to the DC input terminal Sel90. The source of NMOS transistor M1 is connected to the first terminal of resistor R9 and the source of NMOS transistor M2. The drain of NMOS transistor M1 is connected to the DC input terminal VC. The gate of NMOS transistor M2 is connected to... The drain of NMOS transistor M2 is grounded, and the second end of resistor R9 is connected to the output terminal Vc90; the gate of NMOS transistor M3 is connected to... The source of NMOS transistor M3 is connected to the first terminal of resistor R10 and the source of NMOS transistor M4. The drain of NMOS transistor M3 is connected to the DC input terminal VC. The gate of NMOS transistor M4 is connected to the DC input terminal Sel90. The drain of NMOS transistor M4 is grounded. The second terminal of resistor R10 is connected to the output terminal Vc0_90. The gate of NMOS transistor M5 is connected to the DC input terminal Sel90. The source of NMOS transistor M5 is connected to the first terminal of resistor R11 and the source of NMOS transistor M6. The drain of NMOS transistor M5 is connected to the DC input terminal VB. The gate of NMOS transistor M6 is connected to... The drain of NMOS transistor M6 is grounded, and the second end of resistor R11 is connected to the output terminal Vb90; the gate of NMOS transistor M7 is connected to... The source of NMOS transistor M7 is connected to the first terminal of resistor R12 and the source of NMOS transistor M8. The drain of NMOS transistor M7 is connected to the DC input terminal VB. The gate of NMOS transistor M8 is connected to the DC input terminal Sel90. The drain of NMOS transistor M8 is grounded. The second terminal of resistor R12 is connected to the output terminal Vb0_90.

[0060] Specifically, the DC input terminal Sel90 is used to receive a first control signal from outside the chip, and the DC input terminal VP is used to receive a first voltage from outside the chip as the power supply voltage for the 90° polarity switching logic circuit. Further, the first voltage is 2.5V. The DC input terminal VB is used to receive a second voltage from outside the chip. Further, the second voltage is 880mV. The DC input terminal VC is used to receive a third voltage from outside the chip. Further, the third voltage is 1.8V. The 90° polarity switching logic circuit provides voltage to the RF amplifier through the second and third voltages received by the DC input terminals VB and VC.

[0061] In this embodiment, the 90° polarity switching logic circuit generates different 90° state voltages through a first control signal. These 90° state voltages can control the RF amplifier to perform phase shifting. Specifically, when the 90° state voltage is the first 90° state voltage, output terminal Vb90 outputs 880mV, output terminal Vc90 outputs 1.8V, and output terminals Vb0_90 and Vc0_90 output 0V. When the 90° state voltage is the second 90° state voltage, output terminals Vb90 and Vc90 output 0V, output terminal Vc0_90 outputs 1.8V, and output terminal Vb0_90 outputs 880mV.

[0062] Please see Figure 3 , Figure 3 This is a schematic diagram of the circuit structure of an RF amplifier provided in an embodiment of the present invention. The RF amplifier is a Cascode structure, which includes transmission lines TL1, TL2, TL3, and TL4, capacitors C1, C2, C3, C4, C5, and C6, resistors R1, R2, R3, and R4, transistors Q1, Q2, Q3, and Q4, inductors L1 and L2, a power input terminal VDD1, an input terminal IN, and an output terminal OUT1.

[0063] Specifically, the first end of inductor L1 is connected to the input terminal IN, and the second end of inductor L1 is connected to the first end of capacitor C1, which is grounded. The first end of capacitor C2 is connected to the input terminal IN, and the second end of capacitor C2 is connected to the first end of resistor R1 and the base of transistor Q1. The second end of resistor R1 is connected to the output terminal Vb0_90 of the 90° polarity switching logic circuit. The emitter of transistor Q1 is grounded, and the collector of transistor Q1 is connected to the emitter of transistor Q2. The base of transistor Q2 is connected to the first end of resistor R2, and the second end of resistor R2 is connected to the output terminal Vc0_90 of the 90° polarity switching logic circuit. The collector of transistor Q2 is connected to the first end of transmission line TL2, and the second end of transmission line TL2 is connected to the first ends of transmission lines TL1, TL3, and TL4. The second end of transmission line TL1 is connected to the input terminal IN. The source input terminal is VDD1. The second end of transmission line TL3 is connected to the first end of capacitor C6. The second end of capacitor C6 is connected to the output terminal OUT1. The second end of transmission line TL4 is connected to the collector of transistor Q4. The base of transistor Q4 is connected to the first end of resistor R4. The second end of resistor R4 is connected to the output terminal Vc90 of the 90° polarity switching logic circuit. The first end of capacitor C3 is connected to the input terminal IN. The second end of capacitor C3 is connected to the first end of resistor R3 and the base of transistor Q3. The second end of resistor R3 is connected to the output terminal Vb90 of the 90° polarity switching logic circuit. The emitter of transistor Q3 is grounded. The collector of transistor Q3 is connected to the first end of inductor L2 and capacitor C4. The second end of capacitor C4 is grounded. The second end of inductor L2 is connected to the emitter of transistor Q4 and the first end of capacitor C5. The second end of capacitor C5 is grounded.

[0064] In this embodiment, the RF amplifier receives external RF signals through the input terminal IN, and the RF amplifier receives the 90° state voltage output by the 90° polarity switching logic circuit. The 90° state voltage is composed of the voltage values ​​output from the output terminals Vb90, Vb0_90, Vc0_90, and Vc90. Specifically, when the 90° state voltage is the first 90° state voltage, that is, when output terminal Vb90 receives a voltage value of 880mV, output terminal Vc90 receives a voltage value of 1.8V, and output terminals Vb0_90 and Vc0_90 receive a voltage value of 0V, the RF amplifier is in a phase-shifted state, and the RF amplifier performs a 90° phase shift on the received RF signal; when the RF amplifier receives the second 90° state voltage of the 90° polarity switching logic circuit, that is, when output terminals Vb90 and Vc90 receive a voltage value of 0V, output terminal Vc0_90 receives a voltage value of 1.8V, and output terminal Vb0_90 receives a voltage value of 880mV, the RF amplifier is in a reference state, and the RF amplifier achieves a 0° phase shift of the RF signal.

[0065] Furthermore, the RF amplifier provided in this embodiment is an embedded π-type low-pass filter Cascode structure. Transistors Q2 and Q4 are common-base Cascode transistors in the RF amplifier's Cascode structure. The common-base Cascode transistors receive the voltage from the DC input terminal VC of the 90° polarity switching logic circuit as a bias voltage. Transistors Q1 and Q3 are common-emitter amplifier transistors in the RF amplifier's Cascode structure. The common-emitter amplifier receives the voltage from the DC input terminal VB of the 90° polarity switching logic circuit as a bias voltage. The power input terminal VDD1 is used to receive an external 2.5V first voltage as the power supply voltage of the RF amplifier. This embodiment, by designing the RF amplifier as a Cascode structure and providing a bias voltage for the RF amplifier, enables the digitally controlled phase shifter to achieve gain compensation, reduces insertion loss, and provides a small amount of gain.

[0066] Both the input balun and the quadrature signal generator are existing circuit structures. For the circuit structures of the input balun and the quadrature signal generator in this embodiment, please refer to [link to relevant documentation]. Figure 4 The quadrature signal generator is an all-pass filter network structure. The input balun includes a power input terminal VBIAS and a balun transformer. One end of the primary coil of the balun transformer is connected to the output terminal OUT1 of the RF amplifier, and the other end of the primary coil is grounded. The center tap of the secondary coil of the balun transformer is connected to the power input terminal VBIAS. The power input terminal VBIAS is used to receive a 1.8V third voltage provided externally as the power supply voltage for the input balun. The secondary coil of the balun transformer is connected to the quadrature signal generator, which includes a first output terminal I+, a second output terminal I-, a third output terminal Q+, and a fourth output terminal Q-. The quadrature signal generator is used to receive the pair of differential signals from the input balun and convert the pair of differential signals into four pairwise orthogonal differential signals. That is, the signal output from the first output terminal I+ is orthogonal to the signals output from the third output terminal Q+ and the fourth output terminal Q-, and the signal output from the second output terminal I- is orthogonal to the signals output from the third output terminal Q+ and the fourth output terminal Q-.

[0067] Traditional phase shifters use, for example Figure 5 The two analog adders shown require a quadrant switch to achieve phase shifting, so only half of the circuit operates normally in practice. When quadrant boundaries such as 0° and 90° are needed, it degenerates into only one pair of differential transistors operating. When the tail current switch switches, the base input impedance of transistors Q1 to Q8 changes. This impedance directly serves as the load for the quadrature signal generator, meaning the output load of the quadrature signal generator changes. Significant load changes severely affect the amplitude-phase balance of the quadrature signal, directly reducing the phase accuracy of the synthesized signal from the analog adder.

[0068] like Figure 6 As shown, in this embodiment of the invention, the analog adder adopts a dual-injection Gilbert structure, including capacitors C10, C11, C12, and C13, inductors L5, L6, L7, L8, L9, and L10, transistors Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16, NMOS transistors M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, and M32, DC signal input terminals VI and VQ, power input terminal VDD2, output terminal VON, and output terminal VOP.

[0069] The gate and drain of NMOS transistor M25 are shorted and connected to the gates of NMOS transistors M21 and M31, and then connected to the DC signal input terminal VI. The gate and drain of NMOS transistor M27 are shorted and connected to the gates of NMOS transistors M23 and M29, and then connected to the DC signal input terminal VQ. The gate and drain of NMOS transistor M26 are shorted and connected to the source of NMOS transistor M25, the gate of NMOS transistor M22, and the gate of NMOS transistor M32. The source of NMOS transistor M26 is grounded. The gate and drain of NMOS transistor M28 are shorted and connected to the source of NMOS transistor M27, the gate of NMOS transistor M24, and the gate of NMOS transistor M30. The source of NMOS transistor M28 is grounded. Ground; all sources of NMOS transistors M22, M24, M30, and M32 are grounded; the drain of NMOS transistor M22 is connected to the source of NMOS transistor M21; the drain of NMOS transistor M21 is connected to the emitters of transistors Q9 and Q10; the drain of NMOS transistor M24 is connected to the source of NMOS transistor M23; the drain of NMOS transistor M23 is connected to the emitters of transistors Q11 and Q12; the drain of NMOS transistor M30 is connected to the source of NMOS transistor M29; the drain of NMOS transistor M29 is connected to the emitters of transistors Q13 and Q14; the drain of NMOS transistor M32 is connected to the source of NMOS transistor M31; NM The drain of transistor M31 is connected to the emitters of transistors Q15 and Q16; the base of transistor Q9 and the base of transistor Q13 are connected to the first output terminal I+ of the quadrature signal generator; the base of transistor Q10 and the base of transistor Q14 are connected to the second output terminal I- of the quadrature signal generator; the base of transistor Q11 and the base of transistor Q16 are connected to the third output terminal Q+ of the quadrature signal generator; the base of transistor Q12 and the base of transistor Q15 are connected to the fourth output terminal Q- of the quadrature signal generator; the collectors of transistors Q9 and Q11, the first terminal of capacitor C10, and the first terminal of inductor L5 are connected; the collector of transistor Q10 is connected to the collector of transistor Q12. The first terminal of capacitor C11 and the first terminal of inductor L6 are connected; the collector of transistor Q13 is connected to the collector of transistor Q15, the first terminal of capacitor C12, and the first terminal of inductor L9; the collectors of transistor Q14 and Q16, the first terminal of capacitor C13, and the first terminal of inductor L10 are connected; the second terminals of all inductors L5, L6, L9, and L10 are connected to the power input terminal VDD2; the second terminal of capacitor C10 and the first terminal of inductor L8 are connected to the output terminal VON; the second terminal of capacitor C11 and the first terminal of inductor L7 are connected to the output terminal VOP; the second terminal of capacitor C12 is connected to the second terminal of inductor L7, and the second terminal of capacitor C13 is connected to the second terminal of inductor L8.

[0070] Specifically, the power input terminal VDD2 receives a 2.5V first voltage from an external source as its power supply. The output terminals VON and VOP output a pair of differential signals after phase shifting by the analog adder. The DC signal input terminal VI receives a second control signal from an external source, and the DC signal input terminal VQ receives a third control signal from an external source. These second and third control signals are provided by an external numerical control logic device, which includes four input terminals: A, B, C, and D. Each input terminal has two logic values: 1 and 0. The four input terminals can be combined to produce sixteen possible values. Each value corresponds to a different combination of the second and third control signals. Different combinations of the second and third control signals can control the analog adder to achieve different phase shift steps.

[0071] Table 1 is a mapping table of the values ​​of the ABCD input terminals of the off-chip numerical control logic unit provided in the embodiments of the present invention and the second and third control signals.

[0072] Numerical control logic (ABCD) Second control signal (V) Third control signal (V) 0000 0 1.024 0001 0.572 1.019 0010 0.655 1.008 0011 0.707 0.996 0100 0.753 0.981 0101 0.793 0.963 0110 0.830 0.941 0111 0.863 0.917 1000 0.891 0.891 1001 0.915 0.864 1010 0.936 0.837 1011 0.955 0.807 1100 0.970 0.778 1101 0.985 0.743 1110 0.996 0.707 1111 1.008 0.655

[0073] Table 1

[0074] In this embodiment, Table 1 shows sixteen possible values ​​for the second and third control signals. Each row represents the value of the second and third control signals corresponding to the values ​​at the ABCD input terminals. When the second control signal is 0V and the third control signal is 1.024V, the analog adder is in the reference state. The other fifteen combinations of the second and third control signals are all in the phase-shift state. Different combinations of the second and third control signals correspond to different phase-shift steps. The values ​​of the second and third control signals in the first row correspond to a minimum step of 5.625°. The phase-shift step corresponding to the values ​​in the next row increases by 5.625° compared to the previous row, thus achieving a phase-shift range of 5.625° to 90°.

[0075] This embodiment reduces the impedance variation at the input port by keeping the operating currents of the I-path (including the currents output from the first output terminal I+ and the second output terminal I- of the quadrature signal generator) and the Q-path (including the currents from the third output terminal Q+ and the fourth output terminal Q- of the quadrature signal generator) constant and by connecting the transistors in parallel. Specifically, when the circuit is balanced, transistors Q1 to Q8 have a higher characteristic frequency under a 4mA bias state, which can achieve better RF gain characteristics. Therefore, the operating current of the I-path is kept constant at I1 + I2 = 4mA under different phase shift states. The current flowing through NMOS transistors M23 and M24 in the Q-path is the same as that of NMOS transistors M29 and M30 (I2), and the current flowing through NMOS transistors M31 and M32 is the same as that of NMOS transistors M21 and M22 (I1). Therefore, the current in the Q-path also remains constant at 4mA. For the current output at the I+ terminal of the quadrature signal generator, Q9 and Q13 are connected in parallel as the load of the first output terminal I+, and the sum of the currents flowing through Q9 and Q13 is a constant of 4mA; similarly, Q10 and Q14 are connected in parallel as the load of the second output terminal I-, Q11 and Q16 are connected in parallel as the load of the third output terminal Q+, and Q12 and Q15 are the load of the fourth output terminal Q-.

[0076] Although the base input impedance of transistors Q1 to Q8 in different phase shift states will change due to different current states, this structure and current injection method can greatly reduce the magnitude of impedance changes.

[0077] like Figure 7 As shown, the dual-channel RF amplifier has a Cascode structure, including a power input terminal VDD3, an RF signal input terminal IN_N, an RF signal input terminal IN_P, an output terminal OUT2, transmission lines TL5, TL6, TL7, and TL8, a capacitor C7, resistors R5, R6, R7, and R8, and transistors Q5, Q6, Q7, and Q8. The power input terminal VDD3 receives an external 2.5V voltage as the power supply voltage. The RF signal input terminal IN_P is connected to the output terminal VOP of the analog adder. The output terminal OUT2 is the output terminal of the entire digitally controlled phase shifter. The dual-channel RF amplifier is used to shift the signal from the analog adder and output it through the output terminal OUT2.

[0078] Specifically, the base of transistor Q5 is connected to the first terminal of resistor R5 and the RF signal input terminal IN_N, respectively. The RF signal input terminal IN_N is connected to the output terminal VON of the analog adder. The second terminal of resistor R5 is connected to the output terminal Vb0_180 of the 180° polarity switching logic circuit. The emitter of transistor Q5 is grounded, and the collector of transistor Q5 is connected to the emitter of transistor Q6. The base of transistor Q6 is connected to the first terminal of resistor R6, and the second terminal of resistor R6 is connected to the output terminal Vc0_180 of the 180° polarity switching logic circuit. The collector of transistor Q6 is connected to the first terminal of transmission line TL6, and the second terminal of transmission line TL6 is connected to transmission lines TL5, TL7, and TL8. The first end of transmission line TL5 is connected to the power input terminal VDD3; the second end of transmission line TL7 is connected to the first end of capacitor C7, and the second end of capacitor C7 is connected to the output terminal OUT2; the second end of transmission line TL8 is connected to the collector of transistor Q8, the base of transistor Q8 is connected to the first end of resistor R8, and the second end of resistor R8 is connected to the output terminal Vc180 of the 180° polarity switching logic circuit; the base of transistor Q7 is connected to the first end of resistor R7 and the RF signal input terminal IN_P, the second end of resistor R7 is connected to the output terminal Vb180 of the 180° polarity switching logic circuit, the emitter of transistor Q7 is grounded, and the collector of transistor Q7 is connected to the emitter of transistor Q8.

[0079] In this embodiment, the dual-channel RF amplifier receives the 180° state voltage output by the 180° polarity switching logic circuit. When the 180° state voltage is the first 180° state voltage, the dual-channel RF amplifier is in a phase-shifted state, and the dual-channel RF amplifier performs a 180° phase shift on the received signal. When the dual-channel RF amplifier receives the second 180° state voltage from the 180° polarity switching logic circuit, the dual-channel RF amplifier is in a reference state, and the dual-channel RF amplifier performs a 0° phase shift on the received signal.

[0080] In the dual-channel RF amplifier provided in this embodiment, transistors Q6 and Q8 are common-base Cascode transistors in the Cascode structure of the dual-channel RF amplifier. The common-base Cascode transistors receive the voltage from the DC input terminal VC' of the 180° polarity switching logic circuit as a bias voltage. Transistors Q5 and Q7 are common-emitter amplifier transistors in the Cascode structure of the dual-channel RF amplifier. The common-emitter amplifier receives the voltage output from the DC input terminal VB' of the 180° polarity switching logic circuit as a bias voltage. The power input terminal VDD3 is used to receive the external 2.5V first voltage as the power supply voltage of the dual-channel RF amplifier. This embodiment achieves gain compensation for the digitally controlled phase shifter by designing the dual-channel RF amplifier as a Cascode structure and providing a bias voltage for the dual-channel RF amplifier, thereby reducing insertion loss and providing a small amount of gain.

[0081] like Figure 8 As shown, the 180° polarity switching logic circuit includes NMOS transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20; resistors R13, R14, R15, and R16; DC input terminals VB', VC', VP', and Sel180; and output terminals Vb180, Vb0_180, Vc180, and Vc0_180.

[0082] Specifically, PMOS transistor M19 and NMOS transistor M20 form inverter circuit INV2. Inverter circuit INV2 is used to receive the fourth control signal, generate and output the inverted level of the fourth control signal. Further, the gates of PMOS transistor M19 and NMOS transistor M20 are connected to the DC input terminal Sel180, the source and substrate of PMOS transistor M19 are connected to the DC input terminal VP', the source and substrate of NMOS transistor M20 are connected and grounded, and the drain of PMOS transistor M19 is connected to the drain of NMOS transistor M20 as the output terminal of the inverted level of the fourth control signal. For ease of description of subsequent circuit connections, the output terminal of the inverted level of the fourth control signal is labeled as... When the fourth control signal received by the DC input terminal Sel180 is a second-level signal, that is, a low level of 0V, the inverter circuit INV2 obtains a high level of 2.5V, which is the inverted level of the fourth control signal. The output voltage is a high level of 2.5V. When the fourth control signal is a first level signal, that is, when the fourth control signal is a high level of 2.5V, the inverter circuit INV2 obtains a low level of 0V, which is the inverted level of the fourth control signal. The output voltage is 0V. The gate of NMOS transistor M11 is connected to the DC input terminal Sel180, the source of NMOS transistor M11 is connected to the first terminal of resistor R13 and the source of NMOS transistor M12, the second terminal of resistor R13 is connected to the output terminal Vc180, the drain of NMOS transistor M11 is connected to the DC input terminal VC', and the gate of NMOS transistor M12 is connected to... The drain of NMOS transistor M12 is grounded; the gate of NMOS transistor M13 is connected to... The source of NMOS transistor M13 is connected to the first terminal of resistor R14 and the source of NMOS transistor M14. The second terminal of resistor R14 is connected to the output terminal Vc0_180. The drain of NMOS transistor M13 is connected to the DC input terminal VC'. The gate of NMOS transistor M14 is connected to the DC input terminal Sel180. The drain of NMOS transistor M14 is grounded. The gate of NMOS transistor M15 is connected to the DC input terminal Sel180. The source of NMOS transistor M15 is connected to the first terminal of resistor R15 and the source of NMOS transistor M16. The second terminal of resistor R15 is connected to the output terminal Vb180. The drain of NMOS transistor M15 is connected to the DC input terminal VB'. The gate of NMOS transistor M16 is connected to... The drain of NMOS transistor M16 is grounded, and the gate of NMOS transistor M17 is connected to... The source of NMOS transistor M17 is connected to the first terminal of resistor R16 and the source of NMOS transistor M18. The second terminal of resistor R16 is connected to the output terminal Vb0_180. The drain of NMOS transistor M17 is connected to the DC input terminal VB'. The gate of NMOS transistor M18 is connected to the DC input terminal Sel180. The drain of NMOS transistor M18 is grounded.

[0083] Specifically, the DC input terminal Sel180 is used to receive the fourth control signal, and the DC input terminal VP' is used to receive the external 2.5V first voltage as the power supply voltage for the 180° polarity switching logic circuit. The 180° polarity switching logic circuit receives the external 880mV second voltage and 1.8V third voltage through the DC input terminals VB' and VC' respectively to provide voltage for the dual-channel RF amplifier.

[0084] In this embodiment, the 180° polarity switching logic circuit generates different 180° state voltages through a fourth control signal. These 180° state voltages can control the dual-channel RF amplifier to perform phase shifting. Specifically, when the 180° state voltage is the first 180° state voltage, output terminal Vb180 outputs a voltage value of 880mV, output terminal Vc180 outputs a voltage value of 1.8V, and output terminals Vb0_180 and Vc0_180 output a voltage value of 0V. When the 180° state voltage is the second 180° state voltage, output terminals Vb180 and Vc180 output a voltage value of 0V, output terminal Vc0_180 outputs a voltage value of 1.8V, and output terminal Vb0_180 outputs a voltage value of 880mV.

[0085] Table 2 shows the parameter values ​​of each device in the phase shifter provided in this embodiment. The parameter values ​​for transistors and MOSFETs are expressed as length × width × number of parallel connections. The transmission line models all use E1 as the signal layer and LY as the reference layer, with the transmission line parameter values ​​expressed as the length × width of the signal line.

[0086]

[0087]

[0088] Table 2

[0089] The numerically controlled phase shifter in this embodiment uses SiGe BiCMOS technology. All resistors use models and layouts provided in the technology library. The transistors in the RF path, i.e., the transistors involved in RF signal processing throughout the numerically controlled phase shifter, are all high-characteristic-frequency heterojunction bipolar transistors (HBTs). The logic circuits and low-frequency DC structures such as current mirrors use field-effect transistors. All bipolar transistors use models and layouts provided in the technology library. All field-effect transistors use models and layouts provided in the technology library. All capacitors are MIM capacitors. The transmission lines use the designed layout and scattering parameter (S) parameters, and their reference layers are all selected as LY layer metal (material is aluminum). The metal used for the inductors uses the designed layout and S parameters. The metal used for the inductors is the top-layer thick metal provided by this technology. The balun uses the designed layout and S parameters. The metal used for the coils is the top and second-layer thick metal provided by this technology.

[0090] In the numerically controlled phase shifter provided in this embodiment, for the first phase shift module 10 and the third phase shift module 30, when the phase shift module is in the reference state, the gain value of the reference state is the insertion loss of the phase shift module. The difference between the phase shift state and the reference state is the phase shift amount of the phase shift module. The difference between the gain of the phase shift state and the gain of the reference state is the gain fluctuation, and the smaller the gain fluctuation, the better. For the second phase shift module 20, the second phase shift module 20 operates in the reference state when the second control signal is 0V and the third control signal is 1.024V. The other fifteen different combinations of the second and third control signals constitute the phase shift states. Since each phase shift module can be in its own state, there are a total of sixty-four different phase shift states for the entire phase shifter. When all three phase shift modules are in the reference state, the entire phase shifter is in the reference state, and the gain value at this time is the insertion loss of the numerically controlled phase shifter.

[0091] The difference in phase shift transmitted between each state of the phase shifter and the reference state is the phase shift amount of the phase shifter in that state. The difference between this phase shift amount and the phase shift amount under ideal conditions is the phase shift error in that state. The root mean square of the phase shift error in each state is the phase shift accuracy of the entire phase shifter. The smaller the phase shift accuracy, the higher the phase shift accuracy, and the more precise the phase control of the signal by the phase shifter. The gain difference between each state of the phase shifter and the reference state is the gain fluctuation in that state. The root mean square of the difference between the gain value in the sixty-four states and the average gain in all states is the gain accuracy of the entire phase shifter. The smaller the gain accuracy, the smaller the impact of the phase shifter on the gain fluctuation of the entire system. When the gain error is large, the phase shifter will cause mismatch in the system gain, which may seriously affect the gain adjustment circuit, attenuator, power amplifier, etc.

[0092] The high-precision numerically controlled phase shifter provided in this embodiment achieves sixty-four different phase shift states operating at 93–95 GHz using SiGe BiCMOS technology. Phase shift control is achieved by designing 90° and 180° polarity switching logic circuits to control the RF amplifier and dual-channel RF amplifier respectively. Different analog voltages are applied to the bases of different paths in the RF amplifier and dual-channel RF amplifier, and a certain power supply voltage bias is provided to the RF amplifier and dual-channel RF amplifier, thereby achieving gain compensation, reducing insertion loss, and providing a small amount of gain. Compared with traditional switching phase shifter structures, this effectively reduces insertion loss. While achieving 180° phase steps through the 180° polarity switching logic circuit, it also saves the output balun compared to traditional phase shifters, thus reducing the phase shifter area.

[0093] The high-precision CNC phase shifter provided in this embodiment is designed as a dual-injection Gilbert structure through analog adder, which effectively reduces the range of impedance variation at the load end of the quadrature signal, reduces the amplitude and phase imbalance of the quadrature signal under different states, and improves the phase shifting accuracy.

[0094] All simulation results for the numerically controlled phase shifter of this invention are post-simulation results. In this case, the bipolar transistors and field-effect transistors underwent parasitic parameter extraction in Cadence using the Parasitic Extraction (PEX) tool. The remaining passive components were electromagnetically simulated using the Momentum electromagnetic simulation tool in the Advanced Design System (ADS). The results obtained through this co-simulation method are closer to the actual results during chip testing.

[0095] Please see Figure 9 , Figure 9 This is a simulation result diagram of 64 phase states of a W-band high-precision CNC phase shifter using gain compensation technology provided by an embodiment of the present invention. In the 64 states, the phase shift control range of the CNC phase shifter is close to 360°, and at the center frequency of 94GHz, the phase distribution is uniform and the phase control is good.

[0096] Please see Figure 10 , Figure 10 This is a simulation result diagram of the root mean square error of the phase of the numerically controlled phase shifter provided in this embodiment of the invention. The calculation formula for the root mean square error of the phase is as follows:

[0097]

[0098] Where, Δθ RMS The root mean square phase error is θ, N is the number of phase shift states of the phase shifter (64 in this invention), and θ is the root mean square phase error. i and θ ideal The figures show the phase shift value of the phase shifter in the i-th phase-shift state and the phase shift value under ideal conditions, respectively. As can be seen from the figures, the root mean square error of the phase shifter is lowest at 94 GHz, with an error of 1.65°. Within the 93–95 GHz frequency band, the root mean square error of the phase shifter is less than 3°.

[0099] Please see Figure 11 , Figure 11 This is a simulation result diagram of 64 gain states of the numerically controlled phase shifter provided in the embodiment of the present invention. The gain fluctuation of the phase shifter in the 64 states of the numerically controlled phase shifter has an average insertion loss of less than 1.6dB. In the 93-95GHz frequency band, the absolute change of gain in different states is within 4dB.

[0100] Please see Figure 12, Figure 12 This is a simulation result diagram of the root mean square error of the gain of the numerically controlled phase shifter provided in the embodiment of the present invention. According to the formula for calculating the root mean square error of gain:

[0101]

[0102] Among them, A i Let A be the gain / insertion loss of the phase shifter in the i-th phase-shift state. avg This represents the average gain / insertion loss across all phase-shifted states.

[0103] As can be seen from the figure, the numerically controlled phase shifter has the lowest root mean square error of gain at 92 GHz, with a root mean square error of 0.92 dB. In the 93-95 GHz frequency band, the root mean square error of gain is less than 1.1 dB.

[0104] As shown in Figures 13(a) and 13(b), in Figure 13(a), the left vertical axis R represents the real part of the input impedance in the traditional structure, and the letter X represents the imaginary part of the input impedance in the traditional structure. In Figure 13(b), the left vertical axis Z... re Z represents the real part of the impedance of the numerically controlled phase shifter provided in this embodiment. im This represents the imaginary part of the impedance of the numerically controlled phase shifter provided in this embodiment. The distribution of the transistor input impedance under the same current scanning state for both structures is shown in the figure below. The range of variation for both the real and imaginary parts of the impedance in the new structure is significantly improved, especially the real part, which is reduced to 13% of the original. This improvement helps to enhance the quadrature accuracy of the quadrature signal generator under different phase shift states, thereby improving the overall phase shift accuracy of the phase shifter.

[0105] The numerically controlled phase shifter provided in this embodiment realizes phase shift control of signals in the frequency range of 93 to 95 GHz. The phase shift control range is 0 to 354.375°, the phase shift step value is 5.625°, and there are 64 phase shift states. The average insertion loss of the phase shifter is less than 1.6 dB, the root mean square error of the phase is less than 3°, and the root mean square error of the gain is less than 1.1 dB.

[0106] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A W-band high-precision numerically controlled phase shifter employing gain compensation technology, characterized in that, It includes a first phase shift module (10), a second phase shift module (20), and a third phase shift module (30) connected in sequence, wherein, The first phase shift module (10) includes a 90° polarity switching logic circuit and an RF amplifier. The 90° polarity switching logic circuit is used to receive an external first control signal and generate a 90° state voltage according to the first control signal. The input terminal of the RF amplifier is connected to the output terminal of the 90° polarity switching logic circuit. The RF amplifier is used to receive an external RF signal and the 90° state voltage, and to phase-shift the RF signal according to the 90° state voltage, and output the phase-shifted RF signal. The second phase shift module (20) includes an input balun, a quadrature signal generator, and an analog adder. The input terminal of the input balun is connected to the output terminal of the RF amplifier and is used to convert the phase-shifted RF signal into a pair of differential signals. The input terminal of the quadrature signal generator is connected to the output terminal of the input balun and is used to convert the pair of differential signals into four pairs of orthogonal differential signals. The analog adder is connected to the output terminal of the quadrature signal generator and is used to receive a second control signal and a third control signal from outside the chip, synthesize the four pairs of orthogonal differential signals into a pair of differential signals, and phase-shift the synthesized pair of differential signals according to the second control signal and the third control signal, and output the phase-shifted pair of differential signals. The third phase shift module (30) includes a 180° polarity switching logic circuit and a dual-channel RF amplifier. The output of the 180° polarity switching logic circuit is connected to the input of the dual-channel RF amplifier. The 180° polarity switching logic circuit is used to receive an external fourth control signal and generate a 180° state voltage according to the fourth control signal. The input of the dual-channel RF amplifier is connected to the output of the analog adder. The dual-channel RF amplifier is used to receive the 180° state voltage and perform a second phase shift on the phase-shifted pair of differential signals according to the 180° state voltage before outputting them. The 90° polarity switching logic circuit includes NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10; resistors R9, R10, R11, and R12; DC input terminals VB, VC, VP, and Sel90; and output terminals Vb90, Vc90, Vb0_90, and Vc0_90. The gates of the PMOS transistor M9 and the NMOS transistor M10 are connected to the DC input terminal Sel90. The source and substrate of the PMOS transistor M9 are connected to the DC input terminal VP. The source and substrate of the NMOS transistor M10 are connected to the ground terminal. The drain of the PMOS transistor M9 is connected to the drain of the NMOS transistor M10. The gate of NMOS transistor M1 is connected to the DC input terminal Sel90. The source of NMOS transistor M1 is connected to the first terminal of resistor R9 and the source of NMOS transistor M2. The drain of NMOS transistor M1 is connected to the DC input terminal VC. The gate of NMOS transistor M2 is connected to the drain of PMOS transistor M9. The drain of NMOS transistor M2 is grounded. The second terminal of resistor R9 is connected to the output terminal Vc90. The gate of NMOS transistor M3 is connected to the drain of PMOS transistor M9. The source of NMOS transistor M3 is connected to the first terminal of resistor R10 and the source of NMOS transistor M4. The drain of NMOS transistor M3 is connected to the DC input terminal VC. The gate of NMOS transistor M4 is connected to the DC input terminal Sel90. The drain of NMOS transistor M4 is grounded. The second terminal of resistor R10 is connected to the output terminal Vc0_90. The gate of NMOS transistor M5 is connected to the DC input terminal Sel90. The source of NMOS transistor M5 is connected to the first terminal of resistor R11 and the source of NMOS transistor M6. The drain of NMOS transistor M5 is connected to the DC input terminal VB. The gate of NMOS transistor M6 is connected to the drain of PMOS transistor M9. The drain of NMOS transistor M6 is grounded. The second terminal of resistor R11 is connected to the output terminal Vb90. The gate of NMOS transistor M7 is connected to the drain of PMOS transistor M9. The source of NMOS transistor M7 is connected to the first terminal of resistor R12 and the source of NMOS transistor M8. The drain of NMOS transistor M7 is connected to the DC input terminal VB. The gate of NMOS transistor M8 is connected to the DC input terminal Sel90. The drain of NMOS transistor M8 is grounded. The second terminal of resistor R12 is connected to the output terminal Vb0_90. The DC input terminal Sel90 is used to receive the first control signal, and the DC input terminal VP is used to receive the first voltage from outside the chip as the power supply voltage for the 90° polarity switching logic circuit. The 90° polarity switching logic circuit provides voltage to the RF amplifier by receiving the second and third voltages from outside the chip through the DC input terminals VB and VC, respectively. The RF amplifier is a Cascode structure, including transmission lines TL1, TL2, TL3, and TL4; capacitors C1, C2, C3, C4, C5, and C6; resistors R1, R2, R3, and R4; transistors Q1, Q2, Q3, and Q4; inductors L1 and L2; a power input terminal VDD1; an input terminal IN; and an output terminal OUT1. The first end of inductor L1 is connected to the input terminal IN, and the second end of inductor L1 is connected to the first end of capacitor C1, which is grounded. The first end of capacitor C2 is connected to the input terminal IN, and the second end of capacitor C2 is connected to the first end of resistor R1 and the base of transistor Q1. The second end of resistor R1 is connected to the output terminal Vb0_90 of the 90° polarity switching logic circuit. The emitter of transistor Q1 is grounded, and the collector of transistor Q1 is connected to the emitter of transistor Q2. The base of transistor Q2 is connected to the first end of resistor R2, and the second end of resistor R2 is connected to the output terminal Vc0_90 of the 90° polarity switching logic circuit. The collector of transistor Q2 is connected to the first end of transmission line TL2, and the second end of transmission line TL2 is connected to the first ends of transmission lines TL1, TL3, and TL4. The second end of transmission line TL1 is connected to the power input terminal VDD1. The second end of capacitor C3 is connected to the first end of capacitor C6. The second end of capacitor C6 is connected to the output terminal OUT1. The output terminal OUT1 is connected to one end of the primary coil in the input balun. The second end of transmission line TL4 is connected to the collector of transistor Q4. The base of transistor Q4 is connected to the first end of resistor R4. The second end of resistor R4 is connected to the output terminal Vc90 of the 90° polarity switching logic circuit. The first end of capacitor C3 is connected to the input terminal IN. The second end of capacitor C3 is connected to the first end of resistor R3 and the base of transistor Q3. The second end of resistor R3 is connected to the output terminal Vb90 of the 90° polarity switching logic circuit. The emitter of transistor Q3 is grounded. The collector of transistor Q3 is connected to the first end of inductor L2 and capacitor C4. The second end of capacitor C4 is grounded. The second end of inductor L2 is connected to the emitter of transistor Q4 and the first end of capacitor C5. The second end of capacitor C5 is grounded. The input terminal IN is used to receive the radio frequency signal. Transistor Q2 and transistor Q4 are common-base cascode transistors in the cascode structure of the radio frequency amplifier. The common-base cascode transistor receives the voltage from the 90° polarity switching logic circuit through the DC input terminal VC as a bias voltage. Transistor Q1 and transistor Q3 are common-emitter amplifier transistors in the cascode structure of the radio frequency amplifier. The common-emitter amplifier receives the voltage from the 90° polarity switching logic circuit through the DC input terminal VB as a bias voltage. The power input terminal VDD1 is used to receive the first voltage from outside the chip as the power supply voltage of the radio frequency amplifier. The dual-channel RF amplifier has a Cascode structure and includes a power input terminal VDD3, an RF signal input terminal IN_N, an RF signal input terminal IN_P, an output terminal OUT2, transmission lines TL5, TL6, TL7, and TL8, a capacitor C7, resistors R5, R6, R7, and R8, and transistors Q5, Q6, Q7, and Q8. The base of transistor Q5 is connected to the first terminal of resistor R5 and the RF signal input terminal IN_N. The RF signal input terminal IN_N is connected to the output terminal VON of the analog adder. The second terminal of resistor R5 is connected to the output terminal Vb0_180 of the 180° polarity switching logic circuit. The emitter of transistor Q5 is grounded, and the collector of transistor Q5 is connected to the emitter of transistor Q6. The base of transistor Q6 is connected to the first terminal of resistor R6. The second terminal of resistor R6 is connected to the output terminal Vc0_180 of the 180° polarity switching logic circuit. The collector of transistor Q6 is connected to the first terminal of transmission line TL6. The second terminal of transmission line TL6 is connected to the first terminals of transmission lines TL5, TL7, and TL8. The second terminal of transmission line TL5... The following connections are made: The first terminal of the transmission line TL7 is connected to the power input terminal VDD3; the second terminal of the transmission line TL7 is connected to the first terminal of the capacitor C7, and the second terminal of the capacitor C7 is connected to the output terminal OUT2; the second terminal of the transmission line TL8 is connected to the collector of the transistor Q8, the base of the transistor Q8 is connected to the first terminal of the resistor R8, and the second terminal of the resistor R8 is connected to the output terminal Vc180 of the 180° polarity switching logic circuit; the base of the transistor Q7 is connected to the first terminal of the resistor R7 and the RF signal input terminal IN_P, the RF signal input terminal IN_P is connected to the output terminal VOP of the analog adder, the second terminal of the resistor R7 is connected to the output terminal Vb180 of the 180° polarity switching logic circuit, the emitter of the transistor Q7 is grounded, and the collector of the transistor Q7 is connected to the emitter of the transistor Q8. Transistors Q6 and Q8 are common-base cascode transistors in the cascode structure of the dual-channel RF amplifier. The common-base cascode transistor receives the voltage of the DC input terminal VC' in the 180° polarity switching logic circuit as a bias voltage. Transistors Q5 and Q7 are common-emitter amplifier transistors in the cascode structure of the dual-channel RF amplifier. The common-emitter amplifier receives the voltage output from the DC input terminal VB' in the 180° polarity switching logic circuit as a bias voltage. The power input terminal VDD3 is used to receive the first voltage from outside the chip as the power supply voltage of the dual-channel RF amplifier. The dual-channel RF amplifier is used to shift the signal from the analog adder and output it through the output terminal OUT2.

2. The W-band high-precision numerically controlled phase shifter employing gain compensation technology according to claim 1, characterized in that, The first control signal includes a preset first level signal and a preset second level signal, and the 90° state voltage includes a first 90° state voltage and a second 90° state voltage, wherein, When the first control signal is the first level signal, the 90° polarity switching logic circuit generates the first 90° state voltage, and the RF amplifier realizes a 90° phase shift of the RF signal; when the first control signal is the second level signal, the 90° polarity switching logic circuit generates the second 90° state voltage, and the RF amplifier realizes a 0° phase shift of the RF signal.

3. The W-band high-precision numerically controlled phase shifter employing gain compensation technology according to claim 2, characterized in that, The second control signal and the third control signal are preset with different voltage values. The different voltage values ​​of the second control signal and the third control signal are used to control the analog adder to achieve different phase shift steps.

4. The W-band high-precision numerically controlled phase shifter employing gain compensation technology according to claim 3, characterized in that, The fourth control signal includes the first level signal and the second level signal, and the 180° state voltage includes a first 180° state voltage and a second 180° state voltage, wherein... When the fourth control signal is the first level signal, the 180° polarity switching logic circuit generates the first 180° state voltage, and the dual-channel RF amplifier performs a 180° phase shift on the received signal. When the fourth control signal is the second level signal, the 180° polarity switching logic circuit generates the second 180° state voltage, and the dual-channel RF amplifier performs a 0° phase shift on the received signal.

5. The W-band high-precision numerically controlled phase shifter employing gain compensation technology according to claim 1, characterized in that, The analog adder includes capacitors C10, C11, C12, and C13; inductors L5, L6, L7, L8, L9, and L10; transistors Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16; NMOS transistors M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, and M32; DC signal input terminals VI and VQ; power input terminal VDD2; and output terminals VON and VOP. The gate and drain of NMOS transistor M25 are shorted and connected to the gates of NMOS transistors M21 and M31, and then to the DC signal input terminal VI. The gate and drain of NMOS transistor M27 are shorted and connected to the gates of NMOS transistors M23 and M29, and then to the DC signal input terminal VQ. The gate and drain of NMOS transistor M26 are shorted and connected to the source of NMOS transistor M25, the gate of NMOS transistor M22, and the gate of NMOS transistor M32. The source of NMOS transistor M26 is grounded. The gate and drain of NMOS transistor M28 are shorted and connected to the source of NMOS transistor M27, the source of NMOS transistor M25, and M31, and then to the DC signal input terminal VQ. The gate of S-channel transistor M24 is connected to the gate of NMOS transistor M30, and the source of NMOS transistor M28 is grounded; all sources of NMOS transistors M22, M24, M30, and M32 are grounded; the drain of NMOS transistor M22 is connected to the source of NMOS transistor M21; the drain of NMOS transistor M21 is connected to the emitters of transistors Q9 and Q10; the drain of NMOS transistor M24 is connected to the source of NMOS transistor M23; the drain of NMOS transistor M23 is connected to the emitters of transistors Q11 and Q12; the drain of NMOS transistor M30 is connected to the source of NMOS transistor M24. The source of transistor M29 is connected to the source of transistor M31; the drain of transistor M29 is connected to the emitters of transistors Q13 and Q14; the drain of transistor M32 is connected to the source of transistor M31; the drain of transistor M31 is connected to the emitters of transistors Q15 and Q16; the base of transistor Q9 and the base of transistor Q13 are connected to the first output terminal I+ of the quadrature signal generator; the base of transistor Q10 and the base of transistor Q14 are connected to the second output terminal I- of the quadrature signal generator; the base of transistor Q11 and the base of transistor Q16 are connected to the third output terminal Q+ of the quadrature signal generator. The bases of transistors Q12 and Q15 are connected to the fourth output terminal Q- of the quadrature signal generator; the collectors of transistors Q9 and Q11, the first terminal of capacitor C10, and the first terminal of inductor L5 are connected; the collectors of transistors Q10 and Q12, the first terminal of capacitor C11, and the first terminal of inductor L6 are connected; the collectors of transistors Q13 and Q15, the first terminal of capacitor C12, and the first terminal of inductor L9 are connected; the collectors of transistors Q14 and Q16, the first terminal of capacitor C13, and the first terminal of inductor L10 are connected.The second terminals of all inductors L5, L6, L9, and L10 are connected to the power input terminal VDD2; the second terminal of capacitor C10 and the first terminal of inductor L8 are connected to the output terminal VON; the second terminal of capacitor C11 and the first terminal of inductor L7 are connected to the output terminal VOP; the second terminal of capacitor C12 is connected to the second terminal of inductor L7; and the second terminal of capacitor C13 is connected to the second terminal of inductor L8. The power input terminal VDD2 is used to receive the first voltage from outside the chip as a power source. The DC signal input terminal VI is used to receive the second control signal. The DC signal input terminal VQ is used to receive the third control signal. The output terminals VON and VOP are used to output a pair of differential signals after phase shifting by the analog adder.

6. The W-band high-precision numerically controlled phase shifter employing gain compensation technology according to claim 1, characterized in that, The 180° polarity switching logic circuit includes NMOS transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20; resistors R13, R14, R15, and R16; DC input terminals VB', VC', VP', and Sel180; and output terminals Vb180, Vb0_180, Vc180, and Vc0_180. The gate of the PMOS transistor M19 and the gate of the NMOS transistor M20 are connected to the DC input terminal Sel180. The source and substrate of the PMOS transistor M19 are connected to the DC input terminal VP'. The source and substrate of the NMOS transistor M20 are connected and grounded. The drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20. The gate of NMOS transistor M11 is connected to the DC input terminal Sel180. The source of NMOS transistor M11 is connected to the first terminal of resistor R13 and the source of NMOS transistor M12. The second terminal of resistor R13 is connected to the output terminal Vc180. The drain of NMOS transistor M11 is connected to the DC input terminal VC'. The gate of NMOS transistor M12 is connected to the drain of PMOS transistor M19, and the drain of NMOS transistor M12 is grounded. The gate of NMOS transistor M13 is connected to the drain of PMOS transistor M19. The source of NMOS transistor M13 is connected to the first terminal of resistor R14 and the source of NMOS transistor M14. The second terminal of resistor R14 is connected to the output terminal Vc0_180. The drain of NMOS transistor M13 is connected to the DC input terminal VC'. The gate of NMOS transistor M14 is connected to the DC input terminal Sel180, and the drain of NMOS transistor M14 is grounded. The gate of NMOS transistor M15 is connected to the DC input terminal Sel180. The source of NMOS transistor M15 is connected to the first terminal of resistor R15 and the source of NMOS transistor M16. The second terminal of resistor R15 is connected to the output terminal Vb180. The drain of NMOS transistor M15 is connected to the DC input terminal VB'. The gate of NMOS transistor M16 is connected to the drain of PMOS transistor M19. The drain of NMOS transistor M16 is grounded. The gate of NMOS transistor M17 is connected to the drain of PMOS transistor M19. The source of NMOS transistor M17 is connected to the first terminal of resistor R16 and the source of NMOS transistor M18. The second terminal of resistor R16 is connected to the output terminal Vb0_180. The drain of NMOS transistor M17 is connected to the DC input terminal VB'. The gate of NMOS transistor M18 is connected to the DC input terminal Sel180. The drain of NMOS transistor M18 is grounded. The DC input terminal Sel180 is used to receive the fourth control signal, and the DC input terminal VP' is used to receive the first voltage from outside the chip as the power supply voltage of the 180° polarity switching logic circuit. The 180° polarity switching logic circuit receives the second voltage and the third voltage from outside the chip through the DC input terminal VB' and the DC input terminal VC' respectively to provide voltage for the dual-channel RF amplifier.

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