A comparator self-calibration circuit applied to a high-speed time-domain interleaved analog-to-digital converter

Abstract

The application relates to a comparator self-calibration circuit applied to a high-speed time domain interleaving analog-to-digital converter, which is connected with a comparator module, and is used for automatically identifying the positive and negative of the output offset of the comparator module and realizing self-calibration of the offset through feedback in a calibration stage. The comparator self-calibration circuit comprises a logic generation module and an identification calibration module. The logic generation module generates a control signal according to a first clock signal and a first enable signal, and the control signal is input into the identification calibration module to control the working state of the identification calibration module. The input end of the identification calibration module is connected with the output end of the comparator module. The output end of the identification calibration module is connected with the input end of the comparator module. The application calibrates the offset based on an analog domain, and compared with a traditional analog domain calibration method, the required structure is simple, the occupied area and power consumption are smaller, meanwhile, according to the comparison result of the comparator, the positive and negative of the offset can be automatically identified by using the characteristics of a capacitor, and self-calibration of the offset of the comparator is realized.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital converters, and specifically relates to a comparator self-calibration circuit applied to a high-speed time-domain interleaved analog-to-digital converter. Background Technology

[0002] Analog-to-digital converters (ADCs) are an important component of modern electronic systems, widely used in wireless communication, optical communication, image processing, and other systems. Traditionally, high-speed ADCs are mostly implemented using flash architectures. However, as accuracy increases, a large number of comparators are required, which significantly increases system power consumption and area.

[0003] Therefore, to obtain ADCs with high sampling rates and medium to high accuracy, time-interleaved (TI) architectures are currently widely used. An ideal TI-ADC utilizes M sampling rates of F... S The sub-ADCs work in parallel to achieve M*F S The overall sampling rate and accuracy are the same as the sub-ADCs. However, in practice, due to manufacturing processes and other reasons, each sub-ADC may have different offsets, gains, and sampling times. These non-ideal factors can significantly degrade system performance. Offset primarily originates from the comparator. In TI-ADCs, each sub-ADC will generate offsets of varying magnitudes and polarities, leading to offset mismatch. Furthermore, when the number of channels is large, calibrating the offset of each sub-ADC becomes extremely difficult. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a comparator self-calibration circuit for a high-speed time-domain interleaved analog-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a comparator self-calibration circuit for a high-speed time-domain interleaved analog-to-digital converter, characterized in that it is connected to a comparator module and is used to automatically identify the positive or negative output offset of the comparator module during the calibration phase and achieve self-calibration of the offset through feedback.

[0006] The comparator self-calibration circuit includes: a logic generation module and an identification calibration module; wherein, the logic generation module generates a control signal according to a first clock signal and a first enable signal, and the control signal is input to the identification calibration module to control the working state of the identification calibration module;

[0007] The input terminal of the identification calibration module is connected to the output terminal of the comparator module; the output terminal of the identification calibration module is connected to the input terminal of the comparator module.

[0008] In one embodiment of the present invention, the logic generation module includes: a first inverter, a second inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a third NAND gate, and a tenth NAND gate;

[0009] The first clock signal is input to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter and the second input terminal of the tenth NAND gate, respectively.

[0010] The output of the second inverter is connected to the second input of the third NAND gate;

[0011] The first input terminal of the third NAND gate receives the first enable signal, the third input terminal of the third NAND gate is connected to the output terminal of the seventh inverter, and the output terminal of the third NAND gate is connected to the input terminal of the fourth inverter and the input terminal of the fifth inverter respectively.

[0012] The first input terminal of the tenth NAND gate is connected to the output terminal of the sixth inverter, the third input terminal of the tenth NAND gate receives the first enable signal, and the output terminal of the tenth NAND gate is connected to the input terminals of the eighth inverter and the ninth inverter respectively.

[0013] The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter; the output terminal of the eighth inverter is connected to the input terminal of the seventh inverter.

[0014] The output of the third NAND gate outputs a first control signal, and the first control signal generates a second control signal through the fourth inverter.

[0015] The output of the tenth NAND gate outputs a third control signal, and the third control signal generates a fourth control signal through the ninth inverter.

[0016] The first control signal, the second control signal, the third control signal, and the fourth control signal are input to the identification calibration module as control signals.

[0017] In one embodiment of the present invention, the identification calibration module includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, a twenty-second MOS transistor, a first capacitor, and a second capacitor;

[0018] The gates of the first MOS transistor and the second MOS transistor serve as the input terminals of the identification and calibration module. The source of the first MOS transistor is connected to the power supply voltage terminal, and the drain of the first MOS transistor is connected to the drain of the second MOS transistor, the gate of the third MOS transistor, and the gate of the sixth MOS transistor, respectively. The source of the second MOS transistor is connected to the ground terminal.

[0019] The source of the third MOS transistor is connected to the power supply voltage terminal, and the drain of the third MOS transistor is connected to the source of the fourth MOS transistor.

[0020] The drain of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the drain of the seventh MOS transistor, the drain of the thirteenth MOS transistor, and the drain of the seventeenth MOS transistor, respectively, and the gate of the fourth MOS transistor receives a second enable signal.

[0021] The gate of the fifth MOS transistor receives a first enable signal, the source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, and the source of the sixth MOS transistor is connected to the ground terminal.

[0022] The drain of the seventh MOS transistor is connected to the source of the eighth MOS transistor; the gate of the seventh MOS transistor receives the first enable signal; the source of the seventh MOS transistor is connected to the drain of the eighth MOS transistor, the source of the ninth MOS transistor, and the common-mode input terminal of the identification and calibration module; the gate of the eighth MOS transistor receives the second enable signal.

[0023] The source of the ninth MOS transistor is connected to the drain of the eleventh MOS transistor; the gate of the ninth MOS transistor receives the first control signal, and the drain of the ninth MOS transistor is connected to the source of the tenth MOS transistor; the gate of the eleventh MOS transistor receives the second control signal, and the source of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor.

[0024] The gate of the tenth MOS transistor receives the third control signal, the drain of the tenth MOS transistor is connected to the source of the twelfth MOS transistor, and the drain of the tenth MOS transistor serves as the second output terminal (VIPC) of the identification calibration module; the gate of the twelfth MOS transistor receives the fourth control signal.

[0025] The drain of the thirteenth MOS transistor is connected to the source of the fourteenth MOS transistor; the gate of the thirteenth MOS transistor receives the first control signal; the source of the thirteenth MOS transistor is connected to the first plate of the first capacitor and the drain of the fourteenth MOS transistor; the gate of the fourteenth MOS transistor receives the second control signal; the first plate of the second capacitor is connected to the second plate of the first capacitor, and the second plate of the second capacitor is connected to the ground terminal.

[0026] The source of the fifteenth MOS transistor is connected to the drain of the seventeenth MOS transistor; the gate of the fifteenth MOS transistor receives the second control signal, and the drain of the fifteenth MOS transistor is connected to the source of the sixteenth MOS transistor; the gate of the seventeenth MOS transistor receives the first control signal, and the source of the seventeenth MOS transistor is connected to the drain of the eighteenth MOS transistor.

[0027] The gate of the sixteenth MOS transistor receives a fourth control signal, and the drain of the sixteenth MOS transistor is connected to the source of the eighteenth MOS transistor, the source of the nineteenth MOS transistor, and the second plate of the first capacitor, respectively; the gate of the eighteenth MOS transistor receives the third control signal.

[0028] The source of the nineteenth MOS transistor is connected to the drain of the twenty-first MOS transistor; the drain of the nineteenth MOS transistor is connected to the source of the twentieth MOS transistor, and the gate of the nineteenth MOS transistor receives the first control signal; the source of the twenty-first MOS transistor is connected to the drain of the twenty-second MOS transistor, and the gate of the twenty-first MOS transistor receives the second control signal.

[0029] The gate of the twentieth MOS transistor receives the third control signal, the drain of the twentieth MOS transistor is connected to the source of the twelfth MOS transistor, and the drain of the twentieth MOS transistor serves as the first output terminal (VINC) of the identification calibration module; the gate of the twelfth MOS transistor receives the fourth control signal.

[0030] In one embodiment of the present invention, the first capacitor and the second capacitor are used to identify the positive or negative output offset of the comparator module and adjust the calibration speed.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0032] The present invention relates to a comparator self-calibration circuit for a high-speed time-domain interleaved analog-to-digital converter, comprising a logic generation module and an identification calibration module. It calibrates offset based on the analog domain, requiring a simpler structure and consuming less area and power compared to traditional analog domain calibration methods. Furthermore, by utilizing the characteristics of capacitors, the positive or negative offset can be automatically identified based on the comparator's comparison result, thereby controlling the input signals to the comparator at the VINC and VIPC output terminals of the identification calibration module to increase or decrease, thus reducing the comparator offset. The resulting comparator output further alters the output values ​​at VINC and VIPC, thereby achieving self-calibration of the comparator offset.

[0033] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0034] Figure 1 This is a logic generation module diagram of the calibration module circuit in an embodiment of the present invention;

[0035] Figure 2 This is a timing diagram of the calibration module circuit generated according to an embodiment of the present invention;

[0036] Figure 3 This is a diagram of the identification calibration module circuit of an embodiment of the present invention;

[0037] Figure 4 This is a circuit diagram of the comparator module according to an embodiment of the present invention. Detailed Implementation

[0038] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a comparator self-calibration circuit for a high-speed time-domain interleaved analog-to-digital converter proposed according to the present invention.

[0039] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0040] Example 1

[0041] Please refer to the above. Figure 1 and Figure 2 , Figure 1This is a logic generation module diagram of the calibration module circuit in an embodiment of the present invention; Figure 2 This is a timing diagram of the generation of the calibration module circuit in an embodiment of the present invention.

[0042] As shown in the figure, the comparator self-calibration circuit of the present invention, applied to a high-speed time-domain interleaved analog-to-digital converter, is characterized in that it is connected to the comparator module and is used to automatically identify the positive or negative output offset of the comparator module during the calibration stage and realize the self-calibration of the offset through feedback.

[0043] In this embodiment, the comparator self-calibration circuit includes: a logic generation module and an identification calibration module; wherein, the logic generation module generates a control signal according to a first clock signal CLK and a first enable signal CAL, and the control signal is input to the identification calibration module to control the working state of the identification calibration module; the input terminal VIN of the identification calibration module is connected to the output terminal of the comparator module; the output terminal of the identification calibration module is connected to the input terminal of the comparator module.

[0044] In this embodiment, the logic generation module includes: a first inverter I1, a second inverter I2, a fourth inverter I4, a fifth inverter I5, a sixth inverter I6, a seventh inverter I7, an eighth inverter I8, a ninth inverter I9, a third NAND gate I3, and a tenth NAND gate I10.

[0045] In one optional implementation, the first inverter I1 receives a first clock signal CLK at its input terminal, and the output terminal of the first inverter I1 is connected to the input terminal of the second inverter I2 and the second input terminal of the tenth NAND gate I10, respectively; the output terminal of the second inverter I2 is connected to the second input terminal of the third NAND gate I3.

[0046] In an optional implementation, the first input terminal of the third NAND gate I3 receives the first enable signal CAL, the third input terminal of the third NAND gate I3 is connected to the output terminal of the seventh inverter I7, and the output terminal of the third NAND gate I3 is connected to the input terminal of the fourth inverter I4 and the input terminal of the fifth inverter I5, respectively.

[0047] In an optional implementation, the first input of the tenth NAND gate I10 is connected to the output of the sixth inverter I6, the third input of the tenth NAND gate I10 receives the first enable signal CAL, and the output of the tenth NAND gate I10 is connected to the input of the eighth inverter I8 and the input of the ninth inverter I9.

[0048] In an optional implementation, the output of the fifth inverter I5 is connected to the input of the sixth inverter I6; and the output of the eighth inverter I8 is connected to the input of the seventh inverter I7.

[0049] In one optional implementation, the output of the third NAND gate I3 outputs a first control signal N1O, which generates a second control signal N1I through the fourth inverter I4; the output of the tenth NAND gate I10 outputs a third control signal N2O, which generates a fourth control signal N2I through the ninth inverter I9.

[0050] In an optional implementation, the first control signal N1O, the second control signal N1I, the third control signal N2O, and the fourth control signal N2I serve as control signal inputs to the identification and calibration module. When both the first clock signal CLK and the first enable signal CAL are high, the first control signal N1O is low and the third control signal N2O is high.

[0051] Please see Figure 4 , Figure 4 This is a circuit diagram of the comparator module according to an embodiment of the present invention. As shown in the figure, the comparator module adopts a three-stage structure. The first two stages are preamplifiers, which preamplify the input signals respectively, and the last stage performs latching output.

[0052] Please see Figure 3 , Figure 3 This is a diagram of the identification and calibration module of the calibration module circuit in an embodiment of the present invention.

[0053] As shown in the figure, the identification and calibration module of this embodiment includes: a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, an eighteenth MOSFET M18, a nineteenth MOSFET M19, a twentieth MOSFET M20, a twenty-first MOSFET M21, a twenty-second MOSFET M22, a first capacitor C1, and a second capacitor C2.

[0054] In this embodiment, the first MOS transistor M1, the third MOS transistor M3, the fourth MOS transistor M4, the seventh MOS transistor M7, the ninth MOS transistor M9, the tenth MOS transistor M10, the thirteenth MOS transistor M13, the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, and the twentieth MOS transistor M20 are all PMOS transistors.

[0055] The second MOSFET M2, the fifth MOSFET M5, the sixth MOSFET M6, the eighth MOSFET M8, the eleventh MOSFET M11, the twelfth MOSFET M12, the fourteenth MOSFET M14, the fifteenth MOSFET M15, the sixteenth MOSFET M16, the twenty-first MOSFET M21, and the twenty-second MOSFET M22 are all NMOS transistors.

[0056] In an optional implementation, the gates of the first MOSFET M1 and the second MOSFET M2 serve as the input terminal VIN of the identification calibration module. The source of the first MOSFET M1 is connected to the power supply voltage terminal VDD. The drain of the first MOSFET M1 is connected to the drain of the second MOSFET M2, the gate of the third MOSFET M3, and the gate of the sixth MOSFET M6, respectively. The source of the second MOSFET M2 is connected to the ground terminal GND.

[0057] In one optional implementation, the source of the third MOSFET M3 is connected to the power supply voltage terminal VDD, and the drain of the third MOSFET M3 is connected to the source of the fourth MOSFET M4; the drain of the fourth MOSFET M4 is connected to the drain of the fifth MOSFET M5, the drain of the seventh MOSFET M7, the drain of the thirteenth MOSFET M13 and the drain of the seventeenth MOSFET M17, respectively, and the gate of the fourth MOSFET M4 receives the second enable signal CALB.

[0058] In an optional implementation, the gate of the fifth MOSFET M5 is connected to the first enable signal CAL, the source of the fifth MOSFET M5 is connected to the drain of the sixth MOSFET M6, and the source of the sixth MOSFET M6 is connected to the ground terminal GND.

[0059] In one optional implementation, the drain of the seventh MOSFET M7 is connected to the source of the eighth MOSFET M8; the gate of the seventh MOSFET M7 receives a first enable signal CAL; the source of the seventh MOSFET M7 is connected to the drain of the eighth MOSFET M8, the source of the ninth MOSFET M9, and the common-mode input terminal VCOM of the identification and calibration module; the gate of the eighth MOSFET M8 receives a second enable signal CALB.

[0060] In one optional implementation, the source of the ninth MOSFET M9 is connected to the drain of the eleventh MOSFET M11; the gate of the ninth MOSFET M9 receives a first control signal N10, and the drain of the ninth MOSFET M9 is connected to the source of the tenth MOSFET M10; the gate of the eleventh MOSFET M11 receives a second control signal N1I, and the source of the eleventh MOSFET M11 is connected to the drain of the twelfth MOSFET M12.

[0061] In one optional implementation, the gate of the tenth MOSFET M10 is input with a third control signal N2O, the drain of the tenth MOSFET M10 is connected to the source of the twelfth MOSFET M12, and the drain of the tenth MOSFET M10 serves as the second output terminal VIPC of the identification calibration module; the gate of the twelfth MOSFET M12 is input with a fourth control signal N2I.

[0062] In one optional embodiment, the drain of the thirteenth MOSFET M13 is connected to the source of the fourteenth MOSFET M14; the gate of the thirteenth MOSFET M13 receives a first control signal N1O; the source of the thirteenth MOSFET M13 is connected to the first plate of the first capacitor C1 and the drain of the fourteenth MOSFET M14; the gate of the fourteenth MOSFET M14 receives a second control signal N1I; the first plate of the second capacitor C2 is connected to the second plate of the first capacitor C1, and the second plate of the second capacitor C2 is connected to the ground terminal GND.

[0063] In one optional implementation, the source of the fifteenth MOSFET M15 is connected to the drain of the seventeenth MOSFET M17; the gate of the fifteenth MOSFET M15 receives a second control signal N1I, and the drain of the fifteenth MOSFET M15 is connected to the source of the sixteenth MOSFET M16; the gate of the seventeenth MOSFET M17 receives a first control signal N1O, and the source of the seventeenth MOSFET M17 is connected to the drain of the eighteenth MOSFET M18.

[0064] In one optional implementation, the gate of the sixteenth MOSFET M16 receives a fourth control signal N2I, and the drain of the sixteenth MOSFET M16 is connected to the source of the eighteenth MOSFET M18, the source of the nineteenth MOSFET M19, and the second plate of the first capacitor C1, respectively; the gate of the eighteenth MOSFET M18 receives a third control signal N2O.

[0065] In one optional implementation, the source of the nineteenth MOSFET M19 is connected to the drain of the twenty-first MOSFET M21; the drain of the nineteenth MOSFET M19 is connected to the source of the twentieth MOSFET M20, and the gate of the nineteenth MOSFET M19 receives a first control signal N10; the source of the twenty-first MOSFET M21 is connected to the drain of the twenty-second MOSFET M22, and the gate of the twenty-first MOSFET M21 receives a second control signal N1I.

[0066] In one optional implementation, the gate of the twentieth MOSFET M20 is input with a third control signal N2O, the drain of the twentieth MOSFET M20 is connected to the source of the twentieth MOSFET M22, and the drain of the twentieth MOSFET M20 serves as the first output terminal VINC of the identification calibration module; the gate of the twentieth MOSFET M22 is input with a fourth control signal N2I.

[0067] It is worth noting that the first capacitor C1 and the second capacitor C2 are used to identify the positive and negative values ​​of the comparator module's output offset and adjust the calibration speed.

[0068] For example, if the value of the first capacitor C1 remains unchanged while the value of the second capacitor C2 increases, then the value of the output of the first output terminal VINC and the second output terminal VIPC of the identification calibration module will increase in each cycle, that is, the step size of its change will be changed. For a fixed comparator offset value, the value of the change in each cycle increases, and the overall calibration time is shortened.

[0069] In the specific implementation process, when the first clock signal CLK and the first enable signal CAL are both high, the corresponding second clock signal CLKB and the second enable signal CALB are both low. At this time, the comparator module is in working state. The comparator module obtains the comparison results VOUTN and VOUTP based on the values ​​of the first output terminal VINC and the second output terminal VIPC of the input recognition calibration module and the values ​​of the first input signal VINN and the second input signal VINP of the comparator. Simultaneously, the logic generation module begins to operate, generating control signals, where N1O is low, N2O is high, N1I is high, and N2I is low. At this time, the ninth MOSFET M9, the eleventh MOSFET M11, the thirteenth MOSFET M13, the fourteenth MOSFET M14, the fifteenth MOSFET M15, the seventeenth MOSFET M17, the nineteenth MOSFET M19, and the twenty-first MOSFET M21 are all turned off, while the tenth MOSFET M10, the twelfth MOSFET M12, the sixteenth MOSFET M16, the eighteenth MOSFET M18, the twentieth MOSFET M20, and the twenty-second MOSFET M22 are all turned on, and the identification and calibration module operates. The value of VINC at the first output terminal of the identification and calibration module increases or decreases according to the comparison result of the comparator module, and gradually approaches the common-mode value after multiple comparisons and calibrations. The value of VIPC at the second output terminal of the identification and calibration module will eventually remain near the common-mode value. When the values ​​of the first output terminal VINC and the second output terminal VIPC of the identification calibration module change, they in turn affect the gain of the first-stage preamplifier of the comparator module when the first clock signal CLK is high in the next cycle, thus affecting its comparison output result. Again, the comparison result of the comparator module is fed back to the identification calibration module, further changing the values ​​of the first output terminal VINC and the second output terminal VIPC of the identification calibration module. This cycle repeats to calibrate the offset of the comparator module. After calibration, the comparison result of the comparator will be approximately 50%. At this point, the values ​​of the first output terminal VINC and the second output terminal VIPC of the identification calibration module fluctuate within a small range.

[0070] When both the first clock signal CLK and the first enable signal CAL go low, the identification calibration module is in a hold state, meaning it is not working. The values ​​of its first output VINC and second output VIPC do not change with the comparison output of the comparator module, but remain at the fixed values ​​of the previous cycle. Conversely, if it is in a non-hold state, the identification calibration module is working, and the values ​​of its first output VINC and second output VIPC change with the comparison output of the comparator module.

[0071] The comparator self-calibration circuit of this invention, applied to a high-speed time-domain interleaved analog-to-digital converter, includes a logic generation module and an identification calibration module. It calibrates offset based on the analog domain, requiring a simpler structure and consuming less area and power compared to traditional analog domain calibration methods. Simultaneously, utilizing the characteristics of capacitors, it can automatically identify the positive or negative offset based on the comparator's comparison result, thereby controlling the input signals to the comparator at the VINC and VIPC output terminals of the identification calibration module to rise or fall, thus reducing the comparator's offset. The resulting comparator output further alters the output values ​​at VINC and VIPC, thereby achieving self-calibration of the comparator offset.

[0072] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0073] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A comparator self-calibration circuit for a high-speed time-domain interleaved analog-to-digital converter, characterized in that, Connected to the comparator module, it is used to automatically identify the positive or negative sign of the output offset of the comparator module during the calibration phase and realize the self-calibration of the offset through feedback; The comparator self-calibration circuit includes: a logic generation module and an identification calibration module; The logic generation module generates a control signal based on a first clock signal (CLK) and a first enable signal (CAL), and the control signal is input to the identification calibration module to control the working state of the identification calibration module. The input terminal (VIN) of the identification calibration module is connected to the output terminal of the comparator module; the output terminal of the identification calibration module is connected to the input terminal of the comparator module. The logic generation module includes: a first inverter (I1), a second inverter (I2), a fourth inverter (I4), a fifth inverter (I5), a sixth inverter (I6), a seventh inverter (I7), an eighth inverter (I8), a ninth inverter (I9), a third NAND gate (I3), and a tenth NAND gate (I10); the first inverter (I1) receives the first clock signal (CLK) at its input terminal, and its output terminal is connected to the input terminal of the second inverter (I2) and the tenth NAND gate (I10), respectively. The second input terminal of the third NAND gate (I10) is connected to the second input terminal of the third NAND gate (I3); the first enable signal (CAL) is input to the first input terminal of the third NAND gate (I3); the third input terminal of the third NAND gate (I3) is connected to the output terminal of the seventh inverter (I7); the output terminal of the third NAND gate (I3) is connected to the input terminal of the fourth inverter (I4) and the input terminal of the fifth inverter (I5); the first input terminal of the tenth NAND gate (I10) is connected to the sixth NAND gate (I5). The output of inverter (I6) is connected to the third input of the tenth NAND gate (I10), which receives the first enable signal (CAL). The output of the tenth NAND gate (I10) is connected to the input of the eighth inverter (I8) and the ninth inverter (I9). The output of the fifth inverter (I5) is connected to the input of the sixth inverter (I6). The output of the eighth inverter (I8) is connected to the input of the seventh inverter (I7). The output of the third NAND gate (I3) outputs the first control signal (N1). The first control signal (N1O) generates a second control signal (N1I) through the fourth inverter (I4); the output of the tenth NAND gate (I10) outputs a third control signal (N2O), which generates a fourth control signal (N2I) through the ninth inverter (I9); the first control signal (N1O), the second control signal (N1I), the third control signal (N2O), and the fourth control signal (N2I) are input as control signals to the identification calibration module; The identification and calibration module includes: a first MOSFET (M1), a second MOSFET (M2), a third MOSFET (M3), a fourth MOSFET (M4), a fifth MOSFET (M5), a sixth MOSFET (M6), a seventh MOSFET (M7), an eighth MOSFET (M8), a ninth MOSFET (M9), a tenth MOSFET (M10), an eleventh MOSFET (M11), a twelfth MOSFET (M12), a thirteenth MOSFET (M13), a fourteenth MOSFET (M14), a fifteenth MOSFET (M15), a sixteenth MOSFET (M16), a seventeenth MOSFET (M17), an eighteenth MOSFET (M18), a nineteenth MOSFET (M19), a twentieth MOSFET (M20), a twenty-first MOSFET (M21), a twenty-second MOSFET (M22), a first capacitor (C1), and a second capacitor (C2); The gates of the first MOSFET (M1) and the second MOSFET (M2) serve as the input terminals (VIN) of the identification calibration module. The source of the first MOSFET (M1) is connected to the power supply voltage terminal (VDD), and the drain of the first MOSFET (M1) is connected to the drain of the second MOSFET (M2), the gate of the third MOSFET (M3), and the gate of the sixth MOSFET (M6). The source of the second MOSFET (M2) is connected to the ground terminal (GND). The source of the third MOSFET (M3) is connected to the power supply voltage terminal (VDD), and the drain of the third MOSFET (M3) is connected to the source of the fourth MOSFET (M4). The drain of the S-channel MOSFET (M4) is connected to the drains of the fifth MOSFET (M5), the seventh MOSFET (M7), the thirteenth MOSFET (M13), and the seventeenth MOSFET (M17), respectively. The gate of the fourth MOSFET (M4) receives a second enable signal (CALB); the gate of the fifth MOSFET (M5) receives a first enable signal (CAL); the source of the fifth MOSFET (M5) is connected to the drain of the sixth MOSFET (M6), and the source of the sixth MOSFET (M6) is connected to the ground terminal (GND); the drain of the seventh MOSFET (M7) is connected to the source of the eighth MOSFET (M8); the seventh MOSFET... The gate of the S-MOSFET (M7) receives the first enable signal (CAL). The source of the seventh MOSFET (M7) is connected to the drain of the eighth MOSFET (M8), the source of the ninth MOSFET (M9), and the common-mode input (VCOM) of the identification and calibration module. The gate of the eighth MOSFET (M8) receives the second enable signal (CALB). The source of the ninth MOSFET (M9) is connected to the drain of the eleventh MOSFET (M11). The gate of the ninth MOSFET (M9) receives the first control signal (N1O). The drain of the ninth MOSFET (M9) is connected to the source of the tenth MOSFET (M10). The eleventh MOSFET... The gate of the eleventh MOS transistor (M11) receives the second control signal (N1I), and the source of the eleventh MOS transistor (M11) is connected to the drain of the twelfth MOS transistor (M12). The gate of the tenth MOS transistor (M10) receives the third control signal (N2O), and the drain of the tenth MOS transistor (M10) is connected to the source of the twelfth MOS transistor (M12). The drain of the tenth MOS transistor (M10) serves as the second output terminal (VIPC) of the identification calibration module. The gate of the twelfth MOS transistor (M12) receives the fourth control signal (N2I). The drain of the thirteenth MOS transistor (M13) is connected to the source of the fourteenth MOS transistor (M14).The gate of the thirteenth MOSFET (M13) receives the first control signal (N1O), and the source of the thirteenth MOSFET (M13) is connected to the first plate of the first capacitor (C1) and the drain of the fourteenth MOSFET (M14); the gate of the fourteenth MOSFET (M14) receives the second control signal (N1I); the first plate of the second capacitor (C2) is connected to the second plate of the first capacitor (C1), and the second plate of the second capacitor (C2) is connected to the ground terminal (GND); the source of the fifteenth MOSFET (M15) is connected to the tenth MOSFET. The drain of the seventh MOS transistor (M17); the gate of the fifteenth MOS transistor (M15) receives the second control signal (N1I), and the drain of the fifteenth MOS transistor (M15) is connected to the source of the sixteenth MOS transistor (M16); the gate of the seventeenth MOS transistor (M17) receives the first control signal (N1O), and the source of the seventeenth MOS transistor (M17) is connected to the drain of the eighteenth MOS transistor (M18); the gate of the sixteenth MOS transistor (M16) receives the fourth control signal (N2I), and the drain of the sixteenth MOS transistor (M16) is connected to... The source of the eighteenth MOS transistor (M18), the source of the nineteenth MOS transistor (M19), and the second plate of the first capacitor (C1) are connected; the gate of the eighteenth MOS transistor (M18) receives the third control signal (N2O); the source of the nineteenth MOS transistor (M19) is connected to the drain of the twenty-first MOS transistor (M21); the drain of the nineteenth MOS transistor (M19) is connected to the source of the twentieth MOS transistor (M20), and the gate of the nineteenth MOS transistor (M19) receives the first control signal (N1O); the twenty-first MOS transistor (M21)... 1) The source of the MOSFET is connected to the drain of the twelfth MOSFET (M22), and the gate of the eleventh MOSFET (M21) receives the second control signal (N1I); the gate of the twentieth MOSFET (M20) receives the third control signal (N2O), the drain of the twentieth MOSFET (M20) is connected to the source of the twelfth MOSFET (M22), and the drain of the twentieth MOSFET (M20) serves as the first output terminal (VINC) of the identification calibration module; the gate of the twelfth MOSFET (M22) receives the fourth control signal (N2I).

2. The comparator self-calibration circuit for a high-speed time-domain interleaved analog-to-digital converter according to claim 1, characterized in that, The first capacitor (C1) and the second capacitor (C2) are used to identify the positive or negative output offset of the comparator module and adjust the calibration speed.

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