Two-Stage Linear-Exponential Incremental High-Resolution Analog-to-Digital Converter Employing Second-Order Noise Coupling Technique

Abstract

The present invention relates to the technical field of analog integrated circuits, and discloses a two-stage linear-exponential IADC circuit adopting a second-order noise coupling technique, which includes an analog modulator, a digital filter, and a switching switch. It can implement a second-order noise coupling path, and realizes an ultra-high exponential signal accumulation speed through the second-order noise coupling path. By applying the second-order noise coupling path to a two-step IADC and combining it with a first-order IADC, it has good performance, and a corresponding decimation filter is constructed to achieve linear accumulation and exponential accumulation respectively in two stages.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and particularly to a two-stage linear-exponential incremental high-resolution analog-to-digital converter (IADC) using a second-order noise coupling technique. Background Art

[0002] High-resolution analog-to-digital converters (ADCs) are widely used in various fields, such as instrumentation, bio-signal extraction, and industrial measurement. This wide range of applications has also brought huge challenges and higher requirements to them. ΣΔ ADCs are widely used high-precision ADCs, and their oversampling and noise shaping characteristics endow them with excellent high-precision characteristics. However, due to the infinite impulse response (IIR) characteristics of ΣΔ ADCs, they have inherent problems such as high latency and complex decimation filters. The incremental high-resolution analog-to-digital converter (abbreviated as IADC) adds a global reset to the memory element on the basis of ΣΔ ADC, so that it has the characteristics of finite impulse response (FIR). Therefore, the IADC can achieve very low latency and can be multiplexed. At the same time, it can greatly simplify the structure of the decimation filter. In addition, it also exhibits excellent characteristics such as being almost unaffected by idle noise. Therefore, the IADC shows great potential in the field of high-precision ADCs and has good research prospects.

[0003] For a first-order IADC, to achieve N-bit resolution requires 2N clock cycles in each conversion period [see reference [1] Z. Tan, C.-H. Chen, Y. Chae and G. C. Temes, "Incremental Delta-Sigma ADCs: A Tutorial Review," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4161-4173, Dec. 2020.]. The conversion time is too long, resulting in a very slow speed. For a high-order IADC, although the conversion time is shortened, the input-related thermal noise is introduced due to different weights for each input, and the higher the order, the greater the weight difference and the greater the thermal noise. Therefore, the size of the input capacitance must be increased to ensure that the signal-to-noise ratio (hereinafter abbreviated as SNR) does not decrease, which increases the power consumption and area overhead. In addition, the different weights will also greatly reduce the data weighting average (DWA) effect. Therefore, how to make the IADC achieve high precision without sacrificing too much speed is a very critical issue.

[0004] To suppress the input-referred thermal noise and improve the technical effectiveness of DWA while achieving a high signal-to-quantization-noise ratio (hereinafter referred to as SQNR), References 2 / 3 [See Reference [2] B. Wang, S.-W. Sin, S.-P. U., F. Maloberti and R. P. Martins, "A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental ΣΔ ADC With 256 Clock Cycles in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 54, no. 4, pp. 1161-1172, April 2019.

[0005] [3]B. Wang, S.-W. Sin, S.-P. U., F. Maloberti and R. P. Martins, "A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS," 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019, pp. 117-120.] proposed a two-stage linear-exponential IADC, which is implemented by noise coupling in [2] and by positive feedback in [3]. For the structure in [2], in the first stage, it works as a first-order IADC, and the input weights are equalized through multiple cycles of linear accumulation, thus greatly reducing the input-referred thermal noise and improving the effectiveness of DWA. In the second stage, by turning on the noise coupling path [see [4]: K. Lee, M. R. Miller and G. C. Temes, "An 8.1mW, 82dB delta-sigma ADC with 1.9MHz BW and -98dB THD," 2008 IEEE Custom Integrated Circuits Conference, 2008], the exponential accumulation of quantization noise is achieved in only a few cycles. This accumulation method is extremely fast and can bring a significant improvement in SQNR, but it will also cause a large difference in input weights. However, since the exponential accumulation only runs for a few cycles, this negative impact is greatly weakened. Finally, assuming the use of a 1-bit precision quantizer, a signal-to-quantization noise ratio SQNR of 120dB is achieved with only 256 clock cycles and a thermal noise penalty factor of only 1.03 [see [2]]. Summary of the Invention

[0006] The object of the present invention is to provide a two-stage linear-exponential IADC circuit adopting a second-order noise coupling technique, which realizes a second-order noise coupling path and achieves an extremely high exponential signal accumulation speed through the second-order noise coupling path. The second-order noise coupling path is applied to a two-step IADC and used in combination with a first-order IADC, so as to have good performance, and a corresponding decimation filter is constructed to realize linear accumulation and exponential accumulation in two stages respectively.

[0007] The technical solution of the present invention is as follows:

[0008] A two-stage linear-exponential IADC circuit using second-order noise coupling technology, characterized by comprising an analog modulator, a digital filter, and a switching switch;

[0009] The analog modulator includes a loop filter, a Flash quantizer, and a digital-to-analog converter (DAC). The loop filter consists of an integrator, a second-order noise coupling path, a first node, a second node, a third node, and a fourth node. The second-order coupling path has two branches. The first branch has a delay unit, and the second branch has two delay units. The first node has two input terminals and one output terminal. The second node has one output terminal and three input terminals. The third node and the fourth node (116) each have two input terminals and one output terminal;

[0010] The switching switch includes a first switching switch, a second switching switch, a third switching switch (33), and a fourth switching switch;

[0011] The input terminal of the integrator is connected to the output terminal of the first node. The output terminal of the integrator is connected to the second input terminal of the second node through the first switching switch. The output terminal of the second node is divided into two paths. One path is connected to the input terminal of the Flash quantizer, and the other path is connected to the first input terminal of the third node. The output terminal of the Flash quantizer is divided into three paths: the first path is connected to the second input terminal of the third node, the second path is connected to the second input terminal of the first node through the digital-to-analog converter. The output terminal of the third node is divided into two paths: one path is connected to the first input terminal of the fourth node (116) through the first branch, and the other path is connected to the second input terminal of the fourth node through the second branch. The output terminal of the four nodes is connected to the third input terminal of the second node;

[0012] The output terminal of the Flash quantizer is connected to the input terminal of the digital filter;

[0013] The digital filter is formed by cascading a decimation filter and a flip-flop. The output terminal of the flip-flop is the output terminal of the device.

[0014] The decimation filter is an IIR filter controlled by a switching switch and has different connection relationships in two stages. In the first stage, there is only one register. For each clock cycle, after the input is added to the output of the register, the sum is stored in the register and output. In the second stage, there are two registers (assumed to be register 1 and register 2). For each clock cycle, the input, 3× the output of register 1, and -4× the output of register 2 are added together, and the sum is stored in register 1 and output. The output of register 1 is stored in register 2.

[0015] The working process of the present invention is divided into two stages. In the first stage, the loop filter consists of an integrator, and in the second stage, it consists of a second-order noise coupling path.

[0016] The analog modulator includes three basic modules: a loop filter, a Flash quantizer, and a digital-to-analog convertor (DAC). The loop filter consists of an integrator in the first stage and a second-order noise coupling path in the second stage. The integrator and the second-order coupling path have the same reset signal. There are two branches in the second-order coupling path, and each of these two branches has a delay unit / two delay units.

[0017] The digital filter is formed by cascading a decimation filter and a flip-flop. The reset signal is consistent with the reset signal in the loop filter. The decimation filter matches the analog modulator by connecting different branches at different stages. The decimation filter accumulates the digital signals output by the quantizer according to different weights.

[0018] The switching switch is responsible for realizing the switching between the two stages. In the first stage, the integrator is connected into the loop, and in the second stage, the second-order noise coupling path is connected into the loop. And according to different stages, different feedback branches of the decimation filter are connected to achieve correspondence with the analog modulator.

[0019] The beneficial effects of the present invention compared with the prior art are as follows:

[0020] 1) By combining a low-order IADC and a high-order IADC, the present invention not only has the advantages of high SQNR of the high-order IADC but also retains the ability of the low-order IADC to suppress input-related thermal noise, and ensures that the DWA technology has high effectiveness.

[0021] 2) The second-order noise coupling technology proposed by the present invention achieves a faster accumulation speed compared with the first-order noise coupling. Therefore, when reaching the same accuracy, fewer clock cycles are consumed. In addition, using the second-order noise coupling does not lose the ability to suppress thermal noise and the effectiveness of DWA. In the case of achieving the same thermal noise penalty coefficient and SQNR, the present invention has a faster speed, thus increasing the bandwidth. Brief Description of the Drawings

[0022] Figure 1 It is a schematic structural diagram of a two-stage linear-exponential IADC using the first-order noise coupling technology;

[0023] Figure 2It is a schematic structural diagram of a two-stage linear-exponential IADC circuit that adopts second-order noise coupling technology but does not disconnect the integrator from the loop in the second stage and thus has a lower maximum stable amplitude (MSA).

[0024] Figure 3 Schematic structural diagram of an embodiment of a two-stage linear-exponential IADC circuit of the present invention that adopts second-order noise coupling technology;

[0025] Figure 4 Compares the variation of the signal-to-quantization noise ratio (SQNR) with the increase of the input amplitude for three structures: a first-order noise-coupled linear-exponential IADC, a second-order noise-coupled linear-exponential IADC with a low MSA, and a second-order noise-coupled linear-exponential IADC implemented by the present invention;

[0026] Figure 5 Shows the relationship between the SQNR of the present invention and the number of clock cycles in the first and second stages;

[0027] Figure 6 Shows the relationship between the thermal noise penalty coefficient of the present invention and the number of clock cycles in the first and second stages;

[0028] Figure 7 Compares the data weighted averaging (DWA) effectiveness of four structures: the IADC implemented by the present invention, a first-order noise-coupled linear-exponential IADC, a linear-exponential IADC implemented by positive feedback, and an ordinary third-order IADC;

[0029] Figure 8 Displays the simulation results of the power spectral density (PSD). Detailed implementation manners

[0030] The following details the specific implementation manners of the present invention in conjunction with the accompanying drawings and preferred embodiments. The technical solutions in the embodiments of the present invention are described in detail and completely below in conjunction with the diagrams in the embodiments of the present invention. The embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] As Figure 3 shown, it is the schematic structural diagram and timing description of an embodiment of a two-stage linear-exponential IADC circuit of the present invention that adopts second-order noise coupling technology. Its basic connection relationship is: in the first stage, the difference between the input signal and the output of the feedback DAC is input to a transfer function of In the integrator, after the output of the integrator is added to the input signal, the sum is input to the quantizer for quantization. Then, the digital code obtained after quantization is input to the decimation filter for filtering. After that, the filtered digital code is decimated to obtain the output result. In the second stage, the difference between the input and output of the quantizer, i.e., the quantization noise, is input to the second-order noise coupling path. The path includes two branches with one delay and two delays respectively. The sum of the outputs of the two branches is the output of the second-order noise coupling path. After its output is added to the input signal, the sum is input to the quantizer. The output digital code of the quantizer is also input to the decimation filter for filtering and then decimated to obtain the output. The basic principle of the present invention is: similar to the traditional ΔΣ ADC, the residual of the input signal and the feedback signal passes through the loop filter and the quantizer. The generated digital signal is, on the one hand, converted into an analog signal through the digital-to-analog converter and fed back to the input end of the loop filter, and on the other hand, input to the digital filter. The only difference is that the IADC resets the memory element at the beginning of each conversion cycle. In the first stage, by turning off the switching switch, the entire architecture operates as a first-order IADC within N L clock cycles. Subsequently, in the second stage, with the switching switch turned on, the integrator is disconnected from the circuit, and the second-order noise coupling path is connected to the circuit, so that the analog modulator exponentially accumulates the quantization noise within the remaining N E clock cycles. At the same time, the digital filter also realizes exponential counting through switch switching, corresponding to the conversion of the analog modulator.

[0032] Its main modules include:

[0033] Analog modulator, switching switch, digital filter.

[0034] The modules included in the analog modulator are: loop filter, quantizer, digital-to-analog converter (DAC). Among them, the loop filter is a linear integrator in the first stage and a second-order noise coupling path in the second stage. Compared with Figure 1 the first-order noise coupling path used in -1 ), the second-order noise coupling in this embodiment can achieve a noise transfer function of (1 - 2z 2 ), which is equivalent to Figure 1 the square of the noise transfer function in e when k is taken as 1, the same as the power function accumulation. The higher the order of the exponential accumulation, the faster the accumulation speed. For the second-order exponential accumulation, the signal weight in the time domain is shown in Equation (1). It can be seen that its weight is equivalent to a first-order term multiplied by an exponential term. For the first-order noise coupling, there is only an exponential term in the weight. It can be seen that the second-order exponential realizes a faster accumulation speed. In addition, we can choose a larger k e to achieve a faster accumulation speed. In this example, k will be used in the subsequent description.e The case of = 1.

[0035] W(i) = i × a i-1 (1)

[0036] The working mode of the switching switch: In the two - stage linear - exponential IADC adopting the second - order noise coupling technology provided by the embodiments of the present invention, the switching switch is responsible for the conversion of two stages. According to the basic principle that the signal weight in the first stage increases linearly and the signal weight in the second stage increases exponentially, different architectures for the two stages are constructed. The respective signal weights and the sum of signal weights in the two stages are shown in equations (2) and (3) respectively.

[0037]

[0038] It should be noted that in the second stage, the integrator needs to be disconnected from the circuit to increase the MSA. If the integrator in the second stage is still connected in the circuit, the overall structure is as Figure 2 shown, although the noise transfer function in its second stage is (1 - z -1 )(1 - 2z -1 ) 2 , and a faster accumulation speed can be obtained through a higher order, but a higher order usually means a smaller MSA. Figure 4 Set N L and N E to 118 and 10 respectively to simulate the MSA. The second - order coupling 2 corresponds to the case where the integrator in the second stage is connected to the circuit. It can be seen that its MSA is much worse than that of the first - order coupling and the second - order coupling 1 proposed by the present invention. Therefore, a very high - resolution quantizer needs to be used to ensure the stability of the system, increasing a large amount of area and power consumption overhead. Therefore, the present invention selects to disconnect the integrator in the second stage, sacrificing some precision in exchange for better MSA.

[0039] The SQNR of the two - stage linear - exponential IADC adopting the second - order noise coupling technology provided by the embodiments of the present invention can be obtained as shown in equation (4). Where L is the number of quantizer levels, and the larger L is, the higher the resolution of the quantizer. It can be seen that a larger M can be obtained through a faster accumulation speed, thereby achieving a higher SQNR. In addition to the SQNR, the thermal noise penalty factor is also a very critical index. Calculate the thermal noise penalty factor (Penalty Factor) according to equation (5), where N is the oversampling rate, N = N L + N EFor the thermal noise penalty coefficient, the higher the degree of normalization of the input weights, the smaller its value. Therefore, for a first-order IADC with completely equal input weights, the minimum thermal noise penalty coefficient of 1 can be obtained. In the embodiments of the present invention, by operating in the first stage as a first-order IADC, the thermal noise penalty coefficient can be made to approach 1 greatly.

[0040] SQNR = 20×log 10 M(L - 1)(4)

[0041]

[0042] Figure 5 Figure 6 respectively show the relationship between the achievable SQNR and the thermal noise penalty coefficient of the two-stage linear-exponential IADC using the second-order noise coupling technology provided by the embodiments of the present invention and the number of clock cycles in the two stages. It can be seen that both SQNR and the thermal noise penalty coefficient are positively correlated with N E and N L Therefore, in order to achieve a good balance between SQNR and the thermal noise penalty coefficient, a suitable pair of N E and N L .

[0043] The digital filter described above: The IADC provided by the embodiments of the present invention uses a direct type-II IIR filter as the decimation filter, and realizes different transfer functions to match the analog modulator by activating different feedback branches at different stages. In the first stage, the transfer function is The decimation filter works as a counter. In the second stage, the transfer function is The decimation filter realizes second-order exponential accumulation.

[0044] The two-stage linear-exponential IADC using the second-order noise coupling technology described above: Taking the IADC architecture that realizes exponential accumulation with base 2 in the second stage as an example to implement the circuit design. To ensure a large MSA, a quantizer with 5-bit precision is used in this example. In the embodiments of the present invention, we expect to achieve an SQNR of 120 dB and a thermal noise penalty coefficient of 1.06. Therefore, according to Figure 5 and Figure 6 select N L = 75, N E = 6. Figure 8 shows the power spectral density (PSD) simulation results in this case. It can be seen that it achieves an SQNR of about 120 dB, which is consistent with the theoretical value. Considering the DAC mismatch problem, the proposed ADC, the first-order noise-coupled linear-exponential IADC, the linear-exponential IADC implemented with positive feedback, and the traditional third-order IADC are respectively simulated and verified. By setting appropriate oversampling ratios, N Eand N L , so that the SQNR that can be achieved by the four architectures under ideal conditions is 120 dB, Figure 7 shows the comparison of the simulation results of the four architectures. It can be seen that after adding DAC mismatch, the signal-to-noise distortion ratio (SNDR) that can be achieved by the present invention is not much different from that of the first-order linear-exponential architecture and is significantly higher than that of the third-order IADC, indicating that it has high DWA effectiveness. In addition, through the comparison in the following table, it can be found that under the conditions of the same signal-to-noise distortion ratio SNDR, thermal noise penalty coefficient, and DWA effectiveness, the IADC architecture implemented by the present invention consumes more than 50 fewer clock cycles than the first-order noise coupling architecture, thus having a faster speed, that is, a wider bandwidth, and having more advantages in practical applications.

[0045]

[0046] As mentioned above, the above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A two-stage linear-exponential IADC circuit using second-order noise coupling technology, characterized in that It includes an analog modulator, a digital filter, and a switching switch; The analog modulator includes a loop filter, a Flash quantizer, and a digital-to-analog converter. The loop filter consists of an integrator, a second-order noise coupling path, a first node, a second node, a third node, and a fourth node. The second-order coupling path has two branches. The first branch has a delay unit, and the second branch has two delay units. The first node has two input terminals and one output terminal. The second node has one output terminal and three input terminals. The third node and the fourth node each have two input terminals and one output terminal; The switching switch includes a first switching switch, a second switching switch, a third switching switch, and a fourth switching switch; The input terminal of the integrator is connected to the output terminal of the first node. The output terminal of this integrator is connected to the second input terminal of the second node through the first switching switch. The output terminal of the second node is divided into two paths. One path is connected to the input terminal of the Flash quantizer, and the other path is connected to the first input terminal of the third node. The output terminal of this Flash quantizer is divided into three paths: the first path is connected to the second input terminal of the third node, the second path is connected to the second input terminal of the first node through the digital-to-analog converter. The output terminal of the third node is divided into two paths: one path is connected to the first input terminal of the fourth node through the first branch, and the other path is connected to the second input terminal of the fourth node through the second branch. The output terminal of this four-node is connected to the third input terminal of the second node; The output terminal of the Flash quantizer is connected to the input terminal of the digital filter, The digital filter is formed by cascading a decimation filter and a flip-flop. The output terminal of the flip-flop is the output terminal of this device; The decimation filter is an IIR filter controlled by a switching switch. In the first stage, there is only one register. For each clock cycle, after the input is added to the output of the register, the sum is stored in the register and output. In the second stage, there are two registers, namely register 1 and register 2. For each clock cycle, the input, 3 times the output of register 1, and -4 times the output of register 2 are added together. The sum is stored in register 1 and output, and the output of register 1 is stored in register 2; In the first stage, the loop filter consists of an integrator. In the second stage, the loop filter consists of a second-order noise coupling path. The switching switch is responsible for implementing the switching between the two stages. In the first stage, the integrator is connected into the loop. In the second stage, the second-order noise coupling path is connected into the loop, and different feedback branches of the decimation filter are connected according to different stages to achieve correspondence with the analog modulator.

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