A method and system for detecting frame headers of configurable multi-rate SDH lines

Abstract

This invention discloses a frame header detection method and system for configurable multi-rate SDH lines, relating to the field of optical synchronous digital transmission. The method includes: acquiring the serial data stream rate; converting the serial data stream on the SDH line into parallel data; truncating the parallel data into eight segments of different lengths and buffering them into eight corresponding registers; performing bit alignment based on the A1 byte hit result of the data of different lengths; aligning the bit-aligned parallel data based on the A2 byte and outputting a frame header signal; judging the accuracy of each frame header and outputting valid data frames and valid frame header signals; obtaining the current system state based on the output valid frame header signals, and determining that a true frame header has been detected when the current system state is a fixed-frame state. This invention can flexibly configure frame headers for detecting multiple SDH rates, has high accuracy in frame header detection, and continuously provides indications of fixed-frame and frame loss states.

Description

Technical Field

[0001] This invention relates to the field of optical synchronous digital transmission, and specifically to a frame header detection method and system for configurable multi-rate SDH lines. Background Technology

[0002] Synchronous Digital Hierarchy (SDH) technology is widely used in today's society. Commonly used speeds include STM-1, STM-4, STM-16, and STM-64 (collectively referred to as STM-N, N=4). n Extracting STM-N frames from data streams of different rates is a very important task.

[0003] In SDH network systems, the STM-N frame format is used for transmission. The frame location character in the STM-N frame structure consists of 3 × N A1 bytes followed by 3 × N A2 bytes. The A1 byte is the binary number 11110110 (hexadecimal 0xF6), and the A2 byte is the binary number 00101000 (hexadecimal 0x28). The frame location character, composed of A1 and A2 bytes, is located at the beginning of the STM-N structure. Correctly detecting the STM-N frame header is essential for successfully processing the overhead bytes and payload contained within the STM-N frame.

[0004] In traditional frame header detection methods, low-speed STM-1 lines use serial data frame header detection for framing, while high-speed STM-N lines use either a method that compares the shifted parallel data with the A1A2 characters or a method that compares the parallel data with the shifted A1A2 characters for framing. Furthermore, if a transmission error occurs after framing, the frame header detection result becomes invalid, and this framing status should be reported and the frame header re-detected. Summary of the Invention

[0005] The present invention provides a frame header detection method and system for configurable multi-rate SDH lines, which can provide the frame status to the system in real time and re-detect STM-N frames while satisfying the SDH protocol.

[0006] To achieve the above-mentioned objectives, the technical solution adopted by this invention is as follows:

[0007] A frame header detection method for configurable multi-rate SDH lines is provided, comprising the following steps:

[0008] S1. Obtain the serial data stream rate and convert the serial data stream on the SDH line into parallel data;

[0009] S2. Extract 8 segments of parallel data of different lengths and cache them in the corresponding 8 registers. Perform bit alignment based on the result of hitting byte A1 with data of different lengths.

[0010] S3. Align the bit-aligned parallel data based on A2 bytes and output the frame header signal;

[0011] S4. Determine the accuracy of each frame header and output valid data frames and valid frame header signals;

[0012] S5. Obtain the current system state based on the output valid frame header signal, and determine that a real frame header has been detected when the current system state is fixed frame state.

[0013] Furthermore, the serial data stream rates include 155.52 Mbps, 622.08 Mbps, 2.488 Gbps, and 9.953 Gbps, corresponding to the STM-1 frame structure, STM-4 frame structure, STM-16 frame structure, and STM-64 frame structure, respectively; the frame positioning character in the STM-N frame structure consists of 3 × N A1 bytes followed by 3 × N A2 bytes, where N = 1, 4, 16, 64.

[0014] Furthermore, the specific method for converting the serial data stream on the SDH line into a parallel data stream is as follows:

[0015] When the serial data stream rate is 155.52 Mbps and 622.08 Mbps, the bit width of the parallel data is set to 8 bits; when the serial data stream rate is 2.488 Gbps, the bit width of the parallel data is set to 32 bits; and when the serial data stream rate is 9.953 Gbps, the bit width of the parallel data is set to 64 bits.

[0016] Furthermore, the specific method of step S2 includes the following sub-steps:

[0017] S2-1. Determine if the current parallel data has a bit width of 8 bits. If so, concatenate two adjacent parallel data into 16-bit parallel data and proceed to step S2-2; otherwise, proceed directly to step S2-2.

[0018] S2-2. Truncate the current parallel data into lengths of 15 bits, 14 bits, 13 bits, 12 bits, 11 bits, 10 bits, 9 bits, and 8 bits respectively, and cache them into reg1, reg2, reg3, reg4, reg5, reg6, reg7, and reg8 respectively; where reg represents a register.

[0019] S2-3. Right-align the data in the 8 registers, and starting from the rightmost column, take the data in the mth column as a data group, that is, get 8 groups of 8-bit data groups Qn, n = 8 - m, m = 1, 2, 3, 4, 5, 6, 7, 8;

[0020] S2-4. Match the 8 groups of 8-bit data Qn with the A1 byte respectively, and use the n value of the matched data group Qn as the offset n;

[0021] S2-5. Shift the current parallel data left by n bits according to the offset n;

[0022] S2-6. Determine whether the parallel data after the shift is a continuous A1 byte. If so, use the parallel data after the current shift as the bit-aligned parallel data and complete the bit alignment; otherwise, use the parallel data after the current shift as the truncation object and return to step S2-2.

[0023] Furthermore, the specific method of step S3 includes the following sub-steps:

[0024] S3-1. Determine if the initial bit width of the parallel data is 8 bits. If so, output the frame header signal directly and proceed to step S4; otherwise, search for byte A2 in the bit-aligned parallel data and proceed to step S3-2.

[0025] S3-2. Determine if there is non-A1 byte data in the data before the first A2 byte. If so, determine that the frame header is incorrect, take the parallel data after the current bit alignment as the truncation object and return to step S2; otherwise, obtain the corresponding offset according to the current alignment, i.e. the second offset, and proceed to step S3-3.

[0026] S3-3. Shift the currently bit-aligned parallel data to the left according to the second offset, and output a frame header signal to indicate the frame header position of each frame.

[0027] Furthermore, if the alignment involves M A1 bytes, the corresponding offset is set to 8 × M bits.

[0028] Furthermore, the specific method for step S4 is as follows:

[0029] Continuously match 3×N A1 bytes and 3×N A2 bytes byte by byte. If a match is successful, output a valid data frame and a valid frame header signal; otherwise, use the current parallel data after left shifting according to the second offset as the truncation object and return to step S2.

[0030] Furthermore, the specific method for step S5 is as follows:

[0031] Initialize the system state before the frame is correctly determined to be the frame out-of-synchronization state;

[0032] In the frame out-of-sync state, if the correct frame header is detected continuously within 250us, the current system state is changed to fixed frame state.

[0033] In the fixed frame state, if an erroneous frame header is detected continuously within 625us, the current system state is changed to the frame out-of-synchronization state, the current transmitted data is determined to be invalid data, the current parallel data after left shift according to the second offset is taken as the interception object, and the process returns to step S2.

[0034] If the frame synchronization failure state lasts for more than 3ms, the current system state will be changed to frame loss state.

[0035] If the correct frame header is detected continuously within 1.25ms in the frame loss state, the frame loss state will be changed to the fixed frame state.

[0036] When the current system state is fixed frame state, the current frame header is determined to be a correct frame header, and the currently transmitted data is all valid data, thus completing the frame header detection of the SDH line.

[0037] A frame header detection system for configurable multi-rate SDH lines is provided, which includes a CDR clock recovery module, a bit alignment module, a configuration management module, a frame header detection module, a frame header monitoring module, and a frame status determination module.

[0038] The CDR clock recovery module is used to convert serial data streams on SDH lines into parallel data;

[0039] The bit alignment module is used to extract eight different lengths of parallel data output by the CDR clock recovery module and cache them into eight corresponding registers. Bit alignment is performed based on the result of the data of different lengths hitting the A1 byte.

[0040] The configuration management module is used to configure the CDR clock recovery module and bit alignment module according to the serial data stream rate;

[0041] The frame header detection module is used to align the bit-aligned parallel data output by the bit alignment module based on A2 bytes and output the frame header signal.

[0042] The frame header monitoring module is used to judge the accuracy of each frame header output by the frame header detection module and output valid data frames and valid frame header signals.

[0043] The frame-fixed state determination module is used to obtain the current system state based on the valid frame header signal output by the frame header monitoring module, and to determine that a real frame header has been detected when the current system state is a frame-fixed state.

[0044] The beneficial effects of the present invention are as follows: the present invention can flexibly configure frame headers for detecting various SDH rates, and has high accuracy in frame header detection, and continuously provides indications of frame fixing and frame loss status. Attached Figure Description

[0045] Figure 1 This is a flowchart illustrating the method.

[0046] Figure 2 This is a diagram illustrating the bit alignment operation.

[0047] Figure 3 A schematic diagram illustrating the operation to obtain 8 groups of 8-bit data;

[0048] Figure 4 A logical diagram illustrating how to obtain the current system state based on the output valid frame header signal;

[0049] Figure 5 This is a functional block diagram of the system. Detailed Implementation

[0050] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0051] like Figure 1 As shown, the frame header detection method for configurable multi-rate SDH lines includes the following steps:

[0052] S1. Obtain the serial data stream rate and convert the serial data stream on the SDH line into parallel data;

[0053] S2. Extract 8 segments of parallel data of different lengths and cache them in the corresponding 8 registers. Perform bit alignment based on the result of hitting byte A1 with data of different lengths.

[0054] S3. Align the bit-aligned parallel data based on A2 bytes and output the frame header signal;

[0055] S4. Determine the accuracy of each frame header and output valid data frames and valid frame header signals;

[0056] S5. Obtain the current system state based on the output valid frame header signal, and determine that a real frame header has been detected when the current system state is fixed frame state.

[0057] The serial data stream rates include 155.52 Mbps, 622.08 Mbps, 2.488 Gbps and 9.953 Gbps, corresponding to the STM-1 frame structure, STM-4 frame structure, STM-16 frame structure and STM-64 frame structure, respectively; the frame positioning character in the STM-N frame structure consists of 3 × N A1 bytes followed by 3 × N A2 bytes, where N = 1, 4, 16, 64.

[0058] The specific method for converting serial data streams on SDH lines into parallel data streams is as follows: when the serial data stream rate is 155.52 Mbps and 622.08 Mbps, the bit width of the parallel data is set to 8 bits; when the serial data stream rate is 2.488 Gbps, the bit width of the parallel data is set to 32 bits; and when the serial data stream rate is 9.953 Gbps, the bit width of the parallel data is set to 64 bits.

[0059] like Figure 3 As shown, the specific method of step S2 includes the following sub-steps:

[0060] S2-1. Determine if the current parallel data has a bit width of 8 bits. If so, concatenate two adjacent parallel data into 16-bit parallel data and proceed to step S2-2; otherwise, proceed directly to step S2-2.

[0061] S2-2. Truncate the current parallel data into lengths of 15 bits, 14 bits, 13 bits, 12 bits, 11 bits, 10 bits, 9 bits, and 8 bits respectively, and cache them into reg1, reg2, reg3, reg4, reg5, reg6, reg7, and reg8 respectively; where reg represents a register.

[0062] S2-3. Right-align the data in the 8 registers, and starting from the rightmost column, take the data in the mth column as a data group, that is, get 8 groups of 8-bit data groups Qn, n = 8 - m, m = 1, 2, 3, 4, 5, 6, 7, 8, n is 0 to 7;

[0063] S2-4. Match the 8 groups of 8-bit data Qn with the A1 byte respectively, and use the n value of the matched data group Qn as the offset n;

[0064] S2-5. Shift the current parallel data left by n bits according to the offset n;

[0065] S2-6. Determine whether the parallel data after the shift is a continuous A1 byte. If so, use the parallel data after the current shift as the bit-aligned parallel data and complete the bit alignment; otherwise, use the parallel data after the current shift as the truncation object and return to step S2-2.

[0066] The specific method of step S3 includes the following sub-steps:

[0067] S3-1. Determine if the initial bit width of the parallel data is 8 bits. If so, output the frame header signal directly and proceed to step S4; otherwise, search for byte A2 in the bit-aligned parallel data and proceed to step S3-2.

[0068] S3-2. Determine if there is non-A1 byte data in the data before the first A2 byte. If so, determine that the frame header is incorrect, take the parallel data after the current bit alignment as the truncation object and return to step S2; otherwise, obtain the corresponding offset according to the current alignment, i.e. the second offset, and proceed to step S3-3.

[0069] S3-3. Shift the currently bit-aligned parallel data to the left according to the second offset, and output a frame header signal to indicate the frame header position of each frame.

[0070] If the alignment involves M A1 bytes, then the corresponding offset is set to 8 × M bits. Specifically:

[0071] If the bit width of the parallel data is 8 bits, that is, a single parallel data only includes one byte of data, then after bit alignment, the second offset is 0, and there is no need to search for byte A2. We can directly proceed to step S4.

[0072] If the width of the parallel data is 32 bits, the second offset is 8 × 3 = 24 bits when the alignment is A1A1A1A2; 8 × 2 = 16 bits when the alignment is A1A2A2A2; 8 × 1 = 8 bits when the alignment is A2A2A2A2; and 0 bits when the alignment is A2A2A2A2.

[0073] If the bit width of the parallel data is 64 bits, and the alignment is A1A1A1A1A1A1A1A2, A1A1A1A1A1A1A2A2, A1A1A1A1A1A2A2A2, A1A1A1A1A2A2A2, A1A1A1A2A2A2A2, A1A1A2A2A2A2A2, A1A2A2A2A2A2A2, and A2A2A2A2A2A2A2A2, the corresponding second offsets are 56 bits, 48 ​​bits, 40 bits, 32 bits, 24 bits, 16 bits, 8 bits, and 0, respectively.

[0074] The specific method of step S4 is as follows: continuously match 3×N A1 bytes and 3×N A2 bytes by byte. If the match is successful, output a valid data frame and a valid frame header signal; otherwise, take the current parallel data after left shifting according to the second offset as the interception object and return to step S2.

[0075] like Figure 4 As shown, the specific method for step S5 is as follows:

[0076] The system state before the frame is correctly determined is initialized to the out-of-frame (OOF) state;

[0077] In the frame out-of-sync state, if the correct frame header is detected continuously within 250us, the current system state is changed to fixed frame state (In Frame, abbreviated as IF);

[0078] In the fixed frame state, if an erroneous frame header is detected continuously within 625us, the current system state is changed to the frame out-of-synchronization state, the current transmitted data is determined to be invalid data, the current parallel data after left shift according to the second offset is taken as the interception object, and the process returns to step S2.

[0079] If the frame out-of-sync state lasts for more than 3ms, the current system state will be changed to the frame loss state (LOF) so that the system can reset the receiver or implement other measures.

[0080] If the correct frame header is detected continuously within 1.25ms in the frame loss state, the frame loss state will be changed to the fixed frame state.

[0081] When the current system state is fixed frame state, the current frame header is determined to be a correct frame header, and the currently transmitted data is all valid data, thus completing the frame header detection of the SDH line.

[0082] like Figure 5 As shown, the frame header detection system for the configurable multi-rate SDH line includes a CDR clock recovery module, a bit alignment module, a configuration management module, a frame header detection module, a frame header monitoring module, and a frame status determination module.

[0083] The CDR clock recovery module is used to convert serial data streams on SDH lines into parallel data;

[0084] The bit alignment module is used to extract eight different lengths of parallel data output by the CDR clock recovery module and cache them into eight corresponding registers. Bit alignment is performed based on the result of the data of different lengths hitting the A1 byte.

[0085] The configuration management module is used to configure the CDR clock recovery module and bit alignment module according to the serial data stream rate;

[0086] The frame header detection module is used to align the bit-aligned parallel data output by the bit alignment module based on A2 bytes and output the frame header signal.

[0087] The frame header monitoring module is used to judge the accuracy of each frame header output by the frame header detection module and output valid data frames and valid frame header signals.

[0088] The frame-fixed state determination module is used to obtain the current system state based on the valid frame header signal output by the frame header monitoring module, and to determine that a real frame header has been detected when the current system state is a frame-fixed state.

[0089] In one embodiment of the present invention, such as Figure 2 As shown, the current parallel data is 1101111011110111101111……. The data group Q3 is successfully matched with byte A1. Therefore, 110111101110111101111…… is shifted left by 3 bits to obtain the bit-aligned parallel data 1111011011110110111…….

[0090] It's important to note that while the bit width of a single parallel data entry is fixed, multiple parallel data entries are contiguous. The purpose of converting serial data to parallel data for processing is to reduce the system's operating frequency and improve system stability. For example, if the STM-4 line speed is 622.08 Mbps, a parallel output data bit width of 16 bits will allow it to operate normally at a system clock of 38.88 MHz. However, if the STM-64 line speed is 9953.28 Mbps and the parallel output data bit width is also 16 bits, the system clock will reach a staggering 622.08 MHz. At this high clock frequency, devices like FPGAs will not be able to operate normally. If the parallel output data bit width is 64 bits, the system clock will be 155.52 MHz, allowing FPGAs and other devices to operate normally at this clock speed.

Claims

1. A frame header detection method for a configurable multi-rate SDH line, characterized in that, Includes the following steps: S1. Obtain the serial data stream rate and convert the serial data stream on the SDH line into parallel data; S2. Extract 8 segments of parallel data of different lengths and cache them in the corresponding 8 registers. Perform bit alignment based on the result of hitting byte A1 with data of different lengths. S3. Align the bit-aligned parallel data based on A2 bytes and output the frame header signal; S4. Determine the accuracy of each frame header and output valid data frames and valid frame header signals; S5. Obtain the current system state based on the output valid frame header signal, and determine that a real frame header has been detected when the current system state is fixed frame state; The specific method of step S2 includes the following sub-steps: S2-1. Determine if the current parallel data has a bit width of 8 bits. If so, concatenate two adjacent parallel data into 16-bit parallel data and proceed to step S2-2; otherwise, proceed directly to step S2-2. S2-2. Truncate the current parallel data into lengths of 15 bits, 14 bits, 13 bits, 12 bits, 11 bits, 10 bits, 9 bits and 8 bits respectively, and cache them into reg1, reg2, reg3, reg4, reg5, reg6, reg7 and reg8 respectively. Where reg represents a register; S2-3. Right-align the data in the 8 registers, and starting from the rightmost column, take the data in the mth column as a data group, that is, get 8 groups of 8-bit data groups Qn, n=8-m, m=1,2,3,4,5,6,7,8; S2-4. Match the 8 groups of 8-bit data Qn with the A1 byte respectively, and use the n value of the matched data group Qn as the offset n; S2-5. Shift the current parallel data left by n bits according to the offset n; S2-6. Determine whether the parallel data after the shift is a continuous A1 byte. If so, use the parallel data after the current shift as the bit-aligned parallel data and complete the bit alignment; otherwise, use the parallel data after the current shift as the truncation object and return to step S2-2.

2. The frame header detection method for configurable multi-rate SDH lines according to claim 1, characterized in that, The serial data stream rates include 155.52 Mbps, 622.08 Mbps, 2.488 Gbps and 9.953 Gbps, corresponding to the STM-1 frame structure, STM-4 frame structure, STM-16 frame structure and STM-64 frame structure, respectively; the frame positioning character in the STM-N frame structure consists of 3×N A1 bytes followed by 3×N A2 bytes, where N=1,4,16,64.

3. The frame header detection method for configurable multi-rate SDH lines according to claim 2, characterized in that, The specific method for converting a serial data stream on an SDH line into a parallel data stream is as follows: When the serial data stream rate is 155.52 Mbps and 622.08 Mbps, the bit width of the parallel data is set to 8 bits; when the serial data stream rate is 2.488 Gbps, the bit width of the parallel data is set to 32 bits; and when the serial data stream rate is 9.953 Gbps, the bit width of the parallel data is set to 64 bits.

4. The frame header detection method for configurable multi-rate SDH lines according to claim 3, characterized in that, The specific method of step S3 includes the following sub-steps: S3-1. Determine if the initial bit width of the parallel data is 8 bits. If so, output the frame header signal directly and proceed to step S4; otherwise, search for byte A2 in the bit-aligned parallel data and proceed to step S3-2. S3-2. Determine if there is non-A1 byte data in the data before the first A2 byte. If so, determine that the frame header is incorrect, take the parallel data after the current bit alignment as the truncation object and return to step S2; otherwise, obtain the corresponding offset according to the current alignment, i.e. the second offset, and proceed to step S3-3. S3-3. Shift the currently bit-aligned parallel data to the left according to the second offset, and output a frame header signal to indicate the frame header position of each frame.

5. The frame header detection method for configurable multi-rate SDH lines according to claim 4, characterized in that, If the alignment contains M A1 bytes, then the corresponding offset is set to 8 × M bits.

6. The frame header detection method for configurable multi-rate SDH lines according to claim 4, characterized in that, The specific method for step S4 is as follows: Continuously match 3×N A1 bytes and 3×N A2 bytes byte by byte. If a match is successful, output a valid data frame and a valid frame header signal; otherwise, use the current parallel data after left shifting according to the second offset as the truncation object and return to step S2.

7. The frame header detection method for configurable multi-rate SDH lines according to claim 1, characterized in that, The specific method for step S5 is as follows: Initialize the system state before the frame is correctly determined to be in the frame out-of-synchronization state; In the frame out-of-sync state, if the correct frame header is detected continuously within 250us, the current system state is changed to fixed frame state. In the fixed frame state, if an erroneous frame header is detected continuously within 625us, the current system state is changed to the frame out-of-synchronization state, the current transmitted data is determined to be invalid data, the current parallel data after left shift according to the second offset is taken as the interception object, and the process returns to step S2. If the frame loss state lasts for more than 3ms, the current system state will be changed to frame loss state. If the correct frame header is detected continuously within 1.25ms in the frame loss state, the frame loss state will be changed to the fixed frame state. When the current system state is fixed frame state, the current frame header is determined to be a correct frame header, and the currently transmitted data is all valid data, thus completing the frame header detection of the SDH line.

8. A frame header detection system for a configurable multi-rate SDH line based on the frame header detection method for any one of claims 1 to 7, characterized in that, It includes a CDR clock recovery module, a bit alignment module, a configuration management module, a frame header detection module, a frame header monitoring module, and a frame status determination module; The CDR clock recovery module is used to convert serial data streams on SDH lines into parallel data; The bit alignment module is used to extract eight different lengths of parallel data output by the CDR clock recovery module and cache them into eight corresponding registers. Bit alignment is performed based on the result of the data of different lengths hitting the A1 byte. The configuration management module is used to configure the CDR clock recovery module and bit alignment module according to the serial data stream rate; The frame header detection module is used to align the bit-aligned parallel data output by the bit alignment module based on A2 bytes and output the frame header signal. The frame header monitoring module is used to judge the accuracy of each frame header output by the frame header detection module and output valid data frames and valid frame header signals. The frame-fixed state determination module is used to obtain the current system state based on the valid frame header signal output by the frame header monitoring module, and to determine that a real frame header has been detected when the current system state is a frame-fixed state.

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