Frame alignment recovery for high speed signaling interconnects

Abstract

The present disclosure relates to frame alignment recovery for high-speed signaling interconnects. A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame includes a number of bits. The second device is to receive, from each data lane, a first set of bits corresponding to the number of bits in each of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary in response to determining that the first set of bits does not correspond to the frame boundary.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating high-speed communications. For example, at least one embodiment relates to a technique for frame alignment recovery in Ground Reference Signalling (GRS) interconnects. Background Technology

[0002] Communication systems transmit signals from a transmitter to a receiver via a communication channel or medium (e.g., cable, printed circuit board, link, wireless, etc.). To ensure reliable data transmission in chip-to-chip (C2C) communication, the communication system can be trained before data transmission. For example, the communication system can be trained to synchronize the data received at the receiver. Some communication systems attempt to synchronize the data received at the receiver for consecutive frame alignment by sending frame symbols and using a de-skewing first-in-first-out (FIFO) component. Such traditional methods can reduce data transmission rates and bandwidth. This traditional approach also results in repeating the synchronization process each time data transmission is stopped and restarted. Attached Figure Description

[0003] Various embodiments according to this disclosure will be described with reference to the accompanying drawings, in which:

[0004] Figure 1 This is an example communication system employing a method for frame alignment recovery according to at least some embodiments;

[0005] Figure 2 An example communication system employing a method for frame alignment recovery according to at least some embodiments is shown;

[0006] Figure 3 This is an example communication system employing a method for frame alignment recovery according to at least some embodiments;

[0007] Figure 4 This is a diagram illustrating a method for frame alignment recovery in a high-speed interconnect system according to at least some embodiments;

[0008] Figure 5 This is a flowchart of a method for frame alignment restoration according to at least some embodiments;

[0009] Figure 6 This is a flowchart of a method for frame alignment recovery in a high-speed interconnect system according to at least some embodiments;

[0010] Figure 7 An example computer system including a transceiver according to at least some embodiments is shown, the transceiver including a chip-to-chip interconnect for frame alignment recovery. Detailed Implementation

[0011] Communication systems transmit signals from a transmitter to a receiver via a communication channel or medium (e.g., cable, printed circuit board, link, wireless, etc.). In some communication systems, data transmitted from the transmitter may be misaligned or off-target when received at the receiver. This can lead to data corruption and unreliable data transmission within the system. A communication system can be an example of a forwarding clock architecture. For instance, a communication system may include a first device (e.g., a first integrated circuit (IC) or chip) and a second device (e.g., a second IC or chip) and communicate data via a Ground Reference Signalling (GRS) link. For example, the communication system may be a chip-to-chip (C2C) interconnect of two devices, including a transmitter and a receiver. The first device may transmit data framed relative to a first clock signal and also transmit a second clock signal associated with the link to the second device—for example, the transmitter may frame the data according to the first clock signal, and the link may transmit the data according to the second clock signal—for example, data may be transmitted using fixed-length frames, each frame comprising the same number of bits. The second device may divide the second clock signal and attempt to recover the original first clock signal (e.g., generate a recovered clock signal) to determine the frame boundaries of the received data. In some embodiments, the first device and the second device may be asynchronous. In such embodiments, clock phase alignment may be different for the first device and the second device. For example, in a forward clock communication system, the transmitter clock of the first device may not be aligned relative to the recovered clock generated at the second device—for example, because the first device and the second device are asynchronous, the transmitter clock and the recovered clock at the receiver can be arbitrarily aligned.

[0012] Furthermore, each data path in this link can have different physical characteristics—for example, due to variations in the link's manufacturing process, each trace on a printed circuit board may differ from the others. Therefore, data received at one data path in the link may be misaligned or off-aligned relative to the other data paths—for example, due to manufacturing variations, the first data path may receive data before the second. Some communication systems can transmit framing symbols and use a de-alignment first-in-first-out (FIFO) component to indicate the start of data transmission or to align received data. However, transmitting framing symbols consumes additional power, increases latency, and reduces data bandwidth. Furthermore, in such communication systems, frame alignment can occur after each data transmission has stopped, resulting in increased latency with each subsequent data transmission. For example, a communication system might use framing symbols each time new data is transmitted.

[0013] Advantageously, aspects of this disclosure can address the aforementioned deficiencies and other challenges by providing a method for frame alignment using shift logic in a receiver. The receiver can use shift logic to synchronize each data path of the link relative to a frame boundary. The receiver can also use shift logic to synchronize frame boundaries across all data paths—for example, ensuring that all data paths are synchronized relative to the same frame boundary. For example, during initialization (e.g., before data transmission), a first device can send a stored non-aliasing repeating pattern to a second device—for example, the non-aliasing repeating pattern can be used to program components associated with the link in each device so that either device can detect the repeating pattern. The receiver of the second device can determine whether the pattern received at each channel is synchronized relative to a frame boundary by comparing incoming bits with the stored repeating pattern. If the receiver determines that the incoming bit at the corresponding data path does not correspond to a frame boundary, the receiver can shift the incoming bit by one or more unit intervals (UI) until the incoming bit does correspond to a frame boundary—for example, the second device can shift the incoming pattern by one (1) UI, determine whether the shifted pattern corresponds to a frame boundary, and if not, continue shifting by one (1) UI until the incoming pattern corresponds to a frame boundary. The second device can do this for all data paths until each data path is synchronized relative to the frame boundary.

[0014] After synchronization relative to frame boundaries, the first device can transmit a counting pattern (e.g., an incrementing or decrementing counting pattern) on each data path. The second device can receive the counting pattern at each data path and determine the earliest count value received across the data paths. Thus, the second device can determine which data paths are out of sync relative to the other data paths. The receiver can shift incoming counting patterns at data paths that receive count values ​​different from the earliest count value by increasing one or more burst lengths (BL) until each data path receives the same count value. For example, the first data path can receive count value two (2), and the second data path can receive count value four (4). If the receiver receives an incrementing pattern, count value (2) can be considered the earliest value. In this embodiment, the second data path receives count value four (4) faster than the first data path receives count value two (2). Therefore, the second device can shift the counting pattern at the second data path by two (2) burst lengths (e.g., delay the second path by two (2) burst lengths) to match the counting pattern received at the first data path. If the receiver receives a decrementing pattern, count value four (4) can be considered the earliest value. In such an embodiment, the second device may shift the counting pattern at the first data path by two (2) burst lengths (e.g., delay the second path by two (2) burst lengths) to match the counting pattern received at the second data path. In either case, the second device may shift or add the burst length offset to a faster data path for synchronization across data paths. Thus, each data path may be synchronized relative to the same frame boundary. As described herein, the communication system may also perform frame alignment on data transmitted from the second device to the first device.

[0015] By utilizing repetition and counting modes, a communication system can align frames received at the receiver. Furthermore, compared to sending framing symbols for each data transmission, the communication system can increase data bandwidth, reduce latency, and decrease power consumption by utilizing repetition and counting modes all at once. Therefore, embodiments of this application allow for a more reliable method for frame alignment recovery in high-speed interconnect systems.

[0016] Figure 1An example communication system 100 according to at least one exemplary embodiment is illustrated. System 100 includes device 110, communication network 108 including communication channel 109, and device 112. In at least one embodiment, devices 110 and 112 are two endpoint devices in a computing system, such as a central processing unit (CPU) or a graphics processing unit (GPU). In at least one embodiment, devices 110 and 112 are two servers. In at least one example embodiment, devices 110 and 112 correspond to one or more of a personal computer (PC), laptop computer, tablet computer, smartphone, server, server collection, etc. In some embodiments, devices 110 and 112 may correspond to any suitable type of device communicating with other devices connected to a common type of communication network 108. According to embodiments, a receiver 104 of device 110 or 112 may correspond to a GPU, a switch (e.g., a high-speed network switch), a network adapter, a CPU, a memory device, an input / output (I / O) device, other peripheral devices or components on a system-on-a-chip (SoC), or other devices and components that receive or measure signals, etc. As another specific but non-limiting example, devices 110 and 112 may correspond to servers that provide information resources, services and / or applications to user devices, client devices or other hosts in system 100.

[0017] Examples of communication networks 108 that can be used to connect devices 110 and 112 include Internet Protocol (IP) networks, Ethernet, unlimited bandwidth (IB) networks, Fibre Channel networks, the Internet, cellular communication networks, wireless communication networks, terrestrial reference signaling (GRS) links, combinations thereof (e.g., Ethernet Fibre Channel), and variations thereof. In a particular but non-limiting example, communication network 108 is a network capable of transmitting data between devices 110 and 112 using data signals (e.g., digital, optical, and wireless signals).

[0018] Device 110 includes a transceiver 116 for transmitting and receiving signals (e.g., data signals). The data signal may be a digital or optical signal modulated with data or other suitable signals for carrying data.

[0019] Transceiver 116 may include digital data source 120, transmitter 124, receiver 104, and processing circuitry 132 for controlling transceiver 116. Digital data source 120 may include suitable hardware and / or software for outputting data in digital format (e.g., in binary code and / or thermometer code). Digital data output by digital data source 120 may be retrieved from memory (not shown) or generated based on input (e.g., user input).

[0020] Transmitter 124 includes suitable software and / or hardware for receiving digital data from digital data source 120 and outputting data signals based on the digital data for transmission to receiver 104 via communication network 108 to device 112. Additional details of the structure of transmitter 124 are discussed in more detail below with reference to the accompanying drawings.

[0021] The receiver 104 of devices 110 and 112 may include appropriate hardware and / or software for receiving signals (such as data signals) from the communication network 108. For example, receiver 104 may include components for receiving processing signals to extract data for storage in memory, as described below. Figures 2-4 Detailed description. In at least one embodiment, receiver 104 may include shift logic 115. In some embodiments, shift logic 115 may shift bits received at each data path of communication network 108 by one or more unit intervals (UI) or one or more burst lengths (BL). For example, training logic 117 may be configured to initiate frame alignment (e.g., frame recovery training). In such an embodiment, receiver 104 may receive a non-aliased repeating pattern from device 112 at each data path. Receiver 104 may compare the repeating pattern at each data path with a stored repeating pattern at training logic 117. If the repeating pattern at the data path does not match the stored repeating pattern, shift logic 115 may shift the repeating pattern by one or more UI until the received repeating pattern matches the stored pattern. Training logic 117 may then continue aligning each data path with the same frame boundary. For example, receiver 104 may receive a counting pattern at each data path and determine which data path received data earliest. Shift logic 115 at each data path can compare the received value with the earliest value and shift by one or more BLs until the count pattern received at the data path matches the earliest value—for example, shift logic 115 can add a burst length shift to the faster data path that matches the slowest data path. (See reference) Figures 2 to 6 Additional details regarding frame alignment are described.

[0022] Processing circuitry 132 may include software, hardware, or a combination thereof. For example, processing circuitry 132 may include memory containing executable instructions and a processor (e.g., a microprocessor) that executes the instructions on the memory. The memory may correspond to any suitable type of memory device or collection of memory devices configured to store instructions. Non-limiting examples of suitable memory devices that may be used include flash memory, random access memory (RAM), read-only memory (ROM), variations thereof, combinations thereof, etc. In some embodiments, the memory and processor may be integrated into a common device (e.g., a microprocessor may include integrated memory). Additionally or alternatively, processing circuitry 132 may include hardware such as application-specific integrated circuits (ASICs). Other non-limiting examples of processing circuitry 132 include integrated circuit (IC) chips, central processing units (CPUs), general-purpose processing units (GPUs), microprocessors, field-programmable gate arrays (FPGAs), collections of logic gates or transistors, resistors, capacitors, inductors, diodes, etc. Some or all of processing circuitry 132 may be disposed on a printed circuit board (PCB) or a collection of PCBs. It should be understood that any suitable type of electrical component or collection of electrical components may be suitable for inclusion in processing circuitry 132. The processing circuit 132 can send signals to and / or receive signals from other components of the transceiver 116 to control the overall operation of the transceiver 116.

[0023] Transceiver 116 or selected components thereof may take the form of a pluggable card or controller of device 110. For example, transceiver 116 or selected components thereof may be implemented on a network interface card (NIC).

[0024] Device 112 may include a transceiver 136 for transmitting and receiving signals (e.g., data signals) via channel 109 of communication network 108. The same or similar structure of transceiver 116 may be applied to transceiver 136, and therefore the structure of transceiver 136 is not described separately.

[0025] Although not explicitly shown, it should be understood that devices 110 and 112, as well as transceiver 116, may include other processing devices, storage devices, and / or communication interfaces typically associated with computing tasks such as sending and receiving data.

[0026] Figure 2 An example communication system 200 according to at least one exemplary embodiment is shown. System 200 includes, as referenced... Figure 1 The devices 110 and 112 are described. Devices 110 and 112 may include a transmitter 124 and a receiver 104, as referenced. Figure 1 As described above. Devices 110 and 112 can be coupled to link 220. In at least one embodiment, link 220 can be as described in reference... Figure 1 Examples of the described communication network 108. In at least one embodiment, link 220 may be an example of a high-speed interconnect. For example, link 220 may be an example of a Ground Reference Signaling (GRS) link 220. In embodiments, GRS link 220 may be a signaling scheme for serial data transmission between devices 110 and 112. In at least one embodiment, GRS link 220 may be a high-speed link with a frequency of 20 GHz (e.g., 40 gigabits per second (GBPS)) when performing high-speed communication. In at least one embodiment, link 220 may include an RC-dominant channel and an LC transmission line. Furthermore, GRS link 220 may be an on-chip link, a cross-substrate (e.g., organic package) link, or a link signaling on a printed circuit board (PCB). In some examples, GRS link 220 may use a ground network as a signal reference voltage—for example, ground may be a return signaling.

[0027] In at least one embodiment, link 220 may include data paths 202 and 203 configured to transmit signals, data, messages, etc., between device 110 and device 112. For example, data path 202 may be associated with transmitting signals, data, or messages from device 110 to device 112, while data path 203 may be associated with transmitting signals, data, or messages from device 112 to device 110—for example, data path 202 may be associated with transmitter 124 of device 110, and data path 203 may be associated with transmitter of device 112. In at least one embodiment, link 220 may include the same number of data paths 202 and data paths 203. In this embodiment, data path 202 may be associated with data path 203—for example, data path 202-a and data path 203-a may be a single transmitter / receiver data path pair. In at least one embodiment, link 220 may include “N” data path pairs—for example, “N” data paths 202 and data paths 203. In some embodiments, data path 202 may be associated with forwarding clock path 205-a, and data path 203 may be associated with forwarding clock path 205-b. In at least one embodiment, each clock path may be associated with two or more data paths (e.g., at least two data paths 202 or data path 203). In at least one embodiment, data path 202 transmits data to device 112. In such embodiments, the data is latched onto a forwarding clock at receiver 104 of device 112. In some embodiments, data path 202 and the corresponding data path 203 are identical—for example, each data path 202 and the corresponding data path 203 supports the same signaling rate and includes the same drivers and hardware.

[0028] In at least one embodiment, transmitter 124 may include serializer 205, and receiver 104 may include deserializer 210. In such an embodiment, serializer 205 may serialize parallel data stored at device 110 or device 112 and transmit the serialized data via link 220. For example, serializer 205 data may serialize bits 215-a to 215-n for transmission across data path 203-n—for example, serializing “B” of parallel bits for transmission. In this example, the burst length may be equal to the number of “B” bits transmitted—for example, the number of bits transmitted in one clock cycle of the transmitter. In some embodiments, each number “B” may be referred to as a frame. In some embodiments, transmitter 124 may transmit bits 215-a to 215-n at a first clock with a period of “T” (e.g., the transmitter clock). Serializer 205 may serialize the data at a second clock with a period of 2T / B. That is, the clock of transmitter 124 may be slower than the second clock associated with transmitting data via link 220. Serializer 205 can serially transmit bits 215-a to 215-n from device 112 to device 110 on data path 203-n. In some embodiments, serializer 205 can transmit one bit (e.g., bit 215-a) of “B” bits during a unit interval (UI)—for example, bit 215-a is transmitted during a first UI. The transmitter can also transmit a second clock across clock path 205-b—for example, a clock associated with link 220.

[0029] Receiver 104 may include deserializer 210 to deserialize data received from link 220. Specifically, deserializer 210 may recover parallel data bits 215-a to 215-n. To deserialize the data, deserializer 210 may be configured to divide a second clock received from clock path 205-b to recover a first clock—e.g., the transmitter clock. For example, deserializer 210 may divide the second clock to produce a recovered parallel clock. In embodiments where devices 110 and 112 are asynchronous (e.g., the transmitter clock of device 110 is arbitrarily aligned with the recovered clock of device 112), the recovered clock may be out of phase with the first clock. Therefore, communication system 200 may perform frame alignment recovery training before transmitting data from device 110 to device 112 or from device 112 to device 110. For example, communication system 200 may utilize two-stage (e.g., two-stage or two-pass) frame alignment recovery training. In such an example, device 112 may transmit a non-aliased repeating pattern to device 110 at each data path 203 during the first phase. Receiver 104 may compare the incoming non-aliased repeating pattern at each data path 203 with a stored repeating pattern (e.g., device 112 may transmit repeating patterns known or stored at both device 110 and device 112). If the pattern received at data path 203 differs from the stored pattern, the receiver may shift the incoming bits by one or more UI, as shown in the reference. Figures 3 to 5 As described, this continues until each data path is synchronized relative to the frame boundary. Device 112 can then transmit a counting pattern (e.g., an incrementing or decrementing counting pattern) at each data path 203 during the second phase. Receiver 104 can compare the values ​​received at each data path 203, and as referenced... Figures 3 to 5 The described shift is made by one or more BLs until each data path is synchronized relative to the same frame boundary—for example, each data path receives the same count value.

[0030] Figure 3 An example communication system 300 according to at least one exemplary embodiment is shown. In at least one embodiment, the communication system 300 is as described with reference to Figure 1 and Figure 2 Examples of the described communication systems 100 or 200. System 300 includes, as referenced... Figure 1 The devices 110 and 112 are described. Devices 110 and 112 can be coupled to, as referenced... Figure 2 The described link 220—for example, GRS link 220. Device 110 may include, as referenced... Figure 1 The transmitter 124 is described, and the device 112 may include, as referenced Figure 1 The receiver 104 is described. In at least one embodiment, the components shown in receiver 104 can be considered as references. Figure 1 This is a part of the shift logic 115 described. Although Figure 3 A transmitter 124 in device 110 and a receiver 104 for device 112 are shown, but device 112 may include transmitter 124, and device 110 may include receiver 104, as referenced. Figure 2 The transmitter 124 may include a pattern generator 305. The receiver 104 may include data path logic 305 for each data path 203—for example, data path logic 305-a for data path 202-a, data path logic 305-b for data path 202-b, etc. In at least one embodiment, the receiver 104 may be coupled to training logic 117 or otherwise receive signals from processing circuitry 132, as described in reference [reference]. Figure 1 As stated above.

[0031] In some embodiments, devices 110 and 112 may perform frame alignment restoration, as referenced Figure 2 As described. In this embodiment, training logic 117 of device 110 or device 112 may initiate frame alignment recovery as part of an initialization sequence. In some embodiments, training logic 117 may instruct pattern generator 305 to transition from a first stage of frame alignment recovery to a second stage of frame alignment recovery—for example, from a repeat mode to a count mode. For example, training logic 117 of device 112 may select the message to be sent to device 110, instructing device 112 to complete the first stage and transition to the second stage. In embodiments, training logic 117 may determine the maximum number of unit interval (UI) shifts or burst length (BL) shifts for the corresponding frame alignment recovery. In such embodiments, if the maximum number of UI or BL shifts is met and the data path is not yet aligned, training logic 117 may send an error message.

[0032] In some embodiments, pattern generator 305 may be configured to generate patterns to be transmitted. For example, pattern generator 305 may generate repeating patterns (e.g., non-aliased repeating patterns) during the first stage of frame alignment recovery. In some embodiments, pattern generator 305 may generate repeating patterns based on repeating patterns stored at training logic 117—for example, pattern generator 305 may generate patterns stored at both device 110 and device 112, enabling each device to detect repeating patterns. In some embodiments, repeating patterns may be stored in software. In other embodiments, training patterns may be hardwired. In some embodiments, pattern generator 305 may generate frames while generating repeating patterns. For example, pattern generator 305 may generate frames, each with the same number of bits (e.g., as referenced). Figure 2(The “B” bits described). In some embodiments, each generated frame may be identical—for example, each frame may include the same bits corresponding to the repeating pattern. In embodiments, the pattern generator 305 may be configured to generate a counting pattern (e.g., an incrementing pattern or a decrementing pattern) during the second state of frame alignment recovery. For example, the pattern generator 305 may send an incrementing (e.g., sending values ​​1, 2, 3, etc.) or a decrementing (e.g., sending values ​​5, 4, 3, etc.) pattern. In some embodiments, the pattern generator may transmit the count value of the counting pattern in each clock cycle—e.g., a first value during a first clock cycle, a second value during a second clock cycle, etc. In such embodiments, each frame transmitted during the second phase may include a count value (1). In embodiments, the start and stop count values ​​of the counting pattern may be set by training logic 117. For example, training logic 117 may instruct the pattern generator 305 to start from the count value one (1). In embodiments, the pattern generator 305 may stop sending the repeating pattern or the counting pattern based on a signal received from training logic 117—for example, training logic 117 may instruct when to send the repeating pattern or the counting pattern. In some embodiments, the pattern generator 305 can be at a first clock (e.g., as referenced). Figure 2 The first clock described above generates a pattern. In this embodiment, the pattern (e.g., a repeating pattern or a counting pattern) can be serialized and generated at a second clock (e.g., as referenced). Figure 2 The described second clock is transmitted via link 220.

[0033] In embodiments, data path logic 305 can be configured to receive frames (e.g., B" bits) and count values ​​from the corresponding data path 202—for example, data path logic 305 can receive a repeating pattern or a counting pattern from the corresponding data path 202. In some embodiments, receiver 104 or data path logic 305 can be configured to deserialize the received frames to recover, as referenced... Figure 2The original frame described. In an embodiment, during the first phase of frame alignment recovery, data path logic 305-a can be configured to compare incoming bits corresponding to the frame size with a repetition pattern stored at training logic 117. For example, data path logic 305-a can compare the first "B" bits received on data path 202-a with the stored repetition pattern. If data path logic 305 determines that the incoming "B" bits satisfy (e.g., match or are the same as) the repetition pattern, data path logic 305 can avoid performing additional operations during the first phase of frame alignment recovery. If data path logic 305 determines that the incoming "B" bits do not satisfy (e.g., do not match or are not the same as) the repetition pattern, then UI shift logic 310 of data path logic 305 is configured to shift the input bits by one UI. For example, if the first “B” bits received on data path 202-a do not match the stored repeating pattern, the UI shift logic 310-a can skip subsequent bits received after the first “B” bits (e.g., shift by one (1) UI), and then compare the next set of “B” bits received after the skipped bits with the stored repeating pattern. That is, when shifting by one UI, the data path logic 305 can skip one bit when a pattern is detected. The data path logic 305 can continue comparing and shift the UI shift logic 310 by one UI until a set of “B” bits received in each data path 305 matches the stored repeating pattern.

[0034] In some embodiments, data path logic 305 may be configured to receive a count value during the second phase of frame alignment recovery. For example, each data path logic 305 may be configured to receive a count value during each clock cycle (e.g., as referenced). Figure 2During each clock cycle of the described recovery clock, a count value corresponding to the counting pattern is received. In at least one embodiment, training logic 117 may receive a count value from each data path 202 and determine the earliest data path 202—for example, determining which data path 202 receives the earliest count value. For example, training logic 117 may receive count value three (3) from data path 202-a and count value two (2) from data path 202-b. If the counting pattern is incrementing (for example, data path 202-b is the earliest data path 202 used to receive count value two (2), then training logic 117 may determine that data path 202-b receives the earliest count value, or if the counting pattern is decrementing, then training logic 117 may determine that data path 202-a receives the earliest count value—for example, data path 202-a is the first data path 202 used to receive count value three (3). Each data path logic 305 may be configured to compare the count value received from the corresponding data path 202-a with the determined earliest count value. For example, data path 202-a can compare count value three (3) with the earliest determined count value (e.g., with count value two (2)). After the comparison, each data path logic 305 can determine whether to shift the incoming bits—e.g., determine whether to add a burst length shift. For example, if data path logic 305 determines that the received count value does not satisfy (e.g., is different from) the earliest count value, data path logic 305 can cause BL shift logic 315 to add one or more burst length shifts to match the received count value with the earliest count value—e.g., cause BL shift logic 315-a to add a burst length shift so that the count value two (2) received in data path 202-a matches the earliest count value. If data path logic 305 determines that the received count value satisfies the earliest count value, data path logic 305 can avoid performing additional operations during the second phase. Therefore, data path logic 305 can be configured to align the data received in each data path 202 relative to the same frame boundary during frame alignment recovery.

[0035] Figure 4 An example diagram of a method 400 for frame alignment recovery for high-speed interconnects is shown. Method 400 can be executed by processing logic including hardware, software, firmware, or any combination thereof. In at least one embodiment, as referenced... Figure 3As described, method 400 is performed by transmitter 124 or receiver 104 of the first device 110 or the second device 112—for example, by pattern generator 305, training logic 117, and data path logic 305. Although shown in a specific sequence or order, the order of processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Additionally, one or more processes may be omitted in different embodiments. Therefore, not all processes are required in every embodiment. Other diagrams illustrating the method for frame alignment recovery are possible. In embodiments, operations 420 and 425 may be associated with a first stage of frame alignment recovery, and operations 430 and 435 may be associated with a second stage of frame alignment recovery.

[0036] In operation 420, transmitter 124 can send a repeating pattern, as shown in [reference needed]. Figure 2 and Figure 3 As described. In some embodiments, each transmitted frame 415 may contain the same number of bits, wherein each frame 415 is identical—for example, frame 415-a is identical to frame 415-b. In embodiments, as referenced Figure 2 As described, the recovery clock 410 generated by receiver 104 may be misaligned relative to transmitter clock 405. Therefore, frames 415 recovered by the receiver in each data path 202 may be out of alignment relative to the recovery clock 410. For example, recovery frame 415-a at data path 202-b may be out of alignment and received before the rising edge of recovery clock 410, while recovery frame 415-a at data path 202-n may be out of alignment and received after the rising edge of recovery clock 410. In some embodiments, even if transmitter clock 405 and recovery clock 410 are aligned, frames 415 received in each data path 202 may still be out of alignment due to deviations in data path 202 as described above—for example, due to different wiring and physical deviations of data path 202 during manufacturing.

[0037] In operation 425, the data path logic 305 at each data path 202 can compare the incoming bits with the repetition pattern stored at the training logic 117, as shown in the reference. Figure 3As described. In an embodiment, data path logic 305 can determine that incoming bits satisfy (e.g., match) a repetition pattern. For example, data path logic 305-a can determine that the received first set of bits corresponding to the frame size satisfies the repetition pattern—for example, frame 415-a is aligned with recovery clock 410. In an embodiment, data path logic 305 can determine that incoming bits do not satisfy (e.g., mismatch) a repetition pattern. For example, data path logic 305-b can determine that the received first set of bits corresponding to the frame size does not satisfy the repetition pattern—for example, frame 415 is not aligned with recovery clock 410. In such an embodiment, UI shift logic 310-b can shift the incoming bits by one UI shift 435. After the shift, data path logic 305-b can determine that the received second set of bits corresponding to the frame size (bits received after skipping one bit after the first set of bits) does not satisfy the repetition pattern—for example, after the first shift, frame 415-a is not aligned with recovery clock 410. In such an embodiment, UI shift logic 310-b can again shift the incoming bits by one UI shift 435. Data path logic 305-b and UI shift logic 310-b can continue to shift by one UI shift 435 until the incoming bits match the stored repetition pattern—for example, until frame 415-a is aligned with the recovery clock at data path 202-b. In some embodiments, each data path logic 305 can shift the received bits by one UI shift 435 at a time until all frames 415 received at each data path are aligned with the recovery clock 410.

[0038] In operation 430, transmitter 124 can send as shown in [reference]. Figure 2 and Figure 3The described counting pattern. In an embodiment, after operation 425, although each frame 415 may be aligned relative to the recovered clock 410, frame 415 may not be aligned relative to other data paths 202. For example, frame 415-a received at data path 202-n may be aligned with different clock edges than frame 415-a received at data paths 202-a and 202-b. Therefore, transmitter 124 can transmit a count value for each clock cycle on each data path 202. In such an embodiment, data path logic 305 at each data path 202 may send the received count value to training logic 117. In an embodiment, training logic 117 may determine the earliest count value—for example, when data path 202-n is synchronized with different edges of the recovered clock 410, determining that the count value received at data path 202-n is earlier than the count values ​​received at data paths 202-a and 202-b. Training logic 117 may send the earliest count value back to each data path logic 305. In some embodiments, each data path logic 305 can compare a count value received from the corresponding data path 202 with a determined earliest count value. If the data path logic 305 determines that the received count value is the same as the earliest count value, the data path logic 305 can avoid adding a burst length shift. For example, data path logic 305-n can determine that the received count value satisfies the earliest count value and avoid adding a burst length shift. If the data path logic 305 determines that the received count value is different from the earliest count value, the data path logic 305 can add one or more burst length shifts. For example, data path logic 305-a can cause BL shift logic 315-a to add one burst length shift. In an embodiment, adding one burst length shift can cause the incoming pattern to shift by one full clock cycle.

[0039] In operation 435, transmitter 124 can stop transmitting the counting mode. In an embodiment, after one or more BL shifts are added by BL shift logic 315, each data path 202 can be synchronized relative to the same frame boundary. For example, each recovery frame 415-a at receiver 104 can be aligned with the same rising edge of recovery clock 410. Because each data path 202 is synchronized relative to the same frame boundary, training logic 117 can instruct transmitter 124 to stop transmitting the counting mode—for example, indicating the end of frame alignment recovery. In at least one embodiment, the method described herein can be used to synchronize data path 203—for example, to synchronize data transmission from device 112 to device 110.

[0040] Figure 5 An example flowchart of a method 500 for frame alignment restoration for high-speed interconnects is shown. Method 500 can be executed by processing logic including hardware, software, firmware, or any combination thereof. In at least one embodiment, as referenced... Figure 3 As described, method 500 is performed by the transmitter 124 or receiver 104 of the first device 110 or the second device 112—for example, by the pattern generator 305, training logic 117, and data path logic 305. Although shown in a specific sequence or order, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other illustrations of methods for frame alignment recovery are possible.

[0041] In operation 505, each data path logic 305 can capture (e.g., receive) a first value. For example, each data path logic 305 can receive a value corresponding to a reference as shown in the reference. Figure 3 and Figure 4 The first count value of the counting pattern described is transmitted by transmitter 124. In an embodiment, training logic 117 may implement value capture—for example, enabling each logic path 305 to detect the count value. In at least one embodiment, each data path logic 305 may latch the count value received from the corresponding data path 202. In an embodiment, data path logic 305 may latch the count value received in each clock cycle (e.g., each clock cycle of recovery clock 410).

[0042] In operation 510, training logic 117 (or per data path logic 305) can determine the second value—for example, as referenced. Figure 3 and Figure 4 The earliest count value is determined as described. For example, training logic 117 can compare each count value stored at the corresponding data path logic 305. In an embodiment, training logic 117 can determine the minimum count value that each data path 202 can be synchronized for an incrementing count pattern, or the maximum count value that each data path 202 can be synchronized for a decrementing count pattern. For example, if data paths 202-a, 202-b, and 202-n receive count values ​​four (4), four (4), and three (3), respectively, then training logic 117 can determine that the earliest value is three (3) for an incrementing count pattern and four (4) for a decrementing count pattern.

[0043] In operation 515, each data path logic 305 can determine whether the second value is the same as the first value—for example, whether the count value received at the corresponding data path 202 is the same as the earliest count value. For example, each data path logic 305 can compare the first count value with the second count value. If the data path logic 305 determines that the first count value is different from the second count value, then the data path logic 305 can proceed to operation 520. If the data path logic 305 determines that the first count value is the same as the second count value, then the data path logic 305 can proceed to operation 525.

[0044] In operation 520, BL shift logic 315 may add one or more burst length shifts 435. In some embodiments, BL shift logic 315 may determine the difference between a first value and a second value, for example, determining the difference between the earliest count value and a received count value. For example, BL shift logic 315 may determine a difference of five (5) between the first count value and the second count value. In at least one embodiment, BL shift logic 315 may add multiple BL shifts corresponding to this difference—for example, adding five (5) BL shifts when the difference between the first count value and the second count value is five (5). Thus, BL shift logic 315 may cause the first count value received at the corresponding data path to satisfy (e.g., match) the second count value after adding the BL shifts.

[0045] In operation 525, BL shift logic 315 avoids adding BL shift 435. For example, if BL shift logic 315 determines that the first value is the same as the second value (e.g., the received count value is the same as the earliest count value), BL shift logic 315 avoids adding BL shift. Therefore, after operations 520 and 525, each data channel can be synchronized relative to the same frame boundary.

[0046] Figure 6 An example flowchart of a method 600 for frame alignment recovery for high-speed interconnects is shown. Method 600 can be executed by processing logic including hardware, software, firmware, or any combination thereof. In at least one embodiment, method 600 is performed as described in reference... Figure 3The transmitter 124 or receiver 104 of the first device 110 or the second device 112 performs the process—for example, by the pattern generator 305, training logic 117, and data path logic 305. Although shown in a specific sequence or order, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other illustrations of the method for frame alignment recovery are possible. In embodiments, method 600 may be illustrated as referenced. Figure 3 and Figure 4 The second stage of frame alignment recovery is described.

[0047] In operation 605, the processing logic can transmit two or more frames on a link with one or more data paths to synchronize the one or more data paths, wherein each frame includes a certain number of bits (e.g., as referenced). Figure 2 The “B” refers to several bits. In at least one embodiment, the processing logic may send a non-aliasing repeating pattern corresponding to the number of bits. In at least one embodiment, the non-aliasing repeating pattern is stored on both the first device and the second device. In an embodiment, the link is coupled to the first device. In at least one embodiment, each of the two or more frames is identical—for example, each frame includes the same bits.

[0048] In operation 610, the processing logic may receive a first set of bits from each data path, corresponding to the number of bits in each of two or more frames. In an embodiment, the first set of bits may be received at a second device coupled to the link.

[0049] In operation 615, the processing logic may determine that a first set of bits received from a data path in one or more data paths does not correspond to a frame boundary of two or more frames. In an embodiment, the processing logic may compare the first set of bits received at each data path with a stored pattern (e.g., a pattern stored at training logic 117). In at least one embodiment, the processing logic may determine that the received first set of bits is different from the stored pattern, wherein determining that the first set of bits received at a data path does not correspond to a first set of bits at a frame boundary of two or more frames is in response to determining that the first set of bits is different from the stored pattern. In at least one embodiment, the processing logic may determine that the first set of bits received from a data path in one or more data paths does indeed correspond to a frame boundary. In such an embodiment, the processing logic may avoid adding one or more unit interval (UI) shifts to the first set of bits.

[0050] In operation 620, in response to determining that the first set of bits does not correspond to a frame boundary, the processing logic may synchronize each of one or more data paths relative to the frame boundary. In one embodiment, to synchronize each data path, the processing logic may shift the first set of bits received at a data path in one or more data paths by one or more unit intervals (UI) in response to determining that the first set of bits does not correspond to a frame boundary. In some embodiments, the processing logic may further send an indication of synchronization of each of one or more data paths relative to a frame boundary to a first device in response to shifting the first set of bits received at a data path. In some embodiments, the processing logic may compare the shifted first set of bits (e.g., the first set of bits shifted by one UI) with a stored pattern. In such embodiments, the processing logic is able to determine that the shifted first set of bits is associated with a stored pattern, wherein sending an indication of synchronization of one or more data paths relative to a frame boundary is in response to determining that the shifted first set of bits is associated with a stored pattern. In at least one embodiment, the processing logic may determine that the shifted first set of bits does not correspond to a stored pattern. In such an embodiment, the processing logic may, in response to determining that the shifted first set of bits does not correspond to a stored pattern, shift the shifted first set of bits by one or more additional UIs to receive a second shifted first set of bits. The processing logic may then compare the second shifted first set of bits with the stored pattern. In one embodiment, the processing logic is able to determine that the second shifted first set of bits is associated with a stored pattern, wherein sending an indication of synchronization of one or more data paths relative to a frame boundary is in response to determining that the second shifted first set of bits is associated with a stored pattern.

[0051] In operation 625, the processing logic may receive at the first device an indication of synchronization relative to a frame boundary for each of one or more data paths. In such an embodiment, the processing logic may transmit a second set of frames on each of the one or more data paths, each frame in the second set of frames including a value (e.g., a count value) and transmitted during a clock cycle of the transmitter clock. In some embodiments, the second set of frames is associated with a counting mode. In at least one embodiment, the counting mode is an incrementing counting mode. In some embodiments, the counting mode is a decrementing counting mode.

[0052] In operation 630, the processing logic can synchronize each data path relative to the same frame boundary—for example, by executing as referenced. Figures 3 to 5The second stage of frame alignment recovery is described. In some embodiments, to synchronize each data path relative to the same frame boundary, the processing logic may receive a second set of frames on each of one or more data paths. In one embodiment, the processing logic may determine that the value received at a data path in one or more data paths is different from the values ​​received at the remaining data paths in one or more data paths. For example, the processing logic may determine a first value in the second set of frames received at one or more data paths (e.g., as referenced) in response to receiving the second set of frames on each data path. Figure 5 The earliest value described). In some embodiments, the processing logic may compare the first value in the second set of frames with each of the remaining values ​​received at the remaining data paths (e.g., count values ​​received at each respective data path), wherein determining that the value received at a data path is different from the value received at the remaining data paths is based at least in part on comparing the first value in the second set of frames with the remaining values ​​received at one or more data paths.

[0053] In at least one embodiment, the processing logic may shift a second set of frames received at the data path by a burst unit interval (BUI) in response to determining that the values ​​at the data path are different. In one embodiment, the processing logic may compare the shifted value generated after shifting the second set of frames to be received at the data path with the values ​​received at the remaining data paths in one or more data paths. In such an embodiment, the processing logic is able to determine that the shifted value received at the data path is the same as the values ​​received at the remaining data paths in one or more data paths, wherein the indication that the transmit frame boundary is the same for each of the one or more data paths is in response to determining that the shifted value received at the data path is the same.

[0054] In at least one embodiment, the processing logic may compare a shifted value generated after shifting a second set of frames to be received at a data path with values ​​received at the remaining data paths in one or more data paths. In such embodiments, the processing logic may determine that the shifted value at a data path is different from the values ​​received at the remaining data paths in one or more data paths. In some embodiments, the processing logic may shift the shifted value at a data path by a BUI to generate a second shifted value in response to determining that the shifted value is different. In such embodiments, the processing logic may compare the second shifted value at a data path with values ​​received at the remaining data paths in one or more data paths. In some embodiments, the processing logic is capable of determining that the second shifted value at a data path is the same as the values ​​received at the remaining data paths in one or more data paths, wherein an indication that the transmission frame boundary is the same for each of the one or more data paths is in response to determining that the second shifted value received at the data path is the same. In some embodiments, the processing logic may send an indication to a first device that the frame boundary is the same for each of the one or more data paths in response to shifting a second set of frames at a data path.

[0055] Figure 7 A computer system 700 according to at least one embodiment is illustrated, the computer system including a transceiver including chip-to-chip interconnects. In at least one embodiment, the computer system 700 may be a system having interconnected devices and components, a System-on-a-Chip (SoC), or some combination thereof. In at least one embodiment, the computer system 700 is formed with a processor 702, which may include execution units for executing instructions. In at least one embodiment, the computer system 700 may include, but is not limited to, components such as the processor 702, to employ execution units including logic to execute algorithms for processing data. In at least one embodiment, the computer system 700 may include a processor, such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation, Santa Clara, California, although other systems (including PCs, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, the computer system 700 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, but may also use other operating systems (such as UNIX and Linux), embedded software, and / or a graphical user interface.

[0056] In at least one embodiment, the computer system 700 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors (DSPs), SoCs, network computers (“Net PCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system capable of executing one or more instructions. In embodiments, the computer system 700 can be used in network devices such as graphics processing units (GPUs), network adapters, central processing units, and switches such as high-speed direct GPU-to-GPU interconnects, such as NVIDIA GH100 NVLINK or NVIDIA Quantum 2 64-port unlimited bandwidth NDR switches.

[0057] In at least one embodiment, computer system 700 may include, but is not limited to, processor 702, which may include, but is not limited to, one or more execution units 707, said one or more execution units being configured to execute Computing Unified Device Architecture (“CUDA”) programs (CUDA® is developed by NVIDIA Corporation of Santa Clara, California). In at least one embodiment, the CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 700 is a single-processor desktop or server system. In at least one embodiment, computer system 700 may be a multiprocessor system. In at least one embodiment, processor 702 may include, but is not limited to, CISC microprocessors, RISC microprocessors, VLIW microprocessors, processors implementing combinations of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, processor 702 may be coupled to processor bus 710, processor bus 710 being able to transmit data signals between processor 702 and other components in computer system 700.

[0058] In at least one embodiment, processor 702 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 704. In at least one embodiment, processor 702 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to processor 702. In at least one embodiment, processor 702 may also include a combination of both internal and external caches. In at least one embodiment, register file 706 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0059] In at least one embodiment, execution unit 707 (including, but not limited to, logic for performing integer and floating-point operations) also resides in processor 702. Processor 702 may also include a microcode (“ucode”) read-only memory (“ROM”) storing microcode for certain macro instructions. In at least one embodiment, execution unit 707 may include logic for processing packaged instruction set 709. In at least one embodiment, by including packaged instruction set 709 and associated circuitry for executing instructions in the instruction set of general-purpose processor 702, operations used by many multimedia applications can be performed using packaged data in general-purpose processor 702. In at least one embodiment, by using the full width of the processor’s data bus to perform operations on packaged data, many multimedia applications can be accelerated and executed more efficiently, eliminating the need to transfer smaller data units across the processor’s data bus to perform one or more operations on one data element at a time.

[0060] In at least one embodiment, the execution unit may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 700 may include, but is not limited to, memory 720. In at least one embodiment, memory 720 may be implemented as a DRAM device, SRAM device, flash memory device, or other memory device. Memory 720 may store instructions 719 and / or data 721 represented by data signals executable by processor 702.

[0061] In at least one embodiment, the system logic chip may be coupled to processor bus 710 and memory 720. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 716, and processor 702 may communicate with MCH 716 via processor bus 710. In at least one embodiment, MCH 716 may provide a high-bandwidth memory path 718 to memory 720 for instruction and data storage, and for storing graphics commands, data, and textures. In at least one embodiment, MCH 716 may direct data signals between processor 702, memory 720, and other components in computer system 700, and bridge data signals between processor bus 710, memory 720, and system I / O 722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 716 may be coupled to memory 720 via high-bandwidth memory path 718, and graphics / video card 712 may be coupled to MCH 716 via Accelerated Graphics Port (“AGP”) interconnect 714.

[0062] In at least one embodiment, computer system 700 may use system I / O 722, which serves as a dedicated hub interface bus, to couple MCH 716 to I / O controller hub (“ICH”) 730. In at least one embodiment, ICH 730 may provide direct connectivity to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 720, chipset, and processor 702. Examples may include, but are not limited to, an audio controller 729, a firmware hub (“Flash BIOS”) 728, a transceiver 726, a data storage 724, a conventional I / O controller 723 including a user input interface 725 and a keyboard interface, a serial expansion port 727 (such as USB), and a network controller 734. Data storage 724 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device. In an embodiment, transceiver 726 includes a restricted FFE 708.

[0063] In at least one embodiment, Figure 7 A system is shown that includes interconnected hardware devices or "chips" in a transceiver 726, for example, the transceiver 726 includes a chip-to-chip interconnect that includes a first device 110 and a second device 112, as shown in [reference]. Figure 1 (As described). In at least one embodiment, Figure 7 An exemplary SoC may be shown. In at least one embodiment, Figure 7 The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof, and utilize, as shown in [see also...] Figure 2 The GRS link 220 is described. In at least one embodiment, one or more components of system 700 are interconnected using a Fast Compute Link (“CXL”) interconnect. In one embodiment, transceiver 726 may include, as referenced... Figure 1 The shift logic 115 is described above. In such an embodiment, the shift logic 115 can facilitate the frame alignment method for high-speed interconnects as described above. In one embodiment, the shift logic 115 can shift the incoming bits at each data path by one or more UIs or one or more BLs. For example, the shift logic 115 can shift the incoming bits at each data path by one or more UIs to synchronize each data path relative to a frame boundary. The shift logic 115 can also shift the incoming bits at each data path by one or more BLs to synchronize each data path relative to the same frame boundary. Therefore, the shift logic 115 can be configured for use as described in the reference. Figures 2 to 6 The frame alignment recovery described.

[0064] Other variations are within the spirit of this disclosure. Therefore, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments are shown in the accompanying drawings and have been described in detail above. However, it should be understood that this disclosure is not intended to be limited to the one or more specific forms disclosed, but rather, it is intended to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of this disclosure.

[0065] In the context of describing the disclosed embodiments, the terms “a,” “an,” and “the,” and similar references, are to be interpreted as encompassing both the singular and plural, unless otherwise indicated herein or clearly contradicted by the context, and are not defined as terms. Unless otherwise stated, the terms “comprising,” “having,” “including,” and “containing” are to be interpreted as open-ended terms (meaning “including, but not limited to”). “Connection,” when unmodified and referring to a physical connection, is to be interpreted as partially or completely contained within, attached to, or connected together, even with intervening elements. Unless otherwise indicated herein, statements of value ranges herein are intended only as a shorthand for individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as it is individually stated herein. In at least one embodiment, unless otherwise indicated or contradicted by the context, the use of the terms “set” (e.g., “item set”) or “subset” is to be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise stated or contradicted by the context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather that the subset and the corresponding set can be equal.

[0066] Unless explicitly stated otherwise or otherwise clearly contradicted by the context, connective language (such as phrases in the form of "at least one of A, B, and C" or "at least one of A, B, and C") is also understood, along with the context, generally to represent any non-empty subset of a set of items, terms, etc., that can be A or B or C or A and B and C. For example, in an illustrative example of a set with three members, the connective phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any one of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Therefore, such connective language is generally not intended to imply that some embodiments require at least one of A, at least one of B, and at least one of C to each exist. Furthermore, unless explicitly stated otherwise or contradicted by the context, the term "multiple" indicates a state of multiple (e.g., "multiple items" indicates multiple items). In at least one embodiment, the number of items in the plurality is at least two, but may be more when explicitly indicated or indicated by context. Furthermore, unless otherwise stated or clearly understood from the context, the phrase “based on” means “at least partially based on” rather than “based on only.”

[0067] The operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise obviously contradicted by the context. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are executed under the control of one or more computer systems configured with executable instructions and implemented by hardware or combinations thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that executes jointly on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not include transient signals (e.g., propagation of transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a collection of one or more non-transitory computer-readable storage media on which executable instructions are stored (or other memory for storing executable instructions), which, when executed by one or more processors of a computer system (i.e., due to being executed), cause the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media comprises a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media lack all the code, while the plurality of non-transitory computer-readable storage media collectively store all the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors.

[0068] Therefore, in at least one embodiment, the computer system is configured to implement one or more services that individually or jointly perform the operations of the processes described herein, and such a computer system is configured with suitable hardware and / or software capable of performing the operations. Furthermore, the computer system implementing at least one embodiment of this disclosure is a single device, and in another embodiment, it is a distributed computer system comprising multiple devices operating differently, such that the distributed computer system performs the operations described herein, and such that a single device does not perform all the operations.

[0069] The use of any and all examples or exemplary language provided herein (e.g., “such as”) is intended only to better illustrate embodiments of this disclosure and is not intended to limit the scope of this disclosure unless otherwise required. The language in the specification should not be construed as indicating that any unclaimed element is essential to the practice of this disclosure.

[0070] All references cited herein (including publications, patent applications and patents) are incorporated herein by reference to the extent that each reference is individually and precisely identified as incorporated by reference and is listed here in its full text.

[0071] In the specification, the terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms are not intended to be synonyms with each other. Rather, in specific examples, “connected” or “coupled” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0072] Unless otherwise explicitly stated, it will be appreciated that throughout this specification, terms such as “processing,” “computing,” “calculating,” “determining,” or similar terms refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or convert data represented as physical (electronic) quantities in the registers and / or memory of the computing system into other data similarly represented as physical quantities in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0073] Similarly, the term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Moreover, each process can refer to multiple processes for executing instructions sequentially or in parallel, continuously or intermittently. In at least one embodiment, the terms "system" and "method" are used interchangeably herein, provided that the system embodies one or more methods and the methods can be considered as a system.

[0074] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be performed in various ways, such as by receiving data as parameters to a function call or a call to an application programming interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be performed by transmitting data via a serial or parallel interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be performed by transmitting data from a providing entity to an acquiring entity via a computer network. In at least one embodiment, reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be implemented by transmitting data as input or output parameters to a function call, an application programming interface, or an inter-process communication mechanism.

[0075] While the description herein illustrates exemplary embodiments of the described technologies, other architectures may be used to implement the described functionality and are intended to be within the scope of this disclosure. Furthermore, although a particular distribution of responsibilities may be defined above for descriptive purposes, individual functions and responsibilities may be distributed and divided in different ways depending on the environment.

Claims

1. A system for frame alignment recovery in high-speed signaling interconnects, comprising: A first device, comprising a transmitter and coupled to a link including two or more data paths, is used for: - Send two or more frames to synchronize the two or more data paths, wherein each frame includes a certain number of bits; and A second device, coupled to the link and including a receiver, is used for: - Receive from each data path a first set of bits corresponding to the specified number of bits in each of the two or more frames; - Determine that the first set of bits received from one of the two or more data paths does not correspond to the frame boundary of the two or more frames; - In response to determining that the first set of bits does not correspond to the frame boundary, each of the two or more data paths is synchronized relative to the frame boundary; - Receive the count value of the counting pattern sent by the first device from each data path; as well as - Shift the counting pattern received at data paths that receive a different count value than the earliest count value by increasing one or more burst unit intervals (BUI) until each data path receives the same count value.

2. The system of claim 1, wherein, in order to synchronize each of the two or more data paths, the second device is further configured to: In response to determining that the first group of bits does not correspond to the frame boundary, the first group of bits received at one or more data paths in the two or more data paths is shifted by one or more unit intervals UI; and In response to the shift of the first set of bits received at the data path, an indication is sent to the first device that each of the two or more data paths is synchronized relative to the frame boundary.

3. The system according to claim 2, wherein: The first device is further used for: Receive the indication that each of the two or more data paths is synchronized with respect to the frame boundary; A second set of frames is transmitted on each of the two or more data paths, the second set of frames being associated with the counting mode, each frame in the second set of frames including a count value and transmitted during the clock cycle of the transmitter clock; and The second device is further used for: The second set of frames is received on each of the two or more data paths; It is determined that the count value received at one of the two or more data paths is different from the count value received at the remaining data paths in the two or more data paths; In response to determining that the count values ​​at the data path are different, the second set of frames received at the data path is shifted by at least one burst unit interval (BUI). as well as In response to the second set of frames shifted in the data path, the first device is sent an indication that the frame boundary is the same for each of the two or more data paths.

4. The system of claim 3, wherein the second device is further configured to: In response to receiving the second set of frames on each data path, a count value is determined in the second set of frames received on the two or more data paths; and The count value in the second set of frames is compared with each of the remaining count values ​​received in the remaining data paths, wherein determining that the count value received in the data path is different from the remaining count values ​​received in the remaining data paths is based at least in part on comparing the count value in the second set of frames with the remaining count values ​​received in the two or more data paths.

5. The system of claim 3, wherein the second device is further configured to: The shifted counting pattern generated after shifting the second set of frames received at the data path is compared with the counting patterns received at the remaining data paths in the two or more data paths; and The second device determines that the shifted counting pattern at the data path is the same as the counting pattern received at the remaining data paths in the two or more data paths, wherein the second device is configured to send an indication that the frame boundary is the same for each of the two or more data paths in response to determining that the shifted counting pattern received at the data path is the same.

6. The system of claim 3, wherein the second device is further configured to: The shifted counting pattern generated after shifting the second set of frames received at the data path is compared with the counting patterns received at the remaining data paths in the two or more data paths. Determine that the shifted counting pattern at the data path is different from the counting pattern received at the remaining data paths in the two or more data paths; In response to determining that the shifted counting patterns are different, the shifted counting patterns at the data path are shifted by one BUI to generate a second shifted counting pattern. The second shifted counting pattern at the data path is compared with the counting patterns received at the remaining data paths in the two or more data paths; as well as The second device determines that the second shifted counting pattern at the data path is the same as the counting pattern received at the remaining data paths in the two or more data paths, wherein the second device is configured to send an indication that the frame boundary is the same for each of the two or more data paths in response to determining that the second shifted counting pattern received at the data path is the same.

7. The system according to claim 3, wherein: The specified number of bits is a non-aliased repeating pattern.

8. The system of claim 2, wherein the second device is further configured to: Compare the first shifted set of bits with the stored pattern; and The indication that the first shifted set of bits is associated with the stored pattern is determined in response to the determination that the first shifted set of bits is associated with the stored pattern.

9. The system of claim 2, wherein the second device is further configured to: Compare the shifted first group of bits with the stored pattern; It is determined that the shifted first group of bits does not correspond to the stored pattern based on a comparison between the shifted first group of bits and the stored pattern. In response to determining that the shifted first set of bits does not correspond to the stored pattern, the shifted first set of bits is shifted by an additional one or more UIs to receive a second shifted first set of bits; Compare the second shifted first group of bits with the stored pattern; as well as The indication that the second shifted first set of bits is associated with the stored mode is determined in response to the determination that the second shifted first set of bits is associated with the stored mode.

10. The system of claim 1, wherein the second device is further configured to: The first set of bits received at each data path is compared with the stored pattern; and Determining that the first set of bits received at the data path is different from the stored pattern, wherein determining that the first set of bits received at the data path does not correspond to the frame boundary of the two or more frames is in response to determining that the first set of bits is different from the stored pattern.

11. A method for frame alignment recovery for high-speed signaling interconnects, comprising: Synchronization of two or more data paths on a link coupled to a second device, the synchronization comprising a first phase and a second phase, wherein the first phase includes: - Receive a first set of bits from each of two or more data paths, the number of bits in the first set of bits corresponding to the frame size; - Determine that the first set of bits received from one of the two or more data paths does not correspond to the frame boundary of a frame; - In response to determining that the first group of bits does not correspond to the frame boundary, the first group of bits received at one or more data paths in the two or more data paths is shifted by one or more unit intervals UI; and - In response to the shifting of the first set of bits received at the data path, an indication is sent that each of the two or more data paths is synchronized with respect to the frame boundary; The second stage includes: - Receive the count value of the counting pattern sent by the first device from each data path; and - Shift the counting pattern received at data paths that receive a different count value than the earliest count value by increasing one or more burst unit intervals (BUI) until each data path receives the same count value.

12. The method of claim 11, wherein the second stage further comprises: A second set of frames is received on each of the two or more data paths, the second set of frames being associated with the counting mode; It is determined that the count value received at one of the two or more data paths is different from the count value received at the remaining data paths in the two or more data paths; In response to determining that the count values ​​at the data path are different, the second set of frames received at the data path is shifted by at least one burst unit interval (BUI). as well as In response to shifting the second set of frames in the data path, an indication is sent that the frame boundaries are the same for each of the two or more data paths.

13. The method of claim 12, further comprising: In response to receiving the second set of frames on each data path, a count value is determined in the second set of frames received at the two or more data paths; as well as The count value in the second set of frames is compared with each of the remaining count values ​​received in the remaining data paths, wherein determining that the count value received in the data path is different from the remaining count values ​​received in the remaining data paths is based at least in part on comparing the count value with the remaining count values ​​received in the two or more data paths.

14. The method of claim 12, further comprising: The shifted counting pattern generated after shifting the second set of frames received at the data path is compared with the counting patterns received at the remaining data paths in the two or more data paths. as well as The shifted counting pattern is determined to be the same as the counting pattern received at the remaining data paths in the two or more data paths, wherein in response to determining that the shifted counting pattern received at the data paths is the same, an indication is sent that the frame boundary is the same for each of the two or more data paths.

15. The method of claim 12, further comprising: The shifted counting pattern generated after shifting the second set of frames received at the data path is compared with the counting patterns received at the remaining data paths in the two or more data paths. Determine that the shifted counting pattern is different from the counting pattern received at the remaining data paths in the two or more data paths; In response to determining that the shifted counting patterns are different, the shifted counting patterns are shifted by one BUI to generate a second shifted counting pattern; The second shifted counting pattern is compared with the counting patterns received at the remaining data paths in the two or more data paths; as well as The second shifted counting pattern is determined to be the same as the counting pattern received at the remaining data paths in the two or more data paths, wherein in response to determining that the second shifted counting pattern received at the data path is the same, an indication is sent that the frame boundary is the same for each of the two or more data paths.

16. The method of claim 12, wherein: The first set of bits is associated with a non-aliased repeating pattern.

17. The method of claim 11, further comprising: The first group of shifted bits is compared with the stored pattern; as well as The first shifted set of bits is determined to be associated with the stored pattern, wherein, in response to the determination that the first shifted set of bits is associated with the stored pattern, the indication that two or more data paths are synchronized relative to the frame boundary is sent.

18. The method of claim 17, further comprising: The first shifted set of bits is compared with the stored pattern; Based on the comparison between the shifted first group of bits and the stored pattern, it is determined that the shifted first group of bits does not correspond to the stored pattern. In response to determining that the shifted first set of bits does not correspond to the stored pattern, the shifted first set of bits is shifted by an additional one or more UIs to receive a second shifted first set of bits; Compare the second shifted first group of bits with the stored pattern; as well as The second shifted first set of bits is determined to be associated with the storage mode, wherein in response to determining that the second shifted first set of bits is associated with the storage mode, an indication that the two or more data paths are synchronized relative to the frame boundary is sent.

19. An apparatus for frame alignment recovery in high-speed signaling interconnects, comprising: A receiver coupled to a link comprising two or more data paths, the device being used for: A first set of bits is received from each of the two or more data paths, wherein the number of bits in the first set of bits corresponds to the frame size; It is determined that the first set of bits received from one of the two or more data paths does not correspond to the frame boundary of a frame; In response to determining that the first group of bits does not correspond to the frame boundary, the first group of bits received at one or more data paths in the two or more data paths is shifted by one or more unit intervals UI. In response to the shifting of the first set of bits received at the data path, an indication is sent that each of the two or more data paths is synchronized with respect to the frame boundary; Receive the count value of the counting pattern sent by the transmitter from each of the data paths; as well as The counting pattern received at a data path that receives a different count value than the earliest count value is shifted by adding one or more burst unit intervals (BUI) until each data path receives the same count value.

20. The apparatus of claim 19, wherein the apparatus is further configured to: A second set of frames is received on each of the two or more data paths, the second set of frames being associated with the counting mode; It is determined that the count value received at one of the two or more data paths is different from the count value received at the remaining data paths in the two or more data paths; In response to determining that the count values ​​at the data path are different, the second set of frames received at the data path is shifted by a burst unit interval (BUI). as well as In response to shifting the second set of frames in the data path, an indication is sent that the frame boundaries are the same for each of the two or more data paths.

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