A method for implementing a new lightweight hardware-oriented block cipher ASPF

Abstract

The application discloses an implementation method of a novel hardware-oriented lightweight block cipher ASPF, and relates to the technical field of information encryption. The cipher is obtained by dividing plaintext into four-branch plaintext data groups and then processing the plaintext data groups through two different F functions, so that the structure of the encryption algorithm is more flexible, the hardware implementation efficiency is higher, and a permutation layer is additionally added, so that the diffusion speed is improved. In addition, the resource consumption of the cipher algorithm on hardware is very low, and the cipher algorithm can be used in an environment with limited resources, especially in the case that the hardware resource consumption is relatively harsh or the encrypted data is relatively large.

Description

Technical Field

[0001] This invention relates to the field of information encryption technology, and more specifically to a novel hardware-oriented implementation method of the lightweight block cipher ASPF. Background Technology

[0002] With the maturation of video capture, transmission, and storage technologies and the decrease in related costs, the number of surveillance cameras installed is increasing daily. At the same time, the rapid development of video surveillance and computer technology has also created opportunities for criminals. Because most video sensor networks are in an "unprocessed" state, intruders can steal personal privacy by intercepting video data during transmission. Homes typically use IoT terminal devices with relatively weak computing power and limited storage to drive cameras. Encrypting data on these terminal devices can significantly improve security; therefore, using lightweight encryption algorithms is essential.

[0003] Lightweight block ciphers can be broadly classified into four categories: SPN (Substitution Permutation Networks) structure, Feistel structure, ARX (Add-Rotate-XOR) structure, and combinations of these structures.

[0004] In resource-constrained environments, the S-box of the SPN structure typically consumes significant resources, making it unsuitable for some situations. ARX and Feistel structures, on the other hand, consume fewer hardware resources than SPN, offering a hardware advantage and thus gaining widespread popularity. However, in lightweight block cipher design for resource-constrained environments, while a single Feistel structure consumes fewer resources, its slow diffusion speed and high energy consumption result in insufficient diffusion. A single ARX structure is simple to implement but lacks security. Therefore, a hybrid Feistel structure is often used when employing ARX. In cryptography combining Feistel and ARX structures, while using ARX reduces hardware resource consumption and maintains a certain level of security, the slow diffusion problem of the Feistel structure remains unresolved.

[0005] Therefore, proposing a novel hardware-oriented implementation method for the lightweight block cipher ASPF to improve the practicality and applicability of the encryption algorithm and achieve a balance between algorithm security and resource consumption is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a novel hardware-oriented lightweight block cipher, ASPF, suitable for resource-constrained environments. To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A novel hardware-oriented implementation of the lightweight block cipher ASPF includes:

[0008] S1: Obtain m bits of plaintext and group the plaintext by bit to obtain multiple branches;

[0009] S2: Set an n-bit key, perform round key expansion on the key, and generate the required round keys k0 and k1 through the key arrangement function;

[0010] S3: Perform encryption operations on each branch based on the round keys k0 and k1 using the generalized Fesitel structure transformation, where the generalized Fesitel structure transformation includes performing the left branch F function transformation or the right branch F function transformation on each branch.

[0011] S4: Perform position permutation operation on each branch after the F function transformation in S3, shuffle the order of each branch to obtain the ciphertext generated in this round of loop iteration and use it as the input for the next round of loop iteration;

[0012] S5: Loop back to S2 for the next round of looping, encrypting R rounds to generate ciphertext C.

[0013] Optionally, the specific steps of S1 are as follows:

[0014] The plaintext input is m bits. The generalized Feistel structure contains four plaintext branches of the same size. The plaintext is arranged from the high bit to the low bit, and is denoted as plaintext branch p0, plaintext branch p1, plaintext branch p2, and plaintext branch p3 from left to right.

[0015] Optionally, the specific steps for round key expansion in S2 are as follows:

[0016] 3.1) Construct the key arrangement function structure, input the n-bit master key Key, with the subscripts decreasing from left to right, and initialize the shift parameter d;

[0017] 3.2) First, shift the master key left by d bits, then denote the high m / 4 bits (special case: when n = 80, take m / 2) as k. l The lower m / 4 (special case: when n=80, take m / 2) digits are denoted as k. r ;

[0018] 3.3) Let k l After transformation by the left branch F function, k rAfter transformation by the right branch F function, the 6 bits after the high m / 4 bits of the master key (take 5 when n=80) are XORed with the counter, while the other bits remain unchanged. The updated master key is denoted as K.

[0019] 3.4) Round key during each round of encryption

[0020] 3.5) Proceed to step 3.2) Repeat round R to generate all the round keys required for the encryption process.

[0021] Optionally, the specific settings for the F function in S3 include:

[0022] The generalized Feistel structure transformation includes a left-branch F function and a right-branch F function. The left-branch F function uses an ARX structure, which contains shift parameters a, b, and c, corresponding to the number of bits for the circular left shift. The right-branch F function uses an S-box construction.

[0023] Optionally, the specific steps in S4 for performing the encryption operation of the generalized Fesitel structure transformation on each branch based on the round keys k0 and k1 are as follows:

[0024] The plaintext branches p0 and p1 are operated using the left branch F function; where the left branch F function is an ARX structure, including circular left shift, logical AND and XOR operations;

[0025] The plaintext branches p2 and p3 are operated on using the right branch F function; the right branch F function is an S-box structure, including S-box substitution and XOR operation.

[0026] Optionally, the result of the operation using the F function is denoted as p. i,j Let i represent the i-th round and j represent the j-th branch. The result of the F function after the first round is expressed as:

[0027] Optionally, the specific steps for performing position replacement operations on each branch after the F function operation are as follows: In the above steps, after the F function, branches p0 and p2 have not actually changed, only branches p1 and p3 have changed. In order to allow the branches that did not change in the previous round to change in the next round, an additional replacement layer is added to achieve this purpose.

[0028] Shift the plaintext left by m / 4 bits; p 1,0 =p 1,1 p 1,1 =p 1,2 p 1,2 =p 1,3 p 1,3 =p 1,0 The four new branches p0 = p1,0 p1 = p 1,1 p2 = p 1,2 p3 = p 1,3 The ciphertext is generated as part of one round of iteration and used as input for the next round of iteration.

[0029] Optionally, the hardware settings are: IBM 130nm-8RF synthesis library, ASPF64 / 80 serialization level of 4 bits, and hardware consumption of 889GE. As can be seen from the above technical solution, compared with the prior art, this invention discloses a novel hardware-oriented implementation method for the lightweight block cipher ASPF, which has the following beneficial effects:

[0030] This invention is suitable for use in resource-constrained environments. It utilizes a permutation layer to address the slow diffusion rate problem inherent in the Feistel structure. Furthermore, the round function employs a combination of half ARX and half S-box structures, achieving a balance between security and resource consumption. Although this cipher is essentially a generalized Feistel structure, testing has shown that it only requires 9 rounds to satisfy the avalanche criterion in cryptography. Moreover, the encryption components used in this algorithm are all structurally simple and easy to implement in hardware, making it highly suitable for hardware implementation. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure provided by the present invention.

[0033] Figure 2 This is a schematic diagram of an 80-bit key arrangement.

[0034] Figure 3 This is a schematic diagram of a 100-bit key arrangement.

[0035] Figure 4 This is a schematic diagram of a 120-bit key arrangement.

[0036] Figure 5 This is a schematic diagram of a 140-bit key arrangement.

[0037] Figure 6 Hardware architecture diagram for ASPF64 / 80 serialization of 4 bits.

[0038] Figure 7 This is the ASPF flowchart.

[0039] Figure 8 The image shows the results of the ASPF64 / 80 avalanche test.

[0040] Figure 9 This is a schematic diagram of the process of the present invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] This invention discloses a novel hardware-oriented implementation method for the lightweight block cipher ASPF, comprising:

[0043] S1: Obtain m bits of plaintext and group the plaintext by bit to obtain multiple branches;

[0044] S2: Set an n-bit key, perform round key expansion on the key, and generate the required round keys k0 and k1 through the key arrangement function;

[0045] S3: Perform encryption operations on each branch based on the round keys k0 and k1 using the generalized Fesitel structure transformation, where the generalized Fesitel structure transformation includes performing the left branch F function transformation or the right branch F function transformation on each branch.

[0046] S4: Perform position permutation operation on each branch after the F function transformation in S3, shuffle the order of each branch to obtain the ciphertext generated in this round of loop iteration and use it as the input for the next round of loop iteration;

[0047] S5: Loop back to S2 for the next round of looping, encrypting R rounds to generate ciphertext C.

[0048] Furthermore, a schematic diagram of the structure of a novel hardware-oriented lightweight block cipher, ASPF, is shown below. Figure 1 As shown, it includes the following steps:

[0049] 1) Construct the encryption structure, initialize the shift parameters and S-box; the encryption structure is a 4-branch generalized Feistel structure with an added permutation layer, plaintext input m bits, key n bits, ciphertext m bits; the generalized Feistel structure contains 4 plaintext branches of the same size (m / 4 bits), denoted as p0, p1, p2, and p3 from left to right, corresponding to the high to low bits of plaintext P respectively; the F function part is divided into a left branch F function and a right branch F function, wherein the left branch F function uses an ARX structure, which contains shift parameters 3, 8, and 11, each corresponding to the number of bits for a circular left shift; the right branch F function uses an S-box construction, the S-box being {[0xC,0x5,0x6,0xB,0x9,0x0,0xA,0xD,0x3,0xE,0xF,0x8,0x4,0x7,0x1,0x2]}; the invention will be further described below using an A SPF64 / 80;

[0050] 2) Obtain the plaintext. Divide the 64-bit plaintext into four equal parts from the high bit to the low bit, and use them as the data to be encrypted, p0, p1, p2, and p3, and perform encryption operations.

[0051] 3) Obtain the initial key, and generate the round keys k0 and k1 required in this round using the key arrangement function; the key arrangement function includes the following steps:

[0052] 3.1) Construct the key arrangement function structure, with the input being an 80-bit master key Key (indices decreasing from left to right), and initialize the shift parameter to 61;

[0053] 3.2) First, shift the master key left by 61 bits, then denote the high 32 bits as k. l The lower 32 bits are denoted as k r ;

[0054] 3.3) Let k l After transformation by the left branch F function, k r After the right branch F function is modified, bits 47 to 43 of the master key are XORed with the counter (5 bits for round number), while bits 42 to 32 remain unchanged. The updated master key is denoted as K, and Round_key = K[31:0].

[0055] 3.4) During each round of encryption, the round key k0 = Round_key[31:16], k1 = Round_key[15:0];

[0056] 3.5) Proceed to step 3.2) Repeat 30 rounds to generate all the round keys required for the encryption process;

[0057] 4) The encrypted data p0 and p1 are processed using the left branch F function; the left branch F function is an ARX structure, which includes circular left shift, logical AND and XOR operations;

[0058] 5) The encrypted data p2 and p3 are processed using the right branch F function; the right branch F function is an S-box structure, including S-box substitution and XOR operation;

[0059] 6) The result after passing through the F function is denoted as p. i,j (i represents the i-th round, j represents the j-th branch), where the result of the F function after the first round can be expressed as:

[0060] 7) After passing through the F function in steps 4) and 5) above, branches p0 and p2 have not actually changed, only branches p1 and p3 have changed. In order to allow the branches that did not change in the previous round to change in the next round, an additional replacement layer is added to achieve this purpose.

[0061] 8) The substitution operation shifts the plaintext left by 16 bits, which is equivalent to shifting it left by one branch; p 1,0 =p 1,1 p 1,1 =p 1,2 p 1,2 =p 1,3 p 1,3 =p 1,0 ;

[0062] 9) The four new branches p0 = p generated from steps 4) to 8) above will be processed. 1,0 p1 = p 1,1 p2 = p 1,2 p3 = p 1,3 The ciphertext generated in one round of iteration and used as input for the next round of iteration;

[0063] 10) Proceed to step 3) to begin the next round of encryption. After 30 rounds of encryption, ciphertext C is generated.

[0064] Furthermore, an avalanche severity test was conducted on the algorithm described in this invention, and the results are as follows. Figure 5 As shown in the figure, the avalanche level of each character is around 50%, indicating that the avalanche effect of this code is good.

[0065] Furthermore, when the algorithm described in this invention is implemented in ASIC hardware, the synthesis process library is IBM 130nm-8RF, the serialization level is 4 bits, and the hardware consumption is 889GE. The comparison results of GE consumption with some common lightweight algorithms are shown in Table 1.

[0066] Table 1 Comparison of GE Consumption for Common Lightweight Algorithms

[0067] algorithm GE consumption PRESENT 1339 SIMON 1000 SPECK 1127 ALLPC 1023 ASPF 889

[0068] The data in Table 1 shows that the algorithm has lower hardware consumption for serializing 4 bits, surpassing most lightweight block ciphers and achieving better performance.

[0069] Table 2 is an information table for different versions of ASPF.

[0070] Table 2

[0071] Plaintext length / bit Key length / bit Ciphertext length / bit Number of rounds / rounds ASPF64 / 80 64 80 64 30 ASPF128 / 100 128 100 128 35 ASPF192 / 120 192 120 192 38 ASPF256 / 140 256 140 256 40

[0072] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0073] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A novel hardware-oriented implementation method for the lightweight block cipher ASPF, characterized in that, include: S1: Obtain m bits of plaintext and group the plaintext by bit to obtain multiple branches; S2: Set an n-bit key, perform round key expansion on the key, and generate the required round keys k0 and k1 through the key arrangement function; S3: Perform encryption operations on each branch based on the round keys k0 and k1 using the generalized Fesitel structure transformation, where the generalized Fesitel structure transformation includes performing the left branch F function transformation and the right branch F function transformation; The specific steps for the encryption operation of generalized Fesitel structure transformation based on round keys k0 and k1 for each branch are as follows: The plaintext branches p0 and p1 are operated on using the left branch F function; where the left branch F function is an ARX structure, including circular left shift, logical AND and XOR operations; The plaintext branches p2 and p3 are operated on using the right branch F function; where the right branch F function is an S-box structure, including S-box substitution and XOR operation; The result of the operation using the F function is denoted as p. i,j Let i represent the i-th round and j represent the j-th branch. The result of the F function after the first round is represented as: p 1,0 =p0, S4: Perform position permutation operation on each branch after the F function transformation in S3, shuffle the order of each branch to obtain the ciphertext generated in this round of loop iteration and use it as the input for the next round of loop iteration; S5: Loop back to S2 for the next round of looping, encrypting R rounds to generate ciphertext C.

2. The method for implementing a novel hardware-oriented lightweight block cipher ASPF according to claim 1, characterized in that, The specific steps of S1 are as follows: The plaintext input is m bits. The generalized Feistel structure contains four plaintext branches of the same size. The plaintext is arranged from the high bit to the low bit, and is denoted as plaintext branch p0, plaintext branch p1, plaintext branch p2, and plaintext branch p3 from left to right.

3. The method for implementing a novel hardware-oriented lightweight block cipher ASPF according to claim 1, characterized in that, The specific steps for round key expansion in S2 are as follows: 3.1) Construct the key arrangement function structure, input the n-bit master key Key, with the subscripts decreasing from left to right, and initialize the shift parameter d; 3.2) First, shift the master key left by d bits, then denote the high m / 4 bits as k. l The lower m / 4 bits are denoted as k. r ; 3.3) Let k l After transformation by the left branch F function, k r After transformation by the right branch F function, the 6 bits after the high m / 4 bits of the master key are XORed with the counter, while the other bits remain unchanged. The updated master key is denoted as K. 3.4) Round key during each round of encryption 3.5) Proceed to step 3.2) Repeat round R to generate all the round keys required for the encryption process.

4. The method for implementing a novel hardware-oriented lightweight block cipher ASPF according to claim 1, characterized in that, The specific settings for the F function in S3 include: The generalized Feistel structure transformation includes a left-branch F function and a right-branch F function. The left-branch F function uses an ARX structure, which contains shift parameters a, b, and c, corresponding to the number of bits for the circular left shift. The right-branch F function uses an S-box construction.

5. The method for implementing a novel hardware-oriented lightweight block cipher ASPF according to claim 1, characterized in that, The specific steps for performing position permutation on each branch after the F function operation are as follows: Shift the plaintext left by m / 4 bits; p 1,0 =p 1,1 p 1,1 =p 1,2 p 1,2 =p 1,3 p 1,3 =p 1,0 The four new branches p0 = p 1,0 p1 = p 1,1 p2 = p 1,2 p3 = p 1,3 The ciphertext is generated as part of one round of iteration and used as input for the next round of iteration.

6. The method for implementing a novel hardware-oriented lightweight block cipher ASPF according to claim 1, characterized in that, The hardware settings are as follows: the synthesis process library is IBM 130nm-8RF, the ASPF64 / 80 serialization level is 4 bits, and the hardware consumption is 889GE.

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