Lightweight twofish encryption algorithm accelerator and acceleration method thereof

Abstract

The application provides a lightweight Twofish encryption algorithm accelerator and an acceleration method thereof, wherein main modules include a controller module, a sub-key generation module, a round operation module and an input / output whitening module. The application provides a high-efficiency hardware acceleration circuit for realizing the S-box unit permutation function, and introduces a linear feedback shift register for randomly selecting a permutation circuit in the S-box in each round operation, so as to improve the security of the encryption process. The round operation module and the extended sub-key generation unit, which are two core parts, are highly shared in hardware resources, and are alternately operated according to the switching function of the control signal, so that the resource utilization is less, the hardware implementation scale is small and lightweight, and the module can be well adapted to the module integration in the SoC.

Description

TECHNICAL FIELD

[0001] The present application relates to a design of a lightweight Twofish encryption algorithm hardware accelerator, and belongs to the technical field of encryption and decryption algorithm hardware implementation and hardware accelerator in SoC (System on Chip) design. BACKGROUND

[0002] Twofish is a symmetric encryption algorithm, with a block size of 128 bits and a key length of 256 bits. It is a candidate algorithm for the NIST replacement DES algorithm, Advanced Encryption Standard (AES) algorithm. When it was born, the performance of 128-bit keys was slower than Rijndael for most platforms, but the performance of 256-bit keys was better than the Rijndael encryption algorithm.

[0003] Twofish algorithm has been widely used in data encryption and network security communication due to its good fast encryption and decryption capability and excellent confidentiality and attack resistance. In actual application systems, it usually forms a complete encryption system together with other encryption technologies. SUMMARY

[0004] The purpose of the present application is to provide a lightweight Twofish encryption algorithm hardware accelerator to solve the above problems existing in the prior art, while meeting the lightweight integration requirements of the hardware encryption module in SoC.

[0005] TECHNICAL SOLUTION

[0006] A lightweight Twofish encryption algorithm accelerator, comprising:

[0007] A round operation module for encrypting plaintext, implementing a Feistel structure in encryption operation, and repeating the operation until a predetermined number of rounds is met in each encryption process;

[0008] Including a linear feedback shift register, a nonlinear S-box unit, a maximum distance separable matrix multiplication circuit unit, a modulo adder, and a circular shift register;

[0009] The linear feedback shift register module is signal connected with the nonlinear S-box unit, and outputs a N-bit pseudo-random sequence for the round operation module to randomly select a corresponding permutation circuit, N being a natural number;

[0010] A sub-key generation module including a sub-key S generation unit and an extended sub-key K generation unit, for generating a corresponding key according to an input initial key, and outputting to the nonlinear S-box unit;

[0011] A whitening module for implementing input and output whitening processing;

[0012] The controller module is connected to the subkey generation module and the round operation module by signal, and is used to schedule and control the entire encryption hardware system.

[0013] According to one aspect of the present application, the controller module receives an external input control signal, is responsible for counting the rounds performed by the round operation module and the extended subkey K generation unit during the encryption operation, and sends an end signal when the round operation unit reaches a predetermined round;

[0014] The controller module switches between different functional modes by gating the data selector of the common part of the round operation module and the extended subkey K generation unit to achieve alternating operation of the modules;

[0015] The output of the linear feedback shift register is connected to the nonlinear S-box unit through a data selector. The nonlinear S-box containing different permutation circuits is selected according to the different generated sequences to increase the randomness of the module nonlinear S-box selection when the round operation module runs in each round.

[0016] According to one aspect of the present application, the nonlinear S-box unit includes eight circuits with different structures. Each nonlinear S-box unit is composed of three fixed permutation circuits, and each permutation has two different circuits to choose from.

[0017] The nonlinear S-box unit is two-way parallel, and each nonlinear S-box unit is composed of a structure of four ways containing three q-permutation circuits. The configuration of the internal q-permutation circuit is determined by the pseudo-random sequence output by the linear feedback shift register module;

[0018] The q permutation circuits are of two different types; the q permutation circuits are composed of four groups of 4-bit input and 4-bit output ROM lookup tables, four groups of 4-bit exclusive OR circuits, two groups of shift registers, and two groups of circular shift registers; both q permutation circuits are fixed permutations of the same 8-bit structure, and the data used in the ROM lookup tables corresponding to different q permutation circuits are different.

[0019] According to one aspect of the present application, the modular adder is composed of an adder and a shift register. The adder is a 32-bit three-input adder with a first adder and a second adder in parallel, and is used to calculate a finite field operation between two 32-bit input data and an extended key. The 32-bit three-input adder is an adder without carry.

[0020] The input of one of the 32-bit three-input adders is the output result of the upper and lower maximum distance separable matrix multiplication circuits and the extended subkey, and the input of the other three-input adder is the output result of the matrix multiplication circuit, the result of the lower matrix multiplication shifted left by one position by the shift register, and the extended subkey;

[0021] The two inputs of the first adder are the outputs of the two 32-bit maximum distance separable matrix multiplication circuit units, and the three inputs are the two-input one-output data selector controlled by the control module; the two inputs of the data selector are 0 and the even-order expansion sub-key needed for the round operation; when the control signal passes through the data selector to select the signal 0, the adder presents the function of the expansion sub-key generation unit; when the control signal passes through the data selector to select the even-order expansion sub-key, the adder presents the function of the round operation module.

[0022] The one input of the second adder is the output of the first 32-bit maximum distance separable matrix multiplication circuit unit; the two inputs are the two-input one-output data selector controlled by the control module, and the two ends of the data selector are a group of cyclic shift registers and a shift register; the three inputs are the two-input one-output data selector controlled by the control module, and the two ends of the data selector are signal 0 and the odd-order expansion sub-key needed for the round operation, and the cyclic shift register group in the data selector realizes the function of left shifting 8 bits of the input data, and the shift register group realizes the function of left shifting and filling the last bit with zero.

[0023] For the one input of the second adder, when the control signal passes through the data selector to select the cyclic shift register group, the adder presents the function of the expansion sub-key generation unit; when the control signal passes through the data selector to select the shift register group, the adder presents the function of the round operation module; when the control signal passes through the data selector to select the signal 0, the adder presents the function of the expansion sub-key generation unit; when the control signal passes through the data selector to select the odd-order expansion sub-key, the adder presents the function of the round operation module.

[0024] For the second adder, the two outputs are directly connected to the data selector and the cyclic shift register group connected to the data selector, respectively; when the control signal selects the cyclic shift register group, the output result of the adder presents the output of the expansion sub-key generation unit; when the control signal directly selects the output of the adder, the output result presents the output of the round operation module, and the cyclic shift register group connected to the output realizes the shift function of cyclic left shifting 9 bits of the input data.

[0025] According to one aspect of the present application, the expansion sub-key generation unit and the round operation unit jointly use two 32-bit adders, the input ends of the two adders have one and two two-input one-output data selectors, respectively, and the controller module selects different input signals through the control signal to change the actual input of the two adders, so that the adder presents the partial dedicated function of the round operation module or the sub-key K generation unit.

[0026] According to one aspect of the present application, the sub-key S generating unit generates 2 sets of 32-bit sub-keys S required for 16 rounds of operation of the encryption process; and the extended sub-key K generating unit generates 40 sets of 32-bit sub-keys K.

[0027] According to one aspect of the present application, the sub-key S generating unit comprises 8-way parallel 8-bit finite field multipliers, which generate 2 sets of sub-keys participating in the operation of the nonlinear S-box unit; and when the round operation module is in the running state, the 2 sets of sub-keys are XORed with the first 2 sets of output results of the permutation circuit in the S-box unit.

[0028] According to one aspect of the present application, the 40 sets of sub-keys K generated by the extended sub-key K generating unit are used as inputs of the XOR operation circuit together with the plaintext data and the ciphertext data in the input whitening and output whitening stages respectively.

[0029] The first 8 sets of 32-bit sub-keys generated are used for XORing with the word data to be processed in the input / output whitening module; and the last 32 sets of 32-bit sub-keys generated are used as inputs participating in the operation of the 2-way 32-bit adder of the round operation module in a round.

[0030] According to one aspect of the present application, the whitening module is composed of 8 sets of XOR circuits, each of which is 32 bits, and each of which XORs the input plaintext and the 16th round result of the round operation output with the extended sub-key, so as to make the processed data subsequently enter the calculation of the round operation module and output the final ciphertext.

[0031] In further embodiments, there is also provided an acceleration method of the lightweight Twofish encryption algorithm accelerator according to any one of the above embodiments, comprising the following steps:

[0032] Step 1: reading the initial key, initializing the function of the sub-module and the round number information;

[0033] Step 2: the sub-key generating module generates 2 sets of sub-keys S and 8 sets of extended sub-keys K;

[0034] Step 3: XORing the plaintext with the sub-key K to realize input whitening;

[0035] Step 4: through the function switching of the controller module, the round operation module and the extended sub-key K generating unit are alternately run and updated;

[0036] Step 5: the inter-round register updates the word data to be processed in the next round;

[0037] Step 6: repeating steps 4-5 until the predetermined number of rounds is completed;

[0038] Step 7, XOR operation result and sub-key K to achieve output white to get ciphertext.

[0039] Beneficial effects: on the one hand, the hardware accelerator can efficiently produce ciphertext. On the other hand, the design of the dedicated hardware circuit and the resource sharing between modules. Make the resource utilization is higher, the complex calculation circuit involved is less, and the hardware is easier to realize, better meet the needs of the lightweight IP core mounted in SOoC design. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 Is the overall logical structure of the Twofish algorithm accelerator of the present application.

[0041] Figure 2 Is the q permutation circuit diagram of the present application.

[0042] Figure 3 Is the wheel operation module and the common module of the extended sub-key K generation unit of the present application.

[0043] Figure 4 Is the MDS matrix multiplication calculation circuit diagram of the present application.

[0044] Figure 5 Is the random selection of the S-box permutation circuit of the present application. DETAILED DESCRIPTION

[0045] In order to solve the above problems existing in the prior art, the accelerator and the acceleration algorithm are proposed.

[0046] As shown in Figures 1 to 5 According to the first aspect of the present application, a hardware accelerator for lightweight Twofish encryption algorithm is proposed, which specifically includes the following modules:

[0047] A controller for controlling the algorithm flow execution and the data flow of each unit or module;

[0048] A sub-key generation module for processing the user key to obtain the sub-key;

[0049] A linear feedback shift register (LFSR) module for generating pseudo-random sequences to randomly select S-boxes;

[0050] A round operation module including a plurality of operation units for encrypting plaintext;

[0051] An input and output whitening module based on XOR circuit for realizing input and output whitening processing.

[0052] The controller module receives external input control signals, counts the rounds of the round operation module and the extended sub-key K generating unit during the operation of the encryption system, and sends an end signal to control the module to stop working when the round operation unit reaches the 16th round.

[0053] In further embodiments, the controller module switches between two different functional modes by enabling a data selector that is common to the round operation module and the extended sub-key K generating unit, so as to alternate the operation of the two modules.

[0054] Further, the controller module controls the generation of the two groups of sub-keys S by the sub-key S generating unit. The controller module is connected to the sub-key generating module, the round operation module, and the linear feedback shift register module.

[0055] The input / output whitening module is composed of 8 groups of XOR circuits, each group being 32 bits, which respectively perform XOR operations on the input plaintext and the 16th round result of the round operation output and the extended sub-key, so as to make the processed data subsequently enter the calculation of the round operation module and output the final ciphertext.

[0056] The sub-key generating module is composed of a sub-key S generating unit and an extended sub-key K generating unit, which respectively generate two groups of 32-bit sub-keys S and 40 groups of 32-bit sub-keys K required for the 16 rounds of operation in the encryption process.

[0057] Further, the sub-key S generating unit includes 8 parallel 8-bit finite field multipliers, which generate two groups of sub-keys participating in the operation of the S-box unit. Each group of sub-keys has a bit width of 32 bits, and when the round operation module is in the running state, the two groups of sub-keys perform XOR operations with the output results of the first two groups of the permutation circuit in the S-box unit.

[0058] The extended sub-key K generating unit in the sub-key generating module generates 40 groups of keys K, which are used as inputs of the XOR operation circuit together with the plaintext data and the ciphertext data in the input whitening and output whitening stages, respectively.

[0059] Further, the extended sub-key K generating unit generates the first 8 groups of 32-bit sub-keys K0, K1, …, K7 under the control of the controller module, which are used for XOR operations with the word data to be processed in the input / output whitening module; and the last 32 groups of 32-bit sub-keys K8, K9, …, K 39 , each two groups of sub-keys K 2r+8 , and K 2r+9 (r = 0, …, 15) are used as inputs to participate in the operation of the two 32-bit adders in the round operation module in a round.

[0060] Linear feedback shift register module, composed of four single-bit shift registers and XOR circuits, presents a cyclic spatial structure, and outputs a 4-bit pseudo-random sequence.

[0061] Further, the output of the linear feedback shift register module is connected with the S-box unit in the round operation module through a data selector, and different S-boxes containing different q permutation circuits are selected according to different generated sequences, so as to increase the randomness of the selection of the S-box in the round operation module in each round operation.

[0062] The round operation module realizes the processing function of the word data in the Twofish encryption algorithm, and is the core module of the entire encryption system. It contains a cyclic shift register, a nonlinear S-box lookup table, an MDS matrix multiplication circuit unit, a modulo adder, and a cyclic shift register. The round operation module works under the control of the controller module, is a Feistel structure in the encryption operation, and is repeatedly operated until 16 rounds are met in each encryption process.

[0063] Further, the S-box unit is composed of eight different circuits, and a single S-box is composed of three fixed permutation circuits, each permutation having two different circuits to be selected.

[0064] Further, the S-box unit has two parallel paths, and each S-box unit is composed of four paths each containing three q permutation circuits. The input of each S-box is 32 bits, and the output is 32 bits.

[0065] Further, the output of the S-box unit is connected with the MDS matrix multiplication circuit unit, and the composition of the q permutation circuit inside the S-box unit is determined by the pseudo-random sequence output by the linear feedback shift register module.

[0066] Further, the q permutation circuit in the S-box unit is divided into q0 and q1. The q permutation circuit is composed of four groups of 4-bit input and 4-bit output ROM lookup tables, four groups of 4-bit XOR circuits, two groups of shift registers, and two groups of cyclic shift registers. The two kinds of q permutation circuits are 8-bit fixed permutations, have the same structure, and only differ in the data stored in the corresponding ROM lookup table.

[0067] The MDS matrix multiplication circuit unit is composed of four parallel single-bit XOR circuits, and converts the 8-bit finite field multiplication in the matrix operation into bit-by-bit XOR of 8-bit numbers through the XOR circuit.

[0068] Further, the input of the MDS matrix multiplication circuit unit is four 8-bit data, and the total bit width is 32 bits, which is connected with the output of the S-box unit; the output bit width is 32 bits, which is connected with the input of the modulo adder unit.

[0069] Further, each MDS matrix multiplication circuit unit includes four parallel special circuits, and four 8-bit data inputs are operated four times to complete the matrix multiplication, and the final four 8-bit calculation results are combined into 32 bits as the output.

[0070] The modulo adder unit is composed of a 32-bit adder and a shift register, and two parallel 32-bit three-input bit adders are used to calculate the operation between the two 32-bit data outputs of the MDS matrix multiplication unit and the extended key, and the 32-bit three-input adder is a non-carry adder.

[0071] One input of the three-input adder is the sum of the upper and lower MDS calculation output results and the extended sub-key, and the other input of the three-input adder is the upper MDS calculation output result, the lower MDS calculation result shifted left by one bit by the shift register, and the extended sub-key.

[0072] The extended sub-key generation unit and the round operation unit share two 32-bit adders, and the inputs of the two adders are changed by the gating of the data selector through the control signal, so as to realize the common mode between the two units. The two inputs of the first adder are the outputs of the two MDS matrix multiplication circuits with a bit width of 32 bits, and the three inputs are the two-way data selector controlled by the signal of the control module; the two inputs of the data selector are 0 and the even-order extended sub-key required for the round operation. When the control signal passes through the data selector gating signal 0, the adder presents the function of the extended sub-key generation unit; when the control signal passes through the data selector gating signal of the even-order extended sub-key, the adder presents the function of the round operation module.

[0073] The second adder has one input of the first MDS matrix multiplication circuit with a bit width of 32 bits; the second input is a two-way data selector controlled by the signal of the control module, and the two ends of the data selector are a group of cyclic shift registers and a shift register; the third input is a two-way data selector controlled by the signal of the control module, and the two ends of the data selector are signal 0 and the odd-order extended sub-key required for the round operation. The cyclic shift register group inside realizes the function of left shifting the input data by 8 bits, and the shift register group realizes the function of left shifting the input data and filling the last bit with zero.

[0074] Further, for one of the inputs of the second adder, when the control signal selects the cyclic shift register set through the data selector, the adder presents the function of the extended sub-key generation unit; when the control signal selects the shift register set through the data selector, the adder presents the function of the round operation module. When the control signal selects signal 0 through the data selector, the adder presents the function of the extended sub-key generation unit; when the control signal selects the odd-order extended sub-key through the data selector, the adder presents the function of the round operation module.

[0075] Further, for the second adder, two outputs are directly connected to the data selector and the cyclic shift register set connected to the data selector respectively. When the control signal selects the cyclic shift register set, the output result of the adder presents the output of the extended sub-key generation unit; when the control signal directly selects the output of the adder, the output result presents the output of the round operation module. The cyclic shift register set connected to the output realizes the shift function of cyclic left shift of 9 bits on the input data.

[0076] In a second aspect, an acceleration method of the accelerator of the lightweight Twofish encryption algorithm is provided, and the method specifically includes the following steps:

[0077] Step 1, reading the initial key, initializing the function of the sub-module and the round number information by the controller;

[0078] Step 2, generating two groups of sub-keys S and eight groups of extended sub-keys K by the sub-key generation module;

[0079] Step 3, realizing input whitening by XOR between the plaintext and the sub-key K;

[0080] Step 4, constantly switching the function of the controller, and alternately running and updating the round operation module and the extended sub-key K generation unit;

[0081] Step 5, updating the word data needed to be processed in the next round by the inter-round register.

[0082] Step 6, repeating steps 4-5 until 16 rounds are completed;

[0083] Step 7, realizing output whitening to obtain the ciphertext by XOR between the round operation result and the sub-key K.

[0084] In one embodiment, the encryption system receives 128-bit transmission data and a calculation enable signal each time, and in the encryption process, the 128-bit plaintext is first divided into four groups of 32 bits according to high and low to perform initial whitening, each group of numbers is XORed with the secret key K generated by the sub-key generation module iThe corresponding XOR circuit is used to complete the initialization of the input plaintext data. In each round of operation, the 32-bit high and low bits are divided into R0, R1, R2 and R3, which are stored in four 32-bit registers, and then two of the results R0 and R1 are input into the round operation module to obtain the output according to the following iterative relationship:

[0085] T0 = g(R0);

[0086] T1 = g(ROL(R1, 8));

[0087] F0 = (T0 + T1 + K 2r+8 ) mod 2 32 ;

[0088] F1 = (T0 + 2T1 + K 2r+9 ) mod 2 32 .

[0089] In a further embodiment, the result F0 output by the round operation module is input into the XOR circuit with R2, and then passed through a 32-bit circular shift register to make the XOR result right-shifted by one bit to obtain a 32-bit output result C2; the result F1 is input into a 32-bit circular shift register, left-shifted by one bit, and then input into the XOR circuit with R3 to obtain a 32-bit output result C3. After one round of round operation, the values of R0 and R1 stored in the third and fourth of the four 32-bit inter-round registers are transmitted to the first and second and the registers are refreshed; the C2 and C3 data are transmitted to the third and fourth 32-bit inter-round registers, and when the values of the four registers are refreshed once, a round end signal is generated, which is pulled high and lasts for one clock cycle, and the counter value in the controller module is increased. The round operation module performs the next round of operation under the enablement of the round end signal, and lasts for 16 rounds. It should be noted that after the 16th round of operation, the operation result is no longer stored every two bits by the inter-round register, but directly enters the XOR circuit with the corresponding extended key to complete the output whitening process, and finally the encryption system outputs the ciphertext.

[0090] In a further embodiment, the sub-key S generation module in the sub-key generation module generates two groups of S sub-keys through the operation between the two-part initial key and the RS matrix, which involves the multiplication operation of the finite field GF(2 8 ) whose primitive polynomial is g(x) = x 8 +x 6 +x 3 +x 2+1. The RS matrix is a 4*8 matrix, and the single element bit width is 8 bits. The initial key of 128 bits is divided into 16 parts of [127:120], [119:112], [111:104],..., [7:0] according to every 8 bits. The first eight groups of data are subjected to finite field multiplication by eight multipliers and XOR with the eight elements of each row of the RS matrix in the ROM, and the first group of 32-bit sub-key S0 is obtained after four operations; the last eight groups of data are subjected to operations in the same way as the first eight groups to obtain the second group of 32-bit sub-key S1.

[0091] The sub-key K generation module includes two g function circuits, two 32-bit carry-free adders, and two groups of cyclic shift registers. The two parallel g function circuits and three-input adders are multiplexed by the data selector and the F function module. It should be noted that, since the addition of the sub-key K generation module only involves PHT operation between two output data, only two of the three inputs are used when multiplexing the 32-bit adder.

[0092] The sub-key K is responsible for generating 40 groups of keys in the entire encryption process, which are divided into two parts. First, 8 groups of keys K0, K1,..., K7 needed for input and output whitening are generated at one time. The other part of 32 groups of keys K 2i and K 2i+1 are generated by the controller to enable the next round of operation.

[0093] After the sub-key K generation module provides the input and output whitening keys, the sub-key K generation module and the round operation module are alternately operated by the data selector. The sub-key K generation module first generates the keys K 2i and K 2i+1 , and the round operation module then completes a round of processing of the plaintext data. This process is repeated until the 16th round is completed.

[0094] The input of the round operation module is the whitened data, and the input plaintext data is subjected to confusion and nonlinear processing. Two 32-bit results are output every round, and the result is output to the output whitening module after the last round of operation by the round number control module.

[0095] In further embodiments, each S-box unit in the round operation module, for each single S-box with 8-bit input and 8-bit output, is composed of three fixed permutation circuits, each of which is selected from two possible forms of q0 and q1. q0 and q1 are both 8-bit fixed permutations. The data input into each S-box is divided into two groups of high and low 4-bit to enter the q permutation, and then through a cyclic shift register and a lookup table, an 8-bit output is obtained. Each q permutation uses four lookup tables, each of which is a 4-bit input and a 4-bit output.

[0096] In further embodiments, after the 8-bit data is input, it is divided into high 4-bit a0 and low 4-bit b0, a0 and b0 are jointly input into an XOR circuit to obtain a1, while a0 is input into another XOR circuit with a0 left shifted by three bits and b0 right shifted by one bit through a cyclic shift register to obtain b1. a1 and b1 are respectively input into two different 4-bit input and 4-bit output lookup tables to output a2 and b2. a2 and b2 are jointly input into an XOR circuit to obtain a3, while a2 is input into another XOR circuit with a2 left shifted by three bits and b2 right shifted by one bit through a cyclic shift register to obtain b3. a3 and b3 are respectively input into the third and fourth lookup tables, and the two groups of 4-bit results are combined into an 8-bit result output.

[0097] In further embodiments, each S-box contains three permutation circuits that can be selected from q0 and q1, and there are eight different permutation circuit combination modes to form an S-box. Unlike the traditional Twofish encryption algorithm, each S-box in the round operation module uses an independent linear feedback shift register (LFSR) module to randomly generate a 4-bit sequence, and a data selector is used to select and combine q0 and q1 permutation circuits to randomly form a complete S-box containing three q permutation circuits.

[0098] In further embodiments, for a single S-box unit with 32-bit input and 32-bit output, it contains four parallel 8-bit input and 8-bit output S-boxes, and the four result data outputs enter the MDS matrix multiplication circuit unit. The matrix multiplication involves the calculation of the finite field GF(2 8 ) with the primitive polynomial g(x) = x 8 +x 6 +x 5 +x 3 +1. The present application designs a special simplified calculation circuit for MDS matrix multiplication calculation. The special simplified circuit converts the 8-bit mod2 8 multiplication in matrix operation into a bitwise XOR of 8-bit numbers through an XOR circuit.

[0099] In further embodiments, the 32-bit data output from the two-way matrix multiplication circuit enters two 32-bit adders respectively, and subsequent calculations include PHT operation and finite field GF(2 32 ) addition operation. The expression of PHT operation is:

[0100]

[0101] wherein, represents a 32-bit adder. The present application integrates the PHT operation of two-way data and the subsequent finite field modulo addition operation, and uses a 32-bit three-input carryless adder to implement the two operations.

[0102] In further embodiments, when the controller switches the function enable of the round operation module, two 32-bit data enter the adder according to the selection of the data selector, and the third input of the adder is two groups of subkeys K 2r+8 and K 2r+9 generated by the previous round of the extended subkey K generation unit, and the module outputs two 32-bit width of the result of the pair word data processing after completing the operation; when the controller switches the function enable of the extended subkey K generation unit, the third input of the adder is 0, and two-way data only follows the PHT operation mode to enter the adder to complete the operation, and outputs two 32-bit width of the subkeys K 2r+8 and K 2r+9 .

[0103] In further embodiments, under the control of the controller, the round operation module and the extended subkey K generation unit work alternately for 16 rounds until the end of the entire encryption process.

[0104] As above, although the present application has been shown and described with reference to certain preferred embodiments thereof, it is to be understood that such is by way of illustration and not of limitation. Various changes and modifications can be made to the present application without departing from the spirit and scope of the present application as defined in the appended claims.

Claims

1. A lightweight Twofish encryption algorithm accelerator, characterized by, Comprise: Round operation module, for encrypting plaintext, realizing Feistel structure in encryption operation, repeating running in each encryption process until meeting predetermined round; It contains linear feedback shift register, nonlinear S-box unit, maximum distance separable matrix multiplication circuit unit, modulo adder and circular shift register; The linear feedback shift register module is signal connected with the nonlinear S-box unit, and outputs N-bit pseudo-random sequence for the round operation module to randomly select corresponding permutation circuit, N is a natural number; The sub-key generation module comprises a sub-key S generation unit and an extended sub-key K generation unit, and is used for generating corresponding keys according to the input initial key and outputting to the nonlinear S-box unit; Whitening module, for realizing input and output whitening processing; The controller module is signal connected with the sub-key generation module and the round operation module, and is used for scheduling and controlling the whole encryption hardware system; The controller module receives external input control signal, is responsible for round counting of the round operation module and the extended sub-key K generation unit in the encryption running process, and sends an end signal when the round operation unit reaches the predetermined round; The controller module switches between different functional modes through the data selector which is connected with the round operation module and the extended sub-key K generation unit public part, and realizes the alternate running of the modules. The output of the linear feedback shift register is connected with the nonlinear S-box unit through the data selector, and the nonlinear S-box containing different permutation circuits is selected according to the generated sequence, so as to increase the randomness of the nonlinear S-box selection of the round operation module in each round running.

2. The lightweight Twofish encryption algorithm accelerator according to claim 1, wherein The nonlinear S-box unit comprises eight different structures, each nonlinear S-box unit is composed of three fixed permutation circuits, and each permutation has two different circuits to be selected; Each nonlinear S-box unit is composed of four structures containing three q permutation circuits, and the composition of the q permutation circuit inside is determined by the pseudo-random sequence output by the linear feedback shift register module; The q permutation circuit has two different types; the q permutation circuit is composed of four groups of 4-bit input and 4-bit output ROM lookup table, four groups of 4-bit XOR circuit, two groups of shift register and two groups of circular shift register; the two q permutation circuits are fixed permutations with the same structure of 8 bits, and the data used in the ROM lookup table of the different q permutation circuits is different.

3. The lightweight Twofish encryption algorithm accelerator according to claim 1, wherein The modulo adder is composed of an adder and a shift register, the adder is a 32-bit three-input adder in double parallel of first and second adders, which is used for calculating the finite field operation between two 32-bit input data and the extended key, and the 32-bit three-input adder is a non-carried adder. One of the inputs of the 32-bit three-input adder is the output of the upper and lower maximum distance separable matrix multiplication circuit, and the other input of the three-input adder is the output of the matrix multiplication circuit, the lower matrix multiplication circuit output shifted left by one bit by the shift register and the extended sub-key. The two inputs of the first adder are the outputs of the two 32-bit maximum distance separable matrix multiplication circuit units, and the three inputs of the adder are the two-input data selector controlled by the control module; the two inputs of the data selector are 0 and the even-order extended sub-key required by the round operation; when the control signal passes through the data selector to select the signal 0, the adder presents the function of the extended sub-key generation unit; when the control signal passes through the data selector to select the even-order extended sub-key, the adder presents the function of the round operation module. One of the inputs of the second adder is the output of the 32-bit first maximum distance separable matrix multiplication circuit unit, and the other input of the adder is the two-input data selector controlled by the control module; the two inputs of the data selector are a group of cyclic shift registers and a shift register; the third input of the adder is the two-input data selector controlled by the control module; the two inputs of the data selector are signal 0 and the odd-order extended sub-key required by the round operation; the cyclic shift register group in the adder shifts the input data left by 8 bits, and the shift register group shifts the input data left by 8 bits and fills the last bit with zero. For the first input of the second adder, when the control signal passes through the data selector to select the cyclic shift register group, the adder presents the function of the extended sub-key generation unit; when the control signal passes through the data selector to select the shift register group, the adder presents the function of the round operation module; when the control signal passes through the data selector to select the signal 0, the adder presents the function of the extended sub-key generation unit; when the control signal passes through the data selector to select the odd-order extended sub-key, the adder presents the function of the round operation module. For the second adder, the two outputs are directly connected to the data selector and the cyclic shift register group, respectively; when the control signal selects the cyclic shift register group, the output of the adder presents the output of the extended sub-key generation unit; when the control signal directly selects the output of the adder, the output presents the output of the round operation module, and the cyclic shift register group connected to the output realizes the shift function of cyclic left shift of the input data by 9 bits.

4. The lightweight Twofish encryption algorithm accelerator of claim 1, wherein the extended sub-key generation unit and the round operation unit jointly use two 32-bit adders, the input ends of the two adders have one and two two-input data selectors, respectively, and the controller module selects different input signals by control signals to change the actual inputs of the two adders, so that the adder presents the dedicated function of the round operation module or the sub-key K generation unit. ​ 5. The lightweight Twofish encryption algorithm accelerator as claimed in claim 1, wherein, The subkey S generation unit generates two groups of 32-bit subkeys S required for 16 rounds of encryption operations; the extended subkey K generation unit generates 40 groups of 32-bit subkeys K.

6. The lightweight Twofish encryption algorithm accelerator according to claim 5, wherein, The subkey S generation unit includes 8 parallel 8-bit finite field multipliers to generate two groups of subkeys participating in the nonlinear S-box unit operation; when the round operation module is in operation, the two groups of subkeys are XORed with the first two groups of output results of the permutation circuit in the S-box unit.

7. The lightweight Twofish encryption algorithm accelerator as claimed in claim 5, wherein, The 40 groups of keys K generated by the extended subkey K generation unit are used as inputs of the XOR operation circuit together with the plaintext data and the ciphertext data in the input whitening and output whitening stages respectively; The first eight groups of 32-bit subkeys are used to perform XOR with the word data to be processed in the input and output whitening module; the remaining 32 groups of 32-bit subkeys are used as input in one round to participate in the operation of the two 32-bit adders of the round operation module.

8. The lightweight Twofish encryption algorithm accelerator as claimed in claim 1, wherein, The whitening module is composed of 8 groups of XOR circuits, each group is 32 bits, and the input plaintext and the 16th round result of the round operation are XORed with the extended subkey respectively, so that the processed data can subsequently enter the round operation module for calculation and output the final ciphertext.

9. The acceleration method of the lightweight Twofish encryption algorithm accelerator according to any one of claims 1 to 8, characterized by, The following steps are involved: Step 1: Read the initial key and initialize the submodule function and round number information; Step 2: The subkey generation module generates two sets of subkeys S and eight sets of extended subkeys K; Step 3: XOR the plaintext with the subkey K to achieve input whitening; Step 4: Through the function switching of the controller module, the round operation module and the extended subkey K generation unit are alternately operated and updated; Step 5: The inter-round register updates the word data to be processed in the next round; Step 6: Repeat steps 4 to 5 until the scheduled rounds are completed; Step 7: XOR the round operation result with the subkey K to achieve output whitening and obtain the ciphertext.

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