A signal analysis method, device, apparatus and storage medium

Abstract

Embodiments of the present application relate to the technical field of signal testing, and in particular, relate to a signal analysis method and device, equipment and a storage medium, aiming to improve the speed of PCIE signal consistency analysis. The method comprises: loading a signal acquisition script into a server to be tested; when a channel information viewing instruction for the server to be tested is received, obtaining channel information of all PCIE channels corresponding to a CPU in the server to be tested through the signal acquisition script; determining a PCIE channel to be tested from all PCIE channels according to the channel information; when a rate switching instruction for the PCIE channel to be tested is received, switching the signal transmission rate of the PCIE channel to be tested to a target signal transmission rate corresponding to the rate switching instruction through the signal acquisition script; obtaining a signal waveform diagram of the PCIE channel to be tested at the target signal transmission rate; and performing signal analysis on the PCIE channel to be tested according to the signal waveform diagram to obtain a signal analysis result.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of signal testing, in particular, to a signal analysis method and device, equipment and a storage medium. BACKGROUND

[0002] PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion standard) is a data transmission method widely used today. The CPU of a computer transmits data to the corresponding device through PCIE. The signal consistency analysis of PCIE helps to ensure the safety and stability of the data transmission of PCIE, and is a very important work. When performing signal consistency analysis on PCIE signals, signal waveform graphs at various rates need to be collected for corresponding analysis. In the prior art, when performing signal consistency analysis on PCIE, a multi-channel high-speed oscilloscope with a trigger function needs to be connected to the device under test. The oscilloscope sends a pulse signal of a certain frequency to the device under test to switch the signal transmission rate in the PCIE channel, and then collects the signal waveform graph of the PCIE channel at each signal transmission rate to complete the signal consistency analysis of PCIE.

[0003] When performing signal consistency analysis on PCIE, if the connected oscilloscope does not have a trigger function, the signal consistency analysis of PCIE cannot be performed, which affects the efficiency of signal analysis. SUMMARY

[0004] Embodiments of the present application provide a signal analysis method, device, equipment and storage medium, aiming to improve the speed of PCIE signal consistency analysis.

[0005] The first aspect of the embodiments of the present application provides a signal analysis method, which comprises:

[0006] loading a pre-written signal collection script into a server to be tested, the signal collection script being used to execute related tasks of PCIE signal collection of the server to be tested according to received instructions;

[0007] when receiving a channel information viewing instruction for the server to be tested, obtaining channel information of all PCIE channels corresponding to the CPU in the server to be tested through the signal collection script;

[0008] determining a PCIE channel to be tested from the all PCIE channels according to the channel information;

[0009] when receiving a rate switching instruction for the to-be-tested PCIE channel, switching, by the signal collection script, a signal transmission rate of the to-be-tested PCIE channel to a target signal transmission rate corresponding to the rate switching instruction;

[0010] obtaining a signal waveform diagram of the to-be-tested PCIE channel at the target signal transmission rate;

[0011] performing, according to the signal waveform diagram, signal analysis on the to-be-tested PCIE channel to obtain a signal analysis result.

[0012] Optionally, before obtaining, by the signal collection script, channel information of all PCIE channels corresponding to a CPU in the to-be-tested server, the method further comprises:

[0013] connecting a PC device to the to-be-tested server;

[0014] controlling, by the PC device, the to-be-tested server to run the signal collection script.

[0015] Optionally, when receiving a channel information viewing instruction for the to-be-tested server, obtaining, by the signal collection script, channel information of all PCIE channels corresponding to a CPU in the to-be-tested server, comprises:

[0016] when receiving the channel information viewing instruction, performing, by the signal collection script, the information viewing instruction to perform channel scanning on the PCIE channel;

[0017] generating channel information of the PCIE channel according to a connection state and a current signal transmission rate of the PCIE channel obtained by scanning.

[0018] Optionally, the determining, according to the channel information, of the to-be-tested PCIE channel from the all PCIE channels comprises:

[0019] determining, according to the channel information, a connection state of each PCIE channel in the all PCIE channels;

[0020] taking a PCIE channel with a connection state of being connected as the to-be-tested PCIE channel.

[0021] Optionally, when receiving a rate switching instruction for the to-be-tested PCIE channel, switching, by the signal collection script, a signal transmission rate of the to-be-tested PCIE channel to a target signal transmission rate corresponding to the rate switching instruction, comprises:

[0022] determining, according to the rate switching instruction, a target signal transmission rate of the PCIE channel;

[0023] The PCIE channel rate adjustment module of the CPU is called through the signal acquisition script to adjust the signal transmission rate of the PCIE channel to the target signal transmission rate.

[0024] Optionally, the obtaining of the signal waveform diagram of the PCIE channel to be tested at the target signal transmission rate comprises:

[0025] The signal of the PCIE channel to be tested is transmitted to an oscilloscope pre-connected to the server to be tested at the target signal transmission rate.

[0026] The signal waveform diagram corresponding to the signal of the PCIE channel to be tested is generated through the oscilloscope according to the signal of the PCIE channel to be tested.

[0027] Optionally, the signal analysis of the PCIE channel to be tested according to the signal waveform diagram to obtain a signal analysis result comprises:

[0028] The signal waveform diagram is compared with a standard signal waveform diagram pre-stored to obtain a waveform comparison result.

[0029] The signal analysis result is obtained according to a pre-set signal analysis rule in combination with the waveform comparison result.

[0030] The second aspect of the embodiments of the present application provides a signal analysis device, and the device comprises:

[0031] A file loading module is configured to load a pre-written signal acquisition script into a server to be tested, and the signal acquisition script is configured to execute a related task of PCIE signal acquisition of the server to be tested according to a received instruction.

[0032] A channel information acquisition module is configured to acquire channel information of all PCIE channels corresponding to a CPU in the server to be tested through the signal acquisition script when a channel information viewing instruction for the server to be tested is received.

[0033] A to-be-tested channel determination module is configured to determine a PCIE channel to be tested from all the PCIE channels according to the channel information.

[0034] A rate switching module is configured to switch the signal transmission rate of the PCIE channel to be tested to a target signal transmission rate corresponding to a rate switching instruction for the PCIE channel to be tested through the signal acquisition script when the rate switching instruction is received.

[0035] A signal waveform diagram acquisition module is configured to acquire a signal waveform diagram of the PCIE channel to be tested at the target signal transmission rate.

[0036] The signal analysis result acquisition module is configured to perform signal analysis on the to-be-tested PCIE channel according to the signal waveform diagram, and obtain a signal analysis result.

[0037] Optionally, the device further comprises:

[0038] The device connection module is configured to connect a PC device to the to-be-tested server.

[0039] The program running module is configured to control the to-be-tested server to run the signal acquisition script through the PC device.

[0040] Optionally, the channel information acquisition module comprises:

[0041] The channel scanning submodule is configured to perform channel scanning on the PCIE channel by executing the information viewing instruction through the signal acquisition script when the channel information viewing instruction is received.

[0042] The channel information generation submodule is configured to generate channel information of the PCIE channel according to the connection state and the current signal transmission rate of the PCIE channel obtained through scanning.

[0043] Optionally, the to-be-tested channel determination module comprises:

[0044] The connection state determination submodule is configured to determine the connection state of each PCIE channel in the all PCIE channels according to the channel information.

[0045] The to-be-tested channel determination submodule is configured to take the PCIE channel with a connection valid connection state as the to-be-tested PCIE channel.

[0046] Optionally, the rate switching module comprises:

[0047] The target signal transmission rate determination submodule is configured to determine a target signal transmission rate of the PCIE channel according to the rate switching instruction.

[0048] The rate switching submodule is configured to adjust the signal transmission rate of the PCIE channel to the target signal transmission rate by calling a PCIE channel rate adjustment module of the CPU through the signal acquisition script.

[0049] Optionally, the signal waveform diagram acquisition module comprises:

[0050] The signal transmission submodule is configured to transmit the signal of the to-be-tested PCIE channel to an oscilloscope connected to the to-be-tested server in advance at the target signal transmission rate.

[0051] The signal waveform diagram generation submodule is configured to generate a signal waveform diagram corresponding to the signal of the PCIE channel to be tested according to the signal of the PCIE channel to be tested through the oscilloscope.

[0052] Optionally, the signal analysis result acquisition module comprises:

[0053] The waveform comparison result acquisition submodule is configured to compare the signal waveform diagram with a standard signal waveform diagram stored in advance to obtain a waveform comparison result.

[0054] The signal analysis result acquisition submodule is configured to obtain the signal analysis result according to a pre-set signal analysis rule in combination with the waveform comparison result.

[0055] The third aspect of the embodiments of the present application provides a readable storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement the steps in the method according to the first aspect of the present application.

[0056] The fourth aspect of the embodiments of the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the steps of the method according to the first aspect of the present application are implemented.

[0057] The signal analysis method provided in the application loads a pre-written signal collection script into a server to be tested, the signal collection script is used to execute relevant tasks of PCIE signal collection of the server to be tested according to received instructions; when a channel information viewing instruction for the server to be tested is received, the signal collection script is used to acquire channel information of all PCIE channels corresponding to a CPU in the server to be tested; according to the channel information, a PCIE channel to be tested is determined from the all PCIE channels; when a rate switching instruction for the PCIE channel to be tested is received, the signal collection script is used to switch a signal transmission rate of the PCIE channel to be tested to a target signal transmission rate corresponding to the rate switching instruction; a signal waveform diagram of the PCIE channel to be tested at the target signal transmission rate is acquired; and according to the signal waveform diagram, signal analysis is performed on the PCIE channel to be tested to obtain a signal analysis result. In the application, the signal collection script for performing PCIE signal collection is pre-written, the signal collection script is loaded into the server to be tested, when the PCIE signal of the server to be tested is analyzed, the signal collection script is run, the channel information of all PCIE channels corresponding to the CPU in the server to be tested is acquired, according to the channel information, the PCIE channel to be tested is determined, the signal transmission rate of the PCIE channel to be tested is switched to the target signal transmission rate corresponding to the rate switching instruction by the signal collection script, then the PCIE channel is collected to obtain the signal waveform diagram of the PCIE channel at the target signal transmission rate, the signal waveform diagram is analyzed to obtain the analysis result of the PCIE signal consistency, the signal rate switching is not required to be performed by the oscilloscope with the trigger function, only the signal test script is required to be run by sending the instruction to the server to be tested, the signal transmission rate of the PCIE channel can be switched to any signal transmission rate, the time of signal collection during signal analysis is saved, and the speed of PCIE signal consistency analysis is improved. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the application. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0059] Figure 1 is a flowchart of the signal analysis method provided in an embodiment of the application;

[0060] Figure 2 is a PCIE channel scanning result diagram provided in an embodiment of the application;

[0061] Figure 3 is a PCIE signal test connection diagram of a channel that needs to be triggered;

[0062] Figure 4 is a PCIE script instruction diagram provided by an embodiment of the present application.

[0063] Figure 5 is a schematic diagram of a signal analysis device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0064] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of the present application.

[0065] Reference Figure 1 , Figure 1 is a flowchart of a signal analysis method provided by an embodiment of the present application. As shown in the figure, the method comprises the following steps: Figure 1

[0066] S11: loading a pre-written signal collection script into a server to be tested, the signal collection script being used to execute a related task of PCIE signal collection of the server to be tested according to a received instruction.

[0067] In the embodiment, the signal collection script is a collection of program instructions written for a PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion standard) signal collection task. By running the script and inputting a corresponding instruction, the corresponding module in the computer can be invoked to execute the instruction through the script. The PCIE signal is a signal sent by a PCIE channel on a CPU (central processing unit) of the server to be tested. The server to be tested is a target device to be tested. The CPU in the device contains a plurality of PCIE channels.

[0068] In the embodiment, for a related task of PCIE signal collection that needs to be executed, a signal collection script is written through a program language. The script file written is stored in the server to be tested. Running the script can execute the corresponding signal collection task.

[0069] For example, the signal test script file is copied from the developer's device to a mobile storage device. Then, the mobile storage device is connected to the interface of the server to be tested. The script file is loaded into the server to be tested. ​

[0070] S12: When receiving the channel information viewing instruction for the to-be-tested server, acquiring channel information of all PCIE channels corresponding to the CPU in the to-be-tested server through the signal collection script.

[0071] In this embodiment, the channel information viewing instruction is used to trigger the signal collection script to perform PCIE channel scanning on the to-be-tested server and acquire channel information of all PCIE channels hung under the CPU in the to-be-tested server. The channel information includes the name, number, connection state, address of the channel, signal transmission rate of the channel and other related information of the PCIE channel.

[0072] In this embodiment, when performing signal consistency analysis on the PCIE channel, the PC sends a signal viewing instruction to the to-be-tested server. When the to-be-tested server receives the signal viewing instruction, the signal test script is run. The signal test script performs channel scanning on all PCIE channels in the CPU to obtain channel information of all PCIE channels corresponding to the CPU in the to-be-tested server.

[0073] Reference Figure 2 , Figure 2 is a PCIE channel scanning result diagram proposed in an embodiment of the present application. For example, in 0001:00:01.0 - 1DEF:E102 - Bridge Device - PCI / PCI bridge [x0, GEN 1] (Link down) (S0 RC1.0), 0001:00:00.0 is the domain:b:d:f address of the PCIE channel, i.e., the address of the PCIE channel in the to-be-tested server, 1DEF:E102 represents the channel number of the PCIE channel, Bridge Device - PCI / PCI bridge indicates that the channel is a PCIE channel, [x0, GEN 1] indicates that the speed of the x0 channel is GEN1, GEN1 is a speed level, and each speed level corresponds to a different signal transmission rate. (Link down) indicates that the connection state is not connected, and (S0 RC1.0) indicates the physical channel RC1.0 on the 0th CPU. By performing channel scanning on the to-be-tested server, channel information of all PCIE channels corresponding to the CPU in the to-be-tested server can be acquired, and the channel information is arranged and displayed in the operation window to form a display result like Figure 2 .

[0074] In this embodiment, the information viewing instruction is an instruction that is preset when the signal detection script is written. By inputting the information viewing instruction, channel information can be viewed through the signal detection script.

[0075] S13: determining a PCIE channel to be tested from all the PCIE channels according to the channel information.

[0076] In this embodiment, the PCIE channel to be tested is a PCIE channel that needs to be analyzed for signal consistency, and the PCIE channel has been connected to an oscilloscope.

[0077] In this embodiment, the connection state of each PCIE channel can be viewed in the PCIE channel information. According to the connection state of the PCIE channel, it can be determined whether the PCIE channel has established a connection with the oscilloscope, and then the PCIE channel to be tested is determined from all the PCIE channels.

[0078] For example, the PCIE channel information is viewed, and when the connection state of the channel (S0 RC1.0) is displayed as (link on, normal connection) in the PCIE channel information, it is determined that the channel (S0 RC1.0) is the channel to be tested.

[0079] S14: When receiving a rate switching instruction for the PCIE channel to be tested, the signal transmission rate of the PCIE channel to be tested is switched to a target signal transmission rate corresponding to the rate switching instruction through the signal acquisition script.

[0080] In this embodiment, the rate switching instruction is used to switch the signal transmission rate of the PCIE channel. The target signal transmission rate is the signal transmission rate that the PCIE channel needs to reach.

[0081] In this embodiment, the PC end sends a rate switching instruction for the PCIE channel to be tested to the server to be tested, and the server to be tested runs the signal acquisition script. The signal acquisition script calls the signal rate control module in the CPU to switch the signal transmission rate of the PCIE channel to be tested. The signal transmission rate of the PCIE channel to be tested is switched from the original signal transmission rate to the target signal transmission rate.

[0082] For example, the rate switching instruction is pre-set when the signal acquisition script is written, and the format of the instruction is, for example, pci comp<domain:b:d.f> <gen>Specifically, the instruction pci comp 0008:00:07.0 3 7 represents that the signal transmission rate of the PCIE channel with the address of 0008:00:07.0 is switched to GEN3 Preset (preset value) 7.

[0083] S15: Obtain a signal waveform diagram of the PCIE channel to be tested at the target signal transmission rate.

[0084] In this embodiment, the signal waveform diagram is a waveform diagram corresponding to the PCIE signal generated according to the PCIE signal, which indicates the change of the amplitude during signal transmission.

[0085] In this embodiment, the PCIE channel to be tested on the server to be tested is connected to an oscilloscope in advance. When the control CPU sends a signal at a target signal rate, the oscilloscope collects the PCIE signal and generates a signal waveform diagram according to the signal. When testing the PCIE channel, the signal waveform diagrams at different signal transmission rates need to be collected to analyze the signal consistency of the PCIE channel.

[0086] Generally, when analyzing the consistency of the PCIE signal, in one data path (Lane) of the physical link of the PCIE bus, two groups of differential signals, a total of 4 signal lines, are used. The components of the transmitting end (TX) and the components of the receiving end (RX) are connected using a group of differential signals. This link is also called the transmitting end link, which is also the receiving link of the receiving end. The RX component of the transmitting end and the TX component of the receiving end are connected using another group of differential signals. This link is also called the transmitting end receiving link, which is also the transmitting link of the receiving end. One PCIE link can be composed of multiple paths.

[0087] The PCIE link uses differential signals for data transmission. One differential signal is composed of D+ and D- two signals. The receiving end of the signal compares the difference between the two signals to determine whether the transmitting end transmits a logic "1" or a logic "0". Compared with single-ended signals, differential signals have stronger anti-interference ability because differential signals require equal length, equal width, close proximity, and same layer when wiring. Therefore, external interference noise is "value" and "at the same time" for the two differential signals. The difference is 0 in a rational case, and has little effect on the logic value of the signal. Therefore, differential signals can use higher bus frequencies.

[0088] Currently, PCIE has developed to GEN5, with a transmission rate of up to 32 Gb / s. The standard protocol of GEN6 has also been released. In order to ensure the stable execution of data transmission and reception at high speed, the PCIE is collected by the oscilloscope, the signal waveform diagram of the PCIE signal at different signal transmission rates is obtained, and the signal consistency analysis is performed.

[0089] Reference Figure 3 , Figure 3 is a PCIE signal test connection diagram of a channel that needs to be triggered, Figure 3 The connection method during traditional PCIE testing is shown in FIG. 1. A multi-channel high-speed oscilloscope with a triggering function is used to connect the always-on signal CLK and the TX end signal of the PCIE slot of a server to be tested, and the triggering channel of the oscilloscope is connected to the RX end of the PCIE channel to be tested. During testing, channels 1 and 3 of the oscilloscope collect the PCIE TX signal waveform sent by the CPU, channels 2 and 4 collect the clock signal waveform sent by CLK, and the triggering channel is connected to the PCIE RX. The oscilloscope sends a 200 mv pulse signal, which is sent to the RX end of the PCIE channel to realize the rate switching of the TX end signal, and then the signal waveform is collected.

[0090] In this embodiment, unlike the connection method in Figure 3 , an oscilloscope with a trigger signal sending function is not needed. The channels of the oscilloscope are only connected to the TX end of the PCIE slot to receive the PCIE signal. The signal transmission rate is adjusted by the signal collection script to control the CPU. The signal collection is more convenient, the requirements for the oscilloscope are greatly reduced, the cost of signal analysis is saved, and the rate of signal analysis is improved.

[0091] S16: performing signal analysis on the PCIE channel to be tested according to the signal waveform diagram to obtain a signal analysis result.

[0092] In this embodiment, after the signal waveform diagram is obtained, signal consistency analysis is performed on the PCIE channel to be tested according to a pre-set PCIE signal analysis rule to obtain a signal analysis result.

[0093] In this embodiment, after the signal waveform diagram is collected, the signal waveform diagram is obtained by the server to be tested. The signal waveform diagram is compared with a pre-stored standard signal waveform diagram to determine whether the waveform in the collected signal waveform diagram is abnormal. Then, according to a pre-set PCIE signal analysis rule, the problem existing in the PCIE channel is determined.

[0094] In this embodiment, the signal collection script is pre-written to perform the related task of signal collection of the PCIE channel in the server to be tested. The signal transmission rate of the PCIE channel is not adjusted by sending a pulse. The signal transmission rate of the PCIE channel can be adjusted to the required rate by inputting an instruction. The cost of signal consistency analysis is saved, and the rate of signal consistency analysis is improved.

[0095] In another embodiment of the present application, before step S12, the method further comprises:

[0096] S21: connecting a PC device to the server to be tested.

[0097] In this embodiment, the PC (personal computer) device is the computer terminal of the tester, and the PC device is connected to the system serial port of the server to be tested through a serial port line, so that the PC device can control the server to be tested.

[0098] In this embodiment, when performing PCIE signal consistency analysis on the server to be tested, the PC device is connected to the server to be tested.

[0099] For example, the PC device can be a desktop computer or a tablet computer.

[0100] S22: controlling the server to be tested to run the signal collection script through the PC device.

[0101] In this embodiment, after the PC device is connected to the server to be tested, the server to be tested is controlled to run the signal collection script.

[0102] In this embodiment, the terminal simulation software is installed on the PC device, and the terminal simulation software is used to run the signal collection script. The terminal simulation software provides a port, and the tester can interact with the server to be tested through the terminal simulation software, issue an instruction to the server to be tested, and receive data returned by the server to be tested.

[0103] For example, the terminal simulation software is not limited herein, and for example, putty (serial interface connection software) or xSHELL (secure terminal simulation software) can be used.

[0104] In this embodiment, reference is made to Figure 4 , Figure 4 which is a PCIE script instruction diagram provided in an embodiment of the present application. Each instruction in the input Figure 4 can be used to control the script to perform a corresponding function. After the tester starts the signal collection script and inputs the instruction "pci help" in the window of the terminal simulation software, the PCIE related instructions preset in the signal collection script are displayed, and the tester can implement corresponding functions according to the instructions.

[0105] In this embodiment, the server to be tested is connected through the PC device, and the script in the server to be tested is run using the PC device, which facilitates the tester to quickly collect and analyze PCIE signals.

[0106] In another embodiment of the present application, when the channel information viewing instruction for the server to be tested is received, the channel information of all PCIE channels corresponding to the CPU in the server to be tested is acquired through the signal collection script, including:

[0107] S31: When the channel information viewing instruction is received, executing the information viewing instruction through the signal collection script to perform channel scanning on the PCIE channel.

[0108] In this embodiment, when the to-be-tested server receives a channel information viewing instruction, a signal collection script is run to execute the information viewing instruction to perform channel scanning on all PCIE channels corresponding to the CPU in the to-be-tested server. Through channel scanning on the CPU, the connection state of the PCIE channel and the signal transmission rate of the PCIE channel can be obtained.

[0109] S32: Generating channel information of the PCIE channel according to the connection state and the current signal transmission rate of the PCIE channel obtained through scanning.

[0110] In this embodiment, after the connection state and the current signal transmission rate of each PCIE channel are obtained through scanning, channel information of the PCIE channel is generated, as shown in FIG. 4, and the channel information of the PCIE channel is displayed in the window interface of the terminal simulation software of the PC device, so that the tester can view the channel information of any PCIE channel. Figure 2

[0111] In this embodiment, when the signal consistency of the PCIE channel is analyzed, the corresponding instruction is input, and the channel information of all PCIE channels can be directly viewed, thereby improving the speed of PCIE signal consistency analysis.

[0112] In another embodiment of the present application, the to-be-tested PCIE channel is determined from the all PCIE channels according to the channel information, including:

[0113] S41: According to the channel information, determining the connection state of each PCIE channel in the all PCIE channels.

[0114] In this embodiment, the connection state of each PCIE channel is contained in the channel information of the PCIE channel, and the connection state of the PCIE channel can be determined by viewing the channel information of the PCIE channel. The connection state is divided into a connection valid state and an unconnected state.

[0115] For example, the connection valid state is represented as link on, and the unconnected state is represented as link down.

[0116] S42: Taking the PCIE channel with the connection valid state as the to-be-tested PCIE channel.

[0117] In this embodiment, the PCIE channel with the connection valid state is taken as the to-be-tested PCIE channel.​

[0118] In the embodiment, when the connection state of the PCIE channel is valid, it indicates that the PCIE channel has been connected to the oscilloscope, and the signal of the PCIE channel can be sent to the oscilloscope, and then the signal acquisition of the PCIE channel is completed. When the PCIE signal of another channel needs to be acquired, the oscilloscope can be reconnected to another PCIE channel, or all channels can be connected to the oscilloscope in advance, and when the channel signal of a PCIE channel needs to be acquired, the PCIE channel signal to be acquired can be specified through an instruction.

[0119] In the embodiment, the PCIE channel to be tested is determined according to the channel information of the PCIE channel, so that the signal of the PCIE channel to be tested can be accurately acquired.

[0120] In another embodiment of the application, when the rate switching instruction for the PCIE channel to be tested is received, the signal transmission rate of the PCIE channel to be tested is switched to the target signal transmission rate corresponding to the rate switching instruction through the signal acquisition script, and the method comprises the steps of:

[0121] S51: determining the target signal transmission rate of the PCIE channel according to the rate switching instruction.

[0122] In the embodiment, the channel address of the PCIE channel and the target signal transmission rate to which the PCIE channel needs to be switched are contained in the rate switching instruction.

[0123] In the embodiment, when the server to be tested receives the rate switching instruction, the target signal transmission rate contained in the rate switching instruction is read, and the specific signal transmission rate to which the PCIE channel to be tested needs to be switched is determined.

[0124] For example, when the instruction is "pci comp 0008:00:07.0 3 7", the target signal transmission rate contained therein is GEN3, and the specific value of the signal transmission rate of GEN3 is 8 Gb / s.

[0125] S52: adjusting the signal transmission rate of the PCIE channel to the target signal transmission rate through the PCIE channel rate adjustment module of the CPU called by the signal acquisition script.

[0126] In the embodiment, the channel rate adjustment module is a module integrated in the CPU and is used for adjusting the signal transmission rate of the PCIE channel.

[0127] In the embodiment, after the target signal transmission rate is determined, the PCIE channel rate adjustment module in the CPU of the to-be-tested server is called through the signal acquisition script to switch the signal transmission rate of the to-be-tested PCIE channel from the original signal transmission rate to the target signal transmission rate.

[0128] In the embodiment, the signal transmission rate of the PCIE channel is adjusted by the script control CPU, so that the signal transmission rate of the PCIE channel can be switched, and the signal consistency analysis rate is effectively improved.

[0129] In another embodiment of the present application, the signal waveform diagram of the to-be-tested PCIE channel at the target signal transmission rate is obtained, including:

[0130] S61: transmitting the signal of the to-be-tested PCIE channel to the oscilloscope connected in advance to the to-be-tested server at the target signal transmission rate.

[0131] In the embodiment, after the signal transmission rate of the PCIE channel is adjusted to the target signal transmission rate, the signal of the PCIE channel is transmitted to the oscilloscope at the target signal transmission rate.

[0132] S62: generating the signal waveform diagram corresponding to the signal of the to-be-tested PCIE channel according to the signal of the to-be-tested PCIE channel through the oscilloscope.

[0133] In the embodiment, the oscilloscope generates the waveform diagram corresponding to the signal according to the signal of the to-be-tested PCIE channel when receiving the signal transmitted by the PCIE channel.

[0134] In the embodiment, the oscilloscope displays the corresponding signal waveform diagram on the display screen of the oscilloscope according to the amplitude of the signal during the signal receiving. After the waveform diagram is displayed, the oscilloscope can also store and transmit the waveform diagram to the to-be-tested server.

[0135] In another embodiment of the present application, the signal analysis of the to-be-tested PCIE channel is performed according to the signal waveform diagram to obtain a signal analysis result, including:

[0136] S71: comparing the signal waveform diagram with a standard signal waveform diagram stored in advance to obtain a waveform comparison result.

[0137] In the embodiment, the standard signal waveform diagram is a waveform diagram of the PCIE channel signal under normal conditions, and the standard signal waveform diagram is stored in the to-be-tested server in advance.

[0138] In this embodiment, after the server to be tested obtains the signal waveform diagram of the PCIE channel to be tested, the server to be tested obtains a standard signal waveform diagram pre-stored in the storage space of the server, the standard signal waveform diagram corresponds to a signal with a rate being the current rate of the PCIE channel to be tested, and the standard signal waveform diagram is compared with the signal waveform diagram of the PCIE channel to be tested to obtain a waveform diagram comparison result.

[0139] For example, when there is a difference between the two waveform diagrams, the place different from the standard PCIE waveform diagram can be marked in the PCIE waveform diagram to be tested, and the marked PCIE waveform diagram is taken as the waveform diagram comparison result.

[0140] S72: According to a pre-set signal analysis rule, the signal analysis result is obtained in combination with the waveform diagram comparison result.

[0141] In this embodiment, the signal analysis rule is a rule between a waveform diagram image and a corresponding problem, which is summarized according to problems existing in signal waveform diagrams in a historical signal consistency analysis process, and the pre-set signal analysis rule is stored in the server to be tested.

[0142] In this embodiment, after the waveform diagram comparison result is obtained, the server to be tested views the waveform diagram comparison result according to the pre-set signal analysis rule, and when a problem existing in the signal waveform in the waveform diagram comparison result is the same as a problem in the signal analysis rule, a corresponding signal analysis result can be obtained.

[0143] In this embodiment, the signal analysis rule can be set and summarized by itself, and the newly added signal analysis rule can be added to the storage space of the server to be tested at any time.

[0144] In this embodiment, after the signal waveform diagram of the PCIE channel to be tested is collected, a corresponding signal analysis result is obtained according to an abnormality existing in the signal waveform diagram in combination with the pre-set signal analysis rule, and the speed of PCIE signal consistency analysis is improved.

[0145] Based on the same inventive concept, an embodiment of the present application provides a signal analysis device. Referring to Figure 5 , Figure 5 FIG. 5 is a schematic diagram of a signal analysis device 500 according to an embodiment of the present application. As shown in the figure, the device includes: Figure 5

[0146] A file loading module 501 is configured to load a pre-written signal collection script into a server to be tested, the signal collection script being configured to perform a related task of PCIE signal collection of the server to be tested according to a received instruction.

[0147] ​The channel information acquisition module 502 is configured to acquire channel information of all PCIE channels corresponding to a CPU in the to-be-tested server by using the signal acquisition script when a channel information viewing instruction for the to-be-tested server is received.

[0148] The to-be-tested channel determination module 503 is configured to determine a to-be-tested PCIE channel from the all PCIE channels according to the channel information.

[0149] The rate switching module 504 is configured to switch a signal transmission rate of the to-be-tested PCIE channel to a target signal transmission rate corresponding to the rate switching instruction by using the signal acquisition script when a rate switching instruction for the to-be-tested PCIE channel is received.

[0150] The signal waveform chart acquisition module 505 is configured to acquire a signal waveform chart of the to-be-tested PCIE channel at the target signal transmission rate.

[0151] The signal analysis result acquisition module 506 is configured to perform signal analysis on the to-be-tested PCIE channel according to the signal waveform chart to obtain a signal analysis result.

[0152] Optionally, the device further comprises:

[0153] The device connection module is configured to connect a PC device to the to-be-tested server.

[0154] The program running module is configured to control the to-be-tested server to run the signal acquisition script by using the PC device.

[0155] Optionally, the channel information acquisition module comprises:

[0156] The channel scanning submodule is configured to perform channel scanning on the PCIE channels by using the signal acquisition script when the channel information viewing instruction is received.

[0157] The channel information generation submodule is configured to generate channel information of the PCIE channels according to the connection states and current signal transmission rates of the PCIE channels obtained by scanning.

[0158] Optionally, the to-be-tested channel determination module comprises:

[0159] The connection state determination submodule is configured to determine a connection state of each PCIE channel in the all PCIE channels according to the channel information.

[0160] The to-be-tested channel determination submodule is configured to take a PCIE channel with a valid connection state as the to-be-tested PCIE channel.

[0161] Optionally, the rate switching module comprises:

[0162] a target signal transmission rate determination sub-module, configured to determine a target signal transmission rate of the PCIE channel according to the rate switching instruction;

[0163] a rate switching sub-module, configured to call a PCIE channel rate adjustment module of the CPU through the signal collection script, and adjust the signal transmission rate of the PCIE channel to the target signal transmission rate.

[0164] Optionally, the signal waveform chart acquisition module comprises:

[0165] a signal transmission sub-module, configured to transmit the signal of the PCIE channel to be tested to an oscilloscope pre-connected to the server to be tested at the target signal transmission rate;

[0166] a signal waveform chart generation sub-module, configured to generate a signal waveform chart corresponding to the signal of the PCIE channel to be tested through the oscilloscope.

[0167] Optionally, the signal analysis result acquisition module comprises:

[0168] a waveform comparison result acquisition sub-module, configured to compare the signal waveform chart with a pre-stored standard signal waveform chart to obtain a waveform comparison result;

[0169] a signal analysis result acquisition sub-module, configured to obtain the signal analysis result according to a pre-set signal analysis rule in combination with the waveform comparison result.

[0170] Based on the same inventive concept, another embodiment of the present application provides a readable storage medium having a computer program stored thereon, the program being executed by a processor to implement the steps in the signal analysis method according to any one of the above embodiments of the present application.

[0171] Based on the same inventive concept, another embodiment of the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor being executed to implement the steps in the signal analysis method according to any one of the above embodiments of the present application.

[0172] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts are described in the part of the method embodiment.

[0173] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0174] Those skilled in the art will understand that embodiments of the present application can be provided as methods, apparatus, or computer program products. Accordingly, embodiments of the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, and the like) embodying computer readable program code.

[0175] Embodiments of the present application are described herein with reference to the flowchart illustrations and / or block diagrams of the methods, terminal devices (systems), and computer program products according to embodiments of the present application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 means for performing each of the one or more functions specified in the flowchart illustrations and / or block diagrams.

[0176] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing terminal devices to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 means for performing each of the one or more functions specified in the flowchart illustrations and / or block diagrams.

[0177] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices to cause a series of operational steps to be performed on the computer or other programmable terminal devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal devices provide steps for implementing the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 means for performing each of the one or more functions specified in the flowchart illustrations and / or block diagrams.

[0178] While preferred embodiments of the present application have been described, those skilled in the art will appreciate that other alterations and modifications are possible. Therefore, the appended claims are intended to cover all such alterations and modifications that come within the scope of the present application.

[0179] Finally, it needs to be pointed out that in this document, relational terms such as first and second and the like can only be intended to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any such actual relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by an "comprising" statement serves as a means plus function alternative.

[0180] The above provides a detailed description of the signal analysis method, device, equipment and storage medium provided by the present application. The principles and implementation modes of the present application are described in this document. The above example is only used to help understand the method and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed; in view of the above, the content of the specification should not be understood as a limitation of the present application.< / gen>

Claims

1. A signal analysis method, characterized by, The method comprises: loading a pre-written signal acquisition script into a server to be tested, the signal acquisition script being used to execute relevant tasks of PCIE signal acquisition of the server to be tested according to received instructions; when a channel information viewing instruction for the server to be tested is received, obtaining, by the signal acquisition script, channel information of all PCIE channels corresponding to a CPU in the server to be tested; determining, according to the channel information, a PCIE channel to be tested from the all PCIE channels; when a rate switching instruction for the PCIE channel to be tested is received, switching, by the signal acquisition script, a signal transmission rate of the PCIE channel to be tested to a target signal transmission rate corresponding to the rate switching instruction; obtaining a signal waveform diagram of the PCIE channel to be tested under the target signal transmission rate; performing, according to the signal waveform diagram, signal analysis on the PCIE channel to be tested to obtain a signal analysis result.

2. The method of claim 1, wherein, Before the channel information of all PCIE channels corresponding to a CPU in the server to be tested is obtained by the signal acquisition script, the method further comprises: connecting a PC device to the server to be tested; controlling, by the PC device, the server to be tested to run the signal acquisition script.

3. The method of claim 1, wherein, When the channel information viewing instruction for the server to be tested is received, the channel information of all PCIE channels corresponding to the CPU in the server to be tested is obtained by the signal acquisition script, comprising: when the channel information viewing instruction is received, performing, by the signal acquisition script, the information viewing instruction to scan the PCIE channels; generating channel information of the PCIE channels according to the connection state and the current signal transmission rate of the PCIE channels obtained by scanning.

4. The method of claim 1, wherein, The PCIE channel to be tested is determined from the all PCIE channels according to the channel information, comprising: determining, according to the channel information, the connection state of each PCIE channel in the all PCIE channels; taking a PCIE channel with a connection state of connection valid as the PCIE channel to be tested.

5. The method of claim 1, wherein, When the rate switching instruction for the PCIE channel to be tested is received, the signal transmission rate of the PCIE channel to be tested is switched to the target signal transmission rate corresponding to the rate switching instruction by the signal acquisition script, comprising: determining, according to the rate switching instruction, the target signal transmission rate of the PCIE channel; calling, by the signal acquisition script, a PCIE channel rate adjustment module of the CPU to adjust the signal transmission rate of the PCIE channel to the target signal transmission rate.

6. The method of claim 1, wherein, The signal waveform diagram of the PCIE channel to be tested under the target signal transmission rate is obtained, comprising: transmitting the signal of the PCIE channel to be tested to an oscilloscope connected in advance to the server to be tested at the target signal transmission rate; generating, by the oscilloscope, a signal waveform diagram corresponding to the signal of the PCIE channel to be tested according to the signal of the PCIE channel to be tested.

7. The method of claim 1, wherein, The signal analysis result of the to-be-tested PCIE channel is obtained according to the signal waveform diagram. The signal waveform diagram is compared with a standard signal waveform diagram stored in advance to obtain a waveform comparison result. The signal analysis result is obtained according to a pre-set signal analysis rule in combination with the waveform comparison result.

8. A signal analysis apparatus characterized by comprising: The device comprises: A file loading module, configured to load a pre-written signal collection script into a to-be-tested server, the signal collection script being configured to execute a related task of PCIE signal collection of the to-be-tested server according to a received instruction; A channel information acquisition module, configured to acquire channel information of all PCIE channels corresponding to a CPU in the to-be-tested server through the signal collection script when a channel information viewing instruction for the to-be-tested server is received; A to-be-tested channel determination module, configured to determine a to-be-tested PCIE channel from the all PCIE channels according to the channel information; A rate switching module, configured to switch a signal transmission rate of the to-be-tested PCIE channel to a target signal transmission rate corresponding to a rate switching instruction for the to-be-tested PCIE channel through the signal collection script when the rate switching instruction is received; A signal waveform diagram acquisition module, configured to acquire a signal waveform diagram of the to-be-tested PCIE channel at the target signal transmission rate; A signal analysis result acquisition module, configured to perform signal analysis on the to-be-tested PCIE channel according to the signal waveform diagram to obtain a signal analysis result.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps in the method of any one of claims 1 to 7.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps in the method of any one of claims 1 to 7.

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