Picture acquisition synchronization circuit and distributed camera system

Abstract

The application provides a picture acquisition synchronization circuit and a distributed camera system. When an input interface module is connected with a synchronization line, a detection control module outputs a first control signal. When the input interface module is not connected with the synchronization line, the detection control module outputs a detection signal and a second control signal. When the detection signal is received, a master control chip module generates a master clock signal and a frame synchronization signal. When the first control signal is received, a master clock signal transmission module transmits the master clock signal input by the input interface module to an output interface module, and a frame synchronization signal transmission module transmits the frame synchronization signal input by the input interface module to the output interface module. When the second control signal is received, the master clock signal transmission module transmits the master clock signal of the master control chip module to the output interface module, the frame synchronization signal transmission module transmits the frame synchronization signal of the master control chip module to the output interface module, and a camera module acquires a picture based on the frame synchronization signal and the master clock signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of camera circuit, in particular to a picture acquisition synchronization circuit and a distributed camera system. BACKGROUND

[0002] In a conventional distributed camera system, because the master clock and frame synchronization signal of the internal image sensor of each digital camera are independent, the image frame synchronization cannot be achieved well. For example, if the image of the system is 30fps, that is, the number of frames transmitted per second of the image of the system is 30 frames, the time difference of the image frame can reach about 16 milliseconds. If the difference between the master clock signal or the frame synchronization signal of different cameras exceeds 16 milliseconds, it may cause synchronization picture frame error of different cameras.

[0003] Therefore, in the existing distributed camera system, there is a technical problem that the synchronization effect of the images output by each camera is poor.

[0004] Therefore, it is necessary to provide a picture acquisition synchronization circuit and a distributed camera system to solve the above technical problems. SUMMARY

[0005] The present application provides a picture acquisition synchronization circuit and a distributed camera system, which effectively solves the technical problem that the synchronization effect of the images output by each camera in the existing distributed camera system is poor.

[0006] The present application provides a picture acquisition synchronization circuit, which is arranged in the interior of a camera, and characterized in that it comprises:

[0007] an input interface module for inputting a master clock signal or a frame synchronization signal;

[0008] a detection control module for outputting a first control signal to the master clock signal transmission module and the frame synchronization signal transmission module when the input interface module is connected to a synchronization line, and outputting a detection signal to the master control chip module and outputting a second control signal to the master clock signal transmission module and the frame synchronization signal transmission module when the input interface module is not connected to the synchronization line;

[0009] a master control chip module for outputting the master clock signal to the master clock signal transmission module and outputting the frame synchronization signal to the frame synchronization signal transmission module when receiving the detection signal;

[0010] a master clock signal transmission module for transmitting the master clock signal input by the input interface module to the output interface module when receiving the first control signal, and transmitting the master clock signal generated by the master control chip module to the output interface module when receiving the second control signal;

[0011] The frame synchronization signal transmission module is configured to transmit the frame synchronization signal input by the input interface module to the output interface module when the first control signal is received, and transmit the frame synchronization signal generated by the master control chip module to the output interface module when the second control signal is received.

[0012] The camera module is configured to capture a picture based on the frame synchronization signal and the master clock signal.

[0013] The output interface module is configured to output the master clock signal or the frame synchronization signal.

[0014] In the picture capture synchronization circuit, when the input interface module is connected to the synchronization line, the detection control module outputs the detection signal at a high level, and the master control chip module identifies the working mode of the camera as a slave mode; when the input interface module is not connected to the synchronization line, the detection control module outputs the detection signal at a low level, and the master control chip module identifies the working mode of the camera as a master mode.

[0015] In the picture capture synchronization circuit, the detection control module includes a first MOS tube and a second MOS tube, the gate of the first MOS tube is connected to the input interface module and a power supply, the drain of the first MOS tube is connected to the gate of the second MOS tube, the source of the first MOS tube is grounded, the source and the gate of the second MOS tube are connected, the source of the second MOS tube is also connected to the power supply, the drain of the first MOS tube is also used to output the detection signal and the first control signal, and the drain of the second MOS tube is used to output the second control signal.

[0016] In the picture capture synchronization circuit, the master clock signal transmission module includes a master clock signal transmission chip, the master clock signal transmission chip includes a third control pin and a fourth control pin, the third control pin is connected to the drain of the second MOS tube, the third control pin is used to receive the second control signal, the fourth control pin is connected to the drain of the first MOS tube, and the fourth control pin is used to receive the first control signal.

[0017] The master clock signal transmission chip further includes a third input pin, a fourth input pin and a second output pin, the third input pin is connected to the input interface module, the third input pin is used to receive the master clock signal input by the input interface module, the fourth input pin is connected to the master control chip module, the fourth input pin is used to input the master clock signal generated by the master control chip module, and the second output pin is connected to the output interface module, and the second output pin is used to output the master clock signal.

[0018] In the picture acquisition synchronization circuit, the frame synchronization signal transmission module comprises a frame synchronization signal transmission chip, the frame synchronization signal transmission chip comprises a fifth control pin and a sixth control pin, the fifth control pin is connected with the drain of the second MOS tube, the fifth control pin is used for receiving the second control signal, the sixth control pin is connected with the drain of the first MOS tube, and the sixth control pin is used for receiving the first control signal.

[0019] The frame synchronization signal transmission chip further comprises a fifth input pin, a sixth input pin and a third output pin, the fifth input pin is connected with the input interface module, the fifth input pin is used for receiving the frame synchronization signal input by the input interface module, the sixth input pin is connected with the master control chip module, the sixth input pin is used for inputting the frame synchronization signal generated by the master control chip module, and the third output pin is connected with the output interface module, and the third output pin is used for outputting the frame synchronization signal.

[0020] In the picture acquisition synchronization circuit, the master clock signal transmission chip is a fast logic chip, and the type of the master clock signal transmission chip is SN74lVC2G126; the frame synchronization signal transmission chip is a fast logic chip, and the type of the frame synchronization signal transmission chip is SN74lVC2G126.

[0021] In the picture acquisition synchronization circuit, the picture acquisition synchronization circuit further comprises an information transmission module and an instruction module,

[0022] The instruction module is used for generating a control instruction signal and executing the control instruction signal.

[0023] The information transmission module is connected between the input interface modules and the output interface modules of two adjacent cameras, and is used for transmitting the control instruction signal.

[0024] When the input interface module is connected with the synchronization line, the instruction module receives the control instruction signal from the previous camera through the information transmission module and executes the control instruction signal, and the instruction module sends the control instruction signal to the next camera through the information transmission module.

[0025] When the input interface module is not connected with the synchronization line, the instruction module generates the control instruction signal and executes the control instruction signal, and the instruction module sends the control instruction signal to the next camera through the information transmission module.

[0026] In the picture acquisition synchronization circuit, the picture acquisition synchronization circuit further comprises a synchronization instruction signal transmission module, the input interface module is used for inputting a synchronization instruction signal, the master control chip module is used for outputting the synchronization instruction signal to the synchronization instruction signal transmission module when the detection signal is received, the control instruction signal corresponds to the synchronization instruction signal, and the detection control module is further used for outputting a first control signal to the synchronization instruction signal transmission module when the input interface module is connected with a synchronization line; and outputting a second control signal to the synchronization instruction signal transmission module when the input interface module is not connected with the synchronization line.

[0027] The synchronization instruction signal transmission module is used for transmitting the synchronization instruction signal input by the input interface module to the output interface module when the first control signal is received, and transmitting the synchronization instruction signal generated by the master control chip module to the output interface module when the second control signal is received.

[0028] In the picture acquisition synchronization circuit, the synchronization instruction signal transmission module comprises a synchronization instruction signal transmission chip, the synchronization instruction signal transmission chip comprises a first control pin and a second control pin, the first control pin is connected with the drain of a second MOS tube, the first control pin is used for receiving the second control signal, the second control pin is connected with the drain of a first MOS tube, and the second control pin is used for receiving the first control signal.

[0029] The synchronization instruction signal transmission chip further comprises a first input pin, a second input pin and a first output pin, the first input pin is connected with the input interface module, the first input pin is used for receiving the synchronization instruction signal input by the input interface module, the second input pin is connected with the master control chip module, the second input pin is used for inputting the synchronization instruction signal generated by the master control chip module, and the first output pin is connected with the output interface module, and the first output pin is used for outputting the synchronization instruction signal.

[0030] A distributed camera system comprises:

[0031] A plurality of cameras, and each camera is internally provided with any one of the picture acquisition synchronization circuits, one of the cameras is a host camera, and the rest of the cameras are slave cameras, the working mode of the host camera is a host mode, and the working mode of the slave camera is a slave mode.

[0032] A synchronization line, one end of which is connected to the output interface module of the host camera and the other end of which is connected to the input interface module of the slave camera, or connected between the input interface modules and output interface modules of two adjacent slave cameras, is used to transmit control command signals, synchronization command signals, master clock signals and / or frame synchronization signals;

[0033] Each camera generates an image based on the master clock signal and the frame synchronization signal for subsequent synchronized display; each camera performs synchronized control of all cameras based on the control command signal and the synchronization command signal.

[0034] Compared to existing technologies, the advantages of this invention are as follows: This invention provides a screen capture synchronization circuit, which includes an input interface module, a detection and control module, a main control chip module, a main clock signal transmission module, a frame synchronization signal transmission module, and an output interface module. Driven by a second control signal, the main clock signal transmission module transmits the main clock signal input from the input interface module to the output interface module, and the frame synchronization signal transmission module transmits the frame synchronization signal input from the input interface module to the output interface module.

[0035] Driven by the first control signal, the master clock signal transmission module transmits the master clock signal generated by the master control chip module to the output interface module, and the frame synchronization signal transmission module transmits the frame synchronization signal generated by the master control chip module to the output interface module. Multiple cameras equipped with this image acquisition synchronization circuit can form a distributed camera system, whereby the master clock signal and frame synchronization signal of all camera's internal image sensor are generated by the host camera. Therefore, the frame synchronization of images generated by all cameras can reach a very high standard, improving the image synchronization between different cameras. This effectively solves the technical problem of poor image synchronization between cameras in existing distributed camera systems. Attached Figure Description

[0036] Figure 1 This is a block diagram of a first embodiment of the image acquisition synchronization circuit of the present invention.

[0037] Figure 2 This is a circuit diagram of the input interface module of the first embodiment of the image acquisition synchronization circuit of the present invention.

[0038] Figure 3 This is a circuit diagram of the output interface module of the first embodiment of the image acquisition synchronization circuit of the present invention.

[0039] Figure 4 This is a circuit diagram of the detection control module of the first embodiment of the image acquisition synchronization circuit of the present invention.

[0040] Figure 5The circuit diagram of a main clock signal transmission module of a first embodiment of a picture acquisition synchronization circuit of the present application.

[0041] Figure 6 The circuit diagram of a frame synchronization signal transmission module of a first embodiment of a picture acquisition synchronization circuit of the present application.

[0042] Figure 7 The block diagram of a second embodiment of a picture acquisition synchronization circuit of the present application.

[0043] Figure 8 The circuit diagram of a synchronization instruction signal transmission module of a picture acquisition synchronization circuit of the present application.

[0044] Figure 9 The circuit diagram of an information transmission module of a picture acquisition synchronization circuit of the present application.

[0045] Figure 10 The structural schematic diagram of a synchronization circuit of a distributed camera system of the present application.

[0046] In the figure, 10, picture acquisition synchronization circuit; 11, input interface module; 12, detection control module; 13, main control chip module; 14, synchronization instruction signal transmission module; 15, main clock signal transmission module; 16, frame synchronization signal transmission module; 17, output interface module; 18, information transmission module; 181, instruction module; 19, power supply. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0048] The direction terms mentioned in the present application, such as “up”, “down”, “front”, “back”, “left”, “right”, “inner”, “outer”, “side”, “top” and “bottom”, are only the orientation of the drawings, and the direction terms are used to explain and understand the present application, rather than to limit the present application.

[0049] The terms “first”, “second” and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying relative importance, and are not limited as the order of precedence.

[0050] In the figure, the units with similar structures are denoted by the same reference numerals.

[0051] Please refer to Figure 1The following is a detailed description of the first embodiment of the present application:

[0052] The present application provides a picture acquisition synchronization circuit 10, which is arranged in the interior of a camera. The picture acquisition synchronization circuit 10 comprises an input interface module 11, a detection control module 12, a master control chip module 13, a main clock signal transmission module 15, a frame synchronization signal transmission module 16, an output interface module 17, and a camera module 1A.

[0053] Please refer to Figure 1 , Figure 2 The input interface module 11 is used for inputting a main clock signal or a frame synchronization signal, which comes from a previous camera. The main clock signal can be generated by an image sensor in the camera. The detection control module 12 can output a first control signal OE1 and a second control signal OE2. When the input interface module 11 is connected with a synchronization line, the detection control module 12 outputs the first control signal OE1 to the main clock signal transmission module 15 and the frame synchronization signal transmission module 16. When the input interface module 11 is not connected with the synchronization line, the detection control module 12 outputs a low-level detection signal to the master control chip module 13, and outputs the second control signal OE2 to the main clock signal transmission module 15 and the frame synchronization signal transmission module 16. The camera module 1A performs a picture acquisition operation based on the main clock signal outputted by the main clock signal transmission module 15 and the frame synchronization signal outputted by the frame synchronization signal transmission module 16.

[0054] Please refer to Figure 2 and Figure 4 The input interface module 11 comprises a DET pin, and the detection control module 12 comprises a first MOS tube Q1 and a second MOS tube Q2. The gate of the first MOS tube Q1 is connected with the DET pin of the input interface module 11 and a power supply VCC, and the drain of the first MOS tube Q1 is connected with the gate of the second MOS tube Q2. The source of the first MOS tube Q1 is grounded, and the source and the gate of the second MOS tube Q2 are connected. The source of the second MOS tube Q2 is also connected with a power supply 19. The drain of the first MOS tube Q1 is also used for outputting a detection signal and the first control signal OE1, and the drain of the second MOS tube Q2 is used for outputting the second control signal OE2.

[0055] Please refer to Figure 2 , Figure 5 and Figure 6The input interface module 11 comprises a VD IN pin and a MCLK IN pin. The MCLK IN pin is connected with the third input pin U54 of the main clock signal transmission chip U5, and the MCLK IN pin is connected with the third input pin U64 of the main clock signal transmission chip U6. The VD IN pin is connected with the fifth input pin U34 of the frame synchronization signal transmission chip U3, and the VD IN pin is connected with the fifth input pin U44 of the frame synchronization signal transmission chip U4. The VD IN pin is used for inputting the frame synchronization signal from the previous camera, and the MCLK IN pin is used for inputting the main clock signal from the previous camera.

[0056] Please refer to Figure 1 , Figure 3 and Figure 4 , the detection control module 12 further comprises a first resistor R1, a second resistor R2 and a third resistor R3. One end of the first resistor R1 is connected with the gate of the first MOS Q1. The other end of the first resistor R1 is connected with the power supply VCC, and the resistance value of the first resistor R1 is 100KΩ. One end of the second resistor R2 is connected with the source of the second MOS Q2, the other end of the second resistor R2 is connected with the gate of the second MOS Q2, and the resistance value of the second resistor R2 is 10KΩ. One end of the third resistor R3 is connected with the drain of the second MOS Q2, the other end of the third resistor R3 is grounded, and the resistance value of the third resistor R3 is 10KΩ. The output interface module 17 comprises a PULL_DOWN pin and a fourth resistor R4, and one end of the fourth resistor R4 is connected with the PULL_DOWN pin. The fourth resistor R4 is a pull-down resistor, so that when the input interface module 11 and the output interface module 17 of the adjacent two cameras are connected through the synchronization line, the DET pin of the input interface module 11 of the previous camera can be pulled down to low level by the fourth resistor R4 of the output interface module 17 of the next camera.

[0057] Each camera can be a host and a slave, and the connection mode of the synchronization line determines whether the current camera works in the host mode or the slave mode. The camera is internally provided with a master control chip module 13, which can identify the working mode of the camera as the host mode or the slave mode based on the detection signal. When the input interface module 11 is connected with the synchronization line, the detection control module 12 outputs a high-level detection signal, and the master control chip module 13 identifies the working mode of the camera as the slave mode. When the input interface module 11 is not connected with the synchronization line, the detection control module 12 outputs a low-level detection signal, and the master control chip module 13 identifies the working mode of the camera as the host mode.

[0058] Please refer to Figure 2 , Figure 3 and Figure 4, if the input interface module 11 of the camera is not connected to the synchronization line, since the first resistor R1 can be pulled up to the power supply, the gate of the first MOS tube Q1 inputs a high-level signal (the first MOS tube Q1 is turned on). Thus, the drain of the first MOS tube Q1 outputs a low-level detection signal, and based on the low-level detection signal, the master control chip module 13 can identify that the working mode of the camera is the host mode. If the input interface module 11 of the camera is connected to the synchronization line, the input interface module 11 can be connected to the output interface module 17 of another camera through the synchronization line. At this time, the DET pin of the input interface module 11 is connected to the PULL_DOWN pin of the output interface module 17 of another camera. Thus, the DET pin of the input interface module 11 is pulled down to low level by the fourth resistor R4 of another camera through the synchronization line. Further, the gate of the first MOS tube Q1 inputs a low-level signal. And the drain of the first MOS tube Q1 can output a high-level detection signal (the first MOS tube Q1 is turned off). Based on the high-level detection signal, the master control chip module 13 can identify that the working mode of the camera is the slave mode. When receiving the low-level detection signal, the master control chip module 13 outputs the master clock signal to the master clock signal transmission module 15. And the master control chip module 13 outputs the frame synchronization signal to the frame synchronization signal transmission module 16.

[0059] Please refer to Figure 4 and Figure 5 The master clock signal transmission module 15 includes a master clock signal transmission chip, the master clock signal transmission chip is a fast logic chip, and the model of the master clock signal transmission chip is SN74lVC2G126. The number of the master clock signal transmission chip is two, and the master clock signal transmission chip includes a first master clock signal transmission chip U5 and a second master clock signal transmission chip U6. Among them, the first master clock signal transmission chip U5 and the second master clock signal transmission chip U6 are two identical chips. When receiving the first control signal OE1, the master clock signal transmission module 15 transmits the master clock signal input by the input interface module 11 to the output interface module 17. When receiving the second control signal OE2, the master clock signal transmission module 15 transmits the master clock signal generated by the master control chip module 13 to the output interface module 17.

[0060] Please refer to Figure 4 and Figure 5, the main clock signal transmission chip U5 includes a third control pin U51 and a fourth control pin U52, and the main clock signal transmission chip U6 includes a third control pin U61 and a fourth control pin U62. The third control pin U51 and the third control pin U61 are connected to the drain of the second MOS transistor Q2, and the third control pin U61 and the third control pin U51 are used for receiving the second control signal OE2. The fourth control pin U52 and the fourth control pin U62 are connected to the drain of the first MOS transistor Q1, and the fourth control pin U62 and the fourth control pin U52 are used for receiving the first control signal OE1.

[0061] Please refer to Figure 2 , Figure 4 and Figure 5 , the main clock signal transmission chip U5 further includes a third input pin U54, a fourth input pin U53 and a second output pin U55. The main clock signal transmission chip U6 further includes a third input pin U64, a fourth input pin U63 and a second output pin U65, and the input interface module 11 includes an MCLK_IN pin. The third input pin U54 and the third input pin U64 are connected to the MCLK_IN pin of the input interface module 11, and the third input pin U54 and the third input pin U64 are used for receiving the main clock signal input by the input interface module 11. The fourth input pin U53 and the fourth input pin U63 are connected to the master chip module 13, and the fourth input pin U53 and the fourth input pin U63 are used for inputting the main clock signal generated by the master chip module 13. The second output pin U55 and the second output pin U65 are connected to the output interface module 17, and the second output pin U55 and the second output pin U65 are used for outputting the main clock signal. The main clock signal transmission chip includes a VCC pin and a GND pin, the VCC pin is connected to the power supply 19, and the GND pin is grounded.

[0062] Please refer to Figure 4 and Figure 6 , the frame synchronization signal transmission module 16 includes a frame synchronization signal transmission chip, and the frame synchronization signal transmission chip is a fast logic chip. The frame synchronization signal transmission chip is SN74lVC2G126. The number of frame synchronization signal transmission chips is two, and the frame synchronization signal transmission chip includes a first frame synchronization signal transmission chip U3 and a second frame synchronization signal transmission chip U4. When the first control signal OE1 is received, the frame synchronization signal transmission module 16 transmits the frame synchronization signal input by the input interface module 11 to the output interface module 17. When the second control signal OE2 is received, the frame synchronization signal transmission module 16 transmits the frame synchronization signal generated by the master chip module 13 to the output interface module 17.

[0063] Please refer to Figure 4 and Figure 6 The frame synchronization signal transmission chip U3 includes a fifth control pin U31 and a sixth control pin U32, and the frame synchronization signal transmission chip U4 includes a fifth control pin U41 and a sixth control pin U42. The fifth control pin U31 and the fifth control pin U41 are connected to the drain of the second MOS transistor Q2, and are used for receiving the second control signal OE2. The sixth control pin U32 and the sixth control pin U42 are connected to the drain of the first MOS transistor Q1, and are used for receiving the first control signal OE1.

[0064] Please refer to Figure 2 , Figure 4 and Figure 6 The frame synchronization signal transmission chip U3 further includes a fifth input pin U34, a sixth input pin U33 and a third output pin U35. The frame synchronization signal transmission chip U4 further includes a fifth input pin U44, a sixth input pin U43 and a third output pin U45, and the input interface module 11 includes a VD_IN pin. The fifth input pin U34 and the fifth input pin U44 are both connected to the VD_IN pin of the input interface module 11, and are used for receiving the frame synchronization signal input by the input interface module 11. The sixth input pin U33 and the sixth input pin U43 are both connected to the main control chip module 13, and are used for inputting the frame synchronization signal generated by the main control chip module 13. The third output pin U35 and the third output pin U45 are both connected to the output interface module 17, and are used for outputting the frame synchronization signal. The frame synchronization signal transmission chip includes a VCC pin and a GND pin, the VCC pin is connected to the power supply 19, and the GND pin is grounded.

[0065] Please refer to Figure 4 and Figure 5When the camera operates in the master mode, the third control pin U51 and the third control pin U61 can receive the second control signal OE2. At this time, the third control pin U51 and the third control pin U61 receive a high-level signal. At this time, the fourth input pin U53 and the fourth input pin U63 can input the master clock signal generated by the master chip module 13. And the second output pin U55 and the second output pin U65 can output the master clock signal to the output interface module 17. When the camera operates in the slave mode, the fourth control pin U52 and the fourth control pin U62 can receive the first control signal OE1. At this time, the fourth control pin U52 and the fourth control pin U62 receive a high-level signal. At this time, the third input pin U54 and the third input pin U64 are used to receive the master clock signal input by the input interface module 11. And the second output pin U55 and the second output pin U65 can output the master clock signal to the output interface module 17. Therefore, the picture acquisition synchronization circuit 10 can realize the fast synchronization of the master clock signal transmission between multiple cameras.

[0066] Please refer to Figure 4 and Figure 6 When the camera operates in the master mode, the fifth control pin U31 and the fifth control pin U41 can receive the second control signal OE2. At this time, the fifth control pin U31 and the fifth control pin U41 receive a high-level signal. At this time, the sixth input pin U33 and the sixth input pin U43 can input the frame synchronization signal generated by the master chip module 13. And the third output pin U35 and the third output pin U45 can output the frame synchronization signal to the output interface module 17. When the camera operates in the slave mode, the sixth control pin can receive the first control signal OE1. At this time, the sixth control pin U32 and the sixth control pin U42 receive a high-level signal. At this time, the fifth input pin U34 and the fifth input pin U44 are used to receive the frame synchronization signal input by the input interface module 11. And the third output pin U35 and the third output pin U45 can output the frame synchronization signal to the output interface module 17. Therefore, the picture acquisition synchronization circuit 10 can realize the fast synchronization of the frame synchronization signal transmission between multiple cameras. By selecting a fast logic chip, the picture acquisition synchronization circuit 10 can realize the extremely low delay frame synchronization between the adjacent two cameras. The circuit selects the SN74lVC2G126 logic chip, so that the picture acquisition synchronization circuit 10 realizes the frame synchronization within 8ns of the camera module 1A of the adjacent two cameras.

[0067] Please refer to Figure 3The output interface module 17 is used for outputting the main clock signal or the frame synchronization signal to the next camera. The output interface module 17 comprises a VD_OUT pin and a MCLK_OUT pin. The MCLK_OUT pin is connected to the second output pin, and the VD_OUT pin is connected to the third output pin. The IO_OUT pin is used for outputting the synchronization instruction signal to the next camera, the MCLK_OUT pin is used for outputting the main clock signal to the next camera, and the VD_OUT pin is used for outputting the frame synchronization signal to the next camera. A plurality of cameras provided with the picture acquisition synchronization circuit can form a distributed camera system. The main clock signal and the frame synchronization signal of the image sensor of the camera module 1A of all cameras are generated by the host mode camera, so that the frame synchronization of the generated images of all cameras reaches a very high standard, and the image frame numbers output by all cameras are also strictly the same. In a distributed system composed of 100 digital cameras, the time difference of image frames can be within 0.8us. Moreover, a standard USB3.0 type-c to type-c line is used for synchronization, which reduces the cost of the synchronization line and reduces the complexity of the distributed networking of the plurality of cameras.

[0068] Please refer to Figure 7 The following is a detailed description of the second embodiment of the application:

[0069] The picture acquisition synchronization circuit 10 further comprises an information transmission module 18 and an instruction module 181. The instruction module 181 is used for generating and executing the control instruction signal. The information transmission module 18 is connected between the input interface module 11 and the output interface module 17 of two adjacent cameras, and is used for transmitting the control instruction signal.

[0070] When the input interface module 11 is connected to the synchronization line, i.e. the camera is in the slave mode, the instruction module 181 receives the control instruction signal from the previous camera through the information transmission module 18 and executes the control instruction signal. Then, the instruction module 181 sends the control instruction signal to the next camera through the information transmission module 18. When the input interface module is not connected to the synchronization line, i.e. the camera is in the host mode, the instruction module 181 generates and executes the control instruction signal. Then, the instruction module 181 sends the control instruction signal to the next camera through the information transmission module 18. Therefore, the camera in the host mode can control all cameras in the slave mode through the control instruction signal.

[0071] Please refer to Figure 2 , Figure 3 and Figure 9The information transmission module 18 comprises a fifth resistor R10, a sixth resistor R11, a seventh resistor R12 and an eighth resistor R13. The input interface module 11 comprises a UART0_TX pin, a UART0_RX pin, a UART1_TX pin and a UART1_RX pin. The output interface module 17 comprises a UART0_TX_OUT pin, a UART0_RX_IN pin, a UART1_TX_OUT pin and a UART1_RX_IN pin. One end of the fifth resistor R10 is connected to the UART0_TX pin, and the other end of the fifth resistor R10 is connected to the UART0_TX_OUT pin. One end of the sixth resistor R11 is connected to the UART0_RX pin, and the other end of the sixth resistor R11 is connected to the UART0_RX_IN pin. One end of the seventh resistor R12 is connected to the UART1_TX pin, and the other end of the seventh resistor R12 is connected to the UART1_RX_IN pin. One end of the eighth resistor R13 is connected to the UART0_TX pin, and the other end of the eighth resistor R13 is connected to the UART1_RX_IN pin.

[0072] The control instruction signal can be numbering information. When the camera is in the host mode, the instruction module of the host mode camera numbers the camera. Moreover, the instruction module of the host mode camera can generate numbering information and transmit the numbering information to the next camera. When the camera is in the slave mode, the camera receives the numbering information generated by the previous camera through the information transmission module 18, and the instruction module of the camera can number the camera based on the numbering information. Moreover, the instruction module of the camera can generate numbering information and transmit the numbering information to the next camera.

[0073] For example, the networked cameras can be automatically sequentially numbered. The host mode camera numbers itself as 0 and sends the number 1 to the adjacent slave mode camera through the information transmission module 18. The adjacent host mode camera numbers itself as 1 and sends the number 2 to the next adjacent slave mode camera through the information transmission module 18. The next adjacent slave mode camera numbers itself as 2, and so on. This automatic sequential numbering brings convenience to system maintenance work.

[0074] Further, the picture acquisition synchronization circuit 10 further comprises a synchronization instruction signal transmission module 14. The input interface module 11 is configured to input a synchronization instruction signal. When the detection signal is received, the master control chip module 13 outputs the synchronization instruction signal to the synchronization instruction signal transmission module 14. The control instruction signal corresponds to the synchronization instruction signal. Thus, based on the synchronization instruction signal, all cameras can execute the control instruction signal at the same time. Therefore, even if multiple cameras need to execute the control instruction signal, there will be no delay phenomenon. When the input interface module 11 is connected to the synchronization line, the detection control module 12 further outputs a first control signal OE1 to the synchronization instruction signal transmission module 14. When the input interface module 11 is not connected to the synchronization line, the detection control module 12 outputs a second control signal OE2 to the synchronization instruction signal transmission module 14.

[0075] Please refer to Figure 7 and Figure 8 , the synchronization instruction signal transmission module 14 comprises a synchronization instruction signal transmission chip. The synchronization instruction signal transmission chip is a fast logic chip, and the model of the synchronization instruction signal transmission chip is SN74lVC2G126. The number of the synchronization instruction signal transmission chip is two, and the synchronization instruction signal transmission chip comprises a first synchronization instruction signal transmission chip U1 and a second synchronization instruction signal transmission chip U2. The first synchronization instruction signal transmission chip U1 and the second synchronization instruction signal transmission chip U2 are two identical chips. When the first control signal OE1 is received, the synchronization instruction signal transmission module 14 can transmit the synchronization instruction signal input by the input interface module 11 to the output interface module 17. When the second control signal OE2 is received, the synchronization instruction signal transmission module 14 transmits the synchronization instruction signal generated by the master control chip module 13 to the output interface module 17.

[0076] Please refer to Figure 2 , Figure 4 and Figure 9 , the input interface module 11 comprises a VD_IN pin, an IO_IN pin, and an MCLK_IN pin. The IO_IN pin is configured to input a synchronization instruction signal from an adjacent camera. The synchronization instruction signal transmission chip U1 comprises a first control pin U11 and a second control pin U12, and the synchronization instruction signal transmission chip U2 comprises a first control pin U21 and a second control pin U22. The first control pin U11 and the first control pin U21 are connected to the drain of the second MOS tube Q2. The first control pin U11 and the first control pin U21 are configured to receive the second control signal OE2. The second control pin U12 and the second control pin U22 are connected to the drain of the first MOS tube Q1, and the second control pin U12 and the second control pin U22 are configured to receive the first control signal OE1.

[0077] Please refer to Figure 2 and Figure 8 The synchronous instruction signal transmission chip U1 further comprises a first input pin U14, a second input pin U13 and a first output pin U15, and the synchronous instruction signal transmission chip U2 further comprises a first input pin U24, a second input pin U23 and a first output pin U25. The input interface module 11 comprises an IO IN pin, and the first input pin U14 and the first input pin U24 are connected with the IO IN pin of the input interface module 11. The first input pin U14 and the first input pin U24 are used for receiving the synchronous instruction signal input by the input interface module 11, the second input pin U13 and the second input pin U23 are connected with the main control chip module 13, and the second input pin U13 and the second input pin U23 are used for inputting the synchronous instruction signal generated by the main control chip module 13. The first output pin U15 and the first output pin U25 are connected with the output interface module 17, and the first output pin U15 and the first output pin U25 are used for outputting the synchronous instruction signal. The synchronous instruction signal transmission chip comprises a VCC pin and a GND pin, the VCC pin is connected with the power supply 19, and the GND pin is grounded.

[0078] Please refer to Figure 2 , Figure 3 and Figure 8 , when the camera works in the host mode, the first control pin U11 and the first control pin U21 can receive the second control signal OE2. Among them, the first control pin U11 and the first control pin U21 receive a high-level signal. At this time, the second input pin U13 and the second input pin U23 can input the synchronous instruction signal generated by the main control chip module 13. And the first output pin U15 and the first output pin U25 can output the synchronous instruction signal to the output interface module 17. When the camera works in the slave mode, the second control pin U12 and the second control pin U22 can receive the first control signal OE1. Among them, the second control pin U12 and the second control pin U22 receive a high-level signal. At this time, the first input pin U14 and the first input pin U24 are used for receiving the synchronous instruction signal input by the input interface module 11. And the first output pin U15 and the first output pin U25 can output the synchronous instruction signal to the output interface module 17. The output interface module 17 comprises an IO OUT pin, the IO OUT pin is connected with the first output pin, and the IO OUT pin is used for outputting the synchronous instruction signal to the adjacent external camera.

[0079] When the camera is in slave mode, the synchronization instruction signal transmission module 14 transmits the synchronization instruction signal input by the input interface module 11 to the output interface module 17 under the driving of the first control signal OE1. When the camera is in master mode, the synchronization instruction signal transmission module 14 transmits the synchronization instruction signal generated by the master chip module 13 to the output interface module 17 under the driving of the second control signal OE2. Therefore, the picture acquisition synchronization circuit 10 can realize fast synchronization of the transmission of the synchronization instruction signal among multiple cameras.

[0080] The control instruction signal can be a shutter speed signal, and the execution of the control instruction signal based on the synchronization instruction signal can realize shutter speed synchronization. For the shutter speed signal, the camera in master mode can calculate the shutter speed, and then the camera in master mode transmits the shutter speed signal to all cameras in slave mode through the information transmission module 18. Therefore, all cameras in slave mode share the same shutter speed with the camera in master mode. That is, the master sends its shutter speed to the slave in real time, and the slave sends the shutter speed parameter received from the master to its image sensor, so that the entire system can always use the same shutter speed. The control instruction signal can be a time signal, and the execution of the control instruction signal based on the synchronization instruction signal can realize time synchronization. That is, the camera in master mode sends its system time to the camera in slave mode, so that the entire system can always use the same system time. The control instruction signal can be a task signal, and the execution of the control instruction signal based on the synchronization instruction signal can realize task synchronization. For example, the camera in master mode sends a task signal to the camera in slave mode, and all cameras in the entire system can start recording at the same time or stop recording at the same time. The automatic numbering can take effect in real time, while the shutter speed signal, the time signal, and the task signal can be sent first to control the instruction, and then the camera in master mode can control all cameras to trigger execution at the same time.

[0081] The embodiment provides a picture acquisition synchronization circuit 10, which is arranged in the interior of each camera of a distributed camera system. When the input interface module 11 is connected to the synchronization line, that is, the camera is in slave mode. The detection control module 12 outputs the first control signal OE1 to the master clock signal transmission module 15 and the frame synchronization signal transmission module 16. When the input interface module 11 is not connected to the synchronization line, that is, the camera is in master mode. The detection control module 12 outputs a low-level detection signal to the master chip module 13. Moreover, the detection control module 12 outputs the second control signal OE2 to the master clock signal transmission module 15 and the frame synchronization signal transmission module 16.

[0082] When the first control signal OE1 is received, the main clock signal transmission module 15 transmits the main clock signal inputted by the input interface module 11 to the output interface module 17, and the frame synchronization signal transmission module 16 transmits the frame synchronization signal inputted by the input interface module 11 to the output interface module 17. When the second control signal OE2 is received, the main clock signal transmission module 15 transmits the main clock signal generated by the main control chip module 13 to the output interface module 17, and the frame synchronization signal transmission module 16 transmits the frame synchronization signal generated by the main control chip module 13 to the output interface module 17. Moreover, the output interface module 17 can output the main clock signal or the frame synchronization signal.

[0083] Moreover, the picture acquisition synchronization circuit 10 further comprises an information transmission module 18 and an instruction module 181. The instruction module 181 is used for generating and executing a control instruction signal, and the information transmission module 18 is connected between the input interface module and the output interface module of two adjacent cameras, and is used for transmitting the control instruction signal.

[0084] When the input interface module 11 is connected with the synchronization line, i.e. the camera is in the slave mode. The instruction module 181 receives the control instruction signal from the previous camera through the information transmission module 18 and executes the control instruction signal, and the instruction module 181 can also send the control instruction signal to the next camera through the information transmission module 18. When the input interface module 11 is not connected with the synchronization line, i.e. the camera is in the master mode. The instruction module 181 generates and executes the control instruction signal, and the instruction module 181 sends the control instruction signal to the next camera through the information transmission module 18.

[0085] The picture acquisition synchronization circuit 10 further comprises a synchronization instruction signal transmission module 14. When the input interface module 11 is connected with the synchronization line, the detection control module 12 outputs the first control signal OE1 to the synchronization instruction signal transmission module 14. When the input interface module 11 is not connected with the synchronization line, the detection control module 12 outputs a low-level detection signal to the main control chip module 13, and outputs the second control signal OE2 to the synchronization instruction signal transmission module 14. When the low-level detection signal is received, the main control chip module 13 outputs a synchronization instruction signal to the synchronization instruction signal transmission module 14. The control instruction signal corresponds to the synchronization instruction signal. Thus, when the first control signal OE1 is received, the synchronization instruction signal transmission module 14 transmits the synchronization instruction signal inputted by the input interface module 11 to the output interface module 17. When the second control signal OE2 is received, the synchronization instruction signal transmission module transmits the synchronization instruction signal generated by the main control chip module 13 to the output interface module 17.

[0086] Therefore, in the third embodiment of the present application, each camera can generate pictures based on the master clock signal and the frame synchronization signal, so that the subsequent pictures can be synchronously displayed. Since the master clock signal and the frame synchronization signal correspond to each other, the frame synchronization of the pictures generated by all the cameras reaches a very high standard. Moreover, each camera synchronously controls all the cameras based on the control instruction signal and the synchronization instruction signal. Based on the synchronization instruction signal, the host mode camera can control all the cameras to simultaneously trigger the execution of the control instruction signal. Thus, all the cameras will not be delayed when performing the task of the host.

[0087] The present application also includes a distributed camera system, which comprises a plurality of cameras and a synchronization line. The picture acquisition synchronization circuit 10 described above is arranged in each camera in a one-to-one correspondence, wherein one camera is a host camera and the rest are slave cameras. The working mode of the host camera is a host mode, and the working mode of the slave camera is a slave mode. One end of the synchronization line is connected with the output interface module 17 of the host camera, and the other end of the synchronization line is connected with the input interface module 11 of the slave camera. Alternatively, the synchronization line can also be connected between the input interface module 11 and the output interface module 17 of two adjacent slave cameras, and the synchronization line can be used to transmit the control instruction signal, the synchronization instruction signal, the master clock signal or the frame synchronization signal. Wherein, each camera generates pictures based on the master clock signal and the frame synchronization signal for subsequent picture synchronization display, and each camera synchronously controls all the cameras based on the control instruction signal and the synchronization instruction signal. Specifically as shown in the figure, wherein the synchronization signal includes the synchronization instruction signal, the master clock signal and the frame synchronization signal, and the instruction signal includes the control instruction signal. Figure 10

[0088] ​The working principle of the present application is that when the input interface module 11 is not connected with the synchronization line, the detection control module 12 outputs a low-level detection signal. Then, the main control chip module 13 can identify the working mode of the camera as the host mode. And, the main control chip module 13 can generate a main clock signal and a frame synchronization signal. Subsequently, the detection control module 12 outputs a second control signal OE2. The third control pin U51 and the third control pin U61 receive the second control signal OE2. Based on the second control signal OE2, the fourth input pin U53 and the fourth input pin U63 can input the main clock signal generated by the main control chip module 13. And, the second output pin U55 and the second output pin U65 can output the main clock signal to the output interface module 17. Moreover, the fifth control pin U31 and the fifth control pin U41 of the frame synchronization signal transmission chip can receive the second control signal OE2. Based on the second control signal OE2, the sixth input pin U34 and the sixth input pin U44 can input the frame synchronization signal generated by the main control chip module 13. And, the third output pin U35 and the third output pin U45 can output the frame synchronization signal to the output interface module 17. Since the output interface module 17 is connected with the next camera through the synchronization line, the output interface module 17 can output the main clock signal or the frame synchronization signal to the next camera.

[0089] Moreover, the instruction module 181 generates a control instruction signal. At the same time, based on the low-level detection signal, the main control chip module 13 can also generate a synchronization instruction signal. And, the first control pin U11 and the first control pin U21 both receive the second control signal OE2 outputted by the detection control module 12. Based on the second control signal OE2, the second input pin U13 and the second input pin U23 can input the synchronization instruction signal generated by the main control chip module 13. And, the control instruction signal corresponds to the synchronization instruction signal. Therefore, the camera can execute the control instruction signal based on the synchronization instruction signal. Then, the first output pin U15 and the first output pin U25 can output the synchronization instruction signal to the output interface module 17. And, the instruction module 181 also sends the control instruction signal to the next camera through the information transmission module 18.

[0090] When the input interface module 11 is connected with the synchronization line, the input interface module 11 can input the master clock signal or the frame synchronization signal of the previous camera. And the detection control module 12 can output the detection signal of high level. Then, the master control chip module 13 can identify the working mode of the camera as the slave mode. Subsequently, the detection control module 12 outputs the first control signal OE1. And the fourth control pin U52 and the fourth control pin U62 both receive the first control signal OE1. Based on the first control signal OE1, the third input pin U54 and the third input pin U64 can input the master clock signal from the input interface module 11. And the second output pin U55 and the second output pin U65 can output the master clock signal to the output interface module 17. And the sixth control pin U32 and the sixth control pin U42 can receive the first control signal OE1. Based on the first control signal OE1, the fifth input pin U34 and the fifth input pin U44 can input the frame synchronization signal from the input interface module 11. And the third output pin U35 and the third output pin U45 can output the frame synchronization signal to the output interface module 17. And the output interface module 17 can output the master clock signal or the frame synchronization signal to the next camera.

[0091] And the instruction module 181 receives the control instruction signal from the previous camera through the information transmission module 18. At the same time, the second control pin U21 and the second control pin U22 receive the first control signal OE1 output by the detection control module 12. Based on the first control signal OE1, the first input pin U14 and the first input pin U24 can input the synchronization instruction signal from the input interface module 11. And the control instruction signal corresponds to the synchronization instruction signal. Therefore, the camera can execute the control instruction signal based on the synchronization instruction signal. Subsequently, the first output pin U15 and the first output pin U25 can output the synchronization instruction signal to the output interface module 17. And the instruction module 181 can also send the control instruction signal to the next camera through the information transmission module 18.

[0092] The present application provides a kind of picture acquisition synchronization circuit, which includes input interface module, detection control module, master control chip module, master clock signal transmission module, frame synchronization signal transmission module, output interface module. Under the drive of second control signal, master clock signal transmission module transmits the master clock signal input by input interface module to output interface module, frame synchronization signal transmission module transmits the frame synchronization signal input by input interface module to output interface module.

[0093] Under the driving of the first control signal, the main clock signal transmission module transmits the synchronization instruction signal generated by the master chip module to the output interface module, and the frame synchronization signal transmission module transmits the frame synchronization signal generated by the master chip module to the output interface module. A plurality of cameras provided with the picture acquisition synchronization circuit can form a distributed camera system, so that the main clock signal and the frame synchronization signal of the internal image sensor of all cameras are generated by the host mode camera. Therefore, the frame synchronization of the images generated by all cameras can reach a very high standard, and the picture synchronization of different cameras is improved. The technical problem of poor image synchronization effect of each camera output in the existing distributed camera system is effectively solved.

[0094] In summary, although the present application has been disclosed with the preferred embodiments as above, the above preferred embodiments are not intended to limit the present application, and those skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is defined by the scope of the claims.

Claims

1. A picture acquisition synchronization circuit provided inside each camera of a distributed camera system, characterized by, It includes: The input interface module is used for inputting the main clock signal or the frame synchronization signal; The detection control module is used for outputting the first control signal to the main clock signal transmission module and the frame synchronization signal transmission module when the input interface module is connected with the synchronization line; outputting the detection signal to the master chip module and outputting the second control signal to the main clock signal transmission module and the frame synchronization signal transmission module when the input interface module is not connected with the synchronization line; The master chip module is used for outputting the main clock signal to the main clock signal transmission module and outputting the frame synchronization signal to the frame synchronization signal transmission module when receiving the detection signal; The main clock signal transmission module is used for transmitting the main clock signal input by the input interface module to the output interface module when receiving the first control signal; transmitting the main clock signal generated by the master chip module to the output interface module when receiving the second control signal; The frame synchronization signal transmission module is used for transmitting the frame synchronization signal input by the input interface module to the output interface module when receiving the first control signal; transmitting the frame synchronization signal generated by the master chip module to the output interface module when receiving the second control signal; The camera module is used for capturing pictures based on the frame synchronization signal and the main clock signal; The output interface module is used for outputting the main clock signal or the frame synchronization signal; The detection control module includes a first MOS tube and a second MOS tube, the gate of the first MOS tube is connected with the input interface module and a power supply, the drain of the first MOS tube is connected with the gate of the second MOS tube, the source of the first MOS tube is grounded, the source and the gate of the second MOS tube are connected, the source of the second MOS tube is also connected with the power supply, the drain of the first MOS tube is used for outputting the detection signal and the first control signal, and the drain of the second MOS tube is used for outputting the second control signal. When the input interface module is connected with the synchronization line, the detection control module outputs the detection signal with high level, and the master chip module identifies the working mode of the camera as the slave mode; when the input interface module is not connected with the synchronization line, the detection control module outputs the detection signal with low level, and the master chip module identifies the working mode of the camera as the master mode. The main clock signal transmission module includes a main clock signal transmission chip, the main clock signal transmission chip includes a third control pin and a fourth control pin, the third control pin is connected with the drain of the second MOS tube, the third control pin is used for receiving the second control signal, the fourth control pin is connected with the drain of the first MOS tube, and the fourth control pin is used for receiving the first control signal; 2. The picture capture synchronization circuit of claim 1, wherein, ​ 3. The picture acquisition synchronization circuit of claim 1, wherein, ​ The main clock signal transmission chip further comprises a third input pin, a fourth input pin and a second output pin, the third input pin is connected with the input interface module, the third input pin is used for receiving the main clock signal input by the input interface module, the fourth input pin is connected with the main control chip module, the fourth input pin is used for inputting the main clock signal generated by the main control chip module, and the second output pin is connected with the output interface module, and the second output pin is used for outputting the main clock signal.

4. The picture capture synchronization circuit of claim 3, wherein, The frame synchronization signal transmission module comprises a frame synchronization signal transmission chip, the frame synchronization signal transmission chip comprises a fifth control pin and a sixth control pin, the fifth control pin is connected with the drain of the second MOS tube, the fifth control pin is used for receiving the second control signal, and the sixth control pin is connected with the drain of the first MOS tube, and the sixth control pin is used for receiving the first control signal. The frame synchronization signal transmission chip further comprises a fifth input pin, a sixth input pin and a third output pin, the fifth input pin is connected with the input interface module, the fifth input pin is used for receiving the frame synchronization signal input by the input interface module, the sixth input pin is connected with the main control chip module, the sixth input pin is used for inputting the frame synchronization signal generated by the main control chip module, and the third output pin is connected with the output interface module, and the third output pin is used for outputting the frame synchronization signal.

5. The picture capture synchronization circuit of claim 4, wherein, The main clock signal transmission chip is a fast logic chip, and the model of the main clock signal transmission chip is SN74lVC2G126; the frame synchronization signal transmission chip is a fast logic chip, and the model of the frame synchronization signal transmission chip is SN74lVC2G126.

6. The picture capture synchronization circuit of claim 1, wherein, The picture acquisition synchronization circuit further comprises an information transmission module and an instruction module, The instruction module is used for generating a control instruction signal and executing the control instruction signal. The information transmission module is connected between the input interface modules and the output interface modules of two adjacent cameras, and is used for transmitting the control instruction signal. When the input interface module is connected with the synchronization line, the instruction module receives the control instruction signal from the previous camera through the information transmission module and executes the control instruction signal, and the instruction module sends the control instruction signal to the next camera through the information transmission module. When the input interface module is not connected with the synchronization line, the instruction module generates the control instruction signal and executes the control instruction signal, and the instruction module sends the control instruction signal to the next camera through the information transmission module.

7. The picture capture synchronization circuit of claim 6, wherein, The picture acquisition synchronization circuit further comprises a synchronization instruction signal transmission module, the input interface module is configured to input a synchronization instruction signal, the master control chip module is configured to output the synchronization instruction signal to the synchronization instruction signal transmission module when the detection signal is received, the control instruction signal corresponds to the synchronization instruction signal, and the detection control module is further configured to output a first control signal to the synchronization instruction signal transmission module when the input interface module is connected to the synchronization line and output a second control signal to the synchronization instruction signal transmission module when the input interface module is not connected to the synchronization line; The synchronization instruction signal transmission module is configured to transmit the synchronization instruction signal input by the input interface module to the output interface module when the first control signal is received. The synchronization instruction signal transmission module is configured to transmit the synchronization instruction signal generated by the master control chip module to the output interface module when the second control signal is received.

8. The picture capture synchronization circuit of claim 7, wherein, The synchronization instruction signal transmission module comprises a synchronization instruction signal transmission chip, the synchronization instruction signal transmission chip comprises a first control pin and a second control pin, the first control pin is connected to the drain of a second MOS transistor, the first control pin is configured to receive the second control signal, the second control pin is connected to the drain of a first MOS transistor, and the second control pin is configured to receive the first control signal. The synchronization instruction signal transmission chip further comprises a first input pin, a second input pin and a first output pin, the first input pin is connected to the input interface module, the first input pin is configured to receive the synchronization instruction signal input by the input interface module, the second input pin is connected to the master control chip module, the second input pin is configured to input the synchronization instruction signal generated by the master control chip module, and the first output pin is connected to the output interface module, and the first output pin is configured to output the synchronization instruction signal.

9. A distributed camera system, characterized by It comprises: A plurality of cameras, each camera is one-to-one corresponding to a picture acquisition synchronization circuit according to any one of claims 1-8, wherein one of the cameras is a master camera, and the rest of the cameras are slave cameras, the working mode of the master camera is a master mode, and the working mode of the slave camera is a slave mode; A synchronization line, one end of which is connected to the output interface module of the master camera, the other end of which is connected to the input interface module of the slave camera, or is connected between the input interface module and the output interface module of two adjacent slave cameras, and is configured to transmit a control instruction signal, a synchronization instruction signal, a master clock signal and / or a frame synchronization signal; Each camera generates a picture based on the master clock signal and the frame synchronization signal for subsequent picture synchronization display, and each camera performs synchronization control of all cameras based on the control instruction signal and the synchronization instruction signal.

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