Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate; a conductive contact layer on a part of the surface of the substrate, comprising a plurality of first conductive contact layers and a plurality of second conductive contact layers, the first conductive contact layers are projected on the surface of the substrate and surround the second conductive contact layers; a plurality of lower electrode layers on the top surface of the plurality of second conductive contact layers; a dielectric layer covering the top surface and part of the side surface of the lower electrode layer, the dielectric layer near the periphery of the lower electrode layer protrudes outward along the direction parallel to the surface of the substrate; an upper electrode layer covering the top surface and the side surface of the dielectric layer; a first insulating layer on the surface of the plurality of first conductive contact layers away from the substrate, and part of the dielectric layer is on the part of the surface of the first insulating layer away from the substrate, and the first insulating layer is between the plurality of first conductive contact layers and the dielectric layer. At least the electric leakage can be reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] With the continuous development of mobile devices, mobile devices with battery power supply such as mobile phones, tablets, wearable devices, etc. are more and more widely used in life. As an essential element in mobile devices, people have put forward huge demands for the small size and integration of memory.

[0003] At present, dynamic random access memory (DRAM) is widely used in mobile devices due to its fast transmission speed. Dynamic random access memory includes a capacitor for storing electric charge and a transistor connected to the capacitor. Dynamic random access memory stores data in the form of storing electric charge on the capacitor, and needs to regularly charge and discharge the capacitor within a few milliseconds.

[0004] However, the current semiconductor structure still has some leakage problems. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which at least help to reduce the leakage of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, the present disclosure provides a semiconductor structure, comprising: a substrate; a plurality of conductive contact layers on a part of the surface of the substrate, the plurality of conductive contact layers being separated from each other on the surface of the substrate, the plurality of conductive contact layers comprising a plurality of first conductive contact layers and a plurality of second conductive contact layers, a projection of the plurality of first conductive contact layers on the surface of the substrate surrounding the plurality of second conductive contact layers; a plurality of lower electrode layers on a part of the substrate, the plurality of lower electrode layers being arranged in an array on the surface of the substrate, the plurality of lower electrode layers being on the top surface of the substrate away from the plurality of conductive contact layers; a dielectric layer covering the top surface of the plurality of lower electrode layers away from the substrate and a part of the side surface of the plurality of lower electrode layers, the dielectric layer on the periphery of the plurality of lower electrode layers being convex in a direction parallel to the surface of the substrate and away from the plurality of lower electrode layers; an upper electrode layer covering the top surface of the dielectric layer away from the substrate, the upper electrode layer covering the side surface of the dielectric layer; a first insulating layer on the surface of the plurality of first conductive contact layers away from the substrate, a part of the dielectric layer being on a part of the surface of the first insulating layer away from the substrate, the first insulating layer being between the plurality of first conductive contact layers and the dielectric layer.

[0007] According to some other embodiments of the present disclosure, the thickness of the first insulating layer is 20-60 nm.

[0008] According to some other embodiments of the present disclosure, the upper electrode layer specifically comprises: a first upper electrode layer covering the top surface of the dielectric layer away from the substrate, the first upper electrode layer covering the side surface of the dielectric layer; a second upper electrode layer covering the top surface of the first upper electrode layer away from the substrate, the second upper electrode layer covering the side surface of the first upper electrode layer; wherein the thickness of the second upper electrode layer is greater than the thickness of the first upper electrode layer.

[0009] According to some other embodiments of the present disclosure, the material of the first upper electrode layer is different from the material of the second upper electrode layer.

[0010] According to some other embodiments of the present disclosure, further comprising: a second insulating layer covering the side surface and the top surface of the upper electrode layer, the second insulating layer being in contact with the first insulating layer, the second insulating layer being convex in a direction parallel to the surface of the substrate and away from the plurality of lower electrode layers.

[0011] According to some other embodiments of the present disclosure, the material of the second insulating layer is the same as the material of the first insulating layer.

[0012] According to some embodiments of the present disclosure, the semiconductor structure further comprises: a first support layer, the first support layer is located above the substrate, and the first support layer fills the gap between the conductive contact layers, and the first insulating layer is located on part of the surface of the first support layer; a second support layer, the second support layer is located between adjacent lower electrode layers, and the vertical distance between the second support layer and the substrate surface is less than the vertical distance between the top surface of the lower electrode layer and the substrate surface; a third support layer, the third support layer is located between adjacent lower electrode layers, and the vertical distance between the third support layer and the substrate surface is greater than the vertical distance between the second support layer and the substrate surface, and the first support layer, the second support layer and the third support layer constitute a support layer.

[0013] According to some embodiments of the present disclosure, the semiconductor structure further comprises: a dielectric layer, the dielectric layer is located on the surface of the substrate, and the lower electrode layer is located on the surface of the dielectric layer away from the substrate.

[0014] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a manufacturing method of a semiconductor structure, comprising: providing a substrate; forming a conductive contact layer, the conductive contact layer is located on part of the surface of the substrate, and a plurality of conductive contact layers are separated from each other on the surface of the substrate, the conductive contact layer comprises a plurality of first conductive contact layers and a plurality of second conductive contact layers, and the orthogonal projection of the plurality of first conductive contact layers on the surface of the substrate surrounds the plurality of second conductive contact layers; forming a first insulating layer, the first insulating layer is located on the surface of the plurality of first conductive contact layers away from the substrate; forming a plurality of lower electrode layers, the plurality of lower electrode layers are located on part of the area of the substrate, and the plurality of lower electrode layers are arranged in an array on the surface of the substrate, and the plurality of lower electrode layers are located on the top surface of the plurality of second conductive contact layers away from the substrate; forming a dielectric layer, the dielectric layer covers the top surface of the plurality of lower electrode layers away from the substrate and part of the side surface of the plurality of lower electrode layers, the dielectric layer is located on part of the surface of the first insulating layer away from the substrate, and the dielectric layer at the periphery of the plurality of lower electrode layers protrudes in the direction away from the plurality of lower electrode layers in the direction parallel to the surface of the substrate in the area close to the substrate; forming an upper electrode layer, the upper electrode layer covers the top surface of the dielectric layer away from the substrate, and the upper electrode layer covers the side surface of the dielectric layer.

[0015] According to another embodiment of the present disclosure, the forming of the first insulating layer specifically comprises: forming a first insulating film on the surface of the conductive contact layer away from the substrate, and the orthographic projection of the first insulating film on the substrate covers the whole surface of the substrate; forming a photoresist layer on the surface of the first insulating film away from the substrate, and the photoresist layer has an opening in the center region of the photoresist layer, and the plurality of second conductive contact layers can be exposed by etching through the opening; etching the first insulating film along the opening with the photoresist layer as a mask to obtain the first insulating layer.

[0016] According to another embodiment of the present disclosure, the forming of the upper electrode layer comprises: forming a first upper electrode layer covering the top surface of the dielectric layer away from the substrate, and the first upper electrode layer covering the side surface of the dielectric layer; forming a second upper electrode layer covering the top surface of the first upper electrode layer away from the substrate, and the second upper electrode layer covering the side surface of the first upper electrode layer; wherein the thickness of the second upper electrode layer is greater than the thickness of the first upper electrode layer.

[0017] According to another embodiment of the present disclosure, after the forming of the upper electrode layer, the method further comprises: forming a second insulating layer covering the side surface of the upper electrode layer and the second insulating layer being in contact with the first insulating layer.

[0018] The technical scheme provided by the embodiments of the present disclosure has at least the following advantages:

[0019] In the technical solution of the semiconductor structure provided in the embodiments of the present disclosure, the semiconductor structure comprises a substrate, a plurality of conductive contact layers located on a part of the surface of the substrate, and the plurality of conductive contact layers are separated from each other on the surface of the substrate. The conductive contact layers comprise a plurality of first conductive contact layers and a plurality of second conductive contact layers. The orthogonal projection of the plurality of first conductive contact layers on the surface of the substrate surrounds the plurality of second conductive contact layers. A plurality of lower electrode layers are located on a part of the substrate, and the plurality of lower electrode layers are located on the top surface of the plurality of second conductive contact layers away from the substrate. A dielectric layer covers the top surface and part of the side surface of the plurality of lower electrode layers, and the part of the dielectric layer located at the periphery of the plurality of lower electrode layers and close to the substrate protrudes in a direction parallel to the surface of the substrate and away from the plurality of lower electrode layers. An upper electrode layer covers the top surface and the side surface of the dielectric layer. A first insulating layer is located on a part of the surface of the plurality of first conductive contact layers away from the substrate, and the first insulating layer is located between the plurality of first conductive contact layers and the dielectric layer. In the related art, the semiconductor structure does not have a first insulating layer. The part of the dielectric layer close to the substrate and protruding in a direction away from the lower electrode layer is directly in contact with the surface of the first conductive contact layer, and the upper electrode layer is located on the top surface of this part of the dielectric layer. There is only one layer of dielectric layer between the upper electrode layer and the first conductive contact layer. However, the thickness of the dielectric layer is relatively thin. When the semiconductor structure is manufactured by etching process, the edge of the dielectric layer is easily etched to form a leakage channel, so that the upper electrode layer and the first conductive contact layer are in electrical contact to cause leakage, which affects the performance of the semiconductor structure. In the semiconductor structure provided in the embodiments of the present disclosure, the first insulating layer is arranged on the surface of the first conductive contact layer away from the substrate, and the dielectric layer is located on a part of the surface of the first insulating layer away from the substrate, and the first insulating layer is located between the first conductive contact layer and the dielectric layer. The first insulating layer can isolate the upper electrode layer from the first conductive contact layer. Even when the edge of the dielectric layer is etched during the manufacture of the semiconductor structure by etching, the upper electrode layer and the first conductive contact layer will not be in electrical contact, thereby avoiding leakage of the semiconductor structure and affecting the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0020] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not limiting of the embodiments, unless otherwise specifically indicated, the drawings shown in the figures do not necessarily show all customary components of the embodiments. In order to explain the technical solutions in the embodiments of the present disclosure or the prior art more clearly, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only represent some of the embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0021] Figure 1 It is a partial cross-sectional perspective view of a semiconductor structure;

[0022] Figure 2A sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown in the figure;

[0023] Figure 3 A partial sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown in the figure;

[0024] Figure 4 A sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown in the figure;

[0025] Figures 5 to 16 A sectional structure diagram corresponding to each step of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure is shown in the figure. DETAILED DESCRIPTION

[0026] As known from the background, the current semiconductor structure has certain leakage problem.

[0027] REFERENCE Figure 1 , Figure 1 A partial sectional structure diagram of a semiconductor structure is shown in the figure. The semiconductor structure includes: a substrate 10; a conductive contact layer 20, the conductive contact layer 20 is located on part of the surface of the substrate 10, and multiple conductive contact layers 20 are separated from each other on the surface of the substrate 10; multiple lower electrode layers 30, the lower electrode layer 30 is located on part of the area of the substrate 10, and the lower electrode layer 30 is separated from each other on the surface of the substrate 10; a dielectric layer 40, the dielectric layer 40 covers the top surface of the multiple lower electrode layers 30 away from the substrate 10 and part of the side surface of the lower electrode layer 30, and the area of the dielectric layer 40 located at the periphery of the multiple lower electrode layers 30 close to the substrate 10 protrudes in the direction away from the lower electrode layer 30 in parallel to the substrate 10; an upper electrode layer 50, the upper electrode layer 50 covers the top surface of the dielectric layer 40 away from the substrate 10, and the upper electrode layer 50 covers the side surface of the dielectric layer 40.

[0028] In the manufacturing of the semiconductor structure, after the substrate 10, the conductive contact layer 20 and the lower electrode layer 30 are formed, the dielectric layer 40 covering the top surface of the multiple lower electrode layers 30, part of the side surface of the lower electrode layer 30 and the top surface of the conductive contact layer 20 is formed, and then the upper electrode layer 50 covering the top surface and the side surface of the dielectric layer 40 is formed. The dielectric layer 40 and the upper electrode layer 50 need to be etched so that the dielectric layer 40 and the upper electrode layer 50 only cover the top surface of part of the conductive contact layer 20 close to the lower electrode layer 30. When etching, it is easy to form a side notch in the edge area of the dielectric layer 40, and the edge of the dielectric layer 40 on the surface of the conductive contact layer 20 is partially removed, so that the upper electrode layer 50 above the dielectric layer 40 and the conductive contact layer 20 below the dielectric layer 40 are in electrical contact, causing leakage and affecting the performance of the semiconductor structure.

[0029] The analysis finds that in the semiconductor structure, the dielectric layer is easy to be etched to remove a part to form a side notch in the process of manufacturing the semiconductor structure, so that the upper electrode layer 50 and the conductive contact layer 20 are in electrical contact and cause leakage. If a semiconductor structure can be provided, the upper electrode layer 50 and the conductive contact layer 20 will not be in electrical contact due to the side notch of the dielectric layer 40, the above problem can be improved.

[0030] The technical scheme of the semiconductor structure provided by the embodiments of the present disclosure includes a conductive contact layer on part of the surface of the substrate, and a plurality of lower electrode layers, wherein the conductive contact layer includes a plurality of first conductive contact layers and a plurality of second conductive contact layers, the plurality of first conductive contact layers surrounds the plurality of second conductive contact layers in the orthographic projection of the substrate surface, the plurality of lower electrode layers is located on the top surface of the plurality of second conductive contact layers away from the substrate, the dielectric layer covers the top surface and part of the side surface of the plurality of lower electrode layers, the dielectric layer in the area close to the substrate protrudes in the direction parallel to the substrate surface and away from the plurality of lower electrode layers, and the upper electrode layer covers the top surface of the dielectric layer away from the substrate and the side surface of the dielectric layer. Moreover, the semiconductor structure also has a first insulating layer, which is located on the surface of the first conductive contact layer away from the substrate, and the dielectric layer is located on part of the surface of the first insulating layer away from the substrate, and the first insulating layer is located between the first conductive contact layer and the dielectric layer. The upper electrode layer and the first conductive contact layer not only have the dielectric layer, but also have the first insulating layer. Even if the edge of the dielectric layer is etched to remove a part to form a side notch in the process of manufacturing the semiconductor structure, the upper electrode layer and the first conductive contact layer still have the first insulating layer, so that the upper electrode layer and the first conductive contact layer will not be in electrical contact, reducing the leakage in the semiconductor structure and improving the performance of the semiconductor structure.

[0031] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to make the readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed by the present disclosure can be implemented.

[0032] Figures 2 to 3 The cross-sectional structure schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure is shown in the figure, wherein, Figure 3 The partial enlarged view of Figure 2 is shown in the figure, and the enlarged area is shown by the dashed box in Figure 2 . Figure 4 The cross-sectional structure schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure is shown in the figure, wherein,

[0033] Reference is made to Figures 2 to 4The semiconductor structure comprises: a substrate 100; a plurality of conductive contact layers 110, the plurality of conductive contact layers 110 are located on a part of the surface of the substrate 100, and the plurality of conductive contact layers 110 are separated from each other on the surface of the substrate 100, the plurality of conductive contact layers 110 comprise a plurality of first conductive contact layers 111 and a plurality of second conductive contact layers 112, the first conductive contact layers 111 are arranged around the second conductive contact layers 112 in the projection of the surface of the substrate 100; a plurality of lower electrode layers 120, the plurality of lower electrode layers 120 are located on a part of the surface of the substrate 100, and the plurality of lower electrode layers 120 are arranged in an array on the surface of the substrate 100, the plurality of lower electrode layers 120 are located on the top surface of the second conductive contact layers 112 away from the substrate 100; a dielectric layer 130, the dielectric layer 130 covers the top surface of the plurality of lower electrode layers 120 away from the substrate 100 and a part of the side surface of the plurality of lower electrode layers 120, and the dielectric layer 130 located at the periphery of the plurality of lower electrode layers 120 protrudes in a direction away from the plurality of lower electrode layers 120 along a direction parallel to the surface of the substrate 100, and the protruding area is shown by the dashed line frame in FIG. 1; an upper electrode layer 140, the upper electrode layer 140 covers the top surface of the dielectric layer 130 away from the substrate 100, and the upper electrode layer 140 covers the side surface of the dielectric layer 130; a first insulating layer 150, the first insulating layer 150 is located on the surface of the first conductive contact layer 111 away from the substrate 100, and a part of the dielectric layer 130 is located on a part of the surface of the first insulating layer 150 away from the substrate 100, and the first insulating layer 150 is located between the first conductive contact layer 111 and the dielectric layer 130. Figure 3

[0034] In the above semiconductor structure, the first insulating layer 150 is located between the dielectric layer 130 and the first conductive contact layer 111, and the upper electrode layer 140 is located on the top surface of the dielectric layer 130 away from the substrate 100. Even if the dielectric layer 130 is partially removed due to etching process during the manufacturing process of the semiconductor structure, the first insulating layer 150 is still located between the upper electrode layer 140 and the first conductive contact layer 111, and the upper electrode layer 140 and the first conductive contact layer 111 will not be in electrical contact. The problem of electric leakage in the semiconductor structure can be reduced, and the performance of the semiconductor structure can be improved.

[0035] The embodiments of the present disclosure will be described in more detail below with reference to the drawings.

[0036] ​The substrate 100 can include a plurality of discrete active regions and isolation structures (not shown) between adjacent active regions. The plurality of discrete active regions can be arranged in an array on the substrate, and the isolation structures can surround the active regions, with an isolation structure between each two adjacent active regions. The material of the active regions can include silicon, and the active regions can be used to form transistors in a semiconductor structure in subsequent steps. The isolation structures can include silicon oxide, and the isolation structures can be used to isolate different active regions. In addition, the substrate 100 can also have word line structures and bit line structures, the word line structures can be used as switches of the transistors in the active regions, and are connected to the gates of the transistors. The bit line structures are connected to the drains of the transistors, and can be used to read or write the storage states of the basic cells.

[0037] In some embodiments, the semiconductor structure can further include a dielectric layer 160 on the surface of the substrate 100, and the lower electrode layer 120 is on the surface of the dielectric layer 160 away from the substrate 100. The material of the dielectric layer 160 can include SiOC.

[0038] The conductive contact layer 110 covers part of the surface of the substrate 100, and a plurality of conductive contact layers 110 are discrete from each other on the surface of the substrate 100. If the semiconductor structure has the dielectric layer 160, the conductive contact layer 110 covers the surface of the dielectric layer 160 away from the substrate 100. The material of the conductive contact layer 110 is a conductive material, and the material of the conductive contact layer 110 can include titanium nitride, tungsten, titanium silicide, titanium oxide, or tungsten oxide.

[0039] In some embodiments, the semiconductor structure can have a conductive plug 200, which can be on the surface of the substrate 100 and electrically connect the substrate 100 to other devices. The material of the conductive plug 200 can be the same as the material of the conductive contact layer 110, and the material of the conductive plug 200 can include titanium nitride.

[0040] Reference is made to Figure 3 and Figure 4 , the semiconductor structure has a plurality of discrete lower electrode layers 120, and the projections of the plurality of lower electrode layers 120 on the surface of the substrate 100 are located in the central region. The projection of the first conductive contact layer 111 on the surface of the substrate 100 surrounds the periphery of the plurality of lower electrode layers 120. Reference is made to Figure 4 , the central region is shown by the dashed line frame in Figure 4 , and the region outside the dashed line frame is the peripheral region. The lower electrode layer 120 is one electrode of a capacitor structure in the semiconductor structure. The material of the lower electrode layer 120 is a conductive material. The material of the lower electrode layer 120 can include titanium nitride. The plurality of lower electrode layers 120 and the upper electrode layer can form a plurality of capacitors, and the plurality of capacitors can be simultaneously charged and discharged when the semiconductor structure is used, thereby increasing the capacitance.

[0041] In some embodiments, the plurality of lower electrode layers 120 can be long columnar structures. The height of the plurality of lower electrode layers 120 relative to the surface of the substrate 100 is greater than the thickness of the substrate 100.

[0042] The projected area of the plurality of lower electrode layers 120 on the surface of the substrate 100 can be a circular area, a rectangular area, or an irregularly shaped area. Correspondingly, the projected area of the first conductive contact layer 111 surrounding the periphery of the plurality of lower electrode layers 120 on the surface of the substrate 100 can be an annular area, a ring-shaped area, or an annular area of other shapes, which are not listed one by one here.

[0043] The dielectric layer 130 is a structure for isolating the lower electrode layers 120 and the upper electrode layers 140. Between adjacent lower electrode layers 120, the dielectric layer 130 can cover the side surface of the lower electrode layers 120 and can form a closed dielectric layer 130 with a head-to-tail connection around the area between adjacent lower electrode layers 120, and the closed dielectric layer 130 can have an upper electrode layer inside. On the side surface of the outermost lower electrode layer 120, in the area close to the substrate 100, the dielectric layer 130 on the outer side surface of the plurality of lower electrode layers 120 protrudes in a direction parallel to the surface of the substrate 100 and away from the plurality of lower electrode layers 120, that is, the bottom of the dielectric layer 130 covering the outermost side surface of the lower electrode layer 120 extends towards the periphery of the substrate 100. This part of the protruding dielectric layer 130 covers the surface of the first insulating layer 150, and the protruding part is shown in the dashed box of FIG. 1. Figure 3

[0044] In some embodiments, the thickness of the dielectric layer 130 can be 3-9 nm. For example, the thickness of the dielectric layer 130 can be 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, etc. If the thickness of the dielectric layer 130 is too small, the dielectric layer 130 can have a smaller isolation effect on the upper electrode layer and the lower electrode layer, which can affect the performance of the semiconductor structure. If the thickness of the dielectric layer 130 is too large, not only will it cause waste of materials, but also the size of the semiconductor structure will increase. Therefore, the thickness of the dielectric layer 130 needs to be selected in an appropriate range. When the thickness of the dielectric layer 130 is 3-9 nm, the dielectric layer 130 can not only have a better isolation effect between the upper electrode layer and the lower electrode layer, but also will not cause waste.

[0045] ​In some embodiments, the material of the dielectric layer 130 can be a high-K material. The use of high-K material for the dielectric layer 130 can improve the performance of the semiconductor structure, reduce the power consumption of the semiconductor structure, and increase the charge storage capability of the capacitor structure. In particular, in some embodiments, the material of the dielectric layer 130 can include AlO. In other embodiments, the material of the dielectric layer 130 can also include one or more of hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, and strontium oxide.

[0046] The upper electrode layer 140 is another electrode of the capacitor structure in the semiconductor structure corresponding to the lower electrode layer 120. The upper electrode layer 140 between the adjacent plurality of lower electrode layers 120 can be located in the enclosed dielectric layer 130 between the adjacent plurality of lower electrode layers 120. That is, between the adjacent plurality of lower electrode layers 120, the dielectric layer 130 covers the side surface of the lower electrode layer 120, the upper electrode layer 140 covers the side surface of the dielectric layer 130, and the upper electrode layer 140 fills the gap between the plurality of lower electrode layers 120. The material of the upper electrode layer 140 includes a conductive material.

[0047] In some embodiments, the upper electrode layer 140 can specifically include two layers of a first upper electrode layer 141 and a second upper electrode layer 142. The first upper electrode layer 141 covers the top surface of the dielectric layer 130 away from the substrate 100, and the first upper electrode layer 141 covers the side surface of the dielectric layer 130; the second upper electrode layer 142 covers the top surface of the first upper electrode layer 141 away from the substrate 100, and the second upper electrode layer 142 covers the side surface of the first upper electrode layer 141; wherein the thickness of the second upper electrode layer 142 is greater than the thickness of the first upper electrode layer 141. That is, the first upper electrode layer 141 is located on the surface of the dielectric layer 130, and the second upper electrode layer 142 is located on the surface of the first upper electrode layer 141.

[0048] Specifically, between the adjacent plurality of lower electrode layers 120, the first upper electrode layer 141 can cover the side surface of the dielectric layer 130 and can form a closed first upper electrode layer 141 in a ring shape along the area between the adjacent dielectric layers 130, and the second upper electrode layer 142 can be inside the closed first upper electrode layer 141. The second upper electrode layer 142 is on the surface of the first upper electrode layer 141, and the second upper electrode layer 142 fills the gap between the adjacent plurality of lower electrode layers 120. Outside the outermost lower electrode layer 120, the first upper electrode layer 141 covers the entire side surface of the dielectric layer 130 and the bottom surface above the plurality of lower electrode layers 120, and in the area close to the substrate 100, the first upper electrode layer 141 also covers the top surface of the dielectric layer 130 protruding in the direction away from the plurality of lower electrode layers 120. Similarly, outside the outermost lower electrode layer 120, the second upper electrode layer 142 covers the entire side surface of the first upper electrode layer 141 and the bottom surface above the plurality of lower electrode layers 120, and in the area close to the substrate 100, the second upper electrode layer 142 also covers the top surface of the first upper electrode layer 141 protruding in the direction away from the plurality of lower electrode layers 120.

[0049] In some embodiments, the material of the first upper electrode layer 141 and the material of the second upper electrode layer 142 can be different. The first upper electrode layer 141 and the second upper electrode layer 142 can be selected from two different conductive materials, for example, the material of the first upper electrode layer 141 and the material of the second upper electrode layer 142 can include titanium nitride, tungsten, titanium silicide, titanium oxide, or tungsten oxide, etc. In some embodiments, the material of the first upper electrode layer 141 can include TiN; the material of the second upper electrode layer 142 can include SiGe. Dividing the upper electrode layer 140 into two layers with different thicknesses, different materials of the first upper electrode layer 141 and the second upper electrode layer 142 can better play the role of the upper electrode layer 140 in the capacitor structure, improve the performance of the semiconductor structure, and make the semiconductor structure more efficient.

[0050] The first insulating layer 150 is a structure covering the top surface of the first conductive contact layer 111 and located between the first conductive contact layer 111 and the dielectric layer 130. That is, the protruding part of the dielectric layer 130 and the upper electrode layer 140 close to the substrate 100 region is located on part of the top surface of the first insulating layer 150. In the direction perpendicular to the surface of the substrate 100, there is also a first insulating layer 150 between the first conductive contact layer 111 and the dielectric layer 130 and the upper electrode layer 140. The first insulating layer 150 can isolate the upper electrode layer 140 and the first conductive contact layer 111, increase the distance between the upper electrode layer 140 and the first conductive contact layer 111, so that the upper electrode layer 140 and the first conductive contact layer 111 are not easy to be electrically connected, and the semiconductor structure is not easy to be electrically leaked.

[0051] Specifically, in the process of manufacturing the dielectric layer 130 and the upper electrode layer 140, the dielectric layer 130 covering the entire surface of the upper electrode layer 140 and the entire surface of the first insulating layer 150 is first formed, and then the upper electrode layer 140 is formed on the dielectric layer 130, the upper electrode layer 140 covering the entire surface of the dielectric layer 130, and then the dielectric layer 130 in the peripheral area is removed by etching process to expose the first insulating layer 150, and the first insulating layer 150 covers the first conductive contact layer 111. In the etching process, it is easy to cause side notching to form a gap in the dielectric layer 130 with a high dielectric constant, but since the upper electrode layer 140 and the first conductive contact layer 111 are not only separated by the dielectric layer 130 but also separated by the first insulating layer 150, the upper electrode layer 140 and the first conductive contact layer 111 will not be electrically connected, and thus will not cause electrical leakage.

[0052] In some embodiments, the thickness of the first insulating layer 150 can be 20-60 nm. For example, the thickness of the first insulating layer 150 can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm, etc. If the thickness of the first insulating layer 150 is too small, it can not be able to effectively isolate the upper electrode layer 140 and the first conductive contact layer 111. If the thickness of the first insulating layer 150 is too large, the first insulating layer 150 will occupy a larger area in contact with the side surface of the lower electrode layer 120, and the dielectric layer 130 and the upper electrode layer 140 in contact with the remaining side surface of the lower electrode layer 120 will occupy a smaller area, which will affect the performance of the semiconductor structure. Therefore, the thickness of the first insulating layer 150 needs to be selected within an appropriate range. When the thickness of the first insulating layer 150 is 20-60 nm, the first insulating layer 150 can effectively isolate the upper electrode layer 140 and the first conductive contact layer 110, and also ensure that the semiconductor structure has better performance.

[0053] The material of the first insulating layer 150 is an insulating material. In some embodiments, the material of the first insulating layer 150 can include SiN. In other embodiments, the material of the first insulating layer 150 can also be other materials.

[0054] In some embodiments, a second insulating layer 170 can also be included, the second insulating layer 170 covering the side surface and the top surface of the upper electrode layer 140 and the second insulating layer 170 being in contact with the first insulating layer 150, and the area of the second insulating layer 170 close to the substrate 100 protruding in a direction parallel to the surface of the substrate 100 away from the plurality of lower electrode layers 120. The second insulating layer 170 can isolate the upper electrode layer 140 in the entire capacitor structure from other components in the outside world, and play an insulating isolation role.

[0055] In some embodiments, the material of the second insulating layer 170 can be the same as that of the first insulating layer 150. The material of the second insulating layer 170 and that of the first insulating layer 150 are both insulating materials, and the material of the second insulating layer 170 and that of the first insulating layer 150 can both be SiN. In other embodiments, the second insulating layer 170 and the first insulating layer 150 can also be made of different insulating materials.

[0056] In some embodiments, a support layer 180 can also be included, which can include a first support layer 181, a second support layer 182, and a third support layer 183. The first support layer 181 is located above the substrate 100, and the first support layer 181 fills the gaps between the conductive contact layers 110. The first insulating layer 150 is located on the surface of part of the first support layer 181. The first support layer 181 can make the structure between the conductive contact layers 110 and the lower electrode layers 120 in the semiconductor structure complete, and the semiconductor structure has higher stability, and plays a certain supporting role.

[0057] The second support layer 182 is located between adjacent lower electrode layers 120, and the vertical distance between the second support layer 182 and the surface of the substrate 100 is less than the vertical distance between the top surface of the lower electrode layer 120 and the surface of the substrate 100. Because the height of the lower electrode layer 120 relative to the surface of the substrate 100 is too high, the middle region of the lower electrode layer 120 is prone to have the problems of lower mechanical strength and poorer stability. The arrangement of the second support layer 182 can solve this problem to some extent, improve the mechanical strength of the middle region of the lower electrode layer 120, and improve the stability of the semiconductor structure, and play a certain supporting role.

[0058] The third support layer 183 is located between adjacent lower electrode layers 120, and the vertical distance between the third support layer 183 and the surface of the substrate 100 is greater than the vertical distance between the second support layer 182 and the surface of the substrate 100. The first support layer 181, the second support layer 182, and the third support layer 183 constitute the support layer 180. The third support layer 183 can further improve the mechanical strength of the semiconductor structure, improve the stability of the semiconductor structure, and play a supporting role for the semiconductor structure. The combination of the first support layer 181, the second support layer 182, and the third support layer 183 can make the stability of the semiconductor structure achieve a better effect.

[0059] The semiconductor structure provided by the embodiment of the present disclosure includes a substrate, a plurality of conductive contact layers located on a partial surface of the substrate, the conductive contact layers including a plurality of first conductive contact layers and a plurality of second conductive contact layers, a projection of the plurality of first conductive contact layers on the surface of the substrate surrounds the plurality of second conductive contact layers, a plurality of lower electrode layers are located on a surface of the second conductive contact layers away from the substrate, a dielectric layer covers a top surface of the plurality of lower electrode layers away from the substrate and a partial side surface of the plurality of lower electrode layers, and a region of the dielectric layer close to the substrate protrudes in a direction parallel to the surface of the substrate and away from the plurality of lower electrode layers, an upper electrode layer covers a top surface of the dielectric layer away from the substrate, and the upper electrode layer covers a side surface of the dielectric layer, a first insulating layer is located on a surface of the first conductive contact layer away from the substrate, and a dielectric layer is located on a partial surface of the first insulating layer away from the substrate, and the first insulating layer is located between the first conductive contact layer and the dielectric layer. The semiconductor structure can reduce the leakage of electricity and improve the performance of the semiconductor structure.

[0060] Correspondingly, another embodiment of the present disclosure also provides a manufacturing method of a semiconductor structure, which can be used to form the semiconductor structure described above. The semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the drawings. The same or corresponding parts of the previous embodiment can be referred to the corresponding description of the previous embodiment, and will not be described in detail below.

[0061] Figures 5 to 16 The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure includes the following steps. Figures 5 to 7 Figure 9 Figure 11 Figures 13 to 16 The manufacturing method of the semiconductor structure includes the following steps. Figure 3 The partial surface is shown by a dashed line frame in Figure 2 . Figure 8 Figure 10 Figure 12 The manufacturing method of the semiconductor structure includes the following steps.

[0062] Referring to Figure 5 , a substrate 100 is provided.

[0063] ​​​​​The substrate 100 can include a plurality of discrete active regions and isolation structures (not shown) between adjacent active regions. The plurality of discrete active regions can be arranged in an array on the substrate 100, and the isolation structures can surround the active regions, with an isolation structure between each two adjacent active regions. The active regions can include silicon and can be used to form transistors in a semiconductor structure in subsequent steps. The isolation structures can include silicon oxide and can be used to isolate the different active regions. In addition, the substrate can also have word line structures and bit line structures, which can be used as switches for the gates of the transistors in the active regions. The bit line structures can be connected to the drains of the transistors and can be used to read or write the stored states of the basic cells.

[0064] Referring to Figure 6 , a conductive contact layer 110 is formed on a portion of the surface of the substrate 100, and a plurality of conductive contact layers 110 are formed on the surface of the substrate 100 and are discrete from each other. The conductive contact layer 110 includes a plurality of first conductive contact layers 111 and a plurality of second conductive contact layers 112.

[0065] The step of forming the conductive contact layer 110 can include: first forming a conductive contact film covering the entire surface of the substrate 100 on the surface of the substrate 100, and then removing a portion of the conductive contact film to obtain the conductive contact layer 110. In the conductive contact layer 110 formed, the first conductive contact layer 111 has a surface projection that surrounds the second conductive contact layer 112.

[0066] It should be noted that before the conductive contact layer 110 is formed, a dielectric layer 160 can also be formed on the surface of the substrate 100.

[0067] Referring to Figures 7 to 12 , a first insulating layer 150 is formed on the surface of the first conductive contact layer 111 away from the substrate 100.

[0068] In some embodiments, forming the first insulating layer 150 can specifically include: referring to Figures 7 to 8 , Figure 8 To Figure 7 A top view schematic diagram of the semiconductor structure in the step, a first insulating film 151 is formed on the surface of the conductive contact layer 110 away from the substrate 100, and the first insulating film 151 has a surface projection on the substrate 100 that covers the entire surface of the substrate 100. It can be seen that the first insulating film 151 covers the entire surface of the substrate 100.

[0069] Continuing to refer to Figures 7 to 8, forming a photoresist layer 190 on the surface of the first insulating film 151 away from the substrate 100, and the photoresist layer has an opening in the center region of the photoresist layer, and the opening is used for further etching to expose the top surface of the plurality of second conductive contact layers 112 away from the substrate 100. Figure 8 The center region is indicated by a dashed line frame, and the other regions outside the dashed line frame are peripheral regions, and the second conductive contact layers 112 are located in the center region.

[0070] Referring to Figures 9 to 10 , Figure 10 To Figure 9 In the step, a top view schematic diagram of the semiconductor structure is shown. The first insulating film 151 is etched along the opening with the photoresist layer 190 as a mask to obtain the first insulating layer 150. The first insulating layer 150 formed after etching is only located in the peripheral region, which can not only play a role of isolating the first conductive contact layer 111 from the upper electrode layer 140 and reducing the leakage current, but also make the second conductive contact layer 112 and the lower electrode layer 120 formed in the subsequent step be able to be electrically connected smoothly.

[0071] Referring to Figures 11 to 12 , Figure 12 To Figure 11 In the step, a top view schematic diagram of the semiconductor structure is shown. The photoresist layer is removed.

[0072] Referring to Figure 13 , a plurality of lower electrode layers 120 are formed on a part of the surface of the substrate 100, and the plurality of lower electrode layers 120 are arranged in an array on the surface of the substrate 100, and the plurality of lower electrode layers are located on the top surface of the plurality of second conductive contact layers 112 away from the substrate 100.

[0073] The height of the plurality of lower electrode layers 120 is greater than the height of the plurality of second conductive contact layers 112, and the plurality of second conductive contact layers 112 are electrically connected with the plurality of lower electrode layers 120. Each lower electrode layer 120 is in contact with each second conductive contact layer 112.

[0074] Referring to Figure 14 , a dielectric layer 130 is formed, covering the top surface of the plurality of lower electrode layers 120 away from the substrate 100 and part of the side surface of the plurality of lower electrode layers 120, and the dielectric layer 130 is located on part of the surface of the first insulating layer 150 away from the substrate 100, and the dielectric layer 130 located in the periphery of the plurality of lower electrode layers 120 is protruded in the direction away from the plurality of lower electrode layers 120 along the direction parallel to the surface of the substrate 100.

[0075] Referring to Figure 15forming the upper electrode layer 140 covering the top surface of the dielectric layer 130 away from the substrate 100 and covering the side surface of the dielectric layer 130.

[0076] In some embodiments, forming the upper electrode layer 140 comprises: forming a first upper electrode layer 141 covering the top surface of the dielectric layer 130 away from the substrate 100 and covering the side surface of the dielectric layer 130; and forming a second upper electrode layer 142 covering the top surface of the first upper electrode layer 141 away from the substrate 100 and covering the side surface of the first upper electrode layer 141; wherein the thickness of the second upper electrode layer 142 is greater than the thickness of the first upper electrode layer 141.

[0077] Reference is made to Figure 16 In some embodiments, after forming the upper electrode layer 140, the method further comprises: forming a second insulating layer 170 covering the side surface of the upper electrode layer 140 and contacting the first insulating layer 150.

[0078] It should be noted that after forming the second insulating layer 170, a conductive structure connecting the semiconductor structure and an external device can be formed, and the conductive structure can be electrically connected to the first conductive contact layer 111.

[0079] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure comprises: providing a substrate; forming a conductive contact layer on part of the surface of the substrate, the plurality of conductive contact layers being separated from each other on the surface of the substrate, the conductive contact layer comprising a plurality of first conductive contact layers and a plurality of second conductive contact layers, the orthographic projection of the plurality of first conductive contact layers on the surface of the substrate surrounding the plurality of second conductive contact layers; forming a first insulating layer on the surface of the first conductive contact layer away from the substrate; forming a plurality of lower electrode layers on part of the region of the substrate, the plurality of lower electrode layers being located on the top surface of the second conductive contact layer away from the substrate, the plurality of lower electrode layers being separated from each other on the surface of the substrate; forming a dielectric layer covering the top surface of the plurality of lower electrode layers away from the substrate and part of the side surface of the plurality of lower electrode layers, the dielectric layer being located on part of the surface of the first insulating layer away from the substrate, and the region of the dielectric layer close to the substrate being convex in the direction away from the plurality of lower electrode layers in a direction parallel to the surface of the substrate; and forming an upper electrode layer covering the top surface of the dielectric layer away from the substrate and covering the side surface of the dielectric layer. This can reduce the leakage in the semiconductor structure and improve the performance of the semiconductor structure.

[0080] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be limited by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A conductive contact layer is located on a portion of the surface of the substrate, and a plurality of the conductive contact layers are separated from each other on the surface of the substrate. The conductive contact layer includes a plurality of first conductive contact layers and a plurality of second conductive contact layers, and the orthographic projection of the plurality of first conductive contact layers on the surface of the substrate surrounds the plurality of second conductive contact layers. Multiple lower electrode layers are located on a portion of the substrate and are arranged in an array on the surface of the substrate, with the multiple lower electrode layers located on the top surface of the multiple second conductive contact layers away from the substrate; A dielectric layer covers the top surface of the plurality of lower electrode layers away from the substrate and a portion of the side surfaces of the plurality of lower electrode layers, and the region of the dielectric layer near the substrate located on the periphery of the plurality of lower electrode layers protrudes in a direction parallel to the surface of the substrate toward the direction away from the plurality of lower electrode layers; An upper electrode layer, wherein the upper electrode layer covers the top surface of the dielectric layer away from the substrate, and the upper electrode layer covers the side surface of the dielectric layer; A first insulating layer is located on the surface of the plurality of first conductive contact layers away from the substrate, and a portion of the dielectric layer is located on the portion of the first insulating layer away from the substrate. The first insulating layer is located between the plurality of first conductive contact layers and the dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, The thickness of the first insulating layer is 20-60 nm.

3. The semiconductor structure as described in claim 1, characterized in that, The upper electrode layer specifically includes: A first upper electrode layer covers the top surface of the dielectric layer away from the substrate, and the first upper electrode layer also covers the side surface of the dielectric layer. The second upper electrode layer covers the top surface of the first upper electrode layer away from the substrate, and the second upper electrode layer covers the side surface of the first upper electrode layer; The thickness of the second upper electrode layer is greater than the thickness of the first upper electrode layer.

4. The semiconductor structure as described in claim 3, characterized in that, The material of the first upper electrode layer is different from the material of the second upper electrode layer.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second insulating layer covers the side and top surfaces of the upper electrode layer and is in contact with the first insulating layer. The region of the second insulating layer near the substrate protrudes in a direction parallel to the surface of the substrate toward the direction away from the plurality of lower electrode layers.

6. The semiconductor structure as described in claim 5, characterized in that, The second insulating layer is made of the same material as the first insulating layer.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first support layer is located above the substrate and fills the gaps between the conductive contact layers, and a first insulating layer is located on a portion of the surface of the first support layer. A second support layer is located between adjacent lower electrode layers, and the vertical distance between the second support layer and the substrate surface is less than the vertical distance between the top surface of the lower electrode layer and the substrate surface. A third support layer is located between adjacent lower electrode layers, and the vertical distance between the third support layer and the substrate surface is greater than the vertical distance between the second support layer and the substrate surface. The first support layer, the second support layer, and the third support layer constitute a support layer.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: A dielectric layer is located on the surface of the substrate, and a lower electrode layer is located on the side of the dielectric layer away from the substrate.

9. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; A conductive contact layer is formed, the conductive contact layer is located on a portion of the surface of the substrate, and a plurality of the conductive contact layers are separated from each other on the surface of the substrate. The conductive contact layer includes a plurality of first conductive contact layers and a plurality of second conductive contact layers, and the orthographic projection of the plurality of first conductive contact layers on the surface of the substrate surrounds the plurality of second conductive contact layers. A first insulating layer is formed on the surface of the plurality of first conductive contact layers away from the substrate; Multiple lower electrode layers are formed, the multiple lower electrode layers are located on a portion of the substrate, and the multiple lower electrode layers are arranged in an array on the surface of the substrate, the multiple lower electrode layers are located on the top surface of the multiple second conductive contact layers away from the substrate; A dielectric layer is formed, which covers the top surface of the plurality of lower electrode layers away from the substrate and a portion of the side surfaces of the plurality of lower electrode layers. The dielectric layer is located on a portion of the surface of the first insulating layer away from the substrate, and the dielectric layer located around the plurality of lower electrode layers protrudes in a direction parallel to the surface of the substrate in a direction away from the plurality of lower electrode layers in the region near the substrate. An upper electrode layer is formed, which covers the top surface of the dielectric layer away from the substrate and also covers the side surface of the dielectric layer.

10. The manufacturing method as described in claim 9, characterized in that, The formation of the first insulating layer specifically includes: A first insulating film is formed, the first insulating film being located on the surface of the conductive contact layer away from the substrate, and the orthographic projection of the first insulating film onto the substrate covering the entire surface of the substrate; A photoresist layer is formed on the surface of the first insulating film away from the substrate, and the photoresist layer has an opening located in the central region of the photoresist layer. Etching through the opening can expose the entire top surface of the plurality of second conductive contact layers away from the substrate. Using the photoresist layer as a mask, the first insulating film is etched along the opening to obtain the first insulating layer.

11. The manufacturing method as described in claim 9, characterized in that, The formation of the upper electrode layer includes: A first upper electrode layer is formed, the first upper electrode layer covering the top surface of the dielectric layer away from the substrate, and the first upper electrode layer covering the side surface of the dielectric layer; A second upper electrode layer is formed, which covers the top surface of the first upper electrode layer away from the substrate and also covers the side surface of the first upper electrode layer. The thickness of the second upper electrode layer is greater than the thickness of the first upper electrode layer.

12. The manufacturing method as described in claim 9, characterized in that, After forming the upper electrode layer, the method further includes: A second insulating layer is formed, which covers the side of the upper electrode layer and is in contact with the first insulating layer.

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