A method for manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, forming a stack material layer on the substrate, the stack material layer covering a surface of the substrate, and the stack material layer having a first warping degree; introducing a first source gas and a second source gas into a reaction chamber to form a mask layer covering the stack material layer, and a structure composed of the stack material layer and the mask layer having a second warping degree, wherein a difference between the second warping degree and the first warping degree is within a first preset range, and the first source gas at least contains a silicon-containing gas; forming an etching pattern on the mask layer, and etching the mask layer with the etching pattern as a mask to form a plurality of mask patterns exposing part of the stack material layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor structure. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is an important semiconductor device, which can be used as data storage or program storage when electronic devices are operated to perform data processing. However, as Dynamic Random Access Memory (DRAM) continues to develop towards miniaturization and high integration, there are still many factors that reduce the performance of semiconductor devices in the preparation process of Dynamic Random Access Memory (DRAM). SUMMARY

[0003] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, comprising:

[0004] providing a substrate, forming a stack material layer on the substrate, the stack material layer covering a surface of the substrate, the stack material layer having a first warpage;

[0005] introducing a first source gas and a second source gas into a reaction chamber to form a mask layer covering the stack material layer, a structure composed of the stack material layer and the mask layer having a second warpage, a difference between the second warpage and the first warpage being within a first preset range; wherein the first source gas at least contains a silicon-containing gas;

[0006] forming an etching pattern on the mask layer;

[0007] etching the mask layer with the etching pattern as a mask to form a plurality of mask patterns exposing part of the stack material layer.

[0008] In some embodiments, the mask layer is formed by:

[0009] introducing a first source gas into a reaction chamber, the first source gas at least containing a silicon-containing gas, to form a polysilicon material layer;

[0010] introducing a second source gas into the reaction chamber to perform a doping process, the second source gas containing a carbon-containing gas, to form a doped polysilicon layer, the doped polysilicon layer serving as the mask layer, a structure composed of the stack material layer and the mask layer having a second warpage.

[0011] In some embodiments, the mask layer is formed by:

[0012] simultaneously introducing a first source gas and a second source gas into a reaction chamber to form a mask layer on a surface of the substrate, a structure composed of the stack material layer and the mask layer having a second warpage;

[0013] wherein the first source gas comprises a silicon-containing gas and the second source gas comprises a carbon-containing gas.

[0014] In some embodiments, before forming the polysilicon material layer, the preparation method further comprises:

[0015] introducing a silicon-containing gas into the reaction chamber to form an adhesion layer on the stack material layer, the adhesion layer being used to increase adhesion of the polysilicon material layer.

[0016] In some embodiments, after forming the doped polysilicon layer, the preparation method further comprises:

[0017] performing an annealing process, a temperature range of the annealing process being between 450°C and 650°C.

[0018] In some embodiments, the silicon-containing gas comprises any one or a combination of diisopropylaminosilane, monosilane, dichlorosilane or disilane; and the carbon-containing gas comprises ethylene.

[0019] In some embodiments, a carbon doping amount in the mask layer ranges between 2% and 50%.

[0020] In some embodiments, the carbon doping amount in the mask layer has the same or different concentration gradient in a direction from a surface of the mask layer close to the substrate to a surface of the mask layer away from the substrate.

[0021] In some embodiments, the carbon doping amount in the mask layer has a distribution trend from low to high in a direction from a surface of the mask layer close to the substrate to a surface of the mask layer away from the substrate, the doping amount changes linearly, and a change range of the doping amount is between 0% and 20%.

[0022] In some embodiments, etching the mask layer comprises:

[0023] etching the mask layer using the etching pattern as a mask, the mask layer remaining after removing part of the mask layer constituting a plurality of mask patterns;

[0024] wherein a structure composed of the mask patterns and the stack material layer has a third warpage, and a difference between the third warpage and the first warpage is within a second preset range.

[0025] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure comprises: providing a substrate, forming a stack material layer on the substrate, the stack material layer covering a surface of the substrate, the stack material layer having a first warping degree; introducing a first source gas and a second source gas into a reaction chamber to form a mask layer covering the stack material layer, a structure composed of the stack material layer and the mask layer having a second warping degree, a difference between the second warping degree and the first warping degree being within a first preset range; wherein the first source gas at least comprises a silicon-containing gas; forming an etching pattern on the mask layer; etching the mask layer with the etching pattern as a mask to form a plurality of mask patterns exposing part of the stack material layer. It can be understood that, after the stack material layer having the first warping degree is formed, when a material layer serving as a mask function is continuously formed on the stack material layer by using a conventional process, there is usually a large difference between the warping degree of a structure composed of the stack material layer and the subsequently formed material layer and the first warping degree, so that when the material layer is etched to obtain a pattern structure, the pattern structure will be severely tilted, which affects the execution of subsequent processes and seriously reduces the performance of the semiconductor structure finally obtained. In the embodiments of the present disclosure, after the stack material layer is formed, the two source gases are introduced into the reaction chamber to make the obtained mask layer and the stack material layer have an improved warping degree, i.e., the second warping degree, and the difference between the second warping degree and the first warping degree is within a certain preset range, so that the mask pattern obtained on the basis of the mask layer can have a smaller tilt degree, or even no tilt occurs, which can effectively improve the yield and performance of the semiconductor structure finally obtained.

[0026] The details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0028] Figure 1 A flow chart of the method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure is shown in FIG. 1;

[0029] Figures 2 to 10 A process flow chart of the method for manufacturing a semiconductor structure provided by one embodiment of the present disclosure is shown in FIG. 2;

[0030] Figures 11 to 13A process flow diagram of a method of fabricating a semiconductor structure is provided for another embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0032] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate the present disclosure. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate the present disclosure.

[0033] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals can represent like elements throughout the several figures.

[0034] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, when an element is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected to or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0035] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] In a semiconductor structure, such as a DRAM, a capacitor structure is an important component. In forming the capacitor structure, a capacitor hole structure is usually formed first, and then a lower electrode, a dielectric layer and an upper electrode are deposited in the capacitor hole structure to obtain the capacitor structure. In this process, stress and stress-induced warping cannot be ignored. It can be understood that, in addition to the step of performing material deposition in the capacitor hole, the capacitor hole is usually inclined or curved due to the presence of stress in the process of forming the capacitor hole, which affects the electrical performance and the capacitor storage capacity of the finally obtained capacitor structure.

[0038] Based on this, the following technical solutions of the embodiments of the disclosure are proposed:

[0039] The embodiments of the disclosure provide a preparation method of a semiconductor structure, as shown in the figure, the method comprises the following steps: Figure 1 As shown in the figure, the method comprises the following steps:

[0040] Step S101: providing a substrate, forming a stacked material layer on the substrate, the stacked material layer covering the surface of the substrate, the stacked material layer having a first warping degree;

[0041] Step S102: introducing a first source gas and a second source gas into the reaction chamber to form a mask layer covering the stack material layer, the structure composed of the stack material layer and the mask layer having a second warping degree, the difference between the second warping degree and the first warping degree being within a first preset range; wherein the first source gas at least contains a silicon-containing gas;

[0042] Step S103: forming an etching pattern on the mask layer;

[0043] Step S104: etching the mask layer with the etching pattern as a mask to form a plurality of mask patterns exposing part of the stack material layer.

[0044] It can be understood that, after the stack material layer having the first warping degree is formed, when a material layer serving as a mask function is continuously formed on the stack material layer by using a conventional process, there is usually a large difference between the warping degree of the structure composed of the stack material layer and the subsequently formed material layer and the first warping degree, so that when the material layer is etched to obtain a pattern structure, the pattern structure will be severely tilted, which affects the execution of subsequent processes and seriously reduces the performance of the finally obtained semiconductor structure. In the embodiment of the present disclosure, after the stack material layer is formed, the mask layer obtained by introducing two source gases into the reaction chamber can have an improved warping degree, i.e., the second warping degree, and the difference between the second warping degree and the first warping degree is within a certain preset range, so that the mask pattern obtained on the basis of the mask layer can have a smaller tilt degree, or even no tilt occurs, which can effectively improve the yield and performance of the finally obtained semiconductor structure.

[0045] It should be understood that, although Figure 1 each step in the flowchart of FIG. 10 is shown in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 1 at least part of the steps in the flowchart of FIG. 10 can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or sub-steps or stages of other steps.

[0046] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure will be described in detail below with reference to the drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagrams will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples, which should not limit the protection scope of the present disclosure.

[0047] Figures 2 to 10 A process flow chart of a method for manufacturing a semiconductor structure is provided for one embodiment of the present disclosure; Figures 11 to 13 A process flow chart of a method for manufacturing a semiconductor structure is provided for another embodiment of the present disclosure.

[0048] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings.

[0049] First, step S101 is performed, as shown in Figure 2 and Figure 3 , a substrate 10 is provided, and a stack material layer ST is formed on the substrate 10, the stack material layer ST covers the surface of the substrate 10, and the stack material layer ST has a first warping degree.

[0050] Here, the substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (for example, silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (for example, gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, the substrate 10 is a silicon substrate.

[0051] In some embodiments, the semiconductor structure further includes an isolation structure STI, which defines the substrate 10 as a plurality of active regions 101.

[0052] Optionally, other structures can also be provided between the substrate 10 and the stack material layer ST. For example, in some embodiments, the semiconductor structure further includes:

[0053] a bit line contact plug 141 located on the active region 101 and a bit line structure BL located on the bit line contact plug 1411; wherein the bit line structure BL is connected to the active region 101 through the bit line contact plug 141;

[0054] a node contact plug 142 located on the active region 101 and on one side of the bit line contact plug 141;

[0055] a dielectric layer L1 located on the bit line structure BL and the node contact plug 142, the dielectric layer L1 covering the surfaces of the bit line structure BL and the node contact plug 142;

[0056] a conductive structure 13 located in the dielectric layer L1, the conductive structure 13 being connected to the active region 101 through the node contact plug 142.

[0057] In some embodiments, as shown in Figure 3 , the stack material layer ST is formed on the substrate 10, which includes:

[0058] A first sacrificial layer 151 is formed to cover the surface of the dielectric layer L1;

[0059] A first support layer 152 is formed to cover the surface of the first sacrificial layer 151;

[0060] A second sacrificial layer 153 is formed to cover the surface of the first support layer 152;

[0061] A second support layer 154 is formed to cover the surface of the second sacrificial layer 153.

[0062] Here, the material of the first support layer 152 and the second support layer 154 can include, but is not limited to, one or a combination of silicon oxide, silicon nitride, silicon carbon nitride, etc. The material of the first sacrificial layer 151 and the second sacrificial layer 153 can include, but is not limited to, one or a combination of silicon oxide, phosphorus silicon glass (PSG), boro phosphor silicate glass (BPSG), or poly silicon (Poly), etc.

[0063] Optionally, in some embodiments, the material of the first sacrificial layer 152, the first support layer 152, the second sacrificial layer 153, and the second support layer 154 can also be other suitable materials, which can be selected according to actual conditions and are not specifically limited here.

[0064] In addition, the material contained in the first support layer 152 and the material contained in the second support layer 154 can be the same or different. Similarly, the material contained in the first sacrificial layer 151 and the material contained in the second sacrificial layer 153 can be the same or different, which are not specifically limited here.

[0065] It can be understood that due to the characteristics of the material itself or other possible reasons, after the process of ending the deposition of the stack material layer ST, there can be a certain tensile stress in the stack material layer ST, which makes the stack material layer ST have a first warpage.

[0066] In some embodiments, the range of the first warpage can be between 10 μm and 30 μm (including the end point value), for example, about 20 μm.

[0067] Next, step S102 is performed, as shown in FIG. 2, a first support layer 152 is formed to cover the surface of the first sacrificial layer 151. Figure 5 、 Figure 6 and Figure 11As shown, the first source gas and the second source gas are introduced into the reaction chamber to form the mask layer 11 covering the stack material layer ST, and the structure 20 composed of the stack material layer ST and the mask layer 11 has a second warping degree, and a difference between the second warping degree and the first warping degree is within a first preset range. The first source gas at least contains a silicon-containing gas.

[0068] In some embodiments, the first warping degree and the second warping degree can refer to warping degrees of the material layer existing in a direction perpendicular to the surface of the substrate 10. However, the first warping degree and the second warping degree are not limited to this, and in some embodiments, the first warping degree and the second warping degree can refer to warping degrees of the material layer existing in other directions.

[0069] In some embodiments, the thickness of the mask layer 11 can be in a range of 650 nm to 750 nm, for example, 660 nm, 680 nm, 700 nm, 710 nm, 730 nm, etc.

[0070] In one embodiment of the present disclosure, as shown in Figure 5 and Figure 6 As shown, the mask layer 11 is formed, including:

[0071] The first source gas at least containing a silicon-containing gas is introduced into the reaction chamber to form a polysilicon material layer 11a;

[0072] The second source gas containing a carbon-containing gas is introduced into the reaction chamber to perform a doping process, so as to form a doped polysilicon layer as the mask layer 11, and the structure 20 composed of the stack material layer ST and the mask layer 11 has a second warping degree.

[0073] In this embodiment, the doped polysilicon layer as the mask layer 11 is a carbon-doped polysilicon layer.

[0074] Optionally, in some embodiments, the doped polysilicon layer as the mask layer 11 can also be obtained by in-situ doping. The formation mode of the doped polysilicon layer can be flexibly selected according to actual conditions, which is not limited here.

[0075] In some embodiments, the carbon doping amount in the mask layer 11 is in a range of 2% to 50% (including the end value), for example, 5%, 10%, 15%, 20%, 25%, 30%, 40%, 45%, etc.

[0076] It can be understood that, in the embodiments of the present disclosure, in addition to providing the scheme of the carbon doping amount range, a plurality of embodiment schemes about the concentration gradient of the carbon element in the mask layer 11 at different positions in different cases are also provided to help meet different needs of different application scenarios, for example:

[0077] In some embodiments, the carbon doping amount in the mask layer 11 has the same concentration gradient in the direction from the surface S1 of the mask layer 11 close to the substrate 10 to the surface S2 of the mask layer 11 away from the substrate 10.

[0078] In this embodiment, when the carbon element has the same concentration gradient in the mask layer 11, it is beneficial to obtain a relatively stable stress variation of the mask layer 11 at different positions, so as to prevent the occurrence of local stress sudden increase or sudden decrease, thereby making the mask layer 11 obtained in this step have better stability, and being beneficial to obtain a relatively stable warpage improvement effect.

[0079] In other embodiments, the carbon doping amount in the mask layer 11 has different concentration gradients in the direction from the surface S1 of the mask layer 11 close to the substrate 10 to the surface S2 of the mask layer 11 away from the substrate 10.

[0080] In this embodiment, the case that the carbon element has different concentration gradients is beneficial to the operator to design the specific concentration gradient values at different positions of the mask layer 11 according to the warpage adjustment requirements or the stress distribution in the material layer located above the substrate 10, and compared with the case of the same concentration gradient, it is further beneficial to obtain a semiconductor structure that meets the expected warpage improvement effect.

[0081] In yet other embodiments, the carbon doping amount in the mask layer 11 has a distribution trend from low to high in the direction from the surface S1 of the mask layer 11 close to the substrate 10 to the surface S2 of the mask layer 11 away from the substrate 10, the doping amount changes linearly, and the doping amount change range is between 0% and 20%, for example, 2%, 5%, 8%, 10%, 12%, 14%, 16%, 18%, etc.

[0082] It is considered that after forming the doped polysilicon layer, a heat treatment process is usually involved, however, the heat treatment process is easy to cause the carbon element to diffuse in the doped polysilicon layer, in order to reduce the possibility of carbon element diffusion into the stack material layer ST located below the mask layer 11 as much as possible, the scheme provided in this embodiment can be used to reduce the diffusion of carbon element into the stack material layer ST.

[0083] In this embodiment, the concentration gradient of the carbon element in the mask layer 11 changes linearly, and the concentration in the direction from the surface S1 to the surface S2 has a distribution trend from low to high, which can effectively reduce the possibility of carbon element diffusion into the stack material layer ST during the heat treatment operation, thereby effectively avoiding the phenomenon that the size deviation of the stack material layer ST occurs during etching due to the diffusion of carbon element into the stack material layer ST, and being helpful to make the size range of the finally obtained stack structure 17 (for details, please refer to Figure 10 ) meet the expected requirements.

[0084] In addition, in this embodiment, when the concentration of carbon element in the mask layer 11 is distributed from low to high in the direction from the surface S1 to the surface S2, the tensile stress generated by carbon doping has a smaller value at the position close to the surface S1, and the tensile stress generated by carbon doping can have an increasingly large value in the direction from the surface S1 to the surface S2. At this time, when other material layers (including but not limited to the first material layer 12 and the second material layer 16 shown in Figure 7 the surface S2 has a larger tensile stress, which can effectively balance the stress condition in the structure composed of the stacked material layer ST, the mask layer 11 and other material layers, and is beneficial to the semiconductor structure obtained in this step to have a smaller warpage, so as to have a relatively flat upper surface, thereby providing a good prerequisite for the subsequent steps.

[0085] It can be understood that, in some embodiments, after the doped polysilicon layer is formed, the preparation method further comprises:

[0086] performing a heat treatment process, for example, an annealing process, and the annealing process is performed at a temperature in the range of 450°C to 650°C (including the end values), for example, 480°C, 500°C, 550°C, 570°C, 600°C, 610°C, 630°C, etc.

[0087] In some specific embodiments, the annealing process comprises a laser annealing process, and since the laser annealing process can have a faster processing speed, the possibility of diffusion of carbon element into the stacked material layer ST can be further reduced.

[0088] It can be understood that the heat treatment process can repair the damage or defects existing in the polysilicon material layer to a certain extent, but can also cause the tensile stress to continue to increase, and in the embodiments of the present disclosure, through the combined execution of the carbon doping process and the heat treatment process, the damage or defects can be repaired without further increasing the tensile stress, thereby effectively improving the warping phenomenon of the material layer located above the substrate.

[0089] In some embodiments, as shown in Figure 4 before the polysilicon material layer 11a is formed, the preparation method further comprises:

[0090] introducing a silicon-containing gas into the reaction chamber to form an adhesion layer L2 on the stacked material layer ST, and the adhesion layer L2 is used to increase the adhesion of the polysilicon material layer 11a.

[0091] It can be understood that, before forming the polysilicon material layer 11a, forming the adhesion layer L2 is beneficial to enhance the adhesion of the polysilicon material layer 11a on the stacked material layer ST, and prevent the occurrence of gaps, defects or peeling between the polysilicon material layer 11a and the stacked material layer ST.

[0092] Optionally, in some embodiments, the silicon-containing gas used to form the adhesion layer L2 includes, but is not limited to, any one of diisopropylaminosilane and dichlorosilane. However, in some embodiments, the silicon-containing gas used to form the adhesion layer L2 can also be a mixed gas containing both diisopropylaminosilane and dichlorosilane.

[0093] It can be understood that, as shown in Figure 5 , due to the existence of a large compressive stress (in some cases, the compressive stress can reach 0.2 Gpa or even more) in the polysilicon material layer 11a, the stress state in the plurality of material layers on the substrate 10 before and after the formation of the polysilicon material layer 11a changes from a state dominated by tensile stress (corresponding to the stacked material layer ST) to a state dominated by compressive stress (corresponding to the structure 21 composed of the stacked material layer ST and the polysilicon material layer 11a). After performing the carbon doping process, the obtained doped polysilicon layer (the doped polysilicon layer is the mask layer 11 as shown in Figure 6 ) has a certain tensile stress, and the existence of the tensile stress can balance the compressive stress caused by the deposition of the polysilicon material layer 11a to a certain extent.

[0094] Continuing to refer to Figure 6 , in some embodiments, the balance of the tensile stress and the compressive stress can effectively improve the warpage of the structure 20 composed of the stacked material layer ST and the mask layer 11 (i.e., the second warpage).

[0095] In another embodiment of the present disclosure, as shown in Figure 11 , the mask layer 11 is formed by:

[0096] simultaneously introducing the first source gas and the second source gas into the reaction chamber to form the mask layer 11 on the surface of the substrate 10, and the structure 20 composed of the stacked material layer ST and the mask layer 11 has the second warpage.

[0097] , wherein the first source gas contains a silicon-containing gas, and the second source gas contains a carbon-containing gas.

[0098] In this embodiment, the material of the mask layer 11 can include silicon carbide, and due to the presence of carbon element, the structure 20 composed of the stack material layer ST and the mask layer 11 can also have improved warpage (i.e., the second warpage). In this embodiment, due to the use of the mode of simultaneously passing in the first and second source gases instead of sequentially passing in, the process of forming the mask layer 11 in this embodiment can have higher production efficiency compared with the previous embodiment.

[0099] Optionally, in any of the above embodiments, the silicon-containing gas includes any one or a combination of diisopropylaminosilane, silane, dichlorosilane or disilane; and the carbon-containing gas includes ethylene.

[0100] But not limited to this, in some embodiments, the silicon-containing gas and the carbon-containing gas can also be other suitable gas species, which can be selected according to actual conditions, and are not limited here.

[0101] In any of the above embodiments, the second warpage can be in the range of -40 μm to 40 μm (including the end point value), such as -35 μm, -30 μm, -25 μm, -20 μm, -15 μm, -10 μm, -5 μm, 0 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, etc.

[0102] In actual operation, in any of the above embodiments, the structure 20 composed of the stack material layer ST and the mask layer 11 can have improved second warpage by adjusting the ratio of silicon element in the first source gas to carbon element in the second source gas. For example:

[0103] In some embodiments, the structure 20 composed of the stack material layer ST and the mask layer 11 can have improved second warpage, such as the case of 0 μm second warpage, by adjusting the ratio of silicon element in the first source gas to carbon element in the second source gas. It can be understood that when the second warpage is 0 μm, the entire upper surface of the mask layer 11 can be in a flat state. Without considering the fluctuation of warpage that can be caused by other material layers, after undergoing a series of subsequent process steps, this embodiment can obtain a plurality of mask patterns 111 whose boundaries are parallel to each other and perpendicular to the surface of the substrate 10 in the direction perpendicular to the surface of the substrate 10 (for details, please refer to Figure 9 ).

[0104] It can be understood that, compared with the above embodiment, in other embodiments, the doping amount of carbon elements can also be appropriately increased to make the tensile stress in the structure 20 composed of the stacked material layer ST and the mask layer 11 slightly larger than the compressive stress (i.e., the second warping degree is positive), or the doping amount of carbon elements can also be appropriately reduced to make the compressive stress in the structure 20 composed of the stacked material layer ST and the mask layer 11 slightly larger than the tensile stress (i.e., the second warping degree is negative). At this time, the surface of the obtained mask layer 11 has a smaller warping degree (i.e., the second warping degree is smaller), and the warping of the surface of the mask layer 11 is effectively improved, which is beneficial to the mask pattern 111 (see Figure 9 ) formed on the basis of the mask layer 11 having a smaller inclination degree and effectively improving the uniformity between the mask patterns 111.

[0105] In actual operation, considering that during the subsequent etching of the mask layer 11 to form the mask pattern 111 (see Figure 9 ), due to the removal of part of the mask layer 11 material or other factors, the structure 22 composed of the stacked material layer ST and the mask pattern 111 (see Figure 9 ) may have a case of increased tensile stress. At this time, in order to balance the stress change in this step and reduce the influence on the morphology of the mask pattern 111 (see Figure 9 ), compared with the case where the second warping degree is 0 μm, the scheme of appropriately reducing the doping amount of carbon elements (i.e., the case where the second warping degree is negative) can be used to make the compressive stress in the structure 20 composed of the stacked material layer ST and the mask layer 11 larger than the tensile stress, so as to effectively balance the stress change in the subsequent step, thereby being beneficial to the actual operation, and the finally obtained mask pattern 111 (see Figure 9 ) can have a smaller inclination degree and better uniformity; and even being beneficial to obtaining multiple mask patterns 111 (see Figure 9 ) whose boundaries are parallel to each other and perpendicular to the surface of the substrate 10 in the direction perpendicular to the surface of the substrate 10.

[0106] It can be understood that, in some embodiments, the first preset range can be between -30 μm and -20 μm (including the end point value), for example, -29 μm, -28 μm, -26 μm, -25 μm, -24 μm, -22 μm, etc.; or the first preset range can be between 20 μm and 30 μm (including the end point value), for example, 22 μm, 24 μm, 25 μm, 26 μm, 28 μm, 29 μm, etc.

[0107] Compared with the case in the conventional process, the difference between the second warping degree and the first warping degree can be as high as 150 μm or even much higher than 150 μm. However, due to the fact that the warping degree is improved while the mask layer 11 is formed in the embodiment of the present disclosure, the semiconductor structure provided by the embodiment of the present disclosure will not have the problem of alignment difficulty in the operation step involving mask alignment. Meanwhile, the semiconductor structure provided by the embodiment of the present disclosure can have a smaller inclination degree after the mask layer 11 is obtained, and the structures can have better uniformity. Figure 9 Meanwhile, the mask pattern 111 or the stack structure 17 between the capacitor hole structures H can have a smaller inclination degree. Figure 10

[0108] Further, due to the foregoing reasons, in some embodiments, the obtained mask pattern 111 or the stack structure 17 between the capacitor hole structures H (please refer to Figure 10 ) can also be in the case of not having any inclination, in which case the patterns can extend in the direction perpendicular to the surface of the substrate 10 while having boundaries parallel to each other. It can be understood that when the capacitor hole structure H has a better topography, the capacitor structure formed subsequently therein will not have the phenomenon of bending or inclination of the capacitor structure due to the inclination, which affects the charge storage capacity, so as to effectively improve the stability and storage capacity of the capacitor structure. Meanwhile, the capacitor structure and the conductive structure 13 can be better aligned, thereby being beneficial to the improvement of the electrical performance of the capacitor structure.

[0109] Then, step S103 is performed, in which an etching pattern M is formed on the mask layer 11, as shown in Figure 7 and Figure 12 .

[0110] Optionally, in some embodiments, the material of the etching pattern M includes, but is not limited to, photoresist and the like.

[0111] In some embodiments, before the etching pattern M is formed, the preparation method further includes:

[0112] forming a first material layer 12 as a mask function, the first material layer 12 covering the surface of the mask layer 11;

[0113] forming a second material layer 16 as a mask function, the second material layer 16 covering the surface of the first material layer 12.

[0114] ​It can be understood that, when the first material layer 12 and the second material layer 16 as a mask function continue to be formed on the mask layer 11, the process of transferring the etching pattern M downward can help improve the accuracy of pattern transfer. For example, in some embodiments, the etching pattern M can be first transferred into the second material layer 16, and then transferred into the second material layer 12 to form the second pattern 121 shown in the second pattern 121, and then multiple operations of continuing to transfer the second pattern 121 downward are performed. Figure 8

[0115] In some embodiments, the material of the first material layer 12 includes but is not limited to an oxide such as silicon oxide and the like. The second material layer 16 can include a first sub-layer (not labeled in the figure) and a second sub-layer (not labeled in the figure) from bottom to top, wherein the material of the first sub-layer (not labeled in the figure) includes but is not limited to a spin-on hard mask layer, which can include an amorphous carbon layer or an amorphous silicon layer and the like; the material of the second sub-layer (not labeled in the figure) includes but is not limited to an oxynitride such as silicon oxynitride and the like. But not limited to this, in some embodiments, the materials contained in the first material layer 12 and the second material layer 16 can also be other suitable materials.

[0116] Finally, step S104 is performed, as shown in Figure 8 Figure 9 and Figure 13 , the mask layer 11 is etched with the etching pattern M as a mask to form a plurality of mask patterns 111 that expose part of the stack material layer ST.

[0117] In some embodiments, the mask layer 11 is etched, including:

[0118] The mask layer 11 is etched with the etching pattern M as a mask, and the mask layer 11 remaining after part of the mask layer 11 is removed constitutes a plurality of mask patterns 111;

[0119] The structure 22 composed of the mask pattern 111 and the stack material layer ST has a third warping degree, and the difference between the third warping degree and the first warping degree is within a second preset range.

[0120] In some embodiments, the second preset range can be between -20 μm and 20 μm (including the end point value), for example, -18 μm, -15 μm, -10 μm, -5 μm, -3 μm, 0 μm, 5 μm, 8 μm, 10 μm, 13 μm, 15 μm, 18 μm and the like.

[0121] ​​In this embodiment, since the value of the first warp is usually not very large, when the difference between the third warp and the first warp falls within the above range, it indicates that the value of the third warp is also small, and may even be 0 μm. When the third warp is small, the final mask pattern 111 can have a small tilt and good uniformity; while when the third warp is 0 μm, the final mask pattern 111 can have its boundaries parallel to each other and perpendicular to the surface of the substrate 10 in the direction perpendicular to the surface of the substrate 10.

[0122] Optionally, in some embodiments, such as Figure 10 As shown, in the formation Figure 9 and Figure 13 Following the mask pattern 111 shown, the fabrication method may further include:

[0123] Using mask pattern 111 as a mask, an etching process is performed on the stacked material layer ST to remove part of the stacked material layer ST to form a capacitor hole structure H. The remaining stacked material layer ST constitutes the stacked structure 17.

[0124] It is understandable that, since the present invention takes into account the improvement of warpage while forming the mask layer 11, the obtained mask pattern 111 can have a better morphology. As a result, when the stacked material layer ST is etched based on the mask pattern 111 to obtain the capacitor hole structure H, the stacked structures 17 located between the capacitor hole structures H can all have a small degree of tilt and better uniformity.

[0125] Furthermore, for the reasons mentioned above, in some embodiments, the obtained mask pattern 111 is located in the capacitor hole structure H (see details). Figure 10 The stacked structure 17 between the capacitor holes extends in a direction perpendicular to the surface of the substrate 10 while also having parallel boundaries. It is understood that when the capacitor hole structure H has a good morphology, the capacitor structure subsequently formed within it can also have a good morphology, avoiding phenomena such as bending or tilting of the capacitor structure due to significant tilting that affect charge storage capacity. This effectively improves the stability and storage capacity of the capacitor structure. Simultaneously, it allows for better alignment between the capacitor structure and the conductive structure 13, thereby contributing to improved electrical performance of the capacitor structure.

[0126] This disclosure also provides a semiconductor structure, such as... Figure 9 and Figure 13 As shown, the semiconductor structure includes:

[0127] Substrate 10;

[0128] A stacked material layer ST covers the surface of the substrate 10;

[0129] Multiple mask patterns 111 are located on the substrate 10, and the mask patterns 111 expose a portion of the stacked material layer ST; wherein the multiple mask patterns 111 have a small degree of tilt; or, the boundaries of the multiple mask patterns 111 in the direction perpendicular to the surface of the substrate 10 are parallel to each other and perpendicular to the surface of the substrate 10.

[0130] In this embodiment, since the mask pattern 111 has a small degree of tilt or no tilt, when the mask pattern 111 is used as a mask to perform an etching process to form a pattern structure in the stacked material layer ST, a pattern structure with a better morphology can also be obtained in the stacked material layer ST.

[0131] In some embodiments, the material of the mask pattern 111 includes, but is not limited to, at least one or a combination of a doped polysilicon layer (e.g., a carbon-doped polysilicon layer) or a silicon carbide layer.

[0132] In some embodiments, the carbon doping amount in the mask pattern 111 ranges from 2% to 50% (including endpoint values), such as 5%, 10%, 15%, 20%, 25%, 30%, 40%, 45%, etc.

[0133] Optionally, the mask pattern 111 can be formed by introducing a silicon-containing gas and a carbon-containing gas into the reaction chamber. In some embodiments, the silicon-containing gas includes any one or a combination of diisopropylaminosilane, silane, dichlorosilane, or ethylsilane; the carbon-containing gas includes ethylene.

[0134] In some embodiments, such as Figure 9 As shown, when the material of the mask pattern 111 includes a carbon-doped polysilicon layer, the semiconductor structure may also include an adhesion layer L2, which is located between the stacked material layer ST and the mask pattern 111.

[0135] Understandably, the presence of the adhesion layer L2 helps to enhance the adhesion of the mask pattern 111 to the stacked material layer ST, preventing gaps, defects or peeling between the mask pattern 111 and the stacked material layer ST.

[0136] Optionally, in some embodiments, the silicon-containing gas used to form the adhesion layer L2 includes, but is not limited to, any one of diisopropylaminosilane and dichlorosilane. However, it is not limited to this; in some embodiments, the silicon-containing gas used to form the adhesion layer L2 may also be a mixed gas containing both diisopropylaminosilane and dichlorosilane.

[0137] This disclosure also provides a semiconductor structure, such as... Figure 10 As shown, the semiconductor structure includes:

[0138] a substrate 10;

[0139] a stack structure 17 located on the substrate 10; wherein the stack structure 17 has a small degree of inclination, or the boundaries of the stack structure 17 in a direction perpendicular to the surface of the substrate 10 are parallel to each other and perpendicular to the surface of the substrate 10;

[0140] a plurality of capacitor hole structures H located in the stack structure 17, the plurality of capacitor hole structures H have a small degree of inclination, or the boundaries of the plurality of capacitor hole structures H in a direction perpendicular to the surface of the substrate 10 are parallel to each other and perpendicular to the surface of the substrate 10.

[0141] In some embodiments, the semiconductor structure further comprises: a conductive structure 13 located between the substrate 10 and the stack structure 17, and the capacitor hole structure H exposes a surface of the conductive structure 13.

[0142] It can be understood that when the capacitor hole structure H has a good morphology, there will be no problem of difficulty in aligning the capacitor hole structure H with the conductive structure 13, and the capacitor structure subsequently formed therein can also have a good morphology, and there will be no phenomenon of bending or inclination of the capacitor structure due to a large degree of inclination, which affects the charge storage capacity, thereby effectively improving the stability and storage capacity of the capacitor structure.

[0143] It can be understood that the semiconductor structure provided by the embodiments of the present disclosure can be obtained by the preparation method of the semiconductor structure provided by any of the above embodiments.

[0144] It should be noted that the preparation method of the semiconductor device provided by the embodiments of the present disclosure can be applied to a DRAM structure or other semiconductor devices, and is not limited here. The embodiments of the semiconductor device preparation method provided by the present disclosure belong to the same concept as the embodiments of the semiconductor device; the technical features in the technical solutions described in each embodiment can be combined arbitrarily without conflict.

[0145] The above description is only the preferred embodiments of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a stack material layer on the substrate, the stack material layer covering a surface of the substrate, the stack material layer having a first warpage; introducing a first source gas and a second source gas into a reaction chamber to form a mask layer covering the stack material layer, a structure composed of the stack material layer and the mask layer having a second warpage, a difference between the second warpage and the first warpage being within a first preset range; wherein the first source gas comprises at least a silicon-containing gas, and the second source gas comprises a carbon-containing gas; forming an etching pattern on the mask layer; and etching the mask layer using the etching pattern as a mask to form a plurality of mask patterns exposing a portion of the stack material layer. 2.The method of claim 1, wherein forming the mask layer comprises: introducing the first source gas into the reaction chamber, the first source gas comprising at least a silicon-containing gas to form a polysilicon material layer; and introducing a second source gas into the reaction chamber to perform a doping process, the second source gas comprising a carbon-containing gas to form a doped polysilicon layer, the doped polysilicon layer serving as the mask layer, and a structure composed of the stack material layer and the mask layer having a second warpage. 3.The method of claim 1, wherein forming the mask layer comprises: simultaneously introducing a first source gas and a second source gas into the reaction chamber to form the mask layer on the substrate surface, a structure composed of the stack material layer and the mask layer having a second warpage; wherein the first source gas comprises a silicon-containing gas, and the second source gas comprises a carbon-containing gas. 4.The method of claim 2, wherein before forming the polysilicon material layer, the method further comprises: introducing a silicon-containing gas into the reaction chamber to form an adhesion layer on the stack material layer, the adhesion layer being used to increase adhesion of the polysilicon material layer. 5.The method of claim 2, wherein after forming the doped polysilicon layer, the method further comprises: performing an annealing process, a temperature range of the annealing process being between 450 ℃ and 650 ℃. 6.The method of any one of claims 1 to 5, wherein the silicon-containing gas comprises any one or a combination of diisopropylaminosilane, monosilane, dichlorosilane, or disilane; and the carbon-containing gas comprises ethylene. 7.The method of claim 2, wherein a carbon doping amount in the mask layer ranges between 2% and 50%. 8.The method of claim 2, wherein the carbon doping amount in the mask layer has a same or different concentration gradient in a direction from a surface of the mask layer close to the substrate to a surface of the mask layer away from the substrate. 9.The method of claim 2, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The carbon doping amount in the mask layer has a distribution trend from low to high from a surface of the mask layer close to the substrate to a surface of the mask layer away from the substrate, the doping amount changes linearly, and the doping amount changes in a range of 0% to 20%.

10. The preparation method of claim 1, wherein, etching the mask layer, comprising: using the etching pattern as a mask to etch the mask layer, and removing part of the mask layer to form a plurality of mask patterns. The structure composed of the mask pattern and the stack material layer has a third warping degree, and a difference between the third warping degree and the first warping degree is within a second preset range.

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