Dual-transistor NOR-type flash memory storage structure and method for preparing same

Abstract

The present application provides a dual-transistor NOR-type flash memory storage structure, which includes a substrate, a P-type well, a first N-type well, a second N-type well, a third N-type well, an active layer, a polysilicon gate structure, and a bit line structure. The substrate has a deep N-well; the P-type well is disposed on the deep N-well; the first N-type well, the second N-type well, and the third N-type well are spaced apart and disposed in the P-type well, and are spaced apart from the deep N-type well. The second N-type well is located between the first N-type well and the third N-type well; the active layer is disposed on the P-type well, the first N-type well, the second N-type well, and the third N-type well; the polysilicon gate structure and the bit line structure are spaced apart and disposed on the active layer. The active layer, the first N-type well, the second N-type well, and the polysilicon gate form a first transistor, and the active layer, the third N-type well, the second N-type well, and the bit line structure form a second transistor, so as to improve the performance of the storage structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a dual-transistor NOR flash memory structure and a method for manufacturing the same. Background Art

[0002] The NOR (Not-OR) flash memory is mainly used for code storage and a small amount of data storage. The one-transistor NOR flash memory has a smaller bit cell area and is usually used in large-capacity NOR flash memory products. However, its disadvantage is that it is easily interfered by erase, program, and read operations, resulting in poor performance of the memory structure. Summary of the Invention

[0003] In view of this, the present application provides a dual-transistor NOR flash memory structure to improve the performance of the memory structure.

[0004] A dual-transistor NOR flash memory structure provided by the present application is characterized by comprising:

[0005] A substrate having a deep N-well;

[0006] A P-well disposed on the deep N-well;

[0007] A first N-well, a second N-well, and a third N-well are disposed in the P-well at intervals and are spaced from the deep N-well, and the second N-well is located between the first N-well and the third N-well;

[0008] An active layer disposed on the P-well, the first N-well, the second N-well, and the third N-well; and

[0009] A polysilicon gate structure and a bit line structure are disposed on the active layer at intervals. Among them, the polysilicon gate structure is located on part of the first N-well and part of the second N-well, and the bit line structure is located on part of the second N-well and part of the third N-well. The substrate, the P-well, the active layer, the first N-well, the second N-well, and the polysilicon gate form a first transistor, and the substrate, the P-well, the active layer, the third N-well, the second N-well, and the bit line structure form a second transistor.

[0010] Wherein, the polysilicon gate structure includes a floating gate, the bit line structure includes a first bit line, and the floating gate and the first bit line are on the same layer and are disposed on the active layer at intervals.

[0011] Wherein, the polysilicon gate structure further includes a first isolation layer and a control gate that are sequentially stacked on the floating gate, the bit line structure further includes a second isolation layer and a second bit line that are sequentially stacked on the first bit line, the first isolation layer and the second isolation layer are on the same layer and are spaced apart, and the control gate and the second bit line are on the same layer and are spaced apart.

[0012] Wherein, the first isolation layer and the second isolation layer include a first oxide layer, a nitride layer, and a second oxide layer that are sequentially stacked.

[0013] Wherein, the first oxide layer and the second oxide layer are made of the same material.

[0014] Wherein, the materials of the first oxide layer and the second oxide layer both include silicon oxide, and the material of the nitride layer includes silicon nitride.

[0015] This application also provides a method for manufacturing a dual-transistor NOR-type flash memory structure, including:

[0016] Providing a substrate having a deep N well;

[0017] Forming a P well on the deep N well;

[0018] Performing ion implantation on a surface of the P well away from the deep N well to form first, second, and third N wells that are spaced apart, with the second N well located between the first N well and the third N well;

[0019] Forming an active layer on the P well, the first N well, the second N well, and the third N well;

[0020] Forming a polysilicon gate structure and a bit line structure on the active layer, with the polysilicon gate structure and the bit line structure spaced apart. Among them, the polysilicon gate structure is located above part of the first N well and part of the second N well, the bit line structure is located above part of the second N well and part of the third N well, and the substrate, the P well, the active layer, the first N well, the second N well, and the polysilicon gate form a first transistor, and the substrate, the P well, the active layer, the third N well, the second N well, and the bit line structure form a second transistor.

[0021] Wherein, in the step of forming a polysilicon gate structure and a bit line structure on the active layer, with the polysilicon gate structure and the bit line structure spaced apart, it includes:

[0022] Providing a first polysilicon material layer on the active layer;

[0023] Forming an isolation material layer on the first polysilicon material layer;

[0024] Form a second polysilicon material layer on the isolation material layer;

[0025] Etch the first polysilicon material layer, the isolation material layer, and the second polysilicon material layer. The first polysilicon material layer forms floating gates and first bit lines arranged at intervals. The isolation material layer forms first isolation layers and second isolation layers arranged at intervals. The second polysilicon material layer forms control gates and second bit lines arranged at intervals. The floating gates, the first isolation layers, and the control gates are stacked in sequence. The first bit lines, the second isolation layers, and the second bit lines are stacked in sequence.

[0026] Among them, forming the isolation material layer on the first polysilicon material layer includes:

[0027] Stack a first oxide material layer, a nitride material layer, and a second oxide material layer on the first polysilicon material layer in sequence, so that the first oxide material layer forms a first oxide layer, the nitride material forms a nitride layer, and the second oxide material layer forms a second oxide layer.

[0028] Among them, the materials of the first oxide layer and the second oxide layer include silicon oxide, and the material of the nitride layer includes silicon nitride.

[0029] This application provides a dual-transistor NOR flash memory storage structure, including a substrate, a P-type well, a first N-type well, a second N-type well, a third N-type well, an active layer, a polysilicon gate structure, and a bit line structure. The substrate has a deep N-well; the P-type well is disposed on the deep N-well; the first N-type well, the second N-type well, and the third N-type well are arranged at intervals in the P-type well and are spaced from the deep N-well. The second N-type well is located between the first N-type well and the third N-type well; the active layer is disposed on the P-type well, the first N-type well, the second N-type well, and the third N-type well; the polysilicon gate structure and the bit line structure are arranged at intervals on the active layer. The polysilicon gate structure is located above part of the first N-type well and part of the second N-type well, and the bit line structure is located above part of the second N-type well and part of the third N-type well. The substrate, the P-type well, the active layer, the first N-type well, the second N-type well, and the polysilicon gate form a first transistor, and the substrate, the P-type well, the active layer, the third N-type well, the second N-type well, and the bit line structure form a second transistor to improve the performance of the storage structure. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0031] Figure 1 is a schematic plan view of a planar structure of a dual-transistor NOR flash memory structure provided by the present application;

[0032] Figure 2 is Figure 1 a schematic cross-sectional view of the dual-transistor NOR flash memory structure in along line AB;

[0033] Figure 3 is a schematic flow chart of a preparation method of a dual-transistor NOR flash memory structure provided by the present application;

[0034] Figures 4 - 7 is a schematic flow chart of a planar structure of a dual-transistor NOR flash memory structure provided by the present application;

[0035] Figures 8 - 10 is Figures 4 - 7 a schematic three-dimensional structure flow chart of the dual-transistor NOR flash memory structure at position A in .

[0036] Reference numerals:

[0037] 10. Dual-transistor NOR flash memory structure; 100. Substrate; 200. P-type well; 300. First N-type well; 310. Second N-type well; 320. Third N-type well; 400. Active layer; 500. Floating gate; 501. First polysilicon material layer; 600. First isolation layer; 601. Isolation material layer; 700. Control gate; 701. Through hole; 900. First bit line; 1000. Second isolation layer; 1100. Second bit line. Detailed embodiments

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application. Without conflict, the following various embodiments and their technical features can be combined with each other.

[0039] The present application provides a dual-transistor NOR flash memory storage structure, including a substrate, a P-type well, a first N-type well, a second N-type well, a third N-type well, an active layer, a polysilicon gate structure, and a bit line structure. The substrate has a deep N-well; the P-type well is disposed on the deep N-well; the first N-type well, the second N-type well, and the third N-type well are spaced apart and disposed within the P-type well, and are spaced apart from the deep N-well. The second N-type well is located between the first N-type well and the third N-type well; the active layer is disposed on the P-type well, the first N-type well, the second N-type well, and the third N-type well; the polysilicon gate structure and the bit line structure are spaced apart and disposed on the active layer. The polysilicon gate structure is located above a part of the first N-type well and a part of the second N-type well, and the bit line structure is located above a part of the second N-type well and a part of the third N-type well. The substrate, the P-type well, the active layer, the first N-type well, the second N-type well, and the polysilicon gate form a first transistor, and the substrate, the P-type well, the active layer, the third N-type well, the second N-type well, and the bit line structure form a second transistor.

[0040] In the present application, the first N-type well, the second N-type well, and the third N-type well are all set to be N-type doped, that is, a storage structure is made using N-type metal-oxide-semiconductor (NMOS) and dual transistors, thereby reducing the interference of erasing, writing, and reading, and further improving the performance of the storage structure.

[0041] Please refer to Figure 1 and Figure 2 , Figure 1 which is a schematic plan view of the dual-transistor NOR flash memory storage structure provided by the present application, Figure 2 is Figure 1 a schematic cross-sectional view of the dual-transistor NOR flash memory storage structure in

[0042] The present application provides a dual-transistor NOR flash memory storage structure 10, including a substrate 100, a P-type well 200, a first N-type well 300, a second N-type well 310, a third N-type well 320, an active layer 400, a polysilicon gate structure, and a bit line structure.

[0043] Specifically, the substrate 100 has a deep N-well. The substrate 100 is a silicon substrate, and the deep N-well is formed by N-doping a part of the substrate 100.

[0044] The P-type well 200 is disposed on the deep N-well. The first N-type well 300, the second N-type well 310, and the third N-type well 320 are spaced apart and disposed within the P-type well 200, and are spaced apart from the deep N-well. The second N-type well 310 is located between the first N-type well 300 and the third N-type well 320. The first N-type well 300 is connected to the source line (SL), and the third N-type well 320 is connected to the bit line (BL). The first N-type well 300 is an N-type source region, and the third N-type well 320 is an N-type drain region. The N-type well is formed by N-type doping of a part of the P-type well 200. The first N-type well 300, the second N-type well 310, and the third N-type well 320 are provided to control the conductivity in the P-type well 200 under the first transistor and the second transistor during operation.

[0045] The active layer 400 is disposed on the P-type well 200, the first N-type well 300, the second N-type well 310, and the third N-type well 320. The polysilicon gate structure and the bit line structure are spaced apart and disposed on the active layer 400. Among them, the polysilicon gate structure is located above a part of the first N-type well 300 and a part of the second N-type well 310, and the bit line structure is located above a part of the second N-type well 310 and a part of the third N-type well 320. The polysilicon gate structure is connected to the control gate (CG) line, and the bit line structure is connected to the word line (WL). The substrate 100, the P-type well 200, the active layer 400, the first N-type well 300, the second N-type well 310, and the polysilicon gate form the first transistor, and the substrate 100, the P-type well 200, the active layer 400, the third N-type well 320, the second N-type well 310, and the bit line structure form the second transistor. The first transistor and the second transistor constitute a storage structure.

[0046] In one embodiment, the storage structure further has a via 701 that exposes the active layer 400.

[0047] In one embodiment, the polysilicon gate structure includes a floating gate 500, and the bit line structure includes a first bit line 900. The floating gate 500 and the first bit line 900 are on the same layer and are spaced apart and disposed on the active layer 400.

[0048] In one embodiment, the polysilicon gate structure further includes a first isolation layer 600 and a control gate 700 that are sequentially stacked on the floating gate 500, and the bit line structure further includes a second isolation layer 1000 and a second bit line 1100 that are sequentially stacked on the first bit line 900. The first isolation layer 600 and the second isolation layer 1000 are on the same layer and are spaced apart, and the control gate 700 and the second bit line 1100 are on the same layer and are spaced apart. The control gate 700 is connected to the control line, and the first bit line 900 and the second bit line 1100 are connected to the bit line.

[0049] In the present application, by setting the first N-type well 300, the second N-type well 310, and the third N-type well 320 to be N-type doped, that is, using N-Metal-Oxide-Semiconductor (NMOS) and a dual-transistor to form a storage structure, the interference during erasing, writing, and reading is reduced, thereby improving the performance of the storage structure. At the same time, the storage structure can be applied in an environment of -40°C to 150°C; in addition, with this design for the storage structure, the design of its peripheral circuits can be simplified.

[0050] In one embodiment, the first isolation layer 600 and the second isolation layer 1000 both include a first oxide layer, a nitride layer, and a second oxide layer that are sequentially stacked. In the present application, the first isolation layer 600 and the second isolation layer 1000 are formed by stacking multiple layers of the first oxide layer, the nitride layer, and the second oxide layer, such that the first oxide layer can block the stored charges from returning to the substrate.

[0051] In one embodiment, the thickness of the first oxide layer is 16 - 21 angstroms. Specifically, the thickness of the first oxide layer can be 16 angstroms, 19 angstroms, 20 angstroms, or 21 angstroms, etc. By setting the thickness of the first oxide layer within this range, the first oxide can well block the stored charges from returning to the substrate, thereby improving the storage stability.

[0052] In one embodiment, the materials of the first oxide layer and the second oxide layer are the same.

[0053] In one embodiment, the materials of the first oxide layer and the second oxide layer include silicon oxide, and the material of the nitride layer includes silicon nitride.

[0054] Writing principle: The bit line structure is biased at ~Vt, and the third N-type well 320 is at a high positive voltage to generate a high lateral electric field, which induces hot electrons. The bias voltage of the control gate 700 under the high electric field attracts the hot electrons into the floating gate 500.

[0055] The following Table 1 shows various states of the write operation, erase operation, and read operation of the present application. Among them, WL represents the bit line voltage, BL represents the bit line voltage, SL represents the source line voltage, CG represents the control line voltage, Pwell represents the P-type well line voltage, and DNwell represents the deep N-well line voltage.

[0056] Table 1:

[0057] WL BL SL CG Pwell DNwell WL BL SL Sel Un sel Sel Un sel Sel Un sel Sel Un sel Sel Program ~Vtwl 0V 1uA 3V 5V 0.5V Program ~Vtwl 0V 1uA Erase Float Fl Fl Fl Fl Fl Erase Float Fl Fl Read Vcc 0V 1V 0V 0V 0V Read Vcc 0V 1V

[0058] It can be seen therefrom that by setting the first N-type well 300, the second N-type well 310, and the third N-type well 320 to be N-type doped, that is, using N-Metal-Oxide-Semiconductor (NMOS) and a dual-transistor to form a storage structure, the interference during erasing, writing, and reading can be reduced, thereby improving the performance of the storage structure.

[0059] Figure 3 It is a schematic flow chart of a method for manufacturing a dual-transistor NOR flash memory storage structure provided by the present application. The present application also provides a method for manufacturing a dual-transistor NOR flash memory storage structure 10, including:

[0060] B11. Provide a substrate having a deep N-well.

[0061] Figures 4 - 7 It is a schematic plan view flow chart of a dual-transistor NOR flash memory storage structure provided by the present application; Figures 8 - 10 is Figures 4 - 7 a schematic three-dimensional view flow chart of the dual-transistor NOR flash memory storage structure at A in. Provide a substrate 100, and perform ion implantation treatment on one side of the substrate 100 to form a deep N-well.

[0062] B12. Form a P-type well on the deep N-well.

[0063] B13. Perform ion implantation on the side of the P-type well away from the deep N-well to form a first N-type well, a second N-type well, and a third N-type well arranged at intervals, with the second N-type well located between the first N-type well and the third N-type well.

[0064] B14. Form an active layer on the P-type well, the first N-type well, the second N-type well, and the third N-type well.

[0065] B15. Form a polysilicon gate structure and a bit line structure on the active layer, with the polysilicon gate structure and the bit line structure arranged at intervals. Among them, the polysilicon gate structure is located on part of the first N-type well and part of the second N-type well, and the bit line structure is located on part of the second N-type well and part of the third N-type well. The substrate, the P-type well, the active layer, the first N-type well, the second N-type well, and the polysilicon gate form a first transistor, and the substrate, the P-type well, the active layer, the third N-type well, the second N-type well, and the bit line structure form a second transistor.

[0066] Specifically, a first polysilicon material layer 501 is disposed on the active layer 400; then, an isolation material layer 601 is formed on the first polysilicon material layer 501; then, a second polysilicon material layer is formed on the isolation material layer 601; then, the first polysilicon material layer 501, the isolation material layer 601, and the second polysilicon material layer are etched to form a via 701, so that the first polysilicon material layer forms spaced floating gates 500 and first bit lines 900, the isolation material layer forms spaced first isolation layers 600 and second isolation layers 1000, the second polysilicon material layer forms spaced control gates 700 and second bit lines 1100, and the floating gates 500, the first isolation layers 600, and the control gates 700 are stacked in sequence to form a polysilicon gate structure, and the first bit lines 900, the second isolation layers 1000, and the second bit lines 1100 are stacked in sequence to form a bit line structure.

[0067] In the present application, a deep N-well is disposed on the substrate 100, and a P-well 200 is disposed between the first N-well 300, the second N-well 310, the third N-well 320 and the deep N-well. That is, a storage structure is made of N-type Metal-Oxide-Semiconductor (NMOS) and dual transistors, which can reduce the interference of erasing, writing, and reading, and thus improve the performance of the storage structure; in addition, the control gate 700 and the second word line are formed by a single-step process, which can reduce the number of photolithography layers and process complexity, and thus reduce the production cost.

[0068] In an embodiment, forming an isolation material layer on the first polysilicon material layer includes:

[0069] A first oxide material layer, a nitride material layer, and a second oxide material layer are sequentially stacked on the first polysilicon material layer, so that the first oxide material layer forms a first oxide layer, the nitride material forms a nitride layer, and the second oxide material layer forms a second oxide layer.

[0070] In an embodiment, the materials of the first oxide layer and the second oxide layer include silicon oxide, and the material of the nitride layer includes silicon nitride.

[0071] The present application provides a dual-transistor NOR-type flash memory storage structure 10 and a method for manufacturing the same, including a substrate 100, a P-type well 200, a first N-type well 300, a second N-type well 310, a third N-type well 320, an active layer 400, a polysilicon gate structure, and a bit line structure. The substrate 100 has a deep N-well; the P-type well 200 is disposed on the deep N-well; the first N-type well 300, the second N-type well 310, and the third N-type well 320 are spaced apart and disposed within the P-type well 200, and are spaced apart from the deep N-well. The second N-type well 310 is located between the first N-type well 300 and the third N-type well 320; the active layer 400 is disposed on the P-type well 200, the first N-type well 300, the second N-type well 310, and the third N-type well 320; the polysilicon gate structure and the bit line structure are spaced apart and disposed on the active layer 400. The polysilicon gate structure is located above a part of the first N-type well 300 and a part of the second N-type well 310, and the bit line structure is located above a part of the second N-type well 310 and a part of the third N-type well. The substrate 100, the P-type well 200, the active layer 400, the first N-type well 300, the second N-type well 310, and the polysilicon gate form a first transistor, and the substrate 100, the P-type well 200, the active layer 400, the third N-type well 320, the second N-type well 310, and the bit line structure form a second transistor. By setting the first N-type well 300, the second N-type well 310, and the third N-type well 320 to be N-type doped, that is, using N-type metal-oxide-semiconductor (NMOS) and a dual-transistor to make the storage structure, the interference during erasing, writing, and reading is reduced, and thus the performance of the storage structure is improved.

[0072] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or directly or indirectly applied in other related technical fields, shall be included in the patent protection scope of the present application by the same token.

Claims

1. A dual-transistor NOR-type flash memory storage structure, characterized in that, it includes: a substrate having a deep N-well; a P-well disposed on the deep N-well; a first N-well, a second N-well, and a third N-well, which are spaced apart and disposed in the P-well, and are spaced apart from the deep N-well, and the second N-well is located between the first N-well and the third N-well; an active layer disposed on the P-well, the first N-well, the second N-well, and the third N-well; and a polysilicon gate structure and a bit line structure, which are spaced apart and disposed on the active layer, wherein the polysilicon gate structure is located on a part of the first N-well and a part of the second N-well, the bit line structure is located on a part of the second N-well and a part of the third N-well, and the substrate, the P-well, the active layer, the first N-well, the second N-well, and the polysilicon gate form a first transistor, and the substrate, the P-well, the active layer, the third N-well, the second N-well, and the bit line structure form a second transistor; the polysilicon gate structure includes a floating gate, the bit line structure includes a first bit line, and the floating gate and the first bit line are on the same layer and are spaced apart and disposed on the active layer; the polysilicon gate structure further includes a first isolation layer and a control gate that are sequentially stacked on the floating gate, and the bit line structure further includes a second isolation layer and a second bit line that are sequentially stacked on the first bit line, the first isolation layer and the second isolation layer are on the same layer and are spaced apart, and the control gate and the second bit line are on the same layer and are spaced apart.

2. The dual-transistor NOR-type flash memory storage structure according to claim 1, characterized in that, both the first isolation layer and the second isolation layer include a first oxide layer, a nitride layer, and a second oxide layer that are sequentially stacked.

3. The dual-transistor NOR-type flash memory storage structure according to claim 2, characterized in that, the materials of the first oxide layer and the second oxide layer are the same.

4. The dual-transistor NOR-type flash memory storage structure according to claim 3, characterized in that, the materials of the first oxide layer and the second oxide layer include silicon oxide, and the material of the nitride layer includes silicon nitride.

5. A method for manufacturing a dual-transistor NOR-type flash memory storage structure, characterized in that, it includes: providing a substrate having a deep N-well; forming a P-well on the deep N-well; performing ion implantation on a surface of the P-well away from the deep N-well to form a first N-well, a second N-well, and a third N-well that are spaced apart, and the second N-well is located between the first N-well and the third N-well; forming an active layer on the P-well, the first N-well, the second N-well, and the third N-well; A polysilicon gate structure and a bit line structure are formed on the active layer, and the polysilicon gate structure and the bit line structure are spaced apart. Among them, the polysilicon gate structure is located above part of the first N-type well and part of the second N-type well, and the bit line structure is located above part of the second N-type well and part of the third N-type well. The substrate, the P-type well, the active layer, the first N-type well, the second N-type well, and the polysilicon gate form a first transistor, and the substrate, the P-type well, the active layer, the third N-type well, the second N-type well, and the bit line structure form a second transistor; In the step of forming a polysilicon gate structure and a bit line structure on the active layer, where the polysilicon gate structure and the bit line structure are spaced apart, it includes: A first polysilicon material layer is provided on the active layer; An isolation material layer is formed on the first polysilicon material layer; A second polysilicon material layer is formed on the isolation material layer; The first polysilicon material layer, the isolation material layer, and the second polysilicon material layer are etched. The first polysilicon material layer forms a floating gate and a first bit line that are spaced apart, the isolation material layer forms a first isolation layer and a second isolation layer that are spaced apart, the second polysilicon material layer forms a control gate and a second bit line that are spaced apart. The floating gate, the first isolation layer, and the control gate are stacked in sequence, and the first bit line, the second isolation layer, and the second bit line are stacked in sequence.

6. The method for manufacturing a dual-transistor NOR-type flash memory storage structure according to claim 5, characterized in that, In the step of forming an isolation material layer on the first polysilicon material layer, it includes: A first oxidation material layer, a nitride material layer, and a second oxidation material layer are sequentially stacked on the first polysilicon material layer, so that the first oxidation material layer forms a first oxide layer, the nitride material forms a nitride layer, and the second oxidation material layer forms a second oxide layer.

7. The method for manufacturing a dual-transistor NOR-type flash memory storage structure according to claim 6, characterized in that, The materials of the first oxide layer and the second oxide layer include silicon oxide, and the material of the nitride layer includes silicon nitride.

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