Array substrate, display device and method for manufacturing array substrate

Abstract

The present application relates to an array substrate, a display device, and a method for manufacturing an array substrate. The array substrate has a display area and a peripheral area at least partially surrounding the display area, and includes: a substrate base plate; a first conductive layer disposed on the substrate base plate and located in the peripheral area; a second conductive layer disposed on the substrate base plate and located in the display area; a pixel definition layer disposed on the first conductive layer and the second conductive layer; a first opening disposed in the pixel definition layer and exposing a portion of a surface of the first conductive layer away from the substrate base plate; and a second opening disposed in the pixel definition layer and exposing a portion of a surface of the second conductive layer away from the substrate base plate, wherein a width of a bottom of the first opening is greater than a width of a bottom of the second opening.

Description

Technical Field

[0001] This invention relates to the field of display technology. More specifically, it relates to an array substrate, a display device, and a method for manufacturing the array substrate. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have advantages such as self-illumination, high efficiency, and vibrant colors, and have been gradually applied to large-area displays, lighting, and automotive displays. Summary of the Invention

[0003] Embodiments of the present invention provide an array substrate. The array substrate has a display area and a peripheral area at least partially surrounding the display area. The array substrate includes a substrate and further includes:

[0004] A first conductive layer is disposed on the substrate and located in the peripheral region;

[0005] A second conductive layer is disposed on the substrate and located in the display area;

[0006] A pixel definition layer is disposed on the first conductive layer and the second conductive layer;

[0007] A first opening is provided in the pixel definition layer and exposes a portion of the surface of the first conductive layer away from the substrate.

[0008] A second opening is provided in the pixel definition layer and exposes a portion of the surface of the second conductive layer away from the substrate, wherein the width of the bottom of the first opening is greater than the width of the bottom of the second opening;

[0009] A third conductive layer is located above the pixel definition layer in the display area, wherein the third conductive layer extends into the first opening and contacts one side of the substrate of the first conductive layer;

[0010] A light-emitting functional layer is disposed between the second conductive layer and the third conductive layer, wherein the light-emitting functional layer is in contact with the side of the first conductive layer away from the substrate.

[0011] In some embodiments, the contact area between the light-emitting functional layer and the side of the first conductive layer away from the substrate is smaller than the contact area between the third conductive layer and the side of the first conductive layer away from the substrate.

[0012] In some embodiments, the first opening and the second opening are formed by a single patterning process.

[0013] In some embodiments, the angle between the first opening and the substrate is the same as the angle between the second opening and the substrate.

[0014] In some embodiments, the angle between the first opening and the substrate is between about 80° and 90°.

[0015] In some embodiments, the width of the first opening is greater than the height of the first opening.

[0016] In some embodiments, the first conductive layer and the second conductive layer are disposed in the same layer.

[0017] In some embodiments, the second conductive layer includes a plurality of second sub-conductive portions spaced apart from each other, and the array substrate further includes:

[0018] A fourth conductive layer disposed on the substrate has a first sub-part located in the peripheral region and at least one second sub-part located in the display region spaced apart from the first sub-part.

[0019] A passivation layer disposed on the fourth conductive layer;

[0020] A third opening and a fourth opening are provided in the passivation layer, wherein the third opening is located in the peripheral area and the fourth opening is located in the display area;

[0021] Conductive portions are disposed in the third opening and the fourth opening, wherein the first conductive layer is electrically connected to the first sub-part through the third opening, and the third conductive layer is electrically connected to the second sub-part through the fourth opening.

[0022] In some embodiments, the orthographic projection of the first conductive layer on the substrate at least partially overlaps with the orthographic projection of the first sub-part on the substrate, the overlapping area being a first overlapping area, wherein the orthographic projection of the first via on the substrate is located in the first overlapping area; and

[0023] The orthographic projection of the second conductive layer on the substrate and the orthographic projection of the second sub-part on the substrate at least partially overlap, and the overlapping area is the second overlapping area, wherein the orthographic projection of the second via on the substrate is located in the second overlapping area.

[0024] In some embodiments, the side of the light-emitting function near the peripheral region is connected to the surface away from the substrate by a smooth curved surface.

[0025] In some embodiments, the first opening surrounds the display area.

[0026] Embodiments of the present invention also provide a display device. The display device includes an array substrate as described above.

[0027] Embodiments of the present invention also provide a method for manufacturing an array substrate having a display area and a peripheral area at least partially surrounding the display area, the method comprising providing a substrate, the method further comprising:

[0028] A first conductive layer located in the peripheral region is formed on the substrate.

[0029] A second conductive layer located in the display area is formed on the substrate.

[0030] A pixel definition layer is formed on the first conductive layer and the second conductive layer;

[0031] A first opening is formed in the pixel definition layer to expose a portion of the surface of the first conductive layer away from the substrate.

[0032] A second opening is formed in the pixel definition layer to expose a portion of the surface of the second conductive layer away from the substrate, wherein the width of the bottom of the first opening is greater than the width of the bottom of the second opening.

[0033] In some embodiments, the method further includes forming a third conductive layer in the display area on the pixel definition layer, wherein the third conductive layer extends into the first opening and contacts the side of the first conductive layer away from the substrate.

[0034] A light-emitting functional layer is formed between the second conductive layer and the third conductive layer, wherein the light-emitting functional layer is in contact with the side of the first conductive layer away from the substrate.

[0035] In some embodiments, forming the third conductive layer includes depositing the third conductive layer by vapor deposition using a mask having an opening corresponding to the first opening.

[0036] In some embodiments, the first opening and the second opening are formed by a single patterning process.

[0037] In some embodiments, the angle between the first opening and the substrate is substantially the same as the angle between the second opening and the substrate.

[0038] In some embodiments, the angle between the first opening and the substrate is between about 80° and 90°.

[0039] In some embodiments, forming the first conductive layer, the second conductive layer, the pixel definition layer, the first opening, and the second opening includes:

[0040] A first conductive material layer is formed on the substrate.

[0041] The first conductive material layer is patterned to form the first conductive layer and the second conductive layer;

[0042] A pixel definition material layer is formed on the first conductive layer and the second conductive layer;

[0043] The pixel-defined material layer is patterned to form the first opening and the second opening.

[0044] In some embodiments, the method further includes:

[0045] Before the first conductive material layer is formed

[0046] A fourth conductive material layer is formed on the substrate.

[0047] The fourth conductive material layer is patterned to form a fourth conductive layer, wherein the fourth conductive layer has a first sub-part located in the peripheral area and at least one second sub-part located in the display area spaced apart from the first sub-part;

[0048] A passivation layer is formed on the fourth conductive layer;

[0049] The passivation layer is patterned to form a third opening and a fourth opening, the third opening exposing a portion of the surface of the first sub-part away from the substrate, and the fourth opening exposing a portion of the surface of the second sub-part away from the substrate.

[0050] Conductive portions are formed in the third and fourth openings, wherein the first conductive layer is connected to the first sub-part through the third opening, and the second conductive layer is electrically connected to the second sub-part through the fourth opening; and

[0051] After the first opening and the second opening are formed

[0052] A light-emitting functional layer is formed on the pixel definition layer;

[0053] The third conductive portion is formed on the light-emitting functional layer. Attached Figure Description

[0054] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of the present invention and are not intended to limit the present invention, wherein:

[0055] Figure 1This is a schematic diagram of an array substrate according to an embodiment of the present invention;

[0056] Figure 2 This is a schematic diagram of an array substrate according to an embodiment of the present invention;

[0057] Figure 3 This is a schematic diagram of an array substrate according to an embodiment of the present invention;

[0058] Figure 4 This is a schematic diagram of an array substrate according to an embodiment of the present invention;

[0059] Figure 5 This is a schematic diagram of a display device according to an embodiment of the present invention;

[0060] Figure 6 This is a schematic flowchart of a method for manufacturing an array substrate having a display area and at least a peripheral area surrounding the display area according to an embodiment of the present invention;

[0061] Figure 7 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0062] Figure 8 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0063] Figure 9 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0064] Figure 10 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0065] Figure 11 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0066] Figure 12 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0067] Figure 13 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0068] Figure 14 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0069] Figure 15 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0070] Figure 16This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0071] Figure 17 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0072] Figure 18 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0073] Figure 19 This is a schematic diagram of an array substrate according to an embodiment of the present invention. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are also within the scope of protection of the present invention.

[0075] When describing the elements and embodiments of the present invention, the articles “a,” “an,” “the,” and “described” are intended to indicate the presence of one or more elements. The terms “comprising,” “including,” “containing,” and “having” are intended to be inclusive and indicate that additional elements besides those listed may be present.

[0076] For the purposes described below, as indicated by their orientation in the accompanying drawings, the terms “upper,” “lower,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall apply to the invention. The terms “overlapping,” “on top of,” “positioned on,” or “positioned on top of” mean that a first element, such as a first structure, exists on a second element, such as a second structure, wherein an intermediate element, such as an interface structure, may exist between the first and second elements. The term “contact” means connecting a first element, such as a first structure, and a second element, such as a second structure, where there may or may not be other elements at the interface between the two elements.

[0077] Figure 1 This is a schematic diagram of an array substrate according to an embodiment of the present invention. Figure 1As shown, the array substrate according to an embodiment of the present invention may have a display area AA and a peripheral area PA at least partially surrounding the display area. The array substrate may include: a substrate 1, a first conductive layer 2 disposed on the substrate 1 and located in the peripheral area PA, a second conductive layer 3 disposed on the substrate 1 and located in the display area AA, a pixel definition layer 4 disposed on the first conductive layer 2 and the second conductive layer 3, a first opening V1 disposed in the pixel definition layer 4 and exposing a portion of the surface of the first conductive layer 2 away from the substrate 1, and a second opening V2 disposed in the pixel definition layer 4 and exposing a portion of the surface of the second conductive layer 3 away from the substrate 1. Wherein, in a direction parallel to the surface of the substrate 1, the width w1 of the bottom of the first opening V1 is greater than the width w2 of the bottom of the second opening V2.

[0078] The array substrate according to embodiments of the present invention can eliminate the dummy area of ​​conventional array substrates, achieving a narrower bezel design, which can improve product performance while simplifying the process and reducing process costs.

[0079] Figure 2 This is a schematic diagram of an array substrate according to an embodiment of the present invention. Figure 2 As shown, the array substrate according to an embodiment of the present invention may include a third conductive layer 5. The third conductive layer 5 is located above the pixel definition layer 4 in the display area AA, and the third conductive layer 5 further extends into the first opening V1 and contacts the side of the first conductive layer 2 away from the substrate. The third conductive layer 5 can serve as the cathode of a pixel unit of the array substrate, and the second conductive layer 3 can serve as the anode of a pixel unit of the array substrate. The first conductive layer 2 can be used to conduct electrical signals to the third conductive layer 5.

[0080] Embodiments of the present invention can provide a solution that facilitates the bonding of the first conductive layer 2 and the third conductive layer 5, simplifies the manufacturing process, and reduces manufacturing costs.

[0081] In some embodiments, the first opening V1 and the second opening V2 are formed in a single patterning process. This approach eliminates the need for two patterning steps, as in some examples, thereby improving product performance while simplifying the process and reducing costs.

[0082] like Figures 1-2As shown, the angle α1 between the first opening V1 and the substrate 1 can be the same as the angle α2 between the second opening V2 and the substrate. In some embodiments, the angle between the first opening V1 and the substrate 1 can be between approximately 80° and 90°. For example, the angle can be 82°, 85°, 87°, or 90°. Such an angle can prevent crosstalk between pixel units and also ensure the overlap between the first conductive layer 2 and the third conductive layer 5. At the same time, it eliminates the need for two patterning processes, reducing process steps, lowering costs, and improving product yield.

[0083] In some embodiments, the width of the first opening in the direction parallel to the surface of the substrate is greater than the height of the first opening in the direction perpendicular to the surface of the substrate. This also better achieves the technical effects of preventing crosstalk between pixel units, ensuring the overlap between the first conductive layer 2 and the third conductive layer 5, reducing process steps, lowering costs, and improving product yield.

[0084] In some embodiments, the first conductive layer 2 and the second conductive layer 3 may be disposed in the same layer. Here, "disposed in the same layer" means that they can be formed from the same film layer. For example, the first conductive layer and the second conductive layer may include the same material. For example, the first conductive layer and the second conductive layer may include at least one of the following materials: magnesium, zinc, aluminum, or mixtures thereof.

[0085] Figure 3 This is a schematic diagram of an array substrate according to an embodiment of the present invention. Figure 3 As shown, the second conductive layer 3 includes a plurality of second sub-conductive portions 31 spaced apart from each other by a planarization layer 6, and the first conductive layer can also be separated from the second conductive layer 3 by the planarization layer 6.

[0086] like Figure 3 As shown, the array substrate according to an embodiment of the present invention may further include: a fourth conductive layer 7 disposed on a substrate 1, the fourth conductive layer 7 having a first sub-partition 71 located in a peripheral region PA and at least one second sub-partition 72 spaced apart from the first sub-partition 71 and located in a display region AA; a passivation layer 8 disposed on the fourth conductive layer 7; a first via V3 and a second via V4 disposed in the passivation layer 8, the first via being located in the peripheral region and the second via being located in the display region; and conductive portions 9 disposed in the first via V3 and the second via V4, wherein the first conductive layer 2 is electrically connected to the first sub-partition 71 through the first via V3, and the third conductive layer is electrically connected to the second sub-partition 72 through the second via V4.

[0087] The orthographic projection of the first conductive layer 2 on the substrate at least partially overlaps with the orthographic projection of the first sub-part 71 on the substrate, and the overlapping area is the first overlapping area; the orthographic projection of the first via on the substrate is located in the first overlapping area; the orthographic projection of the second conductive layer 3 on the substrate at least partially overlaps with the orthographic projection of the second sub-part 72 on the substrate, and the overlapping area is the second overlapping area; the orthographic projection of the second via on the substrate is located in the second overlapping area.

[0088] The array substrate according to an embodiment of the present invention may further include: a light-emitting functional layer 10 disposed between the second conductive layer 3 and the third conductive layer 5.

[0089] The light-emitting functional layer 10 may include layers for realizing the function of light emission. For example, the light-emitting functional layer may include a hole injection layer (HIL), a hole transport layer (HTL) on the hole injection layer, a light-emitting layer (EML) on the hole transport layer, an electron transport layer (ETL) on the light-emitting layer, and an electron injection layer (EIL) on the electron transport layer.

[0090] The light-emitting functional layer 10 covers the second opening V2 to form multiple light-emitting units. Simultaneously, the light-emitting functional layer (e.g., an organic light-emitting layer) contacts and covers a portion of the structure of the first conductive layer 2. This design allows for a narrower peripheral area and eliminates dummy areas. During manufacturing, the opening of the mask corresponding to the light-emitting functional layer can be designed on the third conductive layer (e.g., a cathode). When depositing the light-emitting functional layer, such as an organic light-emitting layer, the light-emitting functional layer can be directly deposited and overlapped inside the third conductive layer, such as a cathode. Thus, the third conductive layer (e.g., a cathode) can smoothly overlap onto the cathode ring by utilizing the height difference of the light-emitting functional layer, thereby avoiding a single etching of the cathode ring region.

[0091] Figure 19 This is a schematic diagram of an array substrate according to an embodiment of the present invention. Figure 19 As shown, the side of the light-emitting functional layer 5 near the peripheral area PA is connected to the surface away from the substrate by a smooth curved surface.

[0092] It needs to be explained that, Figure 1-3 Taking an array substrate with a first opening as an example, the number of first openings is not limited to one. The first opening may surround the display area.

[0093] Figure 4 This is a schematic diagram of an array substrate according to an embodiment of the present invention. Figure 4 As shown, the array substrate may include at least two first openings. The number of second openings can also be set according to actual needs.

[0094] The shapes of the first opening, the second opening, the first via, and the second via are not limited to the specific shapes shown in the figures. In some embodiments, they can be polygons, for example, triangles, quadrilaterals, or pentagons. In other embodiments, they can be circles or ellipses.

[0095] Figure 5 This is a schematic diagram of a display device according to an embodiment of the present invention. Figure 5 As shown, the display panel 100 according to an embodiment of this disclosure may include an array substrate 200. The array substrate 200 may be... Figures 1-4 The array substrate shown is shown.

[0096] Figure 6 This is a schematic flowchart illustrating a method for manufacturing an array substrate having a display area and at least a peripheral area surrounding the display area according to an embodiment of the present invention. Figure 6 As shown, a method for manufacturing an array substrate according to an embodiment of the present invention may include:

[0097] S1. A first conductive layer located in the peripheral region is formed on the substrate.

[0098] S3. Form a second conductive layer located in the display area on the substrate.

[0099] S5. A pixel definition layer is formed on the first conductive layer and the second conductive layer;

[0100] S7. A first opening is formed in the pixel definition layer to expose a portion of the surface of the first conductive layer away from the substrate.

[0101] S9. A second opening is formed in the pixel definition layer to expose a portion of the surface of the second conductive layer away from the substrate, wherein the width of the bottom of the first opening may be greater than the width of the bottom of the second opening;

[0102] S11. A third conductive layer is formed on top of the pixel definition layer in the display area, wherein the third conductive layer extends into the first opening and contacts the side of the first conductive layer away from the substrate.

[0103] S13. A light-emitting functional layer is formed between the second conductive layer and the third conductive layer, wherein the light-emitting functional layer is in contact with the side of the first conductive layer away from the substrate.

[0104] The method for manufacturing an array substrate according to an embodiment of the present invention can provide a higher performance array substrate, which can eliminate the dummy area of ​​conventional array substrates, achieve a narrower bezel design, and at the same time simplify the process flow and reduce the process cost.

[0105] In some embodiments, the method for manufacturing an array substrate may further include forming a third conductive layer located in the display area on top of the pixel definition layer, wherein the third conductive layer extends into the first opening and contacts the first conductive layer. Such embodiments can provide a solution that facilitates the overlapping of the first and third conductive layers, simplifies the manufacturing process, and reduces manufacturing costs.

[0106] In some embodiments, forming a third conductive layer includes depositing the third conductive layer by vapor deposition using a mask having a first opening corresponding to a first opening.

[0107] In some embodiments, the first and second openings are formed in a single patterning process. This approach eliminates the need for two patterning steps, as in some other examples, thereby improving product performance while simplifying the process and reducing costs.

[0108] In some embodiments, the angle between the first opening and the substrate can be the same as the angle between the second opening and the substrate. In some embodiments, the angle between the first opening and the substrate can be between 80° and 90°. In some embodiments, the angle between the first opening V1 and the substrate 1 can be between approximately 80° and 90°. For example, the angle can be 82°, 85°, 87°, or 90°. Such an angle can prevent crosstalk between pixel units and also ensure the overlap between the first conductive layer 2 and the third conductive layer 5. At the same time, it eliminates the need for two patterning processes, reducing process steps, lowering costs, and improving product yield.

[0109] In some embodiments, the width of the first opening in the direction parallel to the surface of the substrate is greater than the height of the first opening in the direction perpendicular to the surface of the substrate. This also better achieves the technical effects of preventing crosstalk between pixel units, ensuring the overlap between the first conductive layer 2 and the third conductive layer 5, reducing process steps, lowering costs, and improving product yield.

[0110] In some embodiments, the first conductive layer 2 and the second conductive layer 2 may be disposed in the same layer. Here, "disposed in the same layer" means that they can be formed from the same film layer. For example, the first conductive layer and the second conductive layer may include the same material. For example, the first conductive layer and the second conductive layer may include at least one of the following materials: magnesium, zinc, aluminum, or mixtures thereof.

[0111] In some embodiments, forming the first conductive layer, the second conductive layer, the pixel definition layer, the first opening, and the second opening includes:

[0112] S21, A first conductive material layer formed on a substrate;

[0113] S23. Pattern the first conductive material layer to form a first conductive layer and a second conductive layer;

[0114] S25. A pixel definition material layer is formed on the first conductive layer and the second conductive layer;

[0115] S27. Layout the pixel-defined material layer to form the first opening and the second opening.

[0116] In some embodiments, the method for manufacturing an array substrate may further include:

[0117] Before the first conductive material layer is formed

[0118] S31. A fourth conductive material layer is formed on the substrate.

[0119] S33. Patterning the fourth conductive material layer to form a fourth conductive layer, wherein the fourth conductive layer has a first sub-part located in a peripheral region and at least one second sub-part located in a display region spaced apart from the first sub-part.

[0120] S35. A passivation layer is formed on the fourth conductive layer;

[0121] S37. Pattern the passivation layer to form the first via and the second via;

[0122] S39. A conductive portion is formed in the first via and the second via, wherein the first conductive layer is connected to the first sub-part through the first via, and the second conductive layer is electrically connected to the second sub-part through the second via; and

[0123] After the first opening and the second opening are formed

[0124] S41. Form a light-emitting functional layer on the pixel definition layer;

[0125] S43. The third conductive part is formed on the light-emitting functional layer.

[0126] The light-emitting functional layer may include layers for realizing the function of light emission. For example, the light-emitting functional layer may include a hole injection layer (HIL), a hole transport layer (HTL) on the hole injection layer, a light-emitting layer (EML) on the hole transport layer, an electron transport layer (ETL) on the light-emitting layer, and an electron injection layer (EIL) on the electron transport layer.

[0127] Figures 7-18 This is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present invention. Figures 7-18 As shown, a method for manufacturing an array substrate according to an embodiment of the present invention may include:

[0128] like Figure 7As shown, a fourth conductive material layer 7' is formed on the substrate 1. For example, a metal layer can be deposited on the substrate to form the fourth conductive material layer.

[0129] In some embodiments, the substrate may include a semiconductor material. The term "semiconductor material" refers to a material having a conductivity value between a conductor (e.g., copper) and an insulator (e.g., glass). Semiconductor materials can be present as elemental materials or composite materials. Examples of semiconductor materials that can be used as substrates include Si, SiGe, SiGeC, SiC, Ge alloys, III / V compound semiconductors, or II / VI compound semiconductors. In other embodiments of the invention, the substrate may include a combination of semiconductor and dielectric materials; for example, the substrate may be a stack of silicon dioxide and silicon layers from bottom to top. In still other embodiments, the substrate may include ceramic materials, elemental metals, alloys of elemental materials, or any other material or combination of materials.

[0130] like Figure 8 As shown, the fourth conductive material layer 7' is patterned to form the fourth conductive layer 7, wherein the fourth conductive layer 7 has a first sub-part 71 located in the peripheral region PA and at least one second sub-part 72 located in the display region AA spaced apart from the first sub-part 71.

[0131] like Figure 9 As shown, a passivation layer 8 is formed (e.g., deposited) on the fourth conductive layer 7.

[0132] like Figure 10 As shown, the passivation layer is patterned (e.g., etched) to form a first via V3 and a second via V4. The first via exposes a portion of the surface of the first sub-part 71 away from the substrate 1, and the second via exposes a portion of the surface of the second sub-part 72 away from the substrate 1.

[0133] like Figure 11 As shown, conductive portions 9 are formed in the first via V3 and the second via V4. A subsequently formed first conductive layer can be connected to the first sub-part 71 via the first via V3, and a subsequently formed second conductive layer can be electrically connected to the second sub-part 72 via the second via V4. The conductive portions 9 may include a metallic material. For example, the conductive portions may include tungsten.

[0134] like Figure 12 As shown, a first conductive material layer 2' is formed (e.g., deposited) on the passivation layer 8.

[0135] like Figure 13 As shown, the first conductive material layer 2' is patterned (e.g., etched) to form the first conductive layer 2 and the second conductive layer 3.

[0136] like Figure 14 As shown, a planarization layer 6 is formed on the passivation layer. The planarization layer 6 can fill the removed portion of the first conductive material layer 2' to separate the first conductive layer and the second conductive layer, and to separate multiple second sub-conductive portions of the second conductive layer. The surface of the planarization layer 6 away from the substrate 1 can be flush with the surfaces of the first conductive layer 2 and the second conductive layer 3 away from the substrate 1 to provide a flat surface.

[0137] like Figure 15 As shown, a pixel definition material layer 4' is formed on the first conductive layer 2, the second conductive layer 3, and the planarization layer 6.

[0138] like Figure 16 As shown, the pixel definition material layer is patterned to form a first opening V1, a second opening V2, and the patterned pixel definition layer 4.

[0139] like Figure 17 As shown, a light-emitting functional layer 10 is formed on the pixel definition layer. For example, this light-emitting functional layer can be formed by vapor deposition.

[0140] like Figure 18 As shown, a third conductive portion 5 is formed on the light-emitting functional layer 10. For example, this third conductive layer can be formed by vapor deposition using a mask having an opening corresponding to the first opening V1. In some embodiments, the material of the third conductive layer may include a transparent conductive oxide. For example, the material of the third conductive layer may include indium zinc oxide (IZO).

[0141] The array substrate may include at least two first openings. The number of second openings may also be set according to actual needs. The shapes of the first openings, second openings, first vias, and second vias are not limited to the specific shapes shown in the figures. In some embodiments, they may be polygonal, for example, triangular, quadrilateral, or pentagonal. In other embodiments, they may also be circular or elliptical.

[0142] A particular embodiment has been described, which is shown by way of example only and is not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the invention.

Claims

1. An array substrate having a display area and a peripheral area at least partially surrounding the display area, the array substrate comprising a substrate, characterized in that, The array substrate further includes: A first conductive layer is disposed on the substrate and located in the peripheral region; A second conductive layer is disposed on the substrate and located in the display area; A pixel definition layer is disposed on the first conductive layer and the second conductive layer; A first opening is provided in the pixel definition layer and exposes a portion of the surface of the first conductive layer away from the substrate. A second opening is disposed in the pixel definition layer and exposes a portion of the surface of the second conductive layer away from the substrate, wherein the width of the bottom of the first opening is greater than the width of the bottom of the second opening. A third conductive layer is located above the pixel definition layer in the display area, wherein the third conductive layer extends into the first opening and contacts one side of the substrate of the first conductive layer; A light-emitting functional layer is disposed between the second conductive layer and the third conductive layer, wherein the light-emitting functional layer is in contact with the side of the first conductive layer away from the substrate.

2. The array substrate according to claim 1, wherein, The contact area between the light-emitting functional layer and the first conductive layer on the side away from the substrate is smaller than the contact area between the third conductive layer and the first conductive layer on the side away from the substrate.

3. The array substrate according to claim 1, wherein, The first opening and the second opening are formed through a single patterning process.

4. The array substrate according to claim 1, wherein, The angle between the first opening and the substrate is the same as the angle between the second opening and the substrate.

5. The array substrate according to claim 4, wherein, The angle between the first opening and the substrate is between 80° and 90°.

6. The array substrate according to claim 1, wherein, The width of the first opening is greater than the height of the first opening.

7. The array substrate according to claim 1, wherein, The first conductive layer and the second conductive layer are disposed in the same layer.

8. The array substrate according to claim 2, wherein, The second conductive layer includes a plurality of second sub-conductive portions spaced apart from each other, and the array substrate further includes: A fourth conductive layer disposed on the substrate has a first sub-part located in the peripheral region and at least one second sub-part located in the display region spaced apart from the first sub-part. A passivation layer disposed on the fourth conductive layer; A first via and a second via are disposed in the passivation layer, wherein the first via is located in the peripheral area and the second via is located in the display area; Conductive portions are disposed in the first via and the second via, wherein the first conductive layer is electrically connected to the first sub-part through the first via, and the second conductive layer is electrically connected to the second sub-part through the fourth via.

9. The array substrate according to claim 8, wherein, The orthographic projection of the first conductive layer on the substrate at least partially overlaps with the orthographic projection of the first sub-part on the substrate, and the overlapping area is the first overlapping area, wherein the orthographic projection of the first via on the substrate is located in the first overlapping area.

10. The array substrate according to claim 8, wherein, The orthographic projection of the second conductive layer on the substrate and the orthographic projection of the second sub-part on the substrate at least partially overlap, and the overlapping area is the second overlapping area, wherein the orthographic projection of the second via on the substrate is located in the second overlapping area.

11. The array substrate according to claim 1, wherein, The side of the light-emitting functional layer near the peripheral area is connected to the surface away from the substrate by a smooth curved surface.

12. The array substrate according to claim 1, wherein, The first opening surrounds the display area.

13. A display device comprising an array substrate according to any one of claims 1-12.

14. A method for manufacturing an array substrate, the array substrate having a display area and a peripheral area at least partially surrounding the display area, the method comprising providing a substrate, characterized in that, The method further includes: A first conductive layer located in the peripheral region is formed on the substrate. A second conductive layer located in the display area is formed on the substrate. A pixel definition layer is formed on the first conductive layer and the second conductive layer; A first opening is formed in the pixel definition layer to expose a portion of the surface of the first conductive layer away from the substrate. A second opening is formed in the pixel definition layer to expose a portion of the surface of the second conductive layer away from the substrate, wherein the width of the bottom of the first opening is greater than the width of the bottom of the second opening; A third conductive layer is formed on the pixel definition layer in the display area, wherein the third conductive layer extends into the first opening and contacts the side of the first conductive layer away from the substrate. A light-emitting functional layer is formed between the second conductive layer and the third conductive layer, wherein the light-emitting functional layer is in contact with the side of the first conductive layer away from the substrate.

15. The method according to claim 14, wherein, Forming the first conductive layer, the second conductive layer, the pixel definition layer, the first opening, and the second opening includes: A first conductive material layer is formed on the substrate. The first conductive material layer is patterned to form the first conductive layer and the second conductive layer; A pixel definition material layer is formed on the first conductive layer and the second conductive layer; The pixel-defined material layer is patterned to form the first opening and the second opening. The method further includes: Before the first conductive material layer is formed A fourth conductive material layer is formed on the substrate. The fourth conductive material layer is patterned to form a fourth conductive layer, wherein the fourth conductive layer has a first sub-part located in the peripheral area and at least one second sub-part located in the display area spaced apart from the first sub-part; A passivation layer is formed on the fourth conductive layer; The passivation layer is patterned to form a third opening and a fourth opening, the third opening exposing a portion of the surface of the first sub-part away from the substrate, and the fourth opening exposing a portion of the surface of the second sub-part away from the substrate. Conductive portions are formed in the third and fourth openings, wherein the first conductive layer is connected to the first sub-part through the third opening, and the second conductive layer is electrically connected to the second sub-part through the fourth opening; and After the first opening and the second opening are formed A light-emitting functional layer is formed on the pixel definition layer; The third conductive portion is formed on the light-emitting functional layer.

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