A method of monitoring overlay mark process quality

Abstract

The application provides a method for monitoring the quality of overlay mark process, providing a design mark; according to the design mark, the design mark is made on a wafer to obtain an overlay mark; the overlay mark is scanned, and a scanned signal is received to generate a photo of the overlay mark; the CD of the contour of the overlay mark is extracted based on the photo; the CD of the contour of the design mark is compared with the CD of the contour of the overlay mark to measure the difference between the two; or the CDs of different positions of the contour of the overlay mark are compared with each other to measure the difference of the CDs of different positions. The application extracts the edge CD from the picture scanned by an electron microscope, and stacks the contour CD of the design mark or the contour CD of the mark at different positions. If there is a difference, the abnormality can be found in time. If the actual mark deviates, the deviation will be reflected on the overlay measurement result, the process and the measurement result are preliminarily judged in advance, the wrong overlay feedback is avoided, and the guidance for process improvement is provided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for monitoring the quality of overlay marking processes. Background Technology

[0002] Currently, overlay (OVL) measurement monitoring methods include IBO (Image Based Overlay) and DBO (Diffraction Based Overlay), both of which are optical measurements. When the OVL mark is in good condition, the OVL results can be monitored normally. However, if the previous OVL mark is deformed or damaged due to the manufacturing process, the measurement accuracy will be affected, easily causing measurement anomalies and impacting the judgment of the true OVL results. Traditional measurement methods use optical methods, which can only capture the macroscopic morphology of the mark.

[0003] Figure 1 Displayed as a macroscopic image of overprinted markings in the prior art. Figure 2 The image shows a microscopic representation of the overlay markings. One set of markings is divided into inner and outer parts, namely the current layer marking and the previous layer marking. For SADP or SAQP techniques, each bar structure is composed of multiple sidewall spacer or fin structures. However, at the microscopic level, spacers or fins can exhibit various issues such as bending, which can affect the macroscopic measurement of the overlay markings.

[0004] Therefore, a new method is needed to solve the above problems. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for monitoring the quality of overlay marking process, which solves the problem in the prior art that the overlay marking is damaged and therefore the overlay accuracy cannot be accurately measured.

[0006] To achieve the above and other related objectives, the present invention provides a method for monitoring the quality of overlay marking processes, comprising at least:

[0007] Step 1: Provide design markings; Based on the design markings, fabricate the design markings on the wafer to obtain overlay markings;

[0008] Step 2: Scan the overprinted mark and receive the scanned signal to generate a photograph of the overprinted mark;

[0009] Step 3: Extract the CD of the outline of the overlay mark based on the photograph;

[0010] Step 4: Compare the CD of the design mark outline with the CD of the overprint mark outline to measure the difference between them; or compare the CDs of different positions of the overprint mark outline to measure the difference between the CDs of different positions.

[0011] Preferably, the design markings in step one are formed by arranging multiple strip-shaped structures at equal intervals in sequence.

[0012] Preferably, the design markings in step one are formed by arranging multiple strip structures at equal intervals in sequence, and the strip structures are used to form sidewalls.

[0013] Preferably, the overlay mark obtained in step one is formed by arranging multiple strip-shaped structures corresponding to the design mark at equal intervals.

[0014] Preferably, the overlay mark obtained in step one is formed by arranging multiple strip structures at equal intervals corresponding to the design mark, and the strip structures are used to form the sidewall.

[0015] Preferably, in step two, the overlay mark is scanned using an electron microscope.

[0016] Preferably, in step three, the CD of each strip structure in the overlay mark is extracted based on the photograph.

[0017] Preferably, in step three, the overlay mark is extracted based on the photograph to find the CD of each strip structure, and each strip structure is used to form a sidewall.

[0018] Preferably, in step one, the design mark is fabricated on the wafer using SADP to obtain the overlay mark.

[0019] Preferably, in step one, the design mark is fabricated on the wafer using SADP to obtain the overlay mark.

[0020] As described above, the method for monitoring the quality of the overlay marking process of the present invention has the following beneficial effects: The present invention uses images scanned by an electron microscope to extract the edge CD (cutoff zone), and overlays it with the designed marking or the outline CD of markings at different positions. If there are differences, anomalies can be detected in a timely manner. If the actual marking is offset, it will be reflected in the overlay measurement results, allowing for a preliminary judgment on the process and measurement results in advance, avoiding erroneous overlay feedback, and providing guidance for process improvement. Attached Figure Description

[0021] Figure 1 Displayed as a macroscopic image of overlay markings in the prior art;

[0022] Figure 2 Displayed as a microscopic image of overlay markings;

[0023] Figure 3 The image shown is one of the overlay marks of the present invention;

[0024] Figure 4 The diagram shown is a structural schematic of the design markings in this invention.

[0025] Figure 5 An image showing another overlay mark of the present invention;

[0026] Figure 6 This is a schematic diagram showing the design mark and overlay mark of the present invention overlapping;

[0027] Figure 7 The diagram shows a flowchart of the method for monitoring the quality of the overlay marking process according to the present invention. Detailed Implementation

[0028] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0030] This invention provides a method for monitoring the quality of overlay marking processes, such as... Figure 7 As shown, Figure 7 The flowchart shown is a method for monitoring the quality of overlay marking processes according to the present invention. The method includes at least the following steps:

[0031] Step 1: Provide design markings; based on the design markings, fabricate the design markings on the wafer to obtain overlay markings; the design markings in this invention refer to markings used for overlaying on the wafer.

[0032] In a further step of this invention, in step one of this embodiment, the design mark is fabricated on the wafer using SADP to obtain the overlay mark. SADP stands for Self-Aligned Dual Patterning.

[0033] In a further step of this invention, in step one of this embodiment, the design mark is fabricated on the wafer using SAQP to obtain the overlay mark. SAQP stands for Self-Aligned Quadruple Patterning.

[0034] In a further step of this invention, the design markings in step one of this embodiment are formed by arranging multiple strip-shaped structures at equal intervals in sequence. For example... Figure 4 As shown, Figure 4 The diagram shows a structural schematic of the design markings in this invention. In this embodiment, the multiple strip-shaped structures are arranged sequentially at equal intervals. In actual manufacturing processes, these design markings can correspond to the fabrication process of a Fin structure (Fin in a fin transistor). That is, during the formation of the Fin structure, the multiple strip-shaped design markings are formed simultaneously; i.e., the multiple strip-shaped structures are Fin structures.

[0035] In a further embodiment of the present invention, the design markings in step one are formed by a plurality of strip-shaped structures arranged sequentially at equal intervals, and the strip-shaped structures can also be used to form sidewalls. That is to say, in addition to forming overlay markings along with the Fin structure, the design markings can also be used to form sidewalls (spacers) on the wafer using the SAQP or SADP methods.

[0036] Furthermore, in this embodiment, the overlay mark obtained in step one is formed by a plurality of strip-shaped structures corresponding to the design mark arranged sequentially at equal intervals. That is, the design mark is a layout pattern. The design mark is used to transfer the pattern onto the wafer to obtain the overlay mark. Therefore, when the design mark is a plurality of equally spaced strip-shaped structures, the overlay mark also forms a corresponding structure with the design mark. However, due to process variations during manufacturing, the strip-shaped structure CD of the overlay mark may differ from the strip-shaped structure CD of the design mark.

[0037] In further embodiments of the present invention, the overlay mark obtained in step one is formed by multiple strip structures arranged at equal intervals corresponding to the design mark. The strip structures can also be used to form sidewalls. That is, the design mark is a layout pattern. The design mark is transferred to the wafer to obtain the overlay mark. Therefore, when the design mark is multiple strip structures arranged at equal intervals, the overlay mark also forms a corresponding structure with the design mark. However, due to the influence of the manufacturing process, the strip structure CD of the overlay mark may differ from the strip structure CD of the design mark. In addition to forming overlay marks along with the Fin structure, in other embodiments, the design mark can also be used to form sidewalls (spacers) on the wafer using the SAQP or SADP method.

[0038] Step 2: Scan the overprinted mark and receive the scanned signal to generate a photograph of the overprinted mark;

[0039] In a further step of this embodiment, the overlay mark is scanned using an electron microscope in step two.

[0040] like Figure 3 and Figure 5 As shown, Figure 3 and Figure 5 The images show two different overprinted marks of the present invention.

[0041] Step 3: Extract the CD of the outline of the overlay mark based on the photograph;

[0042] Furthermore, in step three of this embodiment, the CD (critical dimension) of each strip structure in the overlay mark is extracted based on the photograph.

[0043] In a further embodiment of the present invention, in step three, the overlay marks are extracted based on the photograph to find the CD of each strip structure, each strip structure being used to form a sidewall.

[0044] Step 4: Overlay and compare the CD of the design mark outline with the CD of the overprinted mark outline to measure the difference between them; or compare the CDs of different positions of the overprinted mark outline to measure the difference between the CDs at different positions. Figure 6 As shown, Figure 6 This diagram illustrates the overlapping of the design mark and the overlay mark of the present invention. In step four, when the design mark and the overlay mark are overlapped, the CD of their corresponding strip structures differs, thus allowing monitoring of the quality of the overlay mark in the actual process. Alternatively, the contours of the strip structures at different positions in the obtained overlay mark can be stacked together for comparison to identify differences in CD.

[0045] In summary, this invention uses images captured by an electron microscope to extract edge CDs, which are then overlaid with the designed markings or outline CDs marked at different positions. Any discrepancies can be detected promptly. If the actual markings are offset, this will be reflected in the overlay measurement results, allowing for preliminary judgment of the process and measurement results in advance, avoiding erroneous overlay feedback, and providing guidance for process improvement. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of monitoring overlay mark process quality, characterized by, At least comprising: Step one, providing design marks; according to the design marks, the design marks are made on a wafer to obtain overlay marks; Step two, scanning the overlay marks and receiving the scanned signals to generate photos of the overlay marks; Step three, extracting the CD of the contour of the overlay marks based on the photos; Step four, comparing the CD of the contour of the design marks with the CD of the contour of the overlay marks to measure the difference between them; or comparing the CD of different positions of the contour of the overlay marks with each other to measure the difference of the CD of different positions.

2. The method of claim 1, wherein: The design marks in step one are a plurality of strip structures arranged in sequence at equal intervals.

3. The method of claim 2, wherein: The design marks in step one are a plurality of strip structures arranged in sequence at equal intervals, and the strip structures are used to form side walls.

4. The method of claim 2, wherein: The overlay marks obtained in step one are a plurality of strip structures corresponding to the design marks arranged in sequence at equal intervals.

5. The method of claim 3, wherein: The overlay marks obtained in step one are a plurality of strip structures corresponding to the design marks arranged at equal intervals, and the strip structures are used to form side walls.

6. The method of claim 1, wherein: In step two, the overlay marks are scanned by an electron microscope.

7. The method of claim 4, wherein: In step three, the CD of each strip structure in the overlay marks is extracted based on the photos.

8. The method of claim 5, wherein: In step three, the CD of each strip structure in the overlay marks is extracted based on the photos, and each strip structure is used to form a side wall.

9. The method of claim 1, wherein: In step one, the design marks are made on the wafer by SADP to obtain the overlay marks.

10. The method of claim 1, wherein: In step one, the design marks are made on the wafer by SAQP to obtain the overlay marks.

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