FPGA-based multi-echo and low-resource consumption time-to-digital conversion method

Abstract

The application discloses a time-to-digital conversion method based on FPGA and low resource consumption, comprising: obtaining a start signal and a stop signal; obtaining a single echo signal based on the start signal and the stop signal; frequency doubling and phase shifting a system clock on a FPGA board to obtain a plurality of sub-clock signals; obtaining a plurality of synchronization signals based on the single echo signal and the plurality of sub-clock signals; obtaining a first sub-clock number based on the plurality of sub-clock signals and the plurality of synchronization signals; performing coarse timing driving by using any one of the plurality of sub-clock signals to obtain a coarse time value of each echo; obtaining a fine time calibration value based on the first sub-clock number, any one of the sub-clock signals performing the coarse timing driving and the remaining sub-clock signals; and obtaining timing data of each echo by using the coarse time value and the fine time calibration value of each echo.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of high-precision time measurement, and particularly relates to a multi-echo and low-resource-consumption time-to-digital conversion method based on FPGA. BACKGROUND

[0002] A time-to-digital converter (TDC) is a high-precision time interval measurement circuit, which can realize the output of a continuous time quantity to a digital quantity, and has been widely applied to scientific experiments and engineering tests, especially in the field of laser radar, and usually needs to obtain multi-echo information of laser pulses to assist in filtering and processing of data, so as to better reveal the characteristics of the measured target. This requirement has led to rapid development of multi-echo time-to-digital converters.

[0003] From the implementation platform of the TDC, it can be divided into two categories: one is a TDC designed by application-specific integrated circuit (ASIC) technology; and the second is a TDC designed by field programmable gate array (FPGA) technology. The TDC realized by the application-specific integrated circuit has the advantages of high measurement accuracy, better reliability and linearity, but the design cost is expensive, the development cycle is long, and it is not conducive to the upgrading and maintenance of the system. The TDC realized by the field programmable gate array can solve the above problems, and has the characteristics of low cost, short development cycle and easier verification. In recent years, with the popularization of FPGA technology and the improvement of design technology, the TDC technology based on FPGA has developed unprecedentedly.

[0004] From the implementation architecture of the TDC, the tapped delay line and the phased clock are currently widely used architectures. The tapped delay line has high resolution, but its integral nonlinearity will deteriorate with the increase of the length of the delay chain, especially in the measurement of multi-echo signals, which is easy to cause serious deviation of the results due to the accumulation of errors, leading to chaotic echo time data, and the measurement range is usually small. The phased clock architecture uses a group of counters working under clocks with the same frequency and equal phase difference to realize the subdivision measurement of time through accumulation, has good linearity, and is easy to realize a high measurement range, and is very suitable for the characteristics of multi-echo signals, but the traditional phased clock architecture needs to use a large number of counters, resulting in high hardware resource usage. Therefore, how to improve this architecture and design a time-to-digital conversion method that takes into account multi-echo measurement and low resource consumption has very important research significance. SUMMARY

[0005] The disclosed FPGA-based multi-echo and low-resource consumption time-to-digital conversion method aims to provide a method for measuring the time interval of multi-echo signals and satisfying low-resource consumption time-to-digital conversion by improving the implementation of a traditional phased clock architecture using FPGA as a deployment device. The method can be used in the fields of laser radar and three-dimensional imaging.

[0006] To achieve the above-mentioned purpose, the present application provides a FPGA-based multi-echo and low-resource consumption time-to-digital conversion method, comprising the following steps:

[0007] Obtaining a start signal and a stop signal;

[0008] Based on the start signal and the stop signal, a single-echo signal is obtained;

[0009] The system clock on the FPGA board is multiplied and phase-shifted to obtain a plurality of sub-clock signals;

[0010] Based on the single-echo signal and the plurality of sub-clock signals, a plurality of synchronization signals are obtained;

[0011] Based on the plurality of sub-clock signals and the plurality of synchronization signals, a first sub-clock number is obtained;

[0012] Any one of the plurality of sub-clock signals is used for coarse timing driving to obtain the coarse time value of each echo;

[0013] Based on the first sub-clock number, any one of the sub-clock signals for coarse timing driving and the remaining sub-clock signals, a fine time calibration value is obtained;

[0014] The coarse time value and the fine time calibration value of each echo are used to obtain the timing data of each echo.

[0015] Optionally, obtaining the single-echo signal comprises:

[0016] The start signal and the stop signal are integrated through an XOR gate to obtain the single-echo signal.

[0017] Optionally, based on the single-echo signal and the plurality of sub-clock signals, the plurality of synchronization signals are obtained, comprising:

[0018] The single-echo signal is synchronized at the rising edge and the falling edge of the plurality of sub-clock signals to obtain the plurality of synchronization signals.

[0019] Optionally, the characteristics of the plurality of synchronization signals comprise:

[0020] The rising edge of each of the plurality of synchronization signals coincides with the rising edge or the falling edge of each of the corresponding plurality of sub-clock signals;

[0021] The falling edge of each of the plurality of synchronization signals coincides with the falling edge of the single echo signal.

[0022] Optionally, the method for obtaining the first sub-clock number comprises:

[0023] The state of each of the plurality of synchronization signals is captured by a flip-flop driven by the plurality of sub-clock signals, and the code of the state of the plurality of synchronization signals is obtained.

[0024] The first sub-clock number is obtained based on the code of the state of the plurality of synchronization signals.

[0025] Optionally, the method for obtaining the first sub-clock number based on the code of the state of the plurality of synchronization signals comprises:

[0026] The number of high and low levels in the code of the state of each of the plurality of synchronization signals is determined based on the code of the state of the plurality of synchronization signals, and the arrival order of the plurality of synchronization signals is obtained.

[0027] The first sub-clock number is obtained based on the arrival order of the plurality of synchronization signals.

[0028] Optionally, the method for obtaining the fine time calibration value based on the first sub-clock number, the arbitrary sub-clock signal for coarse timing driving and the remaining sub-clock signals comprises:

[0029] The phase relationship between the arbitrary sub-clock signal for coarse timing driving and the remaining sub-clock signals is obtained.

[0030] The fine time calibration coefficient of the rising edge and the falling edge of the plurality of sub-clock signals is obtained based on the phase relationship and the first sub-clock number.

[0031] The fine time calibration value of the start signal pulse and the fine time calibration value of the stop signal pulse are obtained based on the fine time calibration coefficient and the system resolution.

[0032] Optionally, the fine time calibration value comprises:

[0033] q = λ x δ

[0034] Wherein, q is the fine time calibration value, λ is the fine time calibration coefficient of the rising edge clock or the falling edge clock of each sub-clock signal, and δ is the system resolution.

[0035] Optionally, the timing data of each echo specifically comprises:

[0036] t n = p n + q0-q n

[0037] Wherein, t n is the timing data of the nth echo, p n is the coarse time value of the current nth echo, q0 is the fine time calibration value for the start signal pulse, q n is the fine time calibration value for the nth stop signal pulse.

[0038] The technical effect of the present application: the multi-echo and low resource consumption time-to-digital conversion method based on FPGA disclosed by the present application realizes a time-to-digital conversion method which can not only measure the time interval of multi-echo signals, but also has low resource consumption, through the improvement and innovation of the traditional phased clock architecture. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings, which form a part of this application, are intended to provide further understanding of the application and are incorporated herein in their entirety, and the illustrative embodiments of the present application and their description serve to explain the present application and do not constitute improper limitations on the present application. In the drawings:

[0040] Figure 1 is the timing diagram of the multi-echo processing module of the embodiment of the present application;

[0041] Figure 2 is the structure diagram of the signal synchronization processing sub-module of the embodiment of the present application;

[0042] Figure 3 is the timing diagram of the clock edge extraction module of the embodiment of the present application;

[0043] Figure 4 is the timing diagram of the coarse counting module of the embodiment of the present application;

[0044] Figure 5 is the timing diagram of the calibration module of the embodiment of the present application;

[0045] Figure 6 is the flowchart of the multi-echo and low resource consumption time-to-digital conversion method based on FPGA of the embodiment of the present application. DETAILED DESCRIPTION

[0046] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0047] It is noted that the steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0048] As shown in the flowchart of the drawings, the steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here. Figure 6 The embodiment provides a multi-echo and low resource consumption time-to-digital conversion method based on FPGA, which includes the following steps:

[0049] Step one, input the Start signal and the Stop signal to the multi-echo processing module, and output the integrated single-echo signal and the flag signal to the clock edge extraction module and the coarse counting module.

[0050] The Start signal and the Stop signal are integrated into a single signal TIME HOLD by using an XOR gate, which is composed of multiple pulse edges, and the first pulse is the Start signal, which is recorded as T0, and then a plurality of Stop echo signals are sequentially generated, and the corresponding time is recorded as T1, T2…T n The multi-echo time interval timing result can be represented by formula (1), t1, t2…t n The time interval corresponding to the first, second, and nth echo is represented by the flag signal WAVE_NUM, which is incremented by one after each echo signal arrives, indicating the number of the current echo, and the result of the coarse counting module is output synchronously, indicating which time interval t k (k = 1, 2…n).

[0051]

[0052] The multi-echo processing module has the following functions: it integrates the Start signal and the Stop signal into a single signal for easy operation of the subsequent module, and also maximizes the difference in time interval calculation error caused by the delay difference of two signals in the internal wiring of the FPGA chip. Another function of this module is to count the echo signals and generate the WAVE_NUM signal to indicate the correspondence between the output results of the subsequent coarse counting module and each echo.

[0053] Step two, the system clock on the FPGA board is multiplied and phase-shifted to obtain a plurality of sub-clock signals with the same frequency and equal phase difference, which are used as reference clocks for the clock edge extraction module.

[0054] The system clock is multiplied and phase-shifted by PLL or MMCM to generate m paths of the same frequency and equal phase difference sub-clock as reference signals. The relationship between phase shift angle θ and clock number m is shown in equation (2). The phase angles of the sub-clocks are 0, θ, 2θ, …, (m-1)θ in turn. Considering that the sub-clocks obtained by even times of phase shift will inevitably have the situation that the rising edge of one clock coincides with the falling edge of another clock, m is selected as an odd number in the system. The timing resolution δ of the final system can be expressed by equation (3), where f is the system clock frequency and l is the frequency multiplication coefficient.

[0055]

[0056]

[0057] Step three, the clock edge extraction module judges the arrival order of the m paths of equal phase difference phase-shifted clocks after the arrival of the single-path echo signal in turn and sends the clock number of the first arriving clock to the calibration module;

[0058] The rising and falling edges of the m paths of clocks obtained in step three are synchronized with the single-path integrated signal TIME HOLD to obtain 2m synchronization signals TIME HOLD1, TIME HOLD1n, TIME HOLD2, TIME HOLD2n, …, TIME HOLDm and TIME HOLDmn. The characteristics of these signals are that the rising edge coincides with the rising or falling edge of the corresponding reference sub-clock and the falling edge coincides with the falling edge of the TIME HOLD signal. Then, the rising and falling edges of the m paths of clocks are used to capture these synchronization signals to obtain 2m encodings in number and bit number. The arrival order of the signals after synchronization can be obtained by judging the number of high and low levels in each encoding. Since the rising edge of the synchronization signal coincides with the edge of the reference sub-clock, the reference clock number corresponding to the first arriving synchronization signal is the clock number required by the calibration module.

[0059] Step four, the coarse counting module completes the counting operation under the driving of the sub-clock signal with a known phase obtained in step two;

[0060] Any one of the sub-clocks obtained in step two is used as the driving clock of the counter. The first rising edge of the synchronization signal TIME HOLDm (or TIME HOLDmn) under the clock is used as the flag of the start of counting, and the subsequent rising edge is used as the flag of the time stamp. When the number of rising edges equal to the set number of echoes is accumulated, the counter is automatically cleared, and the next time interval measurement is prepared. In this timing mode, the time stamp data punched each time is the coarse time value of each echo, which can be expressed by equation (4), where p np n represents the coarse time value of the nth echo, f is the frequency of the sub-clock, N n is the count value of the counter corresponding to the current echo.

[0061]

[0062] Step five, the output of the coarse counting module and the comparison result in step three are simultaneously input into the calibration module for processing to obtain the final timing data of each echo.

[0063] First, according to the phase relationship between the driving clock of the coarse counter and other clocks, the respective fine time calibration coefficients λ are determined for different sub-clock numbers output in step three, and the fine time calibration value q can be represented by formula (5), wherein δ is the system resolution calculated in step two.

[0064] q = λ × δ (5)

[0065] The final measurement value of each echo is composed of three parts, as shown in formula (6). Among them, p n is the coarse time value of the nth echo, q0 is the fine time calibration value for the Start pulse, and q n is the fine time calibration value for the nth Stop pulse.

[0066] t n = p n + q0 - q n (6)

[0067] The role of the calibration module is to determine the unique calibration coefficient λ for each clock according to the phase relationship between the sub-clocks, and then determine the fine time calibration value, and finally correct the measurement result in combination with the time value output by the coarse counting module to obtain the final echo measurement result.

[0068] In the traditional phased clock architecture, a counter needs to be connected under each sub-clock, resulting in large resource consumption. The time-to-digital conversion method in the present application only needs one counter to realize the same resolution by cooperating with the calibration module, which greatly saves the counter resources. This feature makes the present application method very suitable for some large-scale, large-range time interval measurement application occasions. The more the number of bits of the counter used for time counting, the more prominent the resource saving advantage of the method.

[0069] For example Figure 1The shown is a multi-echo processing module timing diagram, the number of echoes is 4 in this example, Start and Stop indicate the start signal and stop signal, T0, T1...T4 indicate the time of the start and stop signal, a single-echo signal TIME HOLD can be obtained by XOR operation of two input signals, WAVE_NUM indicates the number of multiple echoes, which is sequentially increased by one at the arrival of each stop echo and is cleared after the arrival of the next start signal, and the result is output synchronously with the result of the coarse counting module, which is used to indicate to which time interval t the current result belongs k (k = 1, 2, 3, 4). The multi-echo time interval timing result can be represented by formula (7), where t1, t2...t4 represent the first, second, and fourth echoes, respectively.

[0070]

[0071] As Figure 2 The shown is a signal synchronization processing submodule structure diagram in the clock edge extraction module, in this example, the PLL phase-locked loop is used to frequency multiply the on-board 50M system clock to 200M, three sub-clocks are generated by phase shift, according to formula (2), the phase angles of each clock are 0°, 60°, and 120°, respectively, and are sequentially recorded as CLK1, CLK2, and CLK3 (for convenience, CLK1 represents the rising edge working clock, CLK1n represents the falling edge working clock, and the other clocks are the same), the single-integrated signal TIME HOLD is synchronized under CLK1, CLK1n, CLK2, CLK2n, CLK3, and CLK3n, respectively, to obtain six synchronized signals TIME HOLD1, TIME HOLD1n, TIME HOLD2, TIME HOLD2n, TIME HOLD3, and TIME HOLD3n. Figure 3 The shown is a clock edge extraction module timing diagram, the rising edge of the synchronized signal coincides with the rising edge or falling edge of the corresponding reference sub-clock, and the falling edge coincides with the falling edge of the TIME HOLD signal, six groups of flip-flops working at the sub-clock edge are used to capture the states of the six synchronized signals, CAP1, CAP1n, CAP2, CAP2n, CAP3, and CAP3n are the capture values, the working clock corresponding to the flip-flop with an accumulated sum of "1" is the next clock edge after the arrival of the TIME HOLD signal. In this example, the accumulated sums that meet the requirements are CAP2n, CAP3, and CAP2 in turn, so the previous clock edge is the first clock edge after the arrival of TIME HOLD, which are CLK1n, CLK2, and CLK1, respectively.

[0072] As Figure 4The timing diagram of the coarse counting module is shown, and any one of the sub-clocks obtained in step two is used as the driving clock of the counter. This example uses the rising clock CLK1 as the driving clock of the counter and the echo measurement number is 2. CNT_EN is the working flag of the counter, and the counter continuously completes the self-addition operation during the high level period. Each subsequent rising edge is used as the flag for setting the "time stamp", and the WAVE_CNT coarse counting values N1 and N2 are obtained. At the same time, the WAVE_NUM flag signal obtained in step one is output synchronously with the current counting result, which is used to indicate that N1 is the counting value of the first echo and N2 is the counting value of the second echo. When the number of rising edges accumulated is equal to the number of set echoes, the counter is automatically cleared, and the next time interval measurement is prepared. The coarse counting result can be represented by formula (4), where p n represents the coarse time value of the nth echo, f is the frequency of the sub-clock, and N n is the counting value of the counter corresponding to the current echo.

[0073] Figure 5 The timing diagram of the calibration module is shown, CLK1, CLK2 and CLK3 are three phase-shifted sub-clocks, and the rising clock CLK1 is still used as the driving clock of the coarse counter. The time interval between the two rising edges of the TIME HOLD signal can be composed of three parts, where p n is the coarse counting result of the current nth echo, q0 is the fine time calibration value for the Start pulse, and q n is the fine time calibration value for the echo Stop pulse, which are composed of λ times of the system resolution δ. By comparing the phase relationship between the counting clock CLK1 (rising clock) and the remaining five groups of clock edges, the specific method is as follows: from Figure 5 it can be seen that the previous clock edge adjacent to CLK1 is CLK3n (falling clock), and the time interval δ, so the calibration coefficient λ = 1; the previous two clock edges adjacent to CLK1 are CLK2n (falling clock), and the time interval 2δ, so the calibration coefficient λ = 2, and the other clock edges are the same. The fine time calibration coefficient λ can be represented by formula (8) (the selection condition is the first clock number). Since the first clock numbers after the TIME HOLD signal arrives are CLK3 and CLK2 in this example, the fine time calibration value can be represented by formula (9).

[0074]

[0075]

[0076] The measurement values of the final echoes can be represented by formula (6).

[0077] The time-to-digital conversion method in the application can realize measurement of multi-echo time data, and through improvement of a traditional phased clock architecture, a time calibration module is introduced to compress multiple groups of counters into a single one, while ensuring timing performance, greatly reducing the hardware resource usage, and having good use efficiency.

[0078] The above merely describes the preferred embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for multi-echo and low resource consumption time-to-digital conversion based on FPGA, characterized in that, The method comprises the following steps: acquiring a start signal and a stop signal; based on the start signal and the stop signal, acquiring a single-channel echo signal, comprising: integrating the start signal and the stop signal through an XOR gate to obtain the single-channel echo signal; frequency doubling and phase shifting a system clock on a FPGA board to acquire a plurality of sub-clock signals; based on the single-channel echo signal and the plurality of sub-clock signals, acquiring a plurality of synchronization signals, comprising: synchronizing the single-channel echo signal with the rising edge and the falling edge of the plurality of sub-clock signals to acquire the plurality of synchronization signals; based on the plurality of sub-clock signals and the plurality of synchronization signals, acquiring a first sub-clock number, comprising: using a flip-flop driven by the plurality of sub-clock signals to capture the state of each of the plurality of synchronization signals to obtain the encoding of the state of the plurality of synchronization signals; based on the encoding of the state of the plurality of synchronization signals, acquiring the first sub-clock number; using any one of the plurality of sub-clock signals to drive coarse timing to obtain the coarse time value of each echo; based on the first sub-clock number, any one of the plurality of sub-clock signals for driving coarse timing and the remaining sub-clock signals, acquiring a fine time calibration value, comprising: acquiring the phase relationship between the any one of the plurality of sub-clock signals for driving coarse timing and the remaining sub-clock signals; based on the phase relationship and the first sub-clock number, acquiring the fine time calibration coefficient of the rising edge and the falling edge of the plurality of sub-clock signals; based on the fine time calibration coefficient and the system resolution, acquiring the fine time calibration value of the start signal pulse and the fine time calibration value of the stop signal pulse; using the coarse time value and the fine time calibration value of each echo, acquiring the timing data of each echo.

2. The FPGA-based multi-echo and low-resource consumption time-to-digital conversion method of claim 1, wherein, The features of the plurality of synchronization signals comprise: the rising edge of each of the plurality of synchronization signals coincides with the rising edge or the falling edge of the corresponding one of the plurality of sub-clock signals; the falling edge of each of the plurality of synchronization signals coincides with the falling edge of the single-channel echo signal.

3. The FPGA-based multi-echo and low-resource consumption time-to-digital conversion method of claim 1, wherein, The method for acquiring the first sub-clock number based on the encoding of the state of the plurality of synchronization signals comprises: based on the encoding of the state of the plurality of synchronization signals, judging the number of high and low levels in the encoding of the state of each of the plurality of synchronization signals to obtain the arrival order of the plurality of synchronization signals; based on the arrival order of the plurality of synchronization signals, acquiring the first sub-clock number.

4. The FPGA-based multi-echo and low-resource consumption time-to-digital conversion method of claim 1, wherein, The fine time calibration value comprises: ； wherein is a fine time calibration value, is a fine time calibration coefficient of the rising edge clock or the falling edge clock of the respective sub-clock signal, is a system resolution.

5. The FPGA-based multi-echo and low-resource consumption time-to-digital conversion method of claim 4, wherein, the timing data of each echo comprises: ； wherein, is the timing data for the n-th echo, is the coarse time value for the current n-th echo, is the fine time calibration value for the start signal pulse, is the fine time calibration value for the n-th stop signal pulse.

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