Debugging method and system for RISCV system memory
By configuring the interrupt request function and signal conversion of the RISCV kernel, memory read and write operations are enabled without affecting kernel threads. This solves the problem of kernel interruption during memory debugging in existing technologies, saves processor chip area, and simplifies the development process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAMEN XINSIWANG INTEGRATED CIRCUIT TECH CO LTD
- Filing Date
- 2023-03-28
- Publication Date
- 2026-05-29
AI Technical Summary
Existing memory debugging methods for RISC-CV processors require the use of interrupt mechanisms, which leads to interruptions of kernel threads and inconvenience in host computer memory operations, affecting the normal operation of the processor.
By configuring the interrupt request function of the RISCV kernel, the debug module can perform memory read and write operations by using the conversion and time-sharing control of the host computer signals without triggering the exception mechanism, thus avoiding conflicts with kernel read and write operations.
It enables memory read and write operations without affecting kernel threads, saving processor chip area and simplifying host computer application development.
Smart Images
Figure CN116340065B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of processor debugging technology, and specifically to a method and system for debugging memory in a RISC-CV system. Background Technology
[0002] Microprocessor debugging is primarily used to find and reduce the number of errors in the microprocessor software code, enabling it to function as intended.
[0003] Existing RISC-V processors all enter debug mode via an exception (interrupt), terminating the original thread. During this process, the context must be saved, and the context must be restored after exiting debug mode. This is an "intrusive" and destructive debugging process. The host computer's debug program needs to read and write memory, and it also needs to be in a stopped state for the processor (core).
[0004] Therefore, the applicant intends to propose a method and system for debugging RISCV system memory, so as to enable the debugging module to read and write memory without using the interrupt function of the RISCV kernel, and without affecting the kernel's ongoing threads. Summary of the Invention
[0005] The primary objective of this invention is to provide a method for debugging RISCV system memory, thereby enabling the debugging module to read and write memory during the gaps when the RISCV kernel is neither reading nor writing.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] Methods for debugging RISC-CV system memory include:
[0008] Configure the interrupt request function of the RISCV kernel so that entering and exiting debug actions do not trigger the exception mechanism of the RISCV processor;
[0009] Connect the host computer to the RISCV system and enter debug mode;
[0010] The single-cycle valid signal triggered by the host computer executing the debugging action will be converted into a long-term valid signal;
[0011] When the long-term valid signal is valid, it is determined whether the RISCV core is being read or written. If so, the read / write signal of the debugging module is determined to be invalid, and the host computer system is notified that it is busy. If not, the read / write signal of the debugging module is determined to be valid, and the debugging module performs read / write operations on the memory.
[0012] After completing memory read / write and receiving the exit debugging signal from the host computer, the debugging module executes the exit debugging action and invalidates the long-term valid signal.
[0013] Furthermore, the single-cycle valid signal that enables the upper computer to execute the debugging action is used as the asynchronous trigger input signal of the D flip-flop, and the output of the D flip-flop is converted into a long-term valid signal; when the debugging module completes memory read and write and receives the upper computer's exit debugging signal to execute the exit debugging action, the upper computer's exit debugging signal resets the D flip-flop.
[0014] Furthermore, when the read / write signal of the debugging module is invalid, the status flag bit of the interaction register is set to notify the host computer system that it is busy.
[0015] Another object of the present invention is to provide a debugging system for RISC-CV system memory, which utilizes the gaps in the RISC-CV kernel where it neither reads nor writes to enable the debugging module to read and write to memory, comprising:
[0016] Memory;
[0017] The RISCV core, connected to the memory, has its interrupt request function configured so that entering and exiting debug actions do not trigger the exception mechanism of the RISCV processor.
[0018] The debugging module is connected to both the memory and the RISC-CV core. The debugging module converts the single-cycle valid signal enabling the host computer's "Enter Debug" action into a long-term valid signal, and invalidates this long-term valid signal when the host computer executes the "Exit Debug" action. The debugging module time-divisionally controls its read / write operations on the memory with the RISC-CV core. When the long-term valid signal is valid, it determines whether the RISC-CV core is performing read / write operations. If so, the debugging module's read / write signal is invalid, and the host computer is notified that the system is busy. If not, the debugging module's read / write signal is valid, and the debugging module performs read / write operations on the memory.
[0019] The communication interface is connected to the debugging module and is used to establish a connection with the host computer.
[0020] Furthermore, the communication interface is connected to the debugging module through an interactive register. The interactive register has a status flag bit. When the read / write signal of the debugging module is invalid, the status flag bit is set to notify the host computer system that it is busy.
[0021] Furthermore, the debugging module includes a kernel-enabled memory circuit, a debugging module-enabled memory circuit, and a status judgment circuit;
[0022] The kernel-enabled memory circuit includes a first OR gate and a first AND gate. The two inputs of the first OR gate are respectively connected to the read and write signals of the RISCV kernel. The two inputs of the first AND gate are respectively connected to the output of the first OR gate and the RISCV kernel address and memory address matching signal. The output is connected to the kernel's memory enable signal.
[0023] The debug module enable memory circuit includes a first NOR gate and a second AND gate. The two inputs of the first NOR gate are respectively connected to the RISCV core to obtain read and write signals. The three inputs of the second AND gate are respectively connected to the output of the first NOR gate, the debug module address and memory address matching signal, and the long-time valid signal. The output is connected to the debug module's memory enable signal.
[0024] The state determination circuit includes a third AND gate and a second OR gate. The two inputs of the second OR gate are connected to the debugging module to obtain read and write signals. The two inputs of the third AND gate are respectively connected to the outputs of the first OR gate and the second OR gate. The output is connected to the interactive register to output the flag position signal.
[0025] Furthermore, the debugging module enable memory circuit also includes a D flip-flop. The data input terminal of the D flip-flop is connected to the power supply, the clock input terminal is connected to the trigger enable signal for the host computer to enter debugging, the output terminal is connected to the input terminal of the second AND gate, and the reset terminal is connected to the reset signal when the host computer exits debugging.
[0026] Furthermore, the memory includes a memory circuit and a memory control circuit;
[0027] The memory control circuit includes a third OR gate, a fourth OR gate, a first selector, a second selector, a first buffer, and a second buffer;
[0028] The two input terminals of the third OR gate are respectively connected to the output terminals of the first AND gate and the second AND gate, and the output terminal is connected to the enable terminal of the memory circuit.
[0029] The two inputs of the fourth OR gate are respectively connected to the write signals of the RISCV kernel and the debug module, and the output is connected to the write terminal of the memory circuit.
[0030] The control terminal of the first selector is connected to the output terminal of the first OR gate, the output terminal is connected to the address bus of the memory circuit, and the two input terminals are respectively connected to the address buses of the debugging module and the RISCV core.
[0031] The output of the second selector is connected to the input data bus of the memory circuit, the two inputs are respectively connected to the output data buses of the debug module and the RISCV core, and the control terminal is connected to the write signal terminal of the debug module.
[0032] The input terminal of the first buffer is connected to the output data bus of the memory circuit, the control terminal is connected to the read signal of the debugging module, and the output terminal is connected to the input data bus of the debugging module.
[0033] The input terminal of the second buffer is connected to the output data bus of the memory circuit, the control terminal is connected to the read signal of the RISCV core, and the output terminal is connected to the input data bus of the RISCV core.
[0034] By adopting the above technical solution, the present invention has the following advantages compared with the prior art:
[0035] This invention transforms the host computer's debugging enable signal to ensure its long-term effectiveness. Simultaneously, it implements time-sharing control over memory reads and writes by the RISCV kernel and the debugging module, preventing overlapping of their effective states at any given time. This effectively utilizes the gaps when the RISCV kernel is neither reading nor writing, enabling uninterrupted memory debugging by the debugging module without affecting ongoing kernel threads. Compared to traditional systems that use processor interrupt mechanisms for debugging, this invention saves processor chip area (eliminating the need for debugging-related interrupt control, enable, and status registers) and simplifies host computer application development. Attached Figure Description
[0036] Figure 1 This is a schematic diagram of the debugging method for the RISCV system memory of the present invention;
[0037] Figure 2 This is a schematic diagram of the debugging system for the RISCCV system memory of the present invention;
[0038] Figure 3 This is a schematic diagram of the kernel-enabled memory circuit of the present invention;
[0039] Figure 4 This is a schematic diagram of the memory circuit enabling the debugging module of the present invention;
[0040] Figure 5 This is a schematic diagram of the state determination circuit of the present invention;
[0041] Figure 6 This is a schematic diagram of the memory control circuit of the present invention.
[0042] Explanation of reference numerals in the attached figures:
[0043] Memory 100; memory circuit 110, memory control circuit 120, third OR gate 121, fourth OR gate 122, first selector 123, second selector 124, first buffer 125, second buffer 126.
[0044] RISC-CV core 200;
[0045] Debugging module 300: kernel enable memory circuit 310, first OR gate 311, first AND gate 312; debugging module enable memory circuit 320, first NOR gate 321, second AND gate 322, D flip-flop 323; status judgment circuit 330, third AND gate 331, second OR gate 332;
[0046] Interactive register 400;
[0047] Communication interface 500. Detailed Implementation
[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Furthermore, it should be noted that:
[0049] The terms “upper,” “lower,” “left,” “right,” “vertical,” “horizontal,” “inner,” and “outer” are based on the orientation or positional relationship shown in the accompanying drawings and are used merely for the convenience of describing the present invention and simplifying the description. They are not intended to indicate or imply that the device or element of the present invention must have a specific orientation and therefore should not be construed as a limitation of the present invention.
[0050] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.
[0051] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0052] Example 1
[0053] Please refer to Figure 1As shown, this invention discloses a method for debugging the memory of a RISC-CV system, which includes:
[0054] Configure the interrupt request function of the RISCV kernel so that the "enter debug" and "exit debug" actions do not trigger the exception mechanism of the RISCV processor;
[0055] Connect the host computer to the RISCV system and enter debug mode;
[0056] The single-cycle valid signal Halt_DBG, enabled by the host computer executing the "enter debugging" action, is converted into the long-term valid signal Req_DBG.
[0057] When the Req_DBG long-term valid signal is valid, it is determined whether the RISC-CV core is reading or writing (i.e., RD_Core and WR_Core are valid). If so, the read / write signals RD_DBG and WR_DBG of the debug module are determined to be invalid, the status flag bit of the interaction register is set, and the host computer is notified that the system is busy. If not, the read / write signals RD_DBG and WR_DBG of the debug module are determined to be valid, and the debug module performs read / write operations on the memory.
[0058] After the debugging module completes the read and write operations on the memory, it executes the "exit debugging" action and disables the long-term valid Req_DBG signal, without affecting kernel operation.
[0059] When the Req_DBG long-term valid signal is valid, the RISCV kernel and debug module implement memory read and write in a time-division circuit, as detailed in the relevant description of Embodiment 2, which will not be repeated here.
[0060] The conversion of the single-cycle valid signal Halt_DBG triggered by the host computer's "enter debugging" action into the long-term valid signal Req_DBG is achieved through a D flip-flop. Specifically, the single-cycle valid signal Halt_DBG triggered by the host computer's "enter debugging" action is used as the asynchronous trigger clock input signal of the D flip-flop, and the output of the D flip-flop is converted into a long-term valid signal. When the debugging module completes memory read / write and receives the host computer's exit debugging signal, it executes the exit debugging action and outputs a reset signal to reset the D flip-flop. The relevant circuit is described in the relevant description of Embodiment 2 and will not be repeated here.
[0061] Example 2
[0062] Another object of the present invention is to provide a debugging system for RISCV system memory, so as to realize the method described in Embodiment 1, that is, to realize the debugging module's reading and writing of memory by utilizing the gaps in the RISCV kernel where neither reading nor writing is required.
[0063] Please refer to Figure 2As shown, it includes memory 100, RISC-V core 200, debug module 300, interactive register 400, and communication interface 500. Memory 100, RISC-V core 200, and debug module 300 are connected in pairs. Communication interface 500 is connected to debug module 300 through interactive register 400. Communication interface 500 is used to connect to a host computer for debugging.
[0064] The host computer software uses RISCV-specific GDB and OpenOCD, and the hardware interface uses a JTAG interface. The on-chip system's communication interface 500 and interactive register 400 adopt a general design conforming to "RISC-VExternal DebugSupport" V0.13. This application mainly improves three parts: the on-chip debug module 300, the read / write control of memory 100, and the RISCV kernel 200. The read / write of memory 100 is controlled jointly by the RISCV kernel 200 and the debug module 300 in a time-sharing manner, and the RISCV kernel 200 process does not stop. The debug module 300 reads and writes to memory 100 during the gaps when the RISCV kernel 200 is not reading or writing.
[0065] Specifically, the interrupt request function of RISCV Core 200 is configured so that the "enter debug" and "exit debug" actions do not trigger the exception mechanism of the RISCV processor. That is, for RISCV Core 200, the mode in which the RISCV system requires an interrupt to enter debug state has been changed, and the function of triggering an interrupt by the "enter debug" signal Halt_DBG and the function of returning an interrupt by the "exit debug" signal DBG_Resume have been canceled.
[0066] The debugging module 300 converts the single-cycle valid signal Halt_DBG triggered by the host computer's "Enter Debug" action into a long-term valid signal, and invalidates the long-term valid signal when the host computer executes the "Exit Debug" action. In addition, the debugging module 300 time-divisions its read and write operations with the RISCV core 200 to memory 100. When the long-term valid signal is valid, it determines whether the RISCV core 200 is reading or writing. If so, the read / write signal of the debugging module 300 is invalid, the status flag bit of the interaction register 400 is set, and the host computer is notified that "the system is busy" and will try again later. If not, the read / write signal of the debugging module 300 is valid, and the debugging module 300 reads and writes to memory 100.
[0067] Specifically, please refer to Figures 3-5 As shown, the debug module 300 implements time-sharing control of its read and write operations to memory 100 with the RISCV kernel 200 through the kernel enable memory circuit 310, the debug module enable memory circuit 320, and the status judgment circuit 330.
[0068] Please refer to the following: Figure 3As shown, the kernel-enabled memory circuit 310 includes a first OR gate 311 and a first AND gate 312. The two inputs of the first OR gate 311 are connected to the read / write signals RD_Core and WR_Core of the RISCV core 200, respectively. The two inputs of the first AND gate 312 are connected to the output of the first OR gate 311 and the RISCV core 200 memory address matching signal ADDR_Matched_Core (ADDR_Matched_Core means that the address read / written by the RISCV core 200 is within the valid range of memory 100, i.e., address matching is achieved). The output is connected to the RISCV core 200's enable signal EN_Core for memory 100.
[0069] Please refer to Figure 4 As shown, the debug module enable memory circuit 320 includes a first NOR gate 321 and a second AND gate 322. The two inputs of the first NOR gate 321 are connected to the debug module 300 to obtain the read signal RD_Core and the write signal WR_Core of the RISC-V core 200 (that is, as long as the core's read or write signal is valid, the debug enable signal is invalid). The three inputs of the second AND gate 322 are connected to the output of the first NOR gate 321, the address matching signal ADDR_Matched_DBG between the debug module 300 and the memory (ADDR_Matched_DBG means that the address read or written by the debug module 300 is within the valid range of the memory 100, i.e., address matching is achieved), and the long-term valid signal Req_DBG. The output is connected to the debug module's enable signal EN_DBG for the memory 100.
[0070] Please refer to Figure 5 As shown, the status judgment circuit 330 includes a third AND gate 331 and a second OR gate 332. The two inputs of the second OR gate 332 are connected to the debug module 300 to obtain read and write signals. The two inputs of the third AND gate 331 are connected to the outputs of the first OR gate 311 and the first NOR gate 321, respectively, to obtain the read signal RD_Core and the write signal WR_Core of the RISC-V processor, and the read signal RD_DBG and the write signal WR_DBG of the debug module 300, respectively. The output is connected to the interactive register 400 to output the flag set signal. Thus, when the read or write operation of the debug module 300 and the read or write operation of the kernel occur simultaneously, a BUSY prompt signal is generated, the status flag bit of the interactive register 400 is set, and the host computer is notified that "the system is busy" and to try again later.
[0071] As described above, it can be seen that EN_DBG and EN_Core will not have overlapping effective times, ensuring the time-sharing control effect in the circuit. Furthermore, the debug enable signal EN_DBG is only effective when the RISCV core 200 is idle (i.e., RD_Core and WR_Core are low), enabling the debug module 300 to read and write to memory 100 when the RISCV core 200 is idle.
[0072] In this embodiment, the long-duration valid signal Req_DBG is generated by a D flip-flop 323. For details, please refer to... Figure 4 As shown, the debug module's enable memory circuit also includes a D flip-flop 323. The data input of the D flip-flop 323 is connected to the power supply, and its clock input CLK is connected to the single-clock-cycle valid Halt_DBG signal triggered by the host computer to achieve asynchronous triggering. Its output is connected to the input of the second AND gate 322, and its reset input CLR is connected to the reset signal DBG_Resume when the host computer exits the debug operation. Thus, during "entering debug," the single-clock-cycle valid Halt_DBG signal triggers the generation of the long-lasting valid signal Req_DBG. After "exiting debug," Req_DBG needs to be disabled, so DBG_Resume is used to reset the output of the D flip-flop 323.
[0073] In this application, the memory 100 includes a memory circuit 110 and a memory control circuit 120. Please refer to... Figure 6 As shown, this application also improves the memory control circuit 120. Specifically, the memory control circuit 120 includes a third OR gate 121, a fourth OR gate 122, a first selector 123, a second selector 124, a first buffer 125, and a second buffer 126.
[0074] The two input terminals of the third OR gate 121 are respectively connected to the output terminals of the first AND gate 312 and the second AND gate 322 to receive the enable signals EN_Core and EN_DBG, and the output terminal is connected to the enable terminal EN of the memory circuit 110.
[0075] The two inputs of the fourth OR gate 122 are connected to the write signal WR_Core of the RISCV core 200 and the write signal WR_DBG of the debug module 300, respectively, and the output is connected to the write terminal WE of the memory circuit 110. The control terminal of the first selector 123 is connected to the output of the first OR gate 311, and the output is connected to the address bus Addr[31..0] of the memory circuit 110. The two inputs are connected to the address bus Addr_Form_DBG[31..0] of the debug module 300 and the address bus Addr_Form_Core[31..0] of the RISCV core 200, respectively. The output of the second selector 124 is connected to the input data bus DIN[31..0] of the memory circuit 110. The two inputs are connected to the output data bus Data_Form_DBG[31..0] of the debug module 300 and the output data bus Data_Form_CORE[31..0] of the RISCV core 200, respectively, and the control terminal is connected to the write signal terminal WR_Core of the debug module 300.
[0076] The input terminal of the first buffer 125 is connected to the output data bus Dout[31..0] of the memory circuit 110, the control terminal is connected to the read signal RD_DBG of the debugging module 300, and the output terminal is connected to the input data bus Data_TO_DBG[31..0] of the debugging module 300.
[0077] The input of the second buffer 126 is connected to the output data bus Dout[31..0] of the memory circuit 110, the control terminal is connected to the read signal RD_Core of the RISCV core 200, and the output terminal is connected to the input data bus Data_TO_CORE[31..0] of the RISCV core 200.
[0078] Thus, the RISCV core 200 and the debug module 300 each have a set of address buses, data buses, and enable signals to control the memory 100. Signal lines with the _Core suffix are connected to the RISCV core 200, and signal lines with the _DBG suffix are connected to the debug module 300. The address and data buses are time-multiplexed through selectors and buffers. The address bus Addr[31..0] and input data bus Din[31..0] of the memory circuit 110 are enabled when the read / write signal of the RISCV core 200 is invalid, thus selecting the address and data bus inputs of the debug module 300. Correspondingly, the output data bus Dout[31..0] of the memory 100 is enabled when the debug module 300 gains address control, and the buffer output controlled by RD_DBG is enabled, meaning data is output to the debug module 300.
[0079] In summary, the RISCV core 200 and debug module 300 of this application can control memory 100 in a time-sharing manner, enabling read and write operations on memory 100 without using the interrupt function of the RISCV core 200, and without affecting the threads that are currently running in the RISCV core 200. This achieves uninterrupted memory debugging, which saves processor chip area and simplifies application development.
[0080] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A debugging system for RISC-V system memory, characterized in that, include: Memory; The RISCV core is connected to the memory, and the interrupt request function of the RISCV core is configured so that entering and exiting debug actions do not trigger the exception mechanism of the RISCV processor. The debugging module is connected to both the memory and the RISC-CV core. The debugging module converts the single-cycle valid signal enabling the host computer's "Enter Debug" action into a long-term valid signal, and invalidates this long-term valid signal when the host computer executes the "Exit Debug" action. The debugging module time-divisionally controls its read / write operations on the memory with the RISC-CV core. When the long-term valid signal is valid, it determines whether the RISC-CV core is performing read / write operations. If so, the debugging module's read / write signal is invalid, and the host computer is notified that the system is busy. If not, the debugging module's read / write signal is valid, and the debugging module performs read / write operations on the memory. A communication interface, connected to the debugging module, is used to establish a connection with the host computer. The debugging module includes a kernel-enabled memory circuit, a debugging module-enabled memory circuit, and a status judgment circuit. The kernel-enabled memory circuit includes a first OR gate and a first AND gate. The two inputs of the first OR gate are respectively connected to the read and write signals of the RISCV kernel. The two inputs of the first AND gate are respectively connected to the output of the first OR gate and the RISCV kernel address and memory address matching signal. The output is connected to the kernel's memory enable signal. The debug module enable memory circuit includes a first NOR gate and a second AND gate. The two inputs of the first NOR gate are respectively connected to the RISCV core to obtain read and write signals. The three inputs of the second AND gate are respectively connected to the output of the first NOR gate, the debug module address and memory address matching signal and the long-term valid signal. The output is connected to the debug module's memory enable signal. The status judgment circuit includes a third AND gate and a second OR gate. The two inputs of the second OR gate are connected to the debugging module to obtain read and write signals. The two inputs of the third AND gate are respectively connected to the outputs of the first OR gate and the second OR gate, and the outputs output a system busy signal.
2. The debugging system for RISC-CV system memory as described in claim 1, characterized in that: The communication interface is connected to the debugging module through an interactive register. The interactive register has a status flag bit. The system busy signal is notified to the host computer by setting the status flag bit.
3. The debugging system for RISC-CV system memory as described in claim 1, characterized in that: The debugging module enable memory circuit also includes a D flip-flop. The data input terminal of the D flip-flop is connected to the power supply, the clock input terminal is connected to the trigger enable signal of the host computer entering debugging, the output terminal is connected to the input terminal of the second AND gate, and the reset terminal is connected to the reset signal of the host computer when exiting debugging.
4. The debugging system for RISC-CV system memory as described in claim 3, characterized in that: The memory includes a memory circuit and a memory control circuit; The memory control circuit includes a third OR gate, a fourth OR gate, a first selector, a second selector, a first buffer, and a second buffer; The two input terminals of the third OR gate are respectively connected to the output terminals of the first AND gate and the second AND gate, and the output terminal is connected to the enable terminal of the memory circuit. The two inputs of the fourth OR gate are respectively connected to the write signals of the RISCV kernel and the debug module, and the output is connected to the write terminal of the memory circuit. The control terminal of the first selector is connected to the output terminal of the first OR gate, the output terminal is connected to the address bus of the memory circuit, and the two input terminals are respectively connected to the address buses of the debugging module and the RISCV core. The output of the second selector is connected to the input data bus of the memory circuit, the two inputs are respectively connected to the output data buses of the debug module and the RISCV core, and the control terminal is connected to the write signal terminal of the debug module. The input terminal of the first buffer is connected to the output data bus of the memory circuit, the control terminal is connected to the read signal of the debugging module, and the output terminal is connected to the input data bus of the debugging module. The input terminal of the second buffer is connected to the output data bus of the memory circuit, the control terminal is connected to the read signal of the RISCV core, and the output terminal is connected to the input data bus of the RISCV core.
5. A method for debugging RISC-CV system memory, implemented based on the RISC-CV system memory debugging system as described in any one of claims 1-4, characterized in that, include: Configure the interrupt request function of the RISCV kernel so that entering and exiting debug actions do not trigger the exception mechanism of the RISCV processor; Connect the host computer to the RISCV system and enter debug mode; The single-cycle valid signal enabled by the host computer to perform the debugging action will be converted into a long-term valid signal. When the long-term valid signal is valid, it is determined whether the RISCV core is being read or written. If so, the read / write signal of the debugging module is determined to be invalid, and the host computer system is notified that it is busy. If not, the read / write signal of the debugging module is determined to be valid, and the debugging module performs read / write operations on the memory. After completing memory read / write and receiving the exit debugging signal from the host computer, the debugging module executes the exit debugging action and invalidates the long-term valid signal.
6. The method for debugging RISC-CV system memory as described in claim 5, characterized in that: The single-cycle valid signal that enables the upper computer to perform the debugging action is used as the asynchronous trigger input signal of the D flip-flop, and the output of the D flip-flop is converted into a long-term valid signal. When the debugging module completes memory read / write and receives the exit debugging signal from the host computer, it executes the exit debugging action. The exit debugging signal from the host computer resets the D flip-flop.
7. The method for debugging RISC-CV system memory as described in claim 5, characterized in that: When the read / write signal of the debugging module is invalid, the status flag bit of the interaction register is set to notify the host computer system that it is busy.