Sequence signal sensor and differential signal sensing method

Abstract

The present invention is a sequential signal sensor and a differential signal sensing method. The sequential signal sensor includes a voltage comparison module and a hybrid logic filter. The voltage comparison module receives a differential signal pair including a first shift signal and a second shift signal. The voltage comparison module includes a first comparator and a second comparator. The first comparator and the second comparator generate a first comparison signal and a second comparison signal, respectively, according to the first shift signal, the second shift signal, and a voltage threshold. The hybrid logic filter includes a controllable logic gate and a capacitor. The controllable logic gate performs a logic operation related to the first comparison signal and the second comparison signal, and generates a filtered and converted pulse signal accordingly. The controllable logic gate and the capacitor jointly perform a primary filtering operation on the filtered and converted pulse signal when the logic operation is performed.

Description

Technical Field

[0001] This invention relates to a sequence signal sensor and a differential signal sensing method, and more particularly to a sequence signal sensor and a differential signal sensing method covering multiple protocols. Background Technology

[0002] Electronic devices frequently employ serial transmission technology, and serial signal sensing is a crucial aspect of serial signal protocols. Different serial communication protocols, such as PCIe's queue sensing, SATA's out-of-band (OOB) sensing, USB's low-frequency periodic signaling (LFPS), and Ethernet's loss of signal (LOS) sensing, define different signal sensing conditions based on voltage, signal swing, frequency, and pattern.

[0003] Please see Figure 1 This is a schematic diagram of the signal sensing architecture of an existing receiver. With the increasing prevalence of wearable devices, electronic devices need to include different sequence signal sensors to support various protocols. Please note that, for ease of explanation, Figure 1 Only two sequence signal sensors, 10a and 10b, are shown.

[0004] The existing receiver 1 includes sequence signal sensors 10a and 10b and main circuitry 12. Sequence signal sensors 10a and 10b are electrically connected to the main circuitry 12.

[0005] The sequence signal sensors 10a and 10b operate similarly. Sequence signal sensor 10a performs a differential signal sensing operation on the positive input signal Sina_p and the negative input signal Sina_n, generating a sensing signal Sdeta. Sequence signal sensor 10b performs a differential signal sensing operation on the positive input signal Sinb_p and the negative input signal Sinb_n, generating another sensing signal Sdetb. Then, sequence signal sensors 10a and 10b transmit the sensing signals Sdeta and Sdetb to the main circuit 12, respectively. The main circuit 12 then uses the sensing signals Sdeta and Sdetb for other operations. For example, the main circuit 12 can be a serializer / de-serializer (SerDes) circuit used to perform SERDES operations in response to the sensing signals Sdeta and Sdetb.

[0006] like Figure 1 As shown, for electronic devices supporting multiple sequence communication protocols, multiple sequence signal sensors 10a and 10b need to be provided in the existing receiver 1. Accordingly, the more sequence communication protocols the electronic device supports, the more sequence signal sensors are required. However, to implement multiple sequence signal sensors 10a and 10b, the receiver 1 requires a larger area, and the main circuit 12 requires more pins for setting the sequence signal sensors 10a and 10b. In short, individually setting the sequence signal sensors 10a and 10b is quite costly. Summary of the Invention

[0007] This invention relates to a sequence signal sensor and a differential signal sensing method applied to a receiver. The sequence signal sensor and the differential signal sensing method can cover different types of sequence communication protocols.

[0008] According to a first aspect of the present invention, a sequence signal sensor is provided. The sequence signal sensor includes a voltage comparison module and a hybrid logic filter. The voltage comparison module receives a differential signal pair including a first shift signal and a second shift signal. The voltage comparison module includes a first comparator and a second comparator. The first comparator generates a first comparison signal based on the first shift signal, the second shift signal, and a voltage threshold. The second comparator generates a second comparison signal based on the first shift signal, the second shift signal, and the voltage threshold. The hybrid logic filter is electrically connected to the first and second comparators. The hybrid logic filter includes a controllable logic gate and a capacitor. The controllable logic gate performs logic operations related to the first and second comparison signals, thereby generating a filtered and converted pulse signal. The capacitor is electrically connected to the controllable logic gate. During the logic operation, the controllable logic gate and the capacitor jointly perform an initial filtering operation on the filtered and converted pulse signal.

[0009] According to a second aspect of the present invention, a signal sensing method for a receiver is provided. The signal sensing method includes the following steps: First, a differential signal pair comprising a first shift signal and a second shift signal is received. Next, a first comparison signal and a second comparison signal are generated based on the first shift signal, the second shift signal, and a voltage threshold. A logic operation related to the first comparison signal and the second comparison signal is performed. A filtered and converted pulse signal is generated in response to the logic operation. Furthermore, a primary filtering operation is performed on the filtered and converted pulse signal simultaneously with the logic operation. Attached Figure Description

[0010] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:

[0011] Figure 1 This is a schematic diagram of the signal sensing architecture of an existing receiver.

[0012] Figure 2 This is a schematic diagram of the signal sensing architecture of a receiver according to an embodiment of the present disclosure.

[0013] Figure 3 It is a block diagram of signals and elements in a sequence signal sensor according to an embodiment of the present disclosure.

[0014] Figure 4A , Figure 4B It is a schematic diagram illustrating the implementation of a voltage supply circuit.

[0015] Figure 5 It is a waveform diagram of the input and output signals of the sequence signal sensor.

[0016] Figure 6A This is a schematic diagram of an embodiment of a sequence signal sensor.

[0017] Figure 6B , it is Figure 6A The waveform diagram of the sequence signal sensor is shown.

[0018] Figure 7A This is a schematic diagram of another embodiment of a sequence signal sensor.

[0019] Figure 7B , it is Figure 7A The waveform diagram of the sequence signal sensor is shown.

[0020] Figure 8A This is a schematic diagram illustrating a hybrid logic filter.

[0021] Figure 8B It is with Figure 8AThe waveform diagram of the signal associated with the hybrid logic filter is shown.

[0022] Figure 9A This is a schematic diagram illustrating another type of hybrid logic filter.

[0023] Figure 9B It is with Figure 9A The waveform diagram of the signal associated with the hybrid logic filter is shown.

[0024] The reference numerals in the attached figures are explained as follows:

[0025] Sina_p, Sinb_p, Sin_p: Positive input signal

[0026] Sina_n, Sinb_n, Sin_n: Negative input signals

[0027] 10a, 10b, 20, 40, 50: Sequence signal sensors

[0028] Sdeta, Sdetb, Sdet: Sensing signal

[0029] 1, 2: Receiver

[0030] 12, 22: Main circuit

[0031] Sin: Differential input signal

[0032] Spsel: Protocol Selection Signal

[0033] 22a: Temporary Register

[0034] 29: Level offset device

[0035] Sshft_p: Forward shift signal

[0036] Ssfht_n: Negative shift signal

[0037] 21, 31, 33: Reference voltage supply circuit

[0038] Vrefp: Forward reference voltage

[0039] Vrefn: Negative reference voltage

[0040] 23, 43, 53: Voltage Comparison Modules

[0041] 231, 233, 431, 433, 531, 533: Comparators

[0042] 25, 45, 55, 65, 75: Hybrid Logic Filters

[0043] 251: Controllable Logic Gate

[0044] Scmp_p, Scmp_p': Forward comparison signals

[0045] Scmp_n, Scmp_n': Negative comparison signals

[0046] 251a, 451a, 551a: Pull-up circuit

[0047] 251c, 451c, 551c: Pull-down circuit

[0048] flt_Spul: Filtered and converted pulse signal

[0049] Ncnv: Pulse conversion endpoint

[0050] C: Capacitor

[0051] Gnd: Grounding terminal (voltage)

[0052] 27, 57: Interference filtering module

[0053] R1, R2, R3, R4, Ra, Rb: Resistors

[0054] Vdd: Supply voltage (terminal)

[0055] c_src: Current source

[0056] flt_Spul(pos pl), flt_Spul(neg pl): Filtered and converted pulse signals

[0057] Tval1, Tval2, Tval: Valid signal period

[0058] t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11: Time points

[0059] 451: Controllable NOR gate

[0060] Mu1, Mu2, Mu1', Mu2': PMOS transistors

[0061] Md1, Md2, Md1', Md2': NMOS transistors

[0062] 47: Interference Filtering Module

[0063] 471, 473: Interference filters

[0064] 475: Output Inverter

[0065] 471a, 473a: Transmission gates

[0066] Rp, Rp': Programmable resistors

[0067] Sgf1, Sgf2: Interference filtering signals

[0068] 471c, 473c: Inverters

[0069] Sinv1, Sinv2: Reverse signals

[0070] Vth: Voltage Threshold

[0071] CIR1, CIR2, CIR3: Selection of dashed circles

[0072] 553: Input Circuit

[0073] 553a, 553c, 633a, 633c: Input inverters

[0074] 551: Controllable NAND gate Detailed Implementation

[0075] This document provides an integrated sequence signal sensor that can cover different sequence communication protocols. The sequence signal sensor includes elements that can be dynamically configured according to the selected sequence communication protocol.

[0076] Please see Figure 2 This is a schematic diagram of the signal sensing architecture of a receiver according to an embodiment of the present disclosure. The receiver 2 includes a sequence signal sensor 20 and a main circuit 22. The sequence signal sensor 20 is electrically connected to the main circuit 22.

[0077] The main circuit 22 may include a register 22a, the value of which is dynamically set according to the serial communication protocol selected by the user. Based on the value set in the register 22a, the main circuit 22 transmits a protocol selection signal Spsel to the serial signal sensor 20. The protocol selection signal Spsel is determined by the register and is used to notify the serial signal sensor 20 which serial communication protocol is selected. The serial signal sensor 20 modifies its internal settings according to the change in the protocol selection signal Spsel to conform to the specific specifications required by the protocol.

[0078] The sequence signal sensor 20 receives a differential input signal pair Sin, which includes a positive input signal Sin_p and a negative input signal Sin_n. The positive input signal Sin_p and the negative input signal Sin_n can be a differential signal pair defined by any sequence communication protocol. The sequence signal sensor 20 generates a sensing signal Sdet based on the positive input signal Sin_p and the negative input signal Sin_n. Then, the sensing signal Sdet is transmitted to the main circuit 22. Figure 2 As shown, receiver 2 requires only one sequence signal sensor 20. (And...) Figure 1Compared to receiver 1, receiver 2 can significantly reduce costs. Furthermore, because fewer circuits are required, the load at the input terminals of receiver 2 is reduced, and the bandwidth at the input terminals of receiver 2 is not limited.

[0079] Please see Figure 3 This is a block diagram of signals and components in a sequence signal sensor according to an embodiment of the present disclosure. The sequence signal sensor 20 includes a level offset 29, a reference voltage supply circuit 21, a voltage comparison module 23, a hybrid logic filter 25, and an interference filtering module 27.

[0080] Level shifter 29 receives a positive input signal Sin_p and a negative input signal Sin_n. Then, level shifter 29 changes the common mode voltage of the positive input signal Sin_p and the negative input signal Sin_n. After the shift, level shifter 29 generates a positive shift signal Shft_p based on the positive input signal Sin_p, and a negative shift signal Shft_n based on the negative input signal Sin_n.

[0081] The reference voltage supply circuit 21 provides a positive reference voltage Vrefp and a negative reference voltage Vrefn to the voltage comparison module 23. Both the positive and negative reference voltages Vrefp and Vrefn are DC voltages, with the positive reference voltage Vrefp being higher than the negative reference voltage Vrefn. In this paper, the voltage difference between the positive and negative reference voltages Vrefp and Vrefn is defined as the voltage threshold Vth. That is, Vth = (Vrefp - Vrefn).

[0082] In addition to the positive reference voltage Vrefp and the negative reference voltage Vrefn, comparators 231 and 233 also simultaneously receive the positive shift signal Sshft_p and the negative shift signal Sshft_n. Comparator 231 generates a positive comparison signal Scmp_p and sends it to the hybrid logic filter 25; comparator 233 generates a negative comparison signal Scmp_n and sends it to the hybrid logic filter 25.

[0083] In this paper, the voltage difference (Sshft_p-Sshft_n) between the positive shift signal Sshft_p and the negative shift signal Sshft_n is defined as the positive voltage difference ΔVshft_pn, and the voltage difference (Sshft_n-Sshft_p) between the negative shift signal Sshft_n and the positive shift signal Sshft_p is defined as the negative voltage difference ΔVshft_np. That is, the positive voltage difference ΔVshft_pn = (Sshft_p-Sshft_n), and the negative voltage difference ΔVshft_np = (Sshft_n-Sshft_p). According to the above definition, the positive voltage difference ΔVshft_pn and ΔVshft_np are equal in magnitude but opposite in sign.

[0084] Based on the comparison between the voltage threshold Vth and the forward voltage difference ΔVshft_pn, a forward path comparison condition corresponding to comparator 231 is defined. When the forward voltage difference ΔVshft_pn is greater than the voltage threshold Vth (i.e., ΔVshft_pn > Vth), the forward path comparison condition is met, and comparator 231 sets the forward comparison signal Scmp_p to a preset level (e.g., high level H). Alternatively, when the forward voltage difference ΔVshft_pn is less than or equal to the voltage threshold Vth (i.e., ΔVshft_pn ≦ Vth), the forward path comparison condition is not met, and comparator 231 sets the forward comparison signal Scmp_p to another preset level (e.g., low level L).

[0085] Based on the comparison between the voltage threshold Vth and the negative voltage difference ΔVshft_np, a negative path comparison condition corresponding to comparator 233 is defined. When the negative voltage difference ΔVshft_np is greater than the voltage threshold Vth (i.e., ΔVshft_np > Vth), the negative path comparison condition is met, and comparator 233 sets the negative comparison signal Scmp_n to a preset level. Alternatively, when the negative voltage difference ΔVshft_np is less than or equal to the voltage threshold Vth (i.e., ΔVshft_np ≦ Vth), the negative path comparison condition is not met, and comparator 233 sets the negative comparison signal Scmp_n to another preset level.

[0086] The selection of the positive comparison signal Scmp_p based on whether the positive path comparison condition is met depends on the specific application. Similarly, the selection of the preset level of the negative comparison signal Scmp_n based on whether the negative path comparison condition is met also depends on the specific application. Table 1 lists two possible combinations of preset levels when the positive / negative path comparison conditions are met. However, in other applications, other types of preset level selections and combinations may be used.

[0087] Table 1

[0088]

[0089] The following describes two types of implementation examples. Figure 6A , Figure 6B , Figure 7A , Figure 7B In the embodiments, when the comparison conditions corresponding to comparators 231 and 233 are met, comparators 231 and 233 set the positive comparison signal Scmp_p and the negative comparison signal Scmp_n to high levels (Scmp_p=H, Scmp_n=H), respectively, and vice versa. Figure 8A , Figure 8B , Figure 9A , Figure 9B In the embodiments, the preset levels of the positive comparison signal Scmp_p and the negative comparison signal Scmp_n corresponding to the positive / negative path comparison conditions are... Figure 6A , Figure 6B , Figure 7A , Figure 7B The opposite is true for the embodiments. Also note that the design of the hybrid logic filter 25 must be appropriately modified to account for these differences.

[0090] The hybrid logic filter 25 further includes a controllable logic gate 251 and a capacitor C. The controllable logic gate 251 includes a pull-up circuit 251a and a pull-down circuit 251c. The hybrid logic filter 25 performs logic operations (e.g., NOR, OR, AND, NAND, etc.). Furthermore, the hybrid logic filter 25 and the capacitor C jointly perform a primary filtering operation. The logic operation and the primary filtering operation are performed simultaneously. Since the hybrid logic filter 25 is mainly a digital circuit, the circuit area used for filtering is small. Next, the hybrid logic filter 25 generates a filtered and converted pulse signal flt_Spul at the pulse conversion terminal Ncnv and transmits the filtered and converted pulse signal flt_Spul to the interference filtering module 27. Afterwards, the interference filtering module 27 performs a second-order filtering operation on the filtered and converted pulse signal flt_Spul to generate a sensing signal Sdet. Then, the interference filtering module 27 transmits the sensing signal Sdet to the main circuit 22.

[0091] The main circuit 22 transmits the protocol selection signal Spsel, representing the selected serial communication protocol, to the level offset 29, the reference voltage supply circuit 21, comparators 231 and 233, and the controllable logic gate 251. The level offset 29, the reference voltage supply circuit 21, the comparators 231 and 233, and the controllable logic gate 251 dynamically adjust their internal settings (e.g., voltage value, threshold value, resistance value, capacitance value, etc.) according to the protocol selection signal Spsel, thereby performing signal sensing operations corresponding to the selected serial communication protocol.

[0092] Please see Figure 4A , Figure 4B This is a schematic diagram illustrating an example of how a reference voltage supply circuit is implemented. Figure 4A In this circuit, a voltage divider is used as the reference voltage supply circuit 31. The voltage divider includes resistors R1, R2, R3, and R4. The resistance values ​​of resistors R1, R2, R3, and R4 can be freely set according to the protocol selection signal Spsel. Figure 4B In the circuit 33, a reference voltage supply circuit is implemented using a current source c_src and resistors Ra and Rb. The current value of the current source c_src and the resistance values ​​of the resistors Ra and Rb can be freely selected according to the protocol selection signal Spsel.

[0093] In this paper, the symbol Vdd represents both the supply voltage terminal and its voltage (supply voltage); the symbol Gnd represents both the ground terminal and its voltage (ground voltage). The supply voltage Vdd is higher than the ground voltage Gnd (Vdd>Gnd). Figure 4A , 4B As shown, the voltage values ​​of the supply voltage Vdd, the positive reference voltage Vrefp, and the negative reference voltage Vrefn can be freely selected and set according to the requirements of the serial communication protocol. Furthermore, the reference voltage supply circuit 21 can also be implemented using other circuit designs.

[0094] The positive reference voltage Vrefp and the negative reference voltage Vrefn may come from external circuitry of the sequence signal sensor. For ease of explanation, the level offset and voltage supply circuitry are omitted in the following embodiments.

[0095] Please see Figure 5 It is a waveform diagram of the input and output signals of the sequence signal sensor. Figure 5 The top dashed waveform represents the positive shift signal Shft_p, and the solid waveform represents the negative shift signal Shft_n. Figure 5It also includes the waveforms of the positive comparison signal Scmp_p, the negative comparison signal Scmp_n, and the filtered and converted pulse signals flt_Spul (pos pl) and flt_Spul (neg pl). In this paper, the waveform of flt_Spul (pos pul) represents the filtered and converted pulse signal with a positive pulse, and the waveform of flt_Spul (neg pul) represents the filtered and converted pulse signal with a negative pulse.

[0096] like Figure 5 As shown, the waveforms flt_Spul (pos pl) and flt_Spul (negpl) ​​of the filtered and converted pulse signal are complementary. Due to the different designs of comparators 231 and 233 and controllable logic gate 251, the waveform of the output (filtered and converted pulse signal flt_Spul) of the hybrid logic filter 25 is either flt_Spul (pos pl) or flt_Spul (negpl).

[0097] Table 2 summarizes the waveform changes of the positive comparison signal Scmp_p, the negative comparison signal Scmp_n, and the filtered and converted pulse signals flt_Spul (pos pul) and flt_Spul (neg pul) in chronological order.

[0098] Table 2

[0099]

[0100] The table above shows the waveforms from time point t1 to time point t7. The waveforms after time point t7 are similar to those described above and will not be discussed further. Figure 5 In the valid signal periods Tval1 and Tval2, either the positive path comparison condition or the negative path comparison condition is met. During the valid signal periods Tval1 and Tval2, the controllable logic gate 251 generates a filtered and converted pulse signal flt_Spul (pos pul) = H with a positive pulse at the pulse conversion endpoint Ncnv, or generates a filtered and converted pulse signal flt_Spul (neg pul) = L with a negative pulse at the pulse conversion endpoint Ncnv. The invalid signal period represents the period during which neither the positive path comparison condition nor the negative path comparison condition is met. The lengths of the valid signal periods Tval1 and Tval2 are not necessarily equal.

[0101] Theoretically, the hybrid logic filter 25 can directly transmit the filtered and converted pulse signals flt_Spul (pos pul) and flt_Spul (neg pul) to the main circuit. However, in practical applications, the operating speed of comparators 231 and 233 may not be fast enough, and / or the positive / negative shift signals may have boundary values ​​during conversion. Consequently, the positive shift signal Shft_p and the negative shift signal Shft_n cannot change in real time, causing the filtered and converted pulse signals flt_Spul (pos pul) and flt_Spul (neg pul) to be unable to maintain consistency between Tval1 and Tpval2 during the effective signal period. In other words, the filtered and converted pulse signals flt_Spul (pos pul) and flt_Spul (neg pul) may have slight fluctuations within the effective signal period Tval1 and Tval2, making it impossible to maintain a fixed voltage (Vdd / Gnd). The minute fluctuations in the filtered and converted pulse signal flt_Spul during the interval create interference during the main circuit's digital operations. Within these minute fluctuations, the filtered and converted pulse signal flt_Spul is not equal to either the ground voltage Gnd or the supply voltage Vdd. Instead, the filtered and converted pulse signal flt_Spul is merely an intermediate voltage Vm (Gnd) between the ground voltage Gnd and the supply voltage Vdd. <Vm<Vdd)。

[0102] In this paper, the controllable logic gate 251 has a built-in first-order filtering function, and the interference filtering module 27 is used to perform second-order filtering. Then, after filtering out the interference, the interference filtering module 27 generates and transmits a digitally formatted sensing signal Sdet to the main circuit 22.

[0103] Please see Figure 6A This is a schematic diagram of an embodiment of a sequence signal sensor. The sequence signal sensor 40 includes a voltage comparison module 43, a hybrid logic filter 45, and an interference filtering module 47.

[0104] The voltage comparison module 43 includes comparators 431 and 433. Comparators 431 and 433 generate a positive comparison signal Scmp_p and a negative comparison signal Scmp_n, respectively. Figure 6A In the mixed logic filter 45, a controllable NOR gate 451 and a capacitor C are included. The controllable NOR gate 451 further includes a pull-up circuit 451a and a pull-down circuit 451c.

[0105] Pull-up circuit 451a includes PMOS transistors Mu1 and Mu2 (pull-up transistors) and a programmable resistor Rp, and pull-down circuit 451c includes NMOS transistors Md1 and Md2 (pull-down transistors). The programmable resistor Rp is electrically connected to pull-down circuit 451c and capacitor C. Pull-up circuit 451a provides a pull-up path to conduct the supply voltage Vdd to the pulse switching terminal Ncnv. Pull-down circuit 451c provides a pull-down path to conduct the ground voltage Gnd to the pulse switching terminal Ncnv.

[0106] In pull-up circuit 451a, the source of PMOS transistor Mu1 is electrically connected to the supply voltage terminal Vdd, and the drain of PMOS transistor Mu1 is electrically connected to the source of PMOS transistor Mu2. The drain of PMOS transistor Mu2 is electrically connected to resistor Rp. The gates of PMOS transistors Mu1 and Mu2 are electrically connected to comparators 431 and 433, respectively. PMOS transistor Mu1 is controlled by a positive comparison signal Scmp_p (output of comparator 431). PMOS transistor Mu2 is controlled by a negative comparison signal Scmp_n (output of comparator 433).

[0107] Since PMOS transistors Mu1 and Mu2 are connected in sequence, when both PMOS transistors Mu1 and Mu2 are ON, the filtered and converted pulse signal flt_Spul is pulled up to the supply voltage Vdd. When either PMOS transistor Mu1 or Mu2 is OFF, the pull-up path is broken, and the filtered and converted pulse signal flt_Spul is determined by the pull-down path.

[0108] In pull-down circuit 451c, the sources of NMOS transistors Md1 and Md2 are electrically connected to the ground terminal Gnd, and the drains of NMOS transistors Md1 and Md2 are electrically connected to the programmable resistor Rp and the capacitor C. The gates of NMOS transistors Md1 and Md2 are electrically connected to comparators 431 and 433, respectively. NMOS transistor Md1 is controlled by the positive comparison signal Scmp_p (output of comparator 431). NMOS transistor Md2 is controlled by the negative comparison signal Scmp_n (output of comparator 433).

[0109] Since NMOS transistors Md1 and Md2 are connected in parallel, when either Md1 or Md2 is ON, the filtered and converted pulse signal flt_Spul is pulled down to the ground voltage Gnd. When both Md1 and Md2 are OFF, the pull-down path is broken, and the filtered and converted pulse signal flt_Spul is determined by the pull-up path.

[0110] Table 3 summarizes the operations related to the hybrid logic filter 45. Table 3 summarizes the inputs of different combinations of NOR gate 451, the switching states (ON / OFF) of PMOS transistors Mu1, Mu2 and NMOS transistors Md1, Md2, and the output of hybrid logic filter 45.

[0111] Table 3

[0112]

[0113] Table 3 illustrates that when at least one of the positive comparator signal Scmp_p and the negative comparator signal Scmp_n is set to a high level (Scmp_p = H and / or Scmp_n = H), the pull-down path conducts the ground voltage Gnd to the pulse conversion terminal Ncnv (filtered and converted pulse signal flt_Spul = Gnd). Furthermore, when both the positive comparator signal Scmp_p and the negative comparator signal Scmp_n are set to a low level (Scmp_p = Scmp_n = L), the pull-up path conducts the supply voltage Vdd to the pulse conversion terminal Ncnv (filtered and converted pulse signal flt_Spul = Vdd). Therefore, PMOS transistors M1 and M2, along with NMOS transistors M3 and M4, jointly provide NOR operation. Please also note that, according to the definitions of the positive path comparison condition (ΔVshft_pn>Vth) and the negative path comparison condition (ΔVshft_np>Vth), in practical applications, the positive comparison signal Scmp_p and the negative comparison signal Scmp_n will not be set to the high level at the same time (Scmp_p=Scmp_n=H).

[0114] The programmable resistor Rp slows down the transient rate of the filtered and converted pulse signal flt_Spul. Once the transient rate of flt_Spul is reduced, interference is suppressed. The resistance value of the programmable resistor Rp must be selected according to the specifications. For example, the USB and SATA specifications define the maximum and minimum pulse widths for the sensing signal Sdet. Because the programmable resistor Rp adjusts the charging speed of the filtered and converted pulse signal flt_Spul, it consequently affects the pulse width of the sensing signal Sdet.

[0115] When the programmable resistor Rp has a large resistance value, interference in the filtered and converted pulse signal flt_Spul is filtered out, and the pulse width of flt_Spul is narrow. On the other hand, when the programmable resistor Rp has a small resistance value, interference in flt_Spul cannot be filtered out, and the pulse width of flt_Spul is wide.

[0116] Therefore, although a larger resistance value of the programmable resistor Rp results in better interference suppression, it is undesirable for the resistance value of the programmable resistor Rp to be too large, as this would affect the charging speed of the filtered and converted pulse signal flt_Spul. In other words, when selecting the resistance value of the programmable resistor Rp, interference suppression and charging speed must be considered. Table 4 lists the relevant considerations when selecting the resistance value of the programmable resistor Rp.

[0117] Table 4

[0118]

[0119] As described above, the hybrid logic filter 45 generates a filtered and converted pulse signal flt_Spul based on the positive comparison signal Scmp_p and the negative comparison signal Scmp_n. Furthermore, the filtered and converted pulse signal flt_Spul may be subject to interference during the active signal period Tval; therefore, the interference must be removed before transmitting the filtered and converted pulse signal flt_Spul to the main circuit.

[0120] exist Figure 6A In this circuit, the interference filtering module 47 includes interference filters 471 and 473 and an output inverter 475. Interference filters 471 and 473 are used to filter interference present in the filtered and converted pulse signal flt_Spul. Each of interference filters 471 and 473 includes a transmission gate 471a and 473a and an inverter 471c and 473c. In practical applications, the number of interference filters 471 and 473 and the number of output inverters 475 included in the interference filtering module 47 do not need to be limited.

[0121] After receiving the filtered and converted pulse signal flt_Spul, the transmission gate 471a generates an interference-filtering signal Sgf1 as an intermediate stage signal. Then, the inverter 471c inverts the interference-filtering signal Sgf1 to generate an inverted signal Sinv1.

[0122] After receiving the reverse signal Sinv1, the transmission gate 473a generates an interference filtering signal Sgf2 as an intermediate stage signal. Then, the inverter 473c reverses the interference filtering signal Sgf2 to generate the reverse signal Sinv2.

[0123] The output inverter 475 further inverts the inverted signal Sinv2 to generate the sensing signal Sdet. Waveform diagrams are used to illustrate the relationships between these signals and the interference removal effect of interference filters 471 and 473.

[0124] Please see Figure 6B , it is Figure 6A The waveform diagram of the sequence signal sensor is shown below. Please also refer to... Figure 6A , Figure 6B .exist Figure 6B In the table, from top to bottom, the waveforms are: positive shift signal Shft_p, negative shift signal Shft_n, positive comparison signal Scmp_p, negative comparison signal Scmp_n, theoretically converted pulse signal theo_Spul, filtered and converted pulse signal flt_Spul, interference filtering signal Sgf1, inverse signal Sinv1, interference filtering signal Sgf2, and sensing signal Sdet.

[0125] Please refer to the first waveform (positive shift signal Sshft_p), the second waveform (negative shift signal Sshft_n), and the third waveform (positive comparison signal Scmp_p) simultaneously. Ideally, when the positive path comparison condition is met (i.e., ΔVshft_pn > Vth), comparator 431 can instantaneously set the positive comparison signal Scmp_p to a high level (Scmp_p = H); or, when the positive path comparison condition is not met (i.e., ΔVshft_pn ≤ Vth), comparator 431 can instantaneously set the positive comparison signal Scmp_p to a low level (Scmp_p = L). However, in actual circuits, the actual time when comparator 431 generates the positive comparison signal Scmp_p may be slightly later than the time when the positive path comparison condition is met.

[0126] Please refer to the first waveform (positive shift signal Sshft_p), the second waveform (negative shift signal Sshft_n), and the fourth waveform (negative comparison signal Scmp_n) simultaneously. Ideally, when the negative path comparison condition is met (i.e., ΔVshft_np > Vth), comparator 433 can instantaneously set the negative comparison signal Scmp_n to a high level (Scmp_n = H); or, when the negative path comparison condition is not met (i.e., ΔVshft_np ≤ Vth), comparator 433 can instantaneously set the negative comparison signal Scmp_n to a low level (Scmp_n = L). However, in actual circuits, the actual time when comparator 433 generates the negative comparison signal Scmp_n may be slightly later than the time when the negative path comparison condition is met.

[0127] Since the hybrid logic filter 45 provides NOR operation, when both the positive comparison signal Scmp_p and the negative comparison signal Scmp_n are set to low level (Scmp_p=Scmp_n=L), the hybrid logic filter 45 conducts the supply voltage Vdd to the pulse conversion terminal Ncnv (theoretically converted pulse signal theo_Spul=Vdd). When at least one of the positive comparison signal Scmp_p and the negative comparison signal Scmp_n is set to high level (Scmp_p=H and / or Scmp_n=H), the hybrid logic filter 45 conducts the ground voltage Gnd to the pulse conversion terminal Ncnv (theoretically converted pulse signal theo_Spul=Gnd).

[0128] The theoretically converted pulse signal theo_Spul, plotted as a dashed line, represents the filtered and converted pulse signal generated at the pulse conversion endpoint Ncnv when the hybrid logic filter 45 does not include the programmable resistor Rp and capacitor C. On the other hand, the filtered and converted pulse signal flt_Spul is the filtered and converted pulse signal generated at the pulse conversion endpoint Ncnv when the hybrid logic filter 45 includes the programmable resistor Rp and capacitor C.

[0129] For simplicity, the detailed relationships between the positive comparison signal Scmp_p, the negative comparison signal Scmp_n, and the theoretically converted pulse signal theo_Spul are listed here, but not explained in detail. Table 5 lists the states of the negative comparison signal Scmp_n and the theoretically converted pulse signal theo_Spul in chronological order at different times.

[0130] Table 5

[0131]

[0132] Depend on Figure 6B It can be seen that before time point t1 and after time point t10, the theoretically converted pulse signal theo_Spul remains at the supply voltage Vdd. Furthermore, for most of the period between time points t1 and t10, the ground voltage Gnd is conducted to the pulse conversion endpoint Ncnv (the theoretically converted pulse signal theo_Spul = Gnd). That is, although the pulse conversion endpoint Ncnv is roughly maintained at the ground voltage Gnd during the period from time point t1 to t10, it is at the supply voltage Vdd (the theoretically converted pulse signal theo_Spul = Vdd) during certain brief periods within the period from time point t1 to t10 (t2~t3, t4~t5, t6~t7, t8~t9).

[0133] If we disregard the variations in the theoretically converted pulse signal theo_Spul during brief periods (t2~t3, t4~t5, t6~t7, t8~t9), then the waveform of the theoretically converted pulse signal theo_Spul can be roughly considered as a negative pulse with a pulse period between time points t1 and t10. Figure 6B In this context, the pulse period (from time t1 to time t10) corresponding to this negative pulse is defined as the effective signal period Tval.

[0134] For ease of explanation, this paper further defines these brief periods (t2~t3, t4~t5, t6~t7, t8~t9) within the effective signal period Tval as the interval (gap duration) during which the negative pulse of the theoretically converted pulse signal theo_Spul is interrupted (the theoretically converted pulse signal theo_Spul switches from the ground voltage Gnd to the supply voltage Vdd). The possible causes of the intervals (t2~t3, t4~t5, t6~t7, t8~t9) are briefly explained below.

[0135] As mentioned earlier, the timing when comparators 431 and 433 actually generate the positive comparison signal Scmp_p and the negative comparison signal Scmp_n may differ slightly from the time at which the positive and negative path comparison conditions are met. Therefore, one reason for the intervals (t2~t3, t4~t5, t6~t7, t8~t9) is that the circuitry of comparators 431 and 433 has a delay, causing the positive comparison signal Scmp_p and the negative comparison signal Scmp_n to fail to reflect the comparison results of the positive and negative path comparison conditions in real time.

[0136] Furthermore, comparison Figure 5 , Figure 6B From the positive shift signal Shft_p and the negative shift signal Shft_n, it can be seen that... Figure 5 The positive shift signal Sshft_p and the negative shift signal Sshft_n are quite smooth, but Figure 6B The positive shift signal Shft_p and the negative shift signal Shft_n exhibit jitter. This jitter may originate from noise in the signal channel. The presence of jitter also affects the judgment results of comparators 431 and 433, causing errors due to noise. Consequently, the theoretically converted pulse signal theo_Spul also varies during the intervals (t2~t3, t4~t5, t6~t7, t8~t9).

[0137] As mentioned earlier, if the theoretically converted pulse signal theo_Spul during time points t1 to t10 is considered as a negative pulse period, then this negative pulse is equivalent to multiple interruptions during intervals t2~t3, t4~t5, t6~t7, t8~t9) caused by non-ideal characteristics such as circuit delay and signal jitter due to noise of the comparator. To improve the situation of such pulse period interruption, this disclosure further sets a programmable resistor Rp and a capacitor C in the hybrid logic filter 45.

[0138] Comparing the filtered and converted pulse signal flt_Spul with the theoretically converted pulse signal theo_Spul, it can be seen that although the filtered and converted pulse signal flt_Spul exhibits slight signal fluctuations during the intervals (t2~t3, t4~t5, t6~t7, t8~t9), the amplitude of these fluctuations is not as large as that of the theoretically converted pulse signal theo_Spul during the same intervals. Therefore, the combination and setting of the programmable resistor Rp and capacitor C can reduce the signal fluctuation amplitude at the pulse conversion endpoint Ncnv during the intervals (t2~t3, t4~t5, t6~t7, t8~t9), effectively providing a low-pass filter function.

[0139] exist Figure 6B In the diagram, the dashed circles CIR1, CIR2, and CIR3 represent the theoretical converted pulse signal theo_Spul, the filtered and converted pulse signal flt_Spul, and the interference filtering signal Sgf1, respectively, corresponding to the interval (time point t4 to time point t5).

[0140] Next, the waveforms of the theoretically converted pulse signal theo_Spul and the filtered and converted pulse signal flt_Spul are compared. Please also refer to the waveforms of CIR1 and CIR2, selected by the dashed circles. During the interval (time point t4 to time point t5), the theoretically converted pulse signal theo_Spul is set to the supply voltage Vdd. On the other hand, during time point t4 to time point t5, the filtered and converted pulse signal flt_Spul cannot rise to the supply voltage Vdd. Conversely, during time point t4 to time point t5, the filtered and converted pulse signal flt_Spul is much lower than the theoretically converted pulse signal theo_Spul.

[0141] That is, if the hybrid logic filter 45 does not include a programmable resistor Rp and a capacitor C, the theoretically converted pulse signal theo_Spul can rapidly rise from the ground voltage Gnd to the supply voltage Vdd at time t4, and then fall from the supply voltage Vdd back to the ground voltage Gnd at time t5. On the other hand, if the hybrid logic filter 45 includes a programmable resistor Rp and a capacitor C, the programmable resistor Rp will significantly affect the turn-on speed between the supply voltage endpoint Vdd and the pulse conversion endpoint Ncnv. In this paper, the characteristic that the programmable resistor Rp can reduce the turn-on speed is utilized to suppress interference occurring during the effective signal period Tval.

[0142] Because the interval (time point t4-time point t5) is very short, and the rise rate of the filtered and converted pulse signal flt_Spul is affected by the programmable resistor Rp, the filtered and converted pulse signal flt_Spul cannot rise to the supply voltage Vdd before time point t5. Consequently, because the filtered and converted pulse signal flt_Spul does not rise to the supply voltage Vdd as theoretically as the converted pulse signal theo_Spul, the filtered and converted pulse signal flt_Spul can quickly drop to the ground voltage Gnd at time point t5.

[0143] In short, the theoretically converted pulse signal theo_Spul contains a series of short pulses during the effective signal period Tval. Furthermore, when a programmable resistor Rp and capacitor C are used, these short pulses are filtered and converted into broken and incomplete spikes in the filtered, converted pulse signal flt_Spul.

[0144] Similar to the filtered and converted pulse signal flt_Spul, the interference-removing signal Sgf1 has a negative pulse. Compare the waveforms of CIR2 and CIR3 at the dashed circle selection. The interference of the filtered and converted pulse signal flt_Spul at the dashed circle selection of CIR2 is higher than the interference of the interference-removing signal Sgf1 at the dashed circle selection of CIR3. Alternatively, the amplitude of the variation in the interference-removing signal Sgf1 is smaller than the amplitude of the variation in the filtered and converted pulse signal flt_Spul.

[0145] Transmission gate 471a includes a PMOS transistor and an NMOS transistor, both controlled by the filtered and converted pulse signal flt_Spul. When the controllable NOR gate 451 conducts the supply voltage Vdd to the pulse conversion terminal Ncnv (filtered and converted pulse signal flt_Spul = Vdd), the NMOS transistor in transmission gate 471a operates in the linear operating range, providing a low-impedance path for quickly generating the interference filtering signal Sgf1. Alternatively, when the controllable NOR gate 451 conducts the ground voltage Gnd to the pulse conversion terminal Ncnv (filtered and converted pulse signal flt_Spul = Gnd), the PMOS transistor in transmission gate 471a operates in the linear operating range, providing a low-impedance path for quickly generating the interference filtering signal Sgf1.

[0146] However, when the filtered and converted pulse signal flt_Spul is set to the intermediate voltage Vm during the interval, both the PMOS and NMOS transistors in the transmission gate 471a operate in the saturation region, providing a high-impedance path. Because the filtered and converted pulse signal flt_Spul (the input of transmission gate 471a) is set to the intermediate voltage Vm during the interval, the interference-filtered signal flt_Spul (the output of transmission gate 471a) is suppressed due to the high-impedance path. Therefore, the amplitude of the interference-filtered signal Sgf1 is relatively smaller than that of the filtered and converted pulse signal flt_Spul. Thus, comparing the filtered and converted pulse signal flt_Spul with the interference-filtered signal Sgf1 during the effective signal period Tval shows that the interference-filtered signal Sgf1 is smoother.

[0147] Compare the waveforms of the filtered and converted pulse signal flt_Spul, the interference-filtered signal Sgf1, and the inverted signal Sinv. As described above, after suppressing interference in the filtered and converted pulse signal flt_Spul, the transmission gate 471a generates the interference-filtered signal Sgf1. Subsequently, the inverter 471c inverts the interference-filtered signal Sgf1 to generate the inverted signal Sinv1. Therefore, the levels of the interference-filtered signal Sgf1 and the inverted signal Sinv1 are opposite to each other, and the inverted signal Sinv1 has a positive pulse. The interference in the interference-filtered signal Sgf1 is further filtered out by the inverter 471c, so the inverted signal Sinv1 during the effective signal period Tval is approximately equal to the supply voltage Vdd.

[0148] For a system design, interference is undesirable; therefore, interference filters 471 and 473 are used to gradually eliminate interference. The designs of interference filters 471 and 473 are similar, and the number of interference filters included in the interference filtering module 47 does not need to be limited. Figure 6B The waveforms show that during the period from time t1 to time t11, the positive pulse of the interference filtering signal Sgf2 is smoother than the positive pulse of the reverse signal Sinv1, and the smoothness of the sensing signal Sdet is higher than that of the interference filtering signal Sgf2. The sensing signal Sdet has a positive pulse. The positive pulse of the sensing signal Sdet has a clear rising edge and falling edge, therefore, the sensing signal Sdet is quite suitable for use in digital circuits.

[0149] The period from time point t10 to time point t11 ​​is considered the transition period. This period represents the transition from the presence of a signal to the absence of a signal (or signal loss). After time point t11, the waveform relationship is similar to that described above, and the details will not be elaborated further.

[0150] Please see Figure 7A This is a schematic diagram of another embodiment of a sequence signal sensor. Figures 6A-6B Similarly, the sequence signal sensor 50 includes a voltage comparison module 53, a hybrid logic filter 55, and an interference filtering module 57.

[0151] exist Figure 7A In the circuit, voltage comparison module 53 includes comparators 531 and 533; hybrid logic filter 55 includes input circuit 553, controllable NAND gate 551, and capacitor C. Input circuit 553 includes input inverters 553a and 553c. Input inverter 553a inverts the positive comparison signal Scmp_p to generate a complementary positive comparison signal Scmp_pb, and input inverter 553c inverts the negative comparison signal Scmp_n to generate a complementary negative comparison signal Scmp_nb.

[0152] The controllable NAND gate 551 further includes a pull-up circuit 551a and a pull-down circuit 551c. The pull-up circuit 551a provides a pull-up path; the pull-down circuit 551c provides a pull-down path. Both the pull-up circuit 551a and the pull-down circuit 551c are electrically connected to the input inverters 553a and 553c. The pull-up circuit 551a includes PMOS transistors Mu1' and Mu2' (pull-up transistors), and the pull-down circuit 551c includes a programmable resistor Rp' and NMOS transistors Md1' and Md2' (pull-down transistors).

[0153] In pull-up circuit 551a, the sources of PMOS transistors Mu1' and Mu2' are electrically connected to the supply voltage terminal (Vdd), and the drains of PMOS transistors Mu1' and Mu2' are electrically connected to programmable resistor Rp'. The gates of PMOS transistors Mu1' and Mu2' are electrically connected to input inverters 553a and 553c, respectively. PMOS transistor Mu1' is controlled by the complementary positive comparator signal Scmp_pb (output of input inverter 553a). PMOS transistor Mu2' is controlled by the complementary negative comparator signal Scmp_nb (output of input inverter 553c).

[0154] Since PMOS transistors Mu1' and Mu2' are connected in parallel, when either Mu1' or Mu2' is turned on, the filtered and converted pulse signal flt_Spul is pulled up to the supply voltage Vdd. When both Mu1' and Mu2' are turned off, the pull-up path is open, and the filtered and converted pulse signal flt_Spul is determined by the pull-down path.

[0155] In pull-down circuit 551c, the source of NMOS transistor Md1' is electrically connected to ground terminal Gnd, and the drain of NMOS transistor Md1' is electrically connected to the source of NMOS transistor Md2'. The drain of NMOS transistor Md2' is electrically connected to programmable resistor Rp'. Programmable resistor Rp' is electrically connected to pull-up circuit 551a, capacitor C, and interference filtering module 57. The gates of NMOS transistors Md1' and Md2' are electrically connected to input inverters 553a and 553c, respectively. NMOS transistor Md1' is controlled by complementary positive comparison signal Scmp_pb (output of input inverter 553a), and the gate of NMOS transistor Md2' is controlled by complementary negative comparison signal Scmp_nb (output of input inverter 553c).

[0156] Since NMOS transistors Md1' and Md2' are connected sequentially, if both the positive comparator signal Scmp_p and the negative comparator signal Scmp_n are set to low levels (Scmp_p = Scmp_n = L), the filtered and converted pulse signal flt_Spul is pulled down to the ground voltage Gnd. On the other hand, if either the positive comparator signal Scmp_p or the negative comparator signal Scmp_n is set to high levels (Scmp_p = H and / or Scmp_n = H), the filtered and converted pulse signal flt_Spul is pulled up to the supply voltage Vdd. Therefore, the input inverters 553a and 553c, PMOS transistors Mu1' and Mu2', and NMOS transistors Md1' and Md2' together perform an OR operation on the positive comparator signal Scmp_p and the negative comparator signal Scmp_n.

[0157] Table 6 summarizes the operations related to the hybrid logic filter 55.

[0158] Table 6

[0159]

[0160] Please note that, according to the definitions of the positive path comparison condition (ΔVshft_pn>Vth) and the negative path comparison condition (ΔVshft_np>Vth), in practical applications, the positive comparison signal Scmp_p and the negative comparison signal Scmp_n will not be set to the high level at the same time (Scmp_p=Scmp_n=H).

[0161] Please see Figure 7B , it is Figure 7A The waveform diagram of the sequence signal sensor is shown. The waveforms of the positive shift signal Shft_p, the negative shift signal Shft_n, the positive comparison signal Scmp_p, and the negative comparison signal Scmp_n are compared with... Figure 7A The embodiments are the same.

[0162] Since the input inverters 553a and 553c and the controllable NAND gate 551 jointly provide the OR operation, the filtered and converted pulse signal flt_Spul has a positive pulse. Accordingly, the waveforms of the filtered and converted pulse signal flt_Spul, the interference-filtered signal Sgf1, the inverted signal Sinv1, the interference-filtered signal Sgf2, and the sensing signal Sdet are similar to... Figure 6B The waveform is the opposite.

[0163] As shown in Table 1, the preset levels of the positive comparison signal Scmp_p and the negative comparison signal Scmp_n vary depending on the specific application. Figure 8A , Figure 8B , Figure 9A , Figure 9B In the embodiment, the preset levels of the positive comparison signal Scmp_p' and the negative comparison signal Scmp_n' are... Figure 6A , Figure 6B , Figure 7A , Figure 7B The opposite of the embodiments.

[0164] Please see Figure 8AThis is a schematic diagram illustrating an example of a hybrid logic filter. The operation of the hybrid logic filter 75 can be deduced by analogy from the preceding description, and will not be detailed here. In short, input inverter 633a inverts the positive comparison signal Scmp_p' to generate a complementary positive comparison signal Scmp_pb', and input inverter 633c inverts the negative comparison signal Scmp_n' to generate a complementary negative comparison signal Scmp_nb'. Then, the controllable NOR gate 451 performs a NOR operation on the complementary positive comparison signal Scmp_pb' and the complementary negative comparison signal Scmp_nb'. Overall, the input inverters 633a and 633c and the controllable NOR gate 451 within the hybrid logic filter 65 jointly perform an AND operation on the positive comparison signal Scmp_p' and the negative comparison signal Scmp_n'. Table 7 summarizes the operations performed by the hybrid logic filter 65.

[0165] Table 7

[0166]

[0167] Please see Figure 8B It is with Figure 8A The waveform diagram of the signal related to the hybrid logic filter is shown. Figure 8B In the diagram, the waveforms of the positive shift signal Shft_p and the negative shift signal Shft_n are compared with... Figure 6B Consistent, but Figure 8B The positive comparison signal Scmp_p' and the negative comparison signal Scmp_n' and Figure 6B The positive comparison signal Scmp_p is opposite to the negative comparison signal Scmp_n. Figure 8B In the process, because the hybrid logic filter 65 provides AND operations to the positive comparison signal Scmp_p' and the negative comparison signal Scmp_n', the filtered and converted pulse signal flt_Spul has a negative pulse. Because the interference occurs on the negative pulse, Figure 8A A programmable resistor Rp is placed in the pull-up path to delay the pull-up speed of interference.

[0168] Please see Figure 9A This is a schematic diagram illustrating another example of a hybrid logic filter. The operation of the hybrid logic filter 75 can be derived from the foregoing description and will not be detailed here. In short, the hybrid logic filter 75 performs a NAND operation on the positive comparison signal Scmp_p' and the negative comparison signal Scmp_n'. Table 8 summarizes the operations performed by the hybrid logic filter 75.

[0169] Table 8

[0170]

[0171] Please see Figure 9B It is with Figure 9A The waveform diagram of the signal related to the hybrid logic filter is shown. Figure 9B In the diagram, the waveforms of the positive shift signal Shft_p and the negative shift signal Shft_n are compared with... Figure 7B The waveforms of the positive shift signal Sshft_p and the negative shift signal Sshft_n are the same, but the waveforms of the positive comparison signal Scmp_p' and the negative comparison signal Scmp_n' are different. Figure 7B The waveforms of the positive comparison signal Scmp_p and the negative comparison signal Scmp_n are opposite. Figure 9B In the process, because the hybrid logic filter 75 provides NAND operation to the positive comparison signal Scmp_p' and the negative comparison signal Scmp_n', the filtered and converted pulse signal flt_Spul has a positive pulse. Because interference occurs during the positive pulse, Figure 8B A programmable resistor Rp is set in the pull-down path to delay the pull-down speed of interference.

[0172] Based on the foregoing description, the circuit and logic operation of a hybrid logic filter can be designed arbitrarily. Table 9 briefly summarizes the aforementioned embodiments.

[0173] Table 9

[0174]

[0175] When the filtered and converted pulse signal flt_Spul has a negative pulse (such as...) Figure 6B , Figure 8B When (as shown), the programmable resistor Rp is set in the pull-up path (e.g., Figure 6A , Figure 8A (As shown). This reduces the rise rate of interference in the filtered and converted pulse signal flt_Spul. By setting a programmable resistor Rp in the pull-up path, multiple downward interferences in Tval during the effective signal period of the negative pulse can be suppressed.

[0176] When the filtered and converted pulse signal flt_Spul has a positive pulse (such as...) Figure 7B , Figure 9B When (as shown), the programmable resistor Rp is set in the pull-down path (e.g., ...). Figure 7A , Figure 9A As shown, this is used to slow down the rate of decrease of interference in the filtered and converted pulse signal flt_Spul. By setting a programmable resistor Rp in the pull-down path, multiple downward interferences in Tval during the effective signal period of the positive pulse can be suppressed.

[0177] Because this disclosure allows for free selection of the internal settings of the alignment offsetter, reference voltage supply circuit, comparator, and controllable logic gate, the sequence signal sensor can dynamically sense different types of sequence input signals according to the setting of the protocol selection signal Spsel. Based on this design, the sequence signal sensor of this disclosure can be flexibly applied to different types of sequence communication protocols. For example, noise suppression sensing for PCIe, OOB sensing for SATA, LFPS sensing for USB, and LOS sensing for Ethernet.

[0178] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A sequence signal sensor, comprising: A voltage comparison module receives a differential signal pair comprising a first shift signal and a second shift signal, wherein the voltage comparison module comprises: A first comparator generates a first comparison signal based on the first shift signal, the second shift signal, and a voltage threshold; and A second comparator that generates a second comparison signal based on the first shift signal, the second shift signal, and the voltage threshold; and A hybrid logic filter, electrically connected to the first comparator and the second comparator, includes: A controllable logic gate generates a filtered and converted pulse signal at a pulse conversion terminal in response to a logic operation, wherein the logic operation is related to a first comparison signal and a second comparison signal, and the controllable logic gate comprises: A pull-up circuit is electrically connected to the pulse conversion terminal and a supply voltage terminal having a supply voltage, which selectively conducts the supply voltage to the pulse conversion terminal; as well as A pull-down circuit is electrically connected to the pulse conversion terminal and a ground terminal having a ground voltage, which selectively conducts the ground voltage to the pulse conversion terminal, wherein the supply voltage is higher than the ground voltage, and the pull-up circuit and the pull-down circuit are alternately turned on in response to the first comparison signal and the second comparison signal; as well as A capacitor is electrically connected to the pulse conversion terminal, wherein when the logic operation is performed, the controllable logic gate and the capacitor together perform an initial filtering operation on the filtered and converted pulse signal.

2. The sequence signal sensor as claimed in claim 1, wherein the logic operation is a NOR operation, a NAND operation, an AND operation, or an OR operation.

3. The sequence signal sensor of claim 1, wherein the pull-up circuit comprises: A first pull-up transistor, comprising: A first terminal, a second terminal, and a control terminal, wherein the first terminal of the first pull-up transistor is electrically connected to the supply voltage terminal, and the first pull-up transistor is selectively turned on in response to the first comparison signal; and A second pull-up transistor, comprising: The device includes a first terminal, a second terminal, and a control terminal, wherein the second pull-up transistor is selectively turned on in response to the second comparison signal.

4. The sequence signal sensor as claimed in claim 3, wherein, The second terminal of the first pull-up transistor is electrically connected to the first terminal of the second pull-up transistor, wherein, When both the first pull-up transistor and the second pull-up transistor are on, the pull-up circuit conducts the supply voltage to the pulse conversion terminal, and When at least one of the first pull-up transistor and the second pull-up transistor is disconnected, the pull-down circuit transmits the ground voltage to the pulse conversion terminal.

5. The sequence signal sensor of claim 4, wherein the pull-up circuit further comprises: A resistor includes a first terminal and a second terminal, wherein, The first end of the resistor is electrically connected to the second end of the second pull-up transistor, and The second end of the resistor is electrically connected to the pulse conversion terminal.

6. The sequence signal sensor of claim 5, wherein the resistance value of the resistor is adjusted in response to a protocol selection signal, and the protocol selection signal represents one of the following: Universal Serial Bus protocol, Serial Advanced Technology Attachment protocol, Fast Peripheral Component Interconnect Standard protocol, and Ethernet protocol.

7. The sequence signal sensor as claimed in claim 3, wherein, The second terminal of the first pull-up transistor is electrically connected to the pulse switching terminal, and The first and second terminals of the second pull-up transistor are electrically connected to the supply voltage terminal and the pulse conversion terminal, respectively. When at least one of the first pull-up transistor and the second pull-up transistor is turned on, the pull-up circuit conducts the supply voltage to the pulse switching terminal, and When both the first pull-up transistor and the second pull-up transistor are off, the pull-down circuit conducts the ground voltage to the pulse conversion terminal.

8. The sequence signal sensor of claim 3, wherein the hybrid logic filter further comprises: A first input inverter, electrically connected to the control terminal of the first comparator and the first pull-up transistor, inverts the first comparison signal to generate a first complementary comparison signal, and then transmits the first complementary comparison signal to the first pull-up transistor; and A second input inverter, electrically connected to the control terminal of the second comparator and the second pull-up transistor, inverts the second comparison signal to generate a second complementary comparison signal, and then transmits the second complementary comparison signal to the second pull-up transistor.

9. The sequence signal sensor of claim 1, wherein the pull-down circuit comprises: A first pull-down transistor includes: a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first pull-down transistor is electrically connected to the ground terminal, and the first pull-down transistor is selectively turned on in response to a first comparison signal; and A second pull-down transistor includes: a first terminal, a second terminal and a control terminal, wherein the second pull-down transistor is selectively turned on in response to the second comparison signal.

10. The sequence signal sensor of claim 9, wherein, The second terminal of the first pull-down transistor is electrically connected to the pulse conversion terminal, and The first and second terminals of the second pull-down transistor are electrically connected to the ground terminal and the pulse conversion terminal, respectively. When both the first pull-down transistor and the second pull-down transistor are off, the pull-up circuit conducts the supply voltage to the pulse conversion terminal, and When at least one of the first pull-down transistor and the second pull-down transistor is turned on, the pull-down circuit conducts the ground voltage to the pulse conversion terminal.

11. The sequence signal sensor of claim 9, wherein, The second terminal of the first pull-down transistor is electrically connected to the first terminal of the second pull-down transistor, wherein, When at least one of the first pull-down transistor and the second pull-down transistor is disconnected, the pull-up circuit conducts the supply voltage to the pulse switching terminal, and When both the first pull-down transistor and the second pull-down transistor are turned on, the pull-down circuit conducts the ground voltage to the pulse conversion terminal.

12. The sequence signal sensor of claim 11, wherein the pull-down circuit further comprises: A resistor includes a first terminal and a second terminal, wherein the first terminal of the resistor is electrically connected to the second terminal of the second pull-down transistor, and the second terminal of the resistor is electrically connected to the pulse conversion terminal.

13. The sequence signal sensor of claim 12, wherein the resistance value of the resistor is adjusted in response to a protocol selection signal, and the protocol selection signal represents one of the following: Universal Serial Bus protocol, Serial Advanced Technology Attachment protocol, Fast Peripheral Component Interconnect Standard protocol, and Ethernet protocol.

14. The sequence signal sensor of claim 9, wherein the hybrid logic filter further comprises: A first input inverter, electrically connected to the control terminal of the first comparator and the first pull-down transistor, inverts the first comparison signal to generate a first complementary comparison signal and transmits the first complementary comparison signal to the first pull-down transistor; and A second input inverter, electrically connected to the control terminal of the second comparator and the second pull-down transistor, inverts the second comparison signal to generate a second complementary comparison signal and transmits the second complementary comparison signal to the second pull-down transistor.

15. The sequence signal sensor of claim 1, further comprising: An interference filter, comprising: A transmission gate, electrically connected to the pulse conversion terminal, performs a first-order second-order filtering operation on the filtered and converted pulse signal, thereby generating an interference-filtering signal; and An inverter, electrically connected to the transmission gate, reverses the interference-filtered signal to generate a first reverse signal.

16. The sequence signal sensor of claim 1, wherein the voltage threshold is the voltage difference between a first reference voltage and a second reference voltage, wherein the first reference voltage and the second reference voltage are DC voltages, and the first reference voltage is higher than the second reference voltage.

17. The sequence signal sensor of claim 16, wherein, The first comparator receives the first shift signal, the second shift signal, the first reference voltage, and the second reference voltage, wherein... When the voltage difference between the first shift signal and the second shift signal is greater than the voltage threshold, the first comparator sets the first comparison signal as a first threshold, and When the voltage difference between the first shift signal and the second shift signal is less than or equal to the voltage threshold, the first comparator sets the first comparison signal to a second level.

18. The sequence signal sensor of claim 16, wherein, The second comparator receives the first shift signal, the second shift signal, the first reference voltage, and the second reference voltage, wherein... When the voltage difference between the second shift signal and the first shift signal is greater than the voltage threshold, the second comparator sets the second comparison signal to a first threshold, and When the voltage difference between the second shift signal and the first shift signal is less than or equal to the voltage threshold, the second comparator sets the second comparison signal to a second level.

19. A differential signal sensing method applied to a receiver, comprising the following steps: Receive a differential signal pair comprising a first shift signal and a second shift signal; A first comparison signal and a second comparison signal are generated based on the first shift signal, the second shift signal, and a voltage threshold; Perform a logical operation related to the first comparison signal and the second comparison signal; When performing the logic operation, a supply voltage is alternately turned on to a pulse switching terminal or a ground voltage is conducted to the pulse switching terminal in response to the first comparison signal and the second comparison signal, wherein the supply voltage is higher than the ground voltage; A filtered and converted pulse signal is generated at the pulse conversion endpoint according to the aforementioned logic operation; as well as When performing the aforementioned logical operation, an initial filtering operation is performed on the filtered and converted pulse signal.

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