A topology, simulation method and apparatus of a DDR circuit

Abstract

The application relates to a DDR circuit topology structure, a simulation method and a device, the structure comprising a main controller, a transmission line, a plurality of particle loads, a terminating resistor and a reference plane; a plurality of guide holes are arranged on the positive and negative planes of the reference plane, the particle loads are installed in the guide holes and are connected through the transmission line; the initial end of the transmission line is connected with the main controller, and the terminal end of the transmission line is connected with the terminating resistor. The DDR circuit topology structure constructed by the application can realize small-space optimization of DDR4 address signal quality without increasing the layout area and the wiring layer number, is favorable for improving the DDR signal rate, and thus improves the product performance.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and in particular to a topology, simulation method and apparatus for a DDR circuit. Background Technology

[0002] To meet product performance requirements, when designing onboard DDR4 (the next-generation memory specification), a large capacity for DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is often necessary. Due to manufacturing process limitations, a large capacity necessitates placing numerous DRAM chips on the PCB (Printed Circuit Board). Since address signals typically use a daisy-chain topology, the increased capacitive load from numerous DRAM chips can cause severe multiple negative reflections, resulting in insufficient DDR4 address signal speeds. This often leads to low or unstable DDR operating speeds in product designs. Currently, DDR4 signal speeds have reached 3200Mbps, and the quality of address signal design has become a bottleneck affecting DDR4 speed improvement. Therefore, designing a good address signal routing topology is crucial for improving DDR4 performance. Existing technologies, such as top-to-bottom DRAM chip placement with two DRAM chips in the same location, result in large capacitive loads at single points. Furthermore, due to space constraints in the actual layout, the optimization of DRAM surface branch length is limited, leading to generally poor SI (Signal Integrity Quality) characteristics.

[0003] Therefore, there is an urgent need to propose a DDR circuit topology, simulation method, and device that can optimize the quality of DDR4 address signals, improve DDR signal rates, and thus enhance product performance. Summary of the Invention

[0004] Based on this, it is necessary to provide a DDR circuit topology, simulation method, and apparatus that can optimize DDR4 address signal quality, improve DDR signal rate, and thus enhance product performance, in order to address the aforementioned technical problems.

[0005] The first aspect of the present invention provides a topology for a DDR circuit, the structure including a main controller, transmission lines, a plurality of chip loads, terminating resistors and a reference plane;

[0006] The reference plane has several guide holes on its front and back surfaces. The particle load is installed in the guide holes and connected through the transmission line.

[0007] The beginning of the transmission line is connected to the main controller, and the end of the transmission line is connected to the terminating resistor.

[0008] In one embodiment, the method further includes: the number of particle loads corresponds one-to-one with the number of guide holes; the particle loads located on the front plane of the reference plane are defined as top-layer particle loads, and the particle loads located on the back plane of the reference plane are defined as bottom-layer particle loads; the number of bottom-layer particle loads is n, and the number of top-layer particle loads is n+1, where n is a positive integer.

[0009] In one embodiment, the method further includes: a first transmission line connecting the top-layer particle load and a second transmission line connecting the bottom-layer particle load are connected through a through hole disposed at one end of the reference plane; the main controller is disposed at the beginning of the first transmission line; the termination resistor is disposed at the end of the second transmission line; and the through hole is disposed at the end of the first transmission line and the beginning of the second transmission line.

[0010] In one embodiment, the method further includes: the first via selection point corresponding to the top layer particle load and the selection point of the termination resistor are symmetrically distributed based on the reference plane, and the other via selection points corresponding to the top layer particle load and the via selection points corresponding to the bottom layer particle load are symmetrically distributed one by one, and the two symmetrically distributed vias are not interconnected.

[0011] A second aspect of the present invention provides a simulation method for a DDR circuit, the method comprising:

[0012] Step A: Perform reflection simulation on the topology of the DDR circuit to obtain the first position in the transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position;

[0013] Step B: Based on the impedance value corresponding to the first position, obtain the diameter and depth of the guide hole closest to the first position;

[0014] Step C: Based on the aperture and depth, drill holes at the corresponding positions of the reference plane, and install the particle load to generate the final DDR circuit topology.

[0015] In one embodiment, the method for determining the via location includes: simulating and obtaining the line spacing and line width of the DDR circuit based on relevant topologies and preset impedance values ​​in a historical database; determining the via location based on the line spacing and line width of the DDR circuit; and generating an initial DDR circuit topology based on the via location.

[0016] In one embodiment, the method further includes: performing reflection simulation on the topology of the DDR circuit to obtain a first position in the transmission line where the impedance value is lower than a first preset value and the impedance value corresponding to the first position, which includes: performing reflection simulation on the initial DDR circuit topology to monitor whether the impedance of the target transmission line connected to the particle load is continuous; and determining the first position in the target transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position when the impedance of the target transmission line is detected to be discontinuous.

[0017] In one embodiment, the method further includes: obtaining the aperture and depth of the nearest bore at the first position based on the impedance value corresponding to the first position includes: determining the aperture and depth of the nearest bore at the first position based on the impedance value corresponding to the first position through simulation when the target impedance value of the target transmission line is equal to the preset impedance value.

[0018] A third aspect of the present invention provides a simulation apparatus for a DDR circuit, the apparatus comprising:

[0019] The first determining module is used to perform reflection simulation on the topology of the DDR circuit to obtain the first position in the transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position.

[0020] The second determining module is used to obtain the diameter and depth of the guide hole closest to the first position based on the impedance value corresponding to the first position.

[0021] The structure generation module is used to drill holes at the corresponding guide hole positions on the reference plane based on the hole diameter and hole depth, and install the particle load to generate the final DDR circuit topology.

[0022] In another aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0023] Step A: Perform reflection simulation on the topology of the DDR circuit to obtain the first position in the transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position;

[0024] Step B: Based on the impedance value corresponding to the first position, obtain the diameter and depth of the guide hole closest to the first position;

[0025] Step C: Based on the aperture and depth, drill holes at the corresponding positions of the reference plane, and install the particle load to generate the final DDR circuit topology.

[0026] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0027] Step A: Perform reflection simulation on the topology of the DDR circuit to obtain the first position in the transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position;

[0028] Step B: Based on the impedance value corresponding to the first position, obtain the diameter and depth of the guide hole closest to the first position;

[0029] Step C: Based on the aperture and depth, drill holes at the corresponding positions of the reference plane, and install the particle load to generate the final DDR circuit topology.

[0030] The aforementioned DDR circuit topology, simulation method, and apparatus include a main controller, transmission lines, a plurality of chip loads, terminating resistors, and a reference plane. A plurality of vias are provided on both the front and back planes of the reference plane. The chip loads are installed in the vias and connected via the transmission lines. The beginning of the transmission lines is connected to the main controller, and the end of the transmission lines is connected to the terminating resistors. The DDR circuit topology constructed in this application can achieve optimized DDR4 address signal quality in a small space without increasing the layout area and the number of wiring layers, which is beneficial for improving DDR signal rates and thus enhancing product performance. Attached Figure Description

[0031] Figure 1 This is a block diagram of the topology of a DDR circuit in one embodiment;

[0032] Figure 2 This is a schematic diagram of the existing topology layout of a DDR circuit in one embodiment;

[0033] Figure 3 This is a schematic diagram of an optimized topology layout for a DDR circuit in one embodiment.

[0034] Figure 4 This is a schematic diagram of the wiring cross-section of a conventional scheme for the topology of a DDR circuit in one embodiment;

[0035] Figure 5 This is a schematic diagram of the wiring cross-section of an optimized topology scheme for a DDR circuit in one embodiment.

[0036] Figure 6 This is a diagram illustrating the application environment of a simulation method for a DDR circuit in one embodiment.

[0037] Figure 7This is a flowchart illustrating a simulation method for a DDR circuit in one embodiment;

[0038] Figure 8 This is a schematic diagram of the experimental materials for the topology, simulation method, and apparatus of a DDR circuit in one embodiment;

[0039] Figure 9 This is a schematic diagram of the first experimental results of the topology, simulation method, and apparatus of a DDR circuit in one embodiment;

[0040] Figure 10 This is a schematic diagram of the second experimental results of the topology, simulation method, and apparatus of the DDR circuit in one embodiment;

[0041] Figure 11 This is a schematic diagram of the third experimental results of the topology, simulation method, and apparatus of the DDR circuit in one embodiment;

[0042] Figure 12 This is a schematic diagram of the fourth experimental results for the topology, simulation method, and apparatus of the DDR circuit in one embodiment;

[0043] Figure 13 This is a structural block diagram of a simulation device for a DDR circuit in one embodiment;

[0044] Figure 14 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] It should be understood that, in the description of this application, unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0047] It should also be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0048] It should be noted that the terms "S1," "S2," etc., are used only for descriptive purposes and do not specifically refer to the order or sequence, nor are they intended to limit this application. They are merely for the convenience of describing the method of this application and should not be construed as indicating the sequential order of the steps. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0049] As can be seen from the background technology, the existing technology of placing two DRAM chips in the same position with the top and bottom of the DRAM chip in a top-to-bottom layout results in a large capacitive load at a single point. At the same time, due to the limitations of the actual layout space, the optimization of the DRAM surface branch length is limited, and the SI (signal integrity quality) characteristics of the existing technology are generally poor.

[0050] To address the aforementioned technical problems, this application provides a DDR circuit topology, simulation method, and apparatus that can optimize DDR4 address signal quality, improve DDR signal rate, and thus enhance product performance.

[0051] This application provides a simulation method for DDR circuits, which can be applied to, for example... Figure 6 In the application environment shown, terminal 102 communicates with a data processing platform set on server 104 via a network. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. Server 104 can be implemented as a standalone server or a server cluster consisting of multiple servers.

[0052] Example 1

[0053] In one embodiment, such as Figure 1-5 As shown, a topology of a DDR circuit is provided, which includes a main controller, transmission lines, several chip loads, termination resistors, and a reference plane.

[0054] The reference plane has several guide holes on its front and back surfaces. The particle load is installed in the guide holes and connected through the transmission line.

[0055] The beginning of the transmission line is connected to the main controller, and the end of the transmission line is connected to the terminating resistor.

[0056] In one embodiment, the number of particle loads corresponds one-to-one with the number of guide holes. The particle loads located on the front plane of the reference plane are defined as the top particle loads, and the particle loads located on the back plane of the reference plane are defined as the bottom particle loads. The number of bottom particle loads is n, and the number of top particle loads is n+1, where n is a positive integer.

[0057] In one embodiment, a first transmission line connecting the top-level particle load and a second transmission line connecting the bottom-level particle load are connected through a through-hole disposed at one end of the reference plane. The main controller is disposed at the beginning of the first transmission line, the termination resistor is disposed at the end of the second transmission line, and the through-hole is disposed at the end of the first transmission line and the beginning of the second transmission line.

[0058] In one embodiment, the selection point of the first via corresponding to the top-layer particle load and the selection point of the termination resistor are symmetrically distributed based on the reference plane. The selection points of the remaining vias corresponding to the top-layer particle load and the selection points of the vias corresponding to the bottom-layer particle load are symmetrically distributed one by one, and the two symmetrically distributed vias are not interconnected.

[0059] Specifically, such as Figure 1-5 As shown, the aforementioned chip load is DRAMX in the diagram, where X represents an Arabic numeral, SkipviaY represents an Arabic numeral, the first transmission line is L3, the second transmission line is L10, the via is PTHvia1, and the reference plane is the PCB plane. Specifically, the DRAM chips are evenly distributed on both sides of the PCB, with one more chip on the top layer than on the bottom layer. This differs from existing solutions that use vias to connect the top and bottom chips (e.g., ...). Figure 2 The 2*4+1 layout scheme shown in the figure is compared with that of this application (as shown in the figure). Figure 3 As shown, a 1+2*4 particle layout scheme is adopted. Preferably, the terminating resistor is placed opposite the controller and pulled up to the 0.6V power supply.

[0060] Furthermore, because the top and bottom particles in the existing scheme cannot share a through hole (e.g. Figure 4 As shown), SkipVIA technology is required. Specifically, the signal runs from the main controller fanout to L3. The top-layer DRAM chips are connected to the L3 trace via SkipVIA from L1 to L3, and each chip is sequentially connected to the top-layer DRAM. After the last chip in the top layer, a via is used to connect to the bottom layer on L10. The bottom-layer DRAM chips are connected to the L10 trace via SkipVIA from L12 to L10 (e.g., ...). Figure 5 As shown), each chip is sequentially connected to the underlying DRAM. Preferably, the chip closest to the main controller is terminated with a 33-ohm pull-up to a 0.6V power supply. This allows the solution to be implemented without increasing layout space or wiring layers.

[0061] As a preferred implementation, in this embodiment of the invention, the specific steps for obtaining the via diameter and depth through simulation based on the above-described DDR circuit topology include:

[0062] The topology of the DDR circuit is subjected to reflection simulation to obtain the first position in the transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position.

[0063] Based on the impedance value corresponding to the first position, obtain the diameter and depth of the guide hole closest to the first position;

[0064] Based on the aperture and depth, the corresponding guide hole positions on the reference plane are drilled, and the particle load is installed to generate the final DDR circuit topology.

[0065] In a preferred embodiment of the present invention, the specific steps of the method for determining the guide hole position include:

[0066] Based on the relevant topology and preset impedance values ​​in the historical database, the line spacing and line width of the DDR circuit are obtained through simulation.

[0067] The via positions are determined based on the line spacing and line width of the DDR circuit, and an initial DDR circuit topology is generated based on the via positions.

[0068] As a preferred implementation, in this embodiment of the invention, the specific steps for obtaining the first position and the impedance value at the first position include:

[0069] A reflection simulation was performed on the initial DDR circuit topology to monitor whether the impedance of the target transmission line connected to the particle load was continuous.

[0070] In response to detecting an impedance discontinuity in the target transmission line, a first position in the target transmission line where the impedance value is lower than a first preset value and the impedance value corresponding to the first position are determined.

[0071] In a preferred embodiment of the present invention, the specific steps for obtaining the diameter and depth of the guide hole include:

[0072] Based on the impedance value corresponding to the first position, the simulation determines the aperture and depth of the guide hole closest to the first position when the target impedance value of the target transmission line is equal to the preset impedance value.

[0073] In the aforementioned DDR circuit topology, the structure includes a main controller, transmission lines, several DRAM loads, terminating resistors, and a reference plane. Several vias are provided on both the front and back planes of the reference plane. The DRAM loads are mounted in the vias and connected via the transmission lines. The beginning of the transmission line is connected to the main controller, and the end of the transmission line is connected to the terminating resistors. This application addresses the issue that negative reflections of the DDR4 address control signal can easily cause voltage discrepancies, leading to insufficient chip voltage. Therefore, it proposes a routing method using SkipVIA PCB technology with a single-point, single-load series DRAM load, such as D... The RAM chips employ a single-point series connection to reduce capacitive load at single points, thereby reducing single negative reflection voltage. The stack-up design limits the thickness of the dielectric layer from the top layer to the third dielectric layer on both sides to no more than 8 mil to meet the DFM requirements of the SkipVIAPCB process design. Using SkipVIAPCB technology ensures that vias on the top and bottom layers do not overlap, and the single-point, single-load series topology eliminates the need to increase layout area or the number of routing layers. Based on this, this application can optimize DDR4 address signal quality in a small space without increasing layout area or the number of routing layers, which is beneficial for improving DDR circuit signal rates and thus enhancing product performance.

[0074] Example 2

[0075] In one embodiment, such as Figure 7 As shown, a simulation method for a DDR circuit is provided, which can be applied to... Figure 6 Taking the terminal in the example, the explanation includes the following steps:

[0076] S1: Perform reflection simulation on the topology of the DDR circuit to obtain the first position in the transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position.

[0077] It should be noted that the DDR circuit topology described in this embodiment is a layout scheme based on Embodiment 1. The specific scheme for this step is as follows:

[0078] A reflection simulation was performed on the initial DDR circuit topology to monitor whether the impedance of the target transmission line connected to the particle load was continuous.

[0079] In response to detecting an impedance discontinuity in the target transmission line, a first position in the target transmission line where the impedance value is lower than a first preset value and the impedance value corresponding to the first position are determined.

[0080] The specific steps of the method for generating the initial DDR circuit topology are as follows:

[0081] Based on the relevant topology and preset impedance values ​​in the historical database, the line spacing and line width of the DDR circuit are obtained by simulation. The relevant topology is the relevant structural scheme described in Example 1 that is pre-stored in the database. The preset impedance value is a value set according to actual needs, such as 33 ohms. The line spacing and line width of the DDR circuit are determined by simulation based on the above topology and preset impedance values.

[0082] The via positions are determined based on the line spacing and line width of the DDR circuit. Since the number of chips is generally odd and the number of vias is the same as the number of chips, the vias can be evenly distributed on the DDR circuit with the determined line spacing and line width. Furthermore, an initial DDR circuit topology is generated based on the via positions.

[0083] S2: Based on the impedance value corresponding to the first position, obtain the diameter and depth of the guide hole closest to the first position.

[0084] It should be noted that the presence of vias causes a drop in impedance at the via location. This impedance value is lower than the normal impedance, resulting in impedance discontinuity in the target transmission line and affecting the signal integrity of the DDR circuit. Therefore, to ensure the signal integrity of the DDR circuit, it is necessary to determine the location of vias where the target transmission line impedance is lower than the normal impedance. Specifically:

[0085] Based on the impedance value corresponding to the first position, the position of the nearest via at the first position is obtained, and the aperture and depth of the nearest via at the first position are determined by simulation when the target impedance value of the target transmission line is equal to the preset impedance value.

[0086] S3: Based on the aperture and depth, drill holes at the corresponding guide hole positions on the reference plane, and install the particle load to generate the final DDR circuit topology.

[0087] The above-mentioned simulation method for DDR circuit includes: performing reflection simulation on the topology of the DDR circuit to obtain a first position in the transmission line where the impedance value is lower than a first preset value and the impedance value corresponding to the first position; obtaining the aperture and depth of the via closest to the first position based on the impedance value corresponding to the first position; performing hole drilling on the via position corresponding to the reference plane based on the aperture and depth, and installing the chip load to generate the final DDR circuit topology. This application determines the aperture and depth of the via through simulation, thereby generating the final DDR circuit topology, further improving the integrity of signal transmission, optimizing the quality of DDR4 address signals, and improving the signal rate of the DDR circuit, thereby further improving product performance.

[0088] It should be understood that, although Figure 7 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 7 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0089] Example 3

[0090] like Figure 8-12 As shown, in order to verify the actual application effect of this application, the deployment of the scheme of this application and the existing scheme are compared and tested, and the results obtained from the experiment are analyzed.

[0091] Specifically, such as Figure 8 As shown, taking 9 x 8 DDR4 DRAM chips as an example, an 8-layer PCB design is used with ordinary FR4 material. To meet the SkipVIA process requirements, the thickness of L1-L3 needs to be less than 8mil. Nine DRAM chips are set, with L3 layer traces connecting the top 5 DRAM chips and L6 layer connecting the bottom 4 DRAM chips. Address signals are traced across two layers (L3 & L6). Finally, a 33ohm terminating resistor is placed on the opposite side of the chips (L6) to pull up a 0.6V power supply. The branch length of the terminating resistor must be less than 500mil. The length of all SkipVIA vias is less than 10mil, minimizing capacitive load introduced by the vias. Simulation comparison verifies the voltage and eye diagram signal quality of each DRAM chip in the conventional scheme and this optimized scheme. Figure 9-12 As can be seen from the data, after adopting the single-point, single-load series routing scheme, the signal eye diagram quality of the DRAM closest to the controller (the chip closest to the main controller has the most reflections and is the chip with the worst signal) is significantly improved by 16.9%. Figure 9-12 The following table shows the waveform before improvement, the waveform after improvement, the eye image before improvement, and the eye image after improvement, respectively. The specific comparison data is as follows:

[0092]

[0093] In summary, the multiple high-voltage negative reflections at the load location are optimized to twice the number of low-voltage negative reflections. Since the negative reflections do not overlap in time after optimization, the negative reflection voltage is reduced. Experimental results show that the single-point DRAM load of the improved topology is reduced by half, and the via capacitance of SkipVIA is further reduced compared to the existing solution. The overall single-point load is reduced by more than 1 / 2. This application has made significant improvements compared to the existing technology.

[0094] Example 4

[0095] In one embodiment, such as Figure 13 As shown, a simulation device for a DDR circuit is provided, comprising: a first determining module, a second determining module, and a structure generation module, wherein:

[0096] The first determining module is used to perform reflection simulation on the topology of the DDR circuit to obtain the first position in the transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position.

[0097] The second determining module is used to obtain the diameter and depth of the guide hole closest to the first position based on the impedance value corresponding to the first position.

[0098] The structure generation module is used to drill holes at the corresponding guide hole positions on the reference plane based on the hole diameter and hole depth, and install the particle load to generate the final DDR circuit topology.

[0099] In a preferred embodiment of the present invention, the first determining module is specifically used for:

[0100] Based on the relevant topology and preset impedance values ​​in the historical database, the line spacing and line width of the DDR circuit are obtained through simulation.

[0101] The via positions are determined based on the line spacing and line width of the DDR circuit, and an initial DDR circuit topology is generated based on the via positions.

[0102] In a preferred embodiment of the present invention, the first determining module is further configured to:

[0103] A reflection simulation was performed on the initial DDR circuit topology to monitor whether the impedance of the target transmission line connected to the particle load was continuous.

[0104] In response to detecting an impedance discontinuity in the target transmission line, a first position in the target transmission line where the impedance value is lower than a first preset value and the impedance value corresponding to the first position are determined.

[0105] In a preferred embodiment of the present invention, the second determining module is specifically used for:

[0106] Based on the impedance value corresponding to the first position, the simulation determines the aperture and depth of the guide hole closest to the first position when the target impedance value of the target transmission line is equal to the preset impedance value.

[0107] Specific limitations regarding the DDR circuit simulation device can be found in the above description of the DDR circuit simulation method, and will not be repeated here. Each module in the aforementioned DDR circuit simulation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the processor in the computer device, or stored in software in the computer device's memory, so that the processor can call and execute the operations corresponding to each module.

[0108] Example 5

[0109] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 14 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a DDR circuit simulation method. The display screen can be an LCD screen or an e-ink display screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0110] Those skilled in the art will understand that Figure 14 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0111] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0112] S1: Perform reflection simulation on the topology of the DDR circuit to obtain the first position in the transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position;

[0113] S2: Based on the impedance value corresponding to the first position, obtain the diameter and depth of the guide hole closest to the first position;

[0114] S3: Based on the aperture and depth, drill holes at the corresponding guide hole positions on the reference plane, and install the particle load to generate the final DDR circuit topology.

[0115] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0116] Based on the relevant topology and preset impedance values ​​in the historical database, the line spacing and line width of the DDR circuit are obtained through simulation.

[0117] The via positions are determined based on the line spacing and line width of the DDR circuit, and an initial DDR circuit topology is generated based on the via positions.

[0118] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0119] A reflection simulation was performed on the initial DDR circuit topology to monitor whether the impedance of the target transmission line connected to the particle load was continuous.

[0120] In response to detecting an impedance discontinuity in the target transmission line, a first position in the target transmission line where the impedance value is lower than a first preset value and the impedance value corresponding to the first position are determined.

[0121] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0122] Based on the impedance value corresponding to the first position, the simulation determines the aperture and depth of the guide hole closest to the first position when the target impedance value of the target transmission line is equal to the preset impedance value.

[0123] Example 6

[0124] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0125] S1: Perform reflection simulation on the topology of the DDR circuit to obtain the first position in the transmission line where the impedance value is lower than the first preset value and the impedance value corresponding to the first position;

[0126] S2: Based on the impedance value corresponding to the first position, obtain the diameter and depth of the guide hole closest to the first position;

[0127] S3: Based on the aperture and depth, drill holes at the corresponding guide hole positions on the reference plane, and install the particle load to generate the final DDR circuit topology.

[0128] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0129] Based on the relevant topology and preset impedance values ​​in the historical database, the line spacing and line width of the DDR circuit are obtained through simulation.

[0130] The via positions are determined based on the line spacing and line width of the DDR circuit, and an initial DDR circuit topology is generated based on the via positions.

[0131] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0132] A reflection simulation was performed on the initial DDR circuit topology to monitor whether the impedance of the target transmission line connected to the particle load was continuous.

[0133] In response to detecting an impedance discontinuity in the target transmission line, a first position in the target transmission line where the impedance value is lower than a first preset value and the impedance value corresponding to the first position are determined.

[0134] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0135] Based on the impedance value corresponding to the first position, the simulation determines the aperture and depth of the guide hole closest to the first position when the target impedance value of the target transmission line is equal to the preset impedance value.

[0136] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A topology of a DDR circuit, characterized in that, The structure comprises a main controller, a transmission line, a plurality of particle loads, a terminating resistor and a reference plane; A plurality of guide holes are arranged on the positive and negative planes of the reference plane, the particle loads are installed in the guide holes and are connected through the transmission line; The beginning end of the transmission line is connected with the main controller, and the ending end of the transmission line is connected with the terminating resistor; The number of the particle loads corresponds to the number of the guide holes, the particle loads located on the positive plane of the reference plane are defined as top layer particle loads, the particle loads located on the negative plane of the reference plane are defined as bottom layer particle loads, the first transmission line connected with the top layer particle loads and the second transmission line connected with the bottom layer particle loads are connected through a through hole arranged at one end of the reference plane, the main controller is arranged at the beginning end of the first transmission line, the terminating resistor is arranged at the ending end of the second transmission line, the through hole is arranged at the ending end of the first transmission line and the beginning end of the second transmission line, the selection points of the first guide holes corresponding to the top layer particle loads and the terminating resistor are symmetrically distributed based on the reference plane, the selection points of the remaining guide holes corresponding to the top layer particle loads and the bottom layer particle loads are symmetrically distributed one by one, and the two symmetrically distributed guide holes are not penetrated.

2. The topology of a DDR circuit according to claim 1, wherein, The number of the bottom layer particle loads is n, and the number of the top layer particle loads is n+1, wherein n is a positive integer.

3. A simulation method of a DDR circuit applied to a topology of the DDR circuit as claimed in claim 1 or 2, characterized by, The method comprises: reflective simulation is performed on the topology structure of the DDR circuit to obtain a first position where the impedance value in the transmission line is lower than a first preset value and an impedance value corresponding to the first position; based on the impedance value corresponding to the first position, the aperture and the depth of the guide hole closest to the first position are obtained; based on the aperture and the depth, the guide hole position corresponding to the reference plane is processed by hole digging, and the particle load is installed to generate a final DDR circuit topology structure.

4. The simulation method of a DDR circuit according to claim 3, wherein, The method for determining the guide hole position comprises: based on the line distance and the line width of the DDR circuit, the guide hole position is determined, and an initial DDR circuit topology structure is generated based on the guide hole position. The reflective simulation performed on the topology structure of the DDR circuit to obtain a first position where the impedance value in the transmission line is lower than a first preset value and an impedance value corresponding to the first position comprises:

5. The simulation method of a DDR circuit according to claim 4, wherein, reflective simulation is performed on the initial DDR circuit topology structure to monitor whether the impedance of the target transmission line connected with the particle load is continuous; in response to detecting that the impedance of the target transmission line is not continuous, a first position where the impedance value in the target transmission line is lower than a first preset value and an impedance value corresponding to the first position are determined. based on the impedance value corresponding to the first position, the aperture and the depth of the guide hole closest to the first position are obtained; 6. The simulation method of a DDR circuit according to claim 5, wherein, based on the impedance value corresponding to the first position, the aperture and the depth of the guide hole closest to the first position are determined when the target impedance value of the target transmission line is equal to the preset impedance value. The device comprises:

7. A simulation apparatus of a DDR circuit for implementing a simulation method of the DDR circuit according to claim 3, characterized by, ​ The first determining module is configured to perform reflection simulation on the topology of the DDR circuit to obtain a first position where an impedance value in a transmission line is lower than a first preset value and an impedance value corresponding to the first position; The second determining module is configured to obtain an aperture and a hole depth of a hole closest to the first position according to the impedance value corresponding to the first position. The structure generating module is configured to perform hole digging processing on a hole position corresponding to a reference plane based on the aperture and the hole depth, and install a particle load to generate a final DDR circuit topology.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method in any one of claims 3 to 6.

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