Design method of approximate binary multiplier based on multi-objective evolutionary algorithm

Abstract

The present invention belongs to the field of integrated circuit technology, and specifically relates to a method for designing approximate binary multipliers based on a multi-objective evolutionary algorithm. In this method, multipliers and compressors are treated as individuals and genes, respectively, to explore the design of a high-efficiency approximate multiplier composed of multiple approximate compressors in a manner that simulates natural evolution. The proposed design achieves an optimal trade-off between error index, delay, area, and power consumption. Furthermore, based on the characteristics of the partial integral distribution, this paper proposes an error model for the approximate multiplier, which can significantly reduce the number of test vectors in simulations, accelerate the calculation of error indexes, and improve search efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a design method for an approximate binary multiplier based on a multi-objective evolutionary algorithm. Background Art

[0002] Approximate computing is an emerging computing paradigm that aims to optimize chip hardware performance by simplifying circuit complexity by discarding certain forms of precision. Approximate computing is widely used in fault-tolerant computing systems because they do not require completely accurate results. For example, in image and audio signal processing, due to the limited perception of human beings, completely accurate results are not required. In digital signal processing, data truncation operations such as rounding and saturation are required, which can also introduce computational errors. In machine learning and adaptive filtering, related algorithms also have fault-tolerant mechanisms that accept calculation results with errors. In the study of approximate computing, approximate multipliers have been a hot topic in recent years. Multipliers are generally considered the most complex basic arithmetic circuits, which have a significant impact on the system's frequency and power consumption. Introducing approximate computing into multipliers can improve system hardware performance.

[0003] A multiplier typically consists of three parts: partial product generation, partial product compression, and a final adder. Partial product compression requires extensive use of compressors, making them the primary source of power consumption in multipliers. To optimize multiplier hardware performance, recent research on approximate compressors has been extensive. While numerous approximate compressors with varying precision and hardware performance have been proposed, in most approximate multiplier designs, partial product compression is limited to one or two limited approximate compression structures. This severely constrains design options and hinders optimization for performance or power consumption. Designing energy-efficient multipliers using multiple approximate compressors is a complex problem, requiring consideration not only of the approximate compressor design but also of multiple dimensions such as the multiplier's accuracy, latency, area, and power consumption. This represents a complex multi-objective optimization problem (MOP), for which Moti-Objective Evolutionary Algorithms (MOEAs) are a common approach.

[0004] Evolutionary algorithms (EAs) can provide novel solutions to complex problems. They explore the design space through group experience and random search, and are global optimization methods that mimic the natural evolutionary process. In EAs, individuals represent solutions to the problem being solved, and the population represents a collection of distinct individuals. The basic EA process begins with an initial population, then continuously performs operations such as selection, crossover, and mutation until a maximum number of iterations is reached, at which point the search stops and the final population is output. During the EA iteration process, the proportion of excellent individuals in the population increases, gradually guiding the population toward the optimal solution set. Evolutionary algorithms primarily fall into four categories: genetic algorithms (GAs), evolutionary strategies (ESs), evolutionary programming (EPs), and genetic programming (GPs). MOEAs, which can simultaneously optimize across multiple dimensions, have been extensively studied in recent years as an important approach for solving multi-objective optimization problems. Non-dominant Sort Genetic Algorithm II (NSGA-II) is a Pareto-dominant MOEA that uses fast non-dominated sorting to achieve rapid convergence of results.

[0005] EA is currently also being used to optimize complex digital circuits. For example, Cartesian Genetic Programming (CGP) uses a fixed-width Cartesian grid to represent the circuit. By modifying logic gates and adjusting the connections between them, it can reduce circuit latency, area, and power consumption while maintaining the original functionality. Building on CGP, by relaxing the requirements for computational accuracy, EA has also been used for approximate circuit design, and much research has been conducted on this topic. While methods based on CGP and EA can achieve energy-efficient approximate circuit design, the random search process of EA destroys the original circuit structure, making these approximate circuits difficult to understand and analyze. For example, the approximate multipliers generated using these methods lack the original three components—partial product generation, partial product compression, and the final adder—due to their fragmented structure. This makes comparison and analysis of these approximate multipliers with other approximate structures difficult, limiting further research and limiting EA-based approximate multiplier design to algorithm optimization. Summary of the Invention

[0006] Aiming at the defects of traditional approximate binary multiplier design methods, the present invention proposes an approximate binary multiplier design method based on a multi-objective evolutionary algorithm. Through strategic and structural innovations, the approximate multiplier implemented based on this method has excellent accuracy and hardware performance.

[0007] The technical solution of the present invention is:

[0008] A design method for an approximate binary multiplier based on a multi-objective evolutionary algorithm is disclosed. The multiplier includes partial product generation, partial product compression, and a final adder. The partial product generation is used to encode the multiplier and decode the multiplicand according to the encoded signal to generate a partial product array. The partial product compression is used to compress the partial product array, ultimately compressing it into two rows of partial products. The final adder adds the two compressed rows of partial products to obtain the output of the approximate binary multiplier. The present invention mainly improves the partial product compression. The method includes:

[0009] Partial product compression is divided into an exact part and an approximate part, wherein the approximate part is the lowest r columns in the multiplier, and in the approximate part, an N:1 compressor is used to implement approximate partial product compression; the N:1 compressor has an N-bit input and a 1-bit output;

[0010] Add an error compensation unit to the highest column of the approximation part. The error compensation unit also has an N-bit input and a 1-bit output. The input of the error compensation unit is the same as the input of the N:1 compressor in the r-1th column. The error compensation unit generates a 1-bit carry to the rth column. The N:1 compressor and the error compensation unit jointly complete the compression of the partial product. Their specific circuits will be determined by subsequent search.

[0011] The multiplier is designed using a multi-objective evolutionary algorithm. The multiplier is used as an individual and the N:1 compressor as a gene. The population is initialized, the target is evaluated, and the ranks are assigned. A search loop is then performed, where reproduction, an elite strategy, target evaluation, rank assignment, and generation of the next generation population are performed within the maximum number of iterations. Finally, the final population is output as the final multiplier.

[0012] The population initialization is as follows: the approximate multiplier is encoded as a set of integer representations based on the N:1 compressor, and then the population initialization is performed by randomly generating multiple sets of data, which represent the approximate multiplier. The N:1 compressor in the approximate multiplier is the N:1 compressor represented by each segment of the set of integers;

[0013] The reproduction method is as follows: assuming that the current population is the parent population, individuals with high Pareto dominance are selected from the parent population by a competitive tournament selection method as parents, and then offspring individuals are generated by crossover and mutation, wherein crossover represents exchanging some N:1 compressors of two parent multipliers to generate offspring approximate multipliers; mutation represents Pm The probability of randomly changing the N:1 compressors in these child multipliers to other N:1 compressors; setting that the operation bit width N of the N:1 compressor at each position cannot be changed regardless of crossover or mutation;

[0014] The method of the elite strategy is: combining the parent population and the child population, and performing subsequent iterations based on the combined new population;

[0015] The evaluation method is as follows: for error indicators, the error under each partial integral distribution is multiplied by the probability of the distribution, and then the sum is accumulated to calculate the relevant error indicator; for hardware performance indicators such as delay, power consumption and area, the delay, power consumption and area of ​​the N:1 compressor in the multiplier are accumulated to estimate the hardware performance indicator of the multiplier;

[0016] The method for assigning levels is as follows: using the fast non-dominated sorting and congestion degree in NSGA-II to quickly calculate the Pareto dominance relationship of all multipliers in the population, and then classifying the multipliers into multiple levels. Multipliers of different levels have different trade-offs between accuracy and hardware performance. Multipliers at level 0 have the best trade-off and dominate multipliers of other levels. For multipliers of the same level, the higher its congestion degree, the higher its Pareto dominance relationship.

[0017] The specific method of generating the next generation population is: retaining M individuals with the highest Pareto dominance relationship as the next generation population;

[0018] The present invention has the following beneficial effects: It proposes a binary multiplier approximation method based on a multi-objective evolutionary algorithm. This method uses a variety of approximate compressors to compress partial products, and employs an evolutionary algorithm to search for approximate multipliers with excellent accuracy and hardware performance. Consequently, these approximate multipliers are suitable for general fault-tolerant applications and can be deployed on both portable devices and large, high-performance equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of an 8×8 Wallace multiplier.

[0020] Figure 2 This is the unsigned 8×8 approximate multiplier structure proposed by the present invention, where r=8.

[0021] Figure 3 This is the symbol number 8×8 approximate multiplier structure proposed by the present invention, where r=7.

[0022] Figure 4 This is a schematic diagram of the approximate multiplier encoding proposed by the present invention.

[0023] Figure 5 This is a flow chart of the search method proposed in the present invention.

[0024] Figure 6 Schematic diagram of the partial product matrix in the present invention.

[0025] Figure 7 This is a flow chart of the probability calculation of the partial integral distribution in the present invention.

[0026] Figure 8 Comparison diagram between the error model of the present invention and exhaustive simulation

[0027] Figure 9 This is the search result of the unsigned 8×8 multiplier in the present invention.

[0028] Figure 10 This is a specific unsigned 8×8 multiplier circuit in the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described below with reference to the accompanying drawings.

[0030] In evolutionary algorithms, solutions to complex problems are called individuals, which evolve into better solutions. Individuals are encoded as a set of integers based on their characteristics, and this set of integers is called a chromosome. The present invention proposes the concept of N:1 compression and applies a new type of N:1 compressor to the compression of partial products. In the present invention, the multiplier is used as an individual and encoded as a chromosome representation based on the N:1 compressor. In addition, the present invention uses the multi-objective evolutionary algorithm NSGA-II to search for the optimal N:1 compressor structure to achieve the design of a high-efficiency approximate multiplier with the best compromise in accuracy, latency, area and power consumption.

[0031] The hardware design of multipliers is usually represented by tree diagrams and compressors. Figure 1An 8×8 Wallace multiplier is shown. The black dots in the figure represent partial products, and the boxes represent compressors. In typical multiplier approximation schemes, an approximate compressor is used for the lower bits of the partial product matrix. This is because approximate compressors typically have a simpler structure than exact compression, which can optimize multiplier hardware performance. Furthermore, the lower bits of the partial products have a low weight, so the approximate compressor does not produce excessive errors. These traditional approaches all use a bottom-up design process, first designing the approximate compressor and then designing the approximate multiplier based on it. This local-to-global design approach limits partial product compression to one or two limited approximate compressor structures. To explore the design of energy-efficient approximate multipliers using multiple approximate compressors, the multiplier design process can be modified to a top-down approach: first, determine the compression tree structure, and then design the approximate compressor according to design requirements. Therefore, the present invention first defines the input and output ports of the approximate compressor, builds a complete multiplier based on this structure, and then uses an evolutionary algorithm to search for the optimal approximate compressor, achieving the design of an energy-efficient approximate multiplier.

[0032] In the design of an approximate compressor, the hardware complexity can be reduced by reducing the number of input and output ports. For example, in an approximate 4:2 compressor, a structure that removes 1-bit input and output is usually adopted. In the present invention, in order to further reduce the complexity of the approximate compressor, only one output port of the compressor is retained. A compressor with N-bit input and 1-bit output is defined as an N:1 compressor, and its output has the same weight as the input. This article will complete the design of an approximate multiplier based on the Wallace multiplier and the N:1 compressor. For an n×n multiplier, its lowest r columns are defined as the approximate part, and the rest are the exact part. For unsigned multipliers, 1≤r≤n, and for signed multipliers, 1≤r≤n-1. In the approximate part, an N:1 compressor is used instead of an exact compressor to achieve approximate partial product compression.

[0033] First, we introduce the unsigned approximate multiplier. Figure 2An unsigned 8×8 approximate multiplier based on this strategy is presented, with r = 8. Since the exact compressor has multiple bits of output, while the N:1 compressor only has a single bit, the N:1 compressor is highly likely to produce errors, and these errors are negative. Therefore, an error compensation unit is introduced to reduce the precision loss of the multiplier. Similar to the N:1 compressor, the error compensation unit has N-bit inputs and a single-bit output. It shares the same inputs as the N:1 compressor in the r-1th column and produces an output in the rth column, so it is also considered a special N:1 compressor. The error compensation unit is designed this way because the N:1 compressor only has a single bit of output. In most cases, the result of the N:1 compressor will be smaller than the exact compressor, resulting in a significant negative error. Therefore, positive compensation is required to reduce the error. The error compensation unit uses the same inputs as the N:1 compressor in the r-1th column and produces a single-bit carry in the rth column, thus functioning as the carry output in the exact compressor. The present invention adopts an error compensation unit to compensate for the error of the N:1 compressor, thereby greatly improving the accuracy with fewer hardware resources.

[0034] The signed number approximate multiplier proposed in the present invention generates partial products based on the Baugh-Wooley algorithm, adopts the same approximation strategy as the unsigned number multiplier, and uses an N:1 compressor to compress the partial products. The only difference between them is that the length of the approximate part of the signed number approximate multiplier is 1≤r≤n-1, as shown in the following example: Figure 3 This figure shows a signed 8×8 multiplier based on an N:1 compressor. The black dots represent partial products generated directly by AND gates, while the white dots require their inversion. The constant 1 represents the constant term determined by the Baugh-Wooley algorithm. The purpose of distinguishing the r of signed and unsigned multipliers is to ensure that the approximate designs for both structures share commonalities: the inputs used by the N:1 compressor are all partial products generated directly by AND gates. This ensures that signed and unsigned approximate multipliers with the same r share the same approximate partial structure, allowing the design of both unsigned and signed approximate multipliers to be implemented simultaneously.

[0035] For the proposed approximate multiplier, only the ports of the N:1 compressor are defined above, because N:1 compressors have various logical expressions and implementations, and their circuit selection affects the multiplier's accuracy, latency, area, and power consumption. To achieve the best overall performance of the multiplier, each N:1 compressor used in partial product compression needs to be considered, as they are the basic units that constitute the approximate multiplier. For such a multi-objective optimization problem, the present invention uses NSGA-II to search for the optimal result. The approximate multipliers are treated as individuals and encoded as a set of integer representations based on the N:1 compressor.

[0036] Before coding the approximate multiplier, it is necessary to first clarify the circuit of the N:1 compressor, because in the approximate method proposed in this invention, the N:1 compressor is the key to the approximate multiplier. Since the N:1 compressor has a large number of different implementations, it takes a lot of time to design it manually. Therefore, this invention uses behavioral code to describe all possible N:1 compressions and implements them through synthesis tools. For a given N, there are a total of There are different N:1 compression methods, each of which has a corresponding compressor. These N:1 compressors will be used for subsequent encoding and searching. Figure 2 Taking the approximate multiplier in as an example, the compressor operation bit width is 1≤N≤4, involving 4:1 compressor, 3:1 compressor and 2:1 compressor.

[0037] In the search, the multipliers are encoded as a set of integer representations based on an N:1 compressor, which is encoded as the outputs under different inputs arranged in ascending order. Figure 4 The box shows an example of a 2:1 compressor synthesized as a 2-input AND gate, which is encoded as "0001" by arranging the outputs in the order of the inputs "x0x1" from "00" to "11." After encoding the compressor, the multiplier is encoded by arranging the encoded values ​​of the N:1 compressors from left to right and from top to bottom according to their position in the compression tree. Figure 4 Shows the Figure 2 The letters on the N:1 compressor represent their coded values.

[0038] In the present invention, the approximate multiplier is obtained by searching based on the multi-objective algorithm NSGA-II. The search process is as follows: Figure 5 . The search for multipliers first requires population initialization, evaluation of targets, and assignment of ranks, which are used to generate and describe an initial set of multipliers. The search then enters a loop, and each round requires generating child populations, elite strategies, evaluation of targets, assignment of ranks, and adding individuals to the next generation population. These operations will continuously search for multipliers with better targets. Before introducing the search process in detail, the concept of Pareto dominance is first introduced. Assuming that p and q are two solutions, p dominates q when all targets of p are not inferior to q, and p has at least one target that is strictly better than q.

[0039] Before the search begins, the population size M needs to be set, and the population will randomly generate M individuals during initialization. In the approximate method proposed by the present invention, since the approximate multiplier based on the N:1 compressor is used as an individual, the initialization of the population also requires setting the operation bit width n of the multiplier and the length r of the approximate part. Based on the multiplier encoding method introduced above, the present invention will generate M groups of random integers when initializing the population, which represent the approximate multipliers. The N:1 compressor in the approximate multiplier is the N:1 compressor represented by each fragment of this group of integers. Since each group of integers corresponds to an approximate multiplier, these numbers are not completely randomly generated. The length of this group of integers must meet the multiplier's limit on the number of N:1 compressors, and the length of each fragment in the group of integers must also meet the limit on the operation bit width of the N:1 compressor at the corresponding position.

[0040] In the target evaluation, the present invention considers multiplier targets including error, delay, area, and power consumption. Since the error is a domain-specific function, it is necessary to select an appropriate error parameter as a target in different scenarios. Because error calculation significantly impacts search speed, the error calculation utilizes the error model described below, which is more efficient than exhaustive simulation. The multiplier delay, area, and power consumption are estimated by accumulating the delay, area, and power consumption of the N:1 compressor. The hardware performance metrics of these N:1 compressors are statistically analyzed before the search. This allows for direct access to the corresponding values ​​using a table lookup when estimating the hardware performance of the approximate multipliers, accelerating the search. Although this method does not synthesize and simulate these approximate multipliers to accurately calculate hardware performance metrics, because the multipliers being searched share the same compression tree and their hardware performance is correlated with that of the N:1 compressor, this method can quickly assess the relative performance of the multipliers. While this estimation may result in a loss of accuracy, it significantly improves computational efficiency and avoids the need to simulate all approximate multipliers.

[0041] When assigning ranks to individuals, the present invention uses the fast non-dominated sorting and crowding degree of NSGA-II to quickly calculate the Pareto dominance relationship of all multipliers in the population. This is used to classify multipliers into multiple ranks. Multipliers at different ranks have different trade-offs between accuracy and hardware performance. Multipliers at rank 0 have the best trade-off and dominate multipliers at other ranks. For multipliers of the same rank, a higher crowding degree indicates a higher Pareto dominance.

[0042] For the reproduction step, the mutation probability P needs to be set before searching. mWhen breeding, assuming that the current population is the parent population, this method uses a competitive selection method to select individuals with high Pareto dominance in the parent population as parents, and then generates offspring individuals through crossover and mutation. In this method, crossover means exchanging some N:1 compressors in the two parent multipliers to generate offspring approximate multipliers; mutation means P m The probability of randomly changing the N:1 compressors in these child multipliers to other N:1 compressors is 1:1. It should be noted that neither crossover nor mutation can change the operation bit width N of the N:1 compressor at each position, because this will change the structure of the partial product compression. In the present invention, crossover is expressed as exchanging partial segments of two chromosomes to generate a new chromosome; mutation represents randomly changing partial segments in a chromosome. Their common restriction is that the length of each segment of the chromosome cannot be changed.

[0043] The elitist strategy combines the parent and child populations, using the resulting new population as the basis for subsequent iterations. This approach avoids the loss of outstanding individuals from the parent population and accelerates convergence. After the populations are merged, the new population is evaluated for targets and assigned ranks to determine the Pareto dominance of each individual in the new population.

[0044] At the end of each cycle, the M individuals with the highest Pareto dominance are retained as the next generation population. The search ends when the maximum number of iterations is reached, and the final population is output. Through the search, the multipliers in the final population achieve multi-objective optimization compared to the multipliers in the initial population. These multipliers have more suitable N:1 compression, which improves their accuracy, speed, area, and power consumption.

[0045] The proposed error model is introduced below. Accuracy is an important indicator to be considered in approximate calculations. Error indicators are usually used to describe the accuracy of approximate multipliers. For an n×n multiplier, the exact result and approximate result are defined as Y and Y respectively. * The error distance (ED) and relative error distance (RED) are defined as follows:

[0046]

[0047] On this basis, several commonly used error indicators are: Normalized Mean Error Distance (NMED), Mean Relative Error Distance (MRED), Mean Square Error (MSE) and PRED, which are summarized in the following formula (2). Where MAV is the maximum value of the multiplier output, which is 2 in the symbol multiplier. 2n-2 , in the unsigned multiplier it is (2 n -1) 2 .

[0048]

[0049] Most research on approximate multipliers uses exhaustive simulation to calculate errors, but this is a very time-consuming task. As the bit width of the operation increases, the number of test vectors and the simulation time overhead increase exponentially. To reduce the number of test vectors in simulation, the following article analyzes the characteristics of partial product distributions and calculates the probability of partial product distributions based on these characteristics. The probability of a partial product distribution refers to the probability of the approximate part when all partial product bits of the approximate part are considered as a whole.

[0050] For an n×n multiplier, where the lower r columns are the approximate part, suppose A(a n-1 ...a0) and B(b n-1 ...b0) is the input operand, and the partial product bit is represented by p i,j =a i b j .like Figure 6 As shown in , the subscripts of the partial product bits in the r-1th column include the subscripts of the partial product bits of all approximate parts, so this column of partial product bits has the most input operand bits in the approximate part. Therefore, the present invention will analyze the characteristics of the partial product distribution based on this column of partial product bits. The partial product bits in the r-1th column are represented as p ｉ,ｒ-i-1 (0≤i≤r-1). Based on the partial product bit equal to 1, three types of p are listed in formula (3) i,r-i-1 The composition of p i,r-i-2 …p i,0 ≠0 means from p i,r-i-2 to p i,0 The partial product bits of are not all 0.

[0051]

[0052] For an approximate part T, a part of the input operand bits can be determined based on the above expression, and then the remaining input operand bits are assumed to be 0 to obtain a set of operands that can constitute T and Define LA and LB as the following expressions:

[0053]

[0054] As long as the partial product bits in T are not all 0, LA and LB exist because we can find input operand bits that are equal to 1 based on equation (3). Even if Changing to any value, T will not be changed, and Equation (3) still holds, because these input operand bits are not related to the partial product bits equal to 1. In addition, The same relationship exists with LA.

[0055] When all the partial product bits in T are 0, the input operand bits cannot be determined by equation (3), but the input operands can be analyzed based on the above ideas. i =1 and b i-1 ...b0=0, only operands satisfy a n-i-1 …a0=0 can make the partial product bits of the approximate part all 0. In addition, if b n-1 ...b0=0, then a n-1 …a0 can be any value. Based on the above analysis, different input operands can form the same T. P(T) represents the probability of the partial integral distribution, which can be summarized as follows:

[0056]

[0057] In equation (5), T=0 means that all partial product bits in T are 0, and T≠0 means that the partial product bits are not all 0. P(a i )and Respectively a i =1 and a i = 0. When the input follows a uniform distribution, P(a i )=P(b i )=2 -1 , formula (5) can be simplified to formula (6).

[0058]

[0059] In the present invention, since the errors of the multipliers all come from the approximate part, only the results of the approximate part need to be considered when calculating the errors. Since the N:1 compressor is encoded based on the corresponding relationship between input and output, its output can be determined by combining the input and encoding value of the N:1 compressor. Therefore, for any T and the encoding value of the approximate multiplier, the output of each N:1 compressor in the multiplier can be calculated. Assume that Z represents the exact compression result corresponding to the approximate part, which is represented by the sum of these partial product bits. At the same time, assume that Z * represents the approximate compression result corresponding to the approximate part, which is represented by the sum of the last row of operands generated by the N:1 compressor and the output of the error compensation unit. Therefore, ED can be transformed into Equation (7), which is equal to ED in Equation (1). RED cannot be calculated based on T because RED needs to consider the exact multiplication result.

[0060] ED=|ZZ * | (7)

[0061] Based on Equations (5) and (7), the calculation of the error index can be simplified as follows: multiply the error under each partial integral distribution by the probability of the corresponding partial integral distribution, and then accumulate the calculation results under all partial integral distributions to calculate the required error index. Based on this, the calculation of NMED and MSE can be implemented by Equation (8). MRED and PRED do not have similar calculation forms because RED cannot be calculated based solely on T.

[0062]

[0063] As shown in Equation (8), the probability of the partial integral distribution is called multiple times during the error metric calculation. Therefore, it can be calculated in advance and called in the error metric calculation in the form of a lookup table to speed up the calculation. In exhaustive simulation, because different input operands may correspond to the same T, especially as the multiplier operation bit width increases, the number of test vectors increases exponentially, and repeated test vectors will cause a large and unnecessary time overhead. In the proposed error model, since the probability of the partial integral distribution describes the probability of approximating part of T, repeated test vectors are avoided, improving the efficiency of the error metric calculation.

[0064] The following will compare and analyze the number of test vectors in exhaustive simulation and this method. For an n×n multiplier, exhaustive simulation requires 2 2n test vectors. In the error model proposed by the present invention, the number of test vectors depends on the length r of the approximate part, because each r corresponds to a different number of approximate parts T. Since the approximate part contains a total of (r+1)·r / 2 partial product bits, the approximate part has a total of 2 (r+1)·r / 2There are many possible distributions, but most of them are contrary to the principle of partial product generation, and such distributions will not appear in the partial product matrix, such as Figure 7 Flowchart for calculating the probability of partial distribution.

[0065] Figure 7 China A r and B r Represents the input operand bits required for the approximate part, which correspond to a r-1 ...a0 and b r-1 ...b0, both data range from 0 to 2 r -1. In addition, T(A r ,B r ) represents A r and B r As the approximate part of the input, P(T) represents the probability of the partial integral distribution. When calculating the probability of the partial integral distribution, first A r and B r Perform a traversal, and then check T(A r ,B r ) has appeared before. If not, P(T) is calculated based on formula (5); if it has appeared, this distribution is skipped and the traversal continues.

[0066] In order to verify that the proposed error model can avoid repeated test vectors and thus improve the calculation efficiency of the error index, the present invention is based on Figure 7 The process calculates and counts the number of approximate parts T under various r and their corresponding probabilities P(T). Figure 8 The reduction in the number of test vectors between the proposed method and exhaustive simulation is demonstrated, where the operation bit width ranges from 7≤n≤13 and the approximate part length ranges from n-4≤r≤n-1.

[0067] exist Figure 8 In the present invention, when r=n, the number of test vectors is reduced the least, with an average reduction of 55%. As r decreases, the number of test vectors in this method is further reduced. When r=n-3, the number reduction reaches the highest, with an average reduction of 90%. Based on the above experimental data, it can be inferred that if r is further reduced, the reduction in the number of test vectors will reach more than 90%, and the calculation efficiency of the error model proposed in the present invention will be much better than that of exhaustive simulation. In summary, since there are a large number of redundant test vectors in the exhaustive simulation, they all correspond to the same approximate part, so the exhaustive simulation will repeatedly calculate the same partial integral distribution, while the present method uses the probability of the partial integral distribution to calculate the error index, which greatly reduces the number of test vectors and improves the calculation efficiency.

[0068] The parameters required for the approximation method proposed in this invention are: multiplier operation bit width n, approximate part length r, population size M, mutation probability P m , maximum number of iterations t max The following experiment is conducted with an unsigned multiplier to demonstrate the optimization effect of the present invention on the accuracy index and error index. The relevant parameters selected are as follows: the operation bit width is 8×8, M is 100, P m 5%, t max is 50000, MSE is selected as the search target, and the process node used in this experiment is 90nm. When designing a multiplier using the present invention, it is recommended to establish multiple independent searches, each of which will correspond to a type of r (n / 2≤r≤n). Because the setting of r will affect the accuracy and hardware performance of the multiplier, using multiple searches can find the optimal compromise within a larger range of accuracy and hardware performance, thereby achieving a rich approximate multiplier design. Taking the unsigned 8×8 approximate multiplier as an example, there are a total of five groups of independent searches corresponding to r equal to 8, 7, 6, 5 and 4 respectively. In the present invention, because the unsigned multiplier and the signed multiplier have the same approximate part, each search can simultaneously complete the design of two types of approximate multipliers.

[0069] Because the Power Delay Product (PDP) is a comprehensive indicator that describes hardware performance, in order to clearly show the balance between the accuracy and hardware performance of the multiplier, each approximate multiplier will be displayed in a scatter plot comparing four different error indicators and PDP. The four error indicators include: MSE, NMED, MRED and PRED. Each symbol in the figure represents a multiplier. The closer the symbol is to the lower left corner, the better the compromise between the error indicator and PDP of the multiplier. The symbol in the lower left corner reaches the Pareto frontier, and the multiplier it represents achieves the best trade-off between the error indicator and PDP. Figure 9 A comparison chart of the unsigned 8×8 approximate multiplier is shown, where the horizontal axis of each scatter plot corresponds to the error metric and the vertical axis corresponds to the PDP.

[0070] like Figure 10 A specific search result is shown: an unsigned 8×8 approximate multiplier with r=6, located in the lower left corner of the MSE vs. PDP comparison chart. This multiplier exhibits excellent accuracy and hardware performance. It contains six N:1 compressors, with letters in the figure representing their corresponding circuits. The N:1 compressors corresponding to d through j have very simple circuit structures and can be implemented without logic gates. Although some of the N:1 compressors in this multiplier are simple, the multiplier as a whole is quite complex because different N:1 compressors exist at different positions in the compression tree.

[0071] In summary, the present invention proposes an evolutionary algorithm-based approximate binary multiplier design method. This method uses an N:1 compressor to build a multiplier. Thanks to the simple structure of the N:1 compressor, the approximate multiplier has excellent hardware performance. By searching for multipliers based on the evolutionary algorithm and comprehensively considering the accuracy and hardware performance of the multiplier, a high-efficiency multiplier is designed. Based on the characteristics of the N:1 compressor and the partial integral distribution, a corresponding error model is proposed, which improves the computational efficiency of the error index.

Claims

1. An approximate binary multiplier design method based on a multi-objective evolutionary algorithm, characterized in that: include: The partial product is compressed into an exact part and an approximate part, where the approximate part is the lowest r column in the multiplier. For unsigned Multiplier, , for the symbol number Multiplier, ; and in the approximation portion, implementing approximate partial product compression using an N:1 compressor having an N-bit input and a 1-bit output; An error compensation unit is added to the highest column of the approximation part. The error compensation unit also has an N-bit input and a 1-bit output. The input of the error compensation unit is the same as the input of the N:1 compressor of the r-1th column. The error compensation unit generates a 1-bit carry to the rth column. The N:1 compressor and the error compensation unit jointly complete the compression of the partial product. The multiplier is designed through a multi-objective evolutionary algorithm: the multiplier is regarded as an individual and the N:1 compressor is regarded as a gene. The population is initialized, the target is evaluated, and the ranking is assigned. Then a search loop is performed to perform reproduction, elite strategy, evaluation target, ranking and generation of next generation population within the maximum number of iterations, and finally the final population is output to obtain the multiplier circuit structure; The population initialization is as follows: the approximate multiplier is encoded as a set of integers based on the N:1 compressor, and then the population initialization is performed by randomly generating M groups of data, which represent the approximate multiplier, that is, M individuals. The N:1 compressor in the approximate multiplier is the N:1 compressor represented by each segment of this set of integers; The reproduction method is as follows: assuming that the current population is the parent population, individuals with high Pareto dominance are selected from the parent population by a competitive tournament selection method as parents, and then offspring individuals are generated by crossover and mutation, wherein crossover represents exchanging some N:1 compressors of the two parent multipliers to generate offspring approximate multipliers; mutation represents The probability of randomly changing the N:1 compressors in these child multipliers to other N:1 compressors; setting that the operation bit width N of the N:1 compressor at each position cannot be changed regardless of crossover or mutation; The method of the elite strategy is: combining the parent population and the child population, and performing subsequent iterations based on the combined new population; The evaluation method is as follows: for the error index, the error under each partial integral distribution is multiplied by the probability of the distribution, and then the sum is accumulated to calculate the relevant error index; for the hardware performance index of delay, power consumption and area, the delay, power consumption and area of ​​the N:1 compressor in the multiplier are accumulated to estimate the hardware performance index of the multiplier; The method for assigning levels is as follows: using the fast non-dominated sorting and congestion degree in NSGA-II to quickly calculate the Pareto dominance relationship of all multipliers in the population, and then classifying the multipliers into multiple levels. Multipliers of different levels have different trade-offs between accuracy and hardware performance. Multipliers at level 0 have the best trade-off and dominate multipliers of other levels. For multipliers of the same level, the higher its congestion degree, the higher its Pareto dominance relationship. The specific method of generating the next generation population is: retaining M individuals with the highest Pareto dominance relationship as the next generation population.

Images