SOP chip pin defect detection method and system based on lenet-5 model

Abstract

The application provides a SOP chip pin defect detection method and system based on a Lenet-5 model, the method comprising collecting images of chips to be detected; extracting ROI images of the chips from the collected images; performing tilt correction on the ROI images to obtain a corrected image sample set; selecting a plurality of image samples and performing cutting, dividing the cut images into different categories and marking labels to make a data set; inputting the data set into a pre-constructed Lenet-5 neural network to train and obtain a SOP chip pin defect detection model based on the Lenet-5 model; and inputting samples into the SOP chip pin defect detection model based on the Lenet-5 model to obtain detection results of pin samples. The application improves the SOP chip pin defect detection efficiency and accuracy.

Description

Technical Field

[0001] This invention relates to the fields of vision and chip pin defect detection technology, and in particular to a method and system for detecting pin defects in SOP chips based on the Lenet-5 model. Background Technology

[0002] As chips become increasingly miniaturized, manually inspecting chip pins for defects requires significant time and labor costs. Furthermore, since some chip pins are on the order of millimeters in length, defects are difficult to detect manually.

[0003] Machine vision uses machines to replace human eyes for measurement and judgment. It is commonly used in hazardous working environments unsuitable for manual labor or in situations where human vision is insufficient. Furthermore, in large-scale industrial production, manual inspection of product quality is inefficient and lacks precision; machine vision inspection methods can significantly improve production efficiency and automation. Moreover, machine vision facilitates information integration and is a fundamental technology for computer-integrated manufacturing. Currently, machine vision applications span various industries including manufacturing, agriculture, medicine, military, aerospace, meteorology, astronomy, public security, transportation, safety, and scientific research.

[0004] With the rapid development of computer technology, researchers have discovered that computers can be used to extract information from acquired images as a data source and process it to simulate human vision. Starting from vision, enabling computers to extract information from images and simulate human eyes to detect product defects is a worthy research topic, and deep learning is a method for computer vision inspection. Using deep learning algorithms to detect surface defects in objects can not only replace manual labor, saving costs, but also improve detection speed and accuracy. Therefore, applying deep learning to the industrial field to detect chip pin defects has become an urgent need. Summary of the Invention

[0005] To address this, embodiments of the present invention provide a method and system for detecting pin defects in SOP chips based on the Lenet-5 model, which solves the problems of high time and labor costs and high error rate of manual detection in existing pin defect detection technologies.

[0006] To address the aforementioned problems, this invention provides a method for detecting pin defects in SOP chips based on the Lenet-5 model. The method includes:

[0007] S1: Acquire an image of the chip to be tested;

[0008] S2: Extract the ROI (Region of Interest) image of the chip from the acquired image;

[0009] S3: Perform tilt correction on the ROI image to obtain a corrected image sample set;

[0010] S4: Select several image samples and cut them into different categories. Divide the cut images into different categories and label them to create a dataset.

[0011] S5: Input the dataset into the pre-built Lenet-5 neural network model for training to obtain the SOP chip pin defect detection model based on the Lenet-5 model;

[0012] S6: Input the sample into the SOP chip pin defect detection model based on the Lenet-5 model to obtain the detection results of the sample pin;

[0013] Step S5 specifically includes the following steps:

[0014] S51: Divide the dataset into a training set and a test set in a ratio of 4:1;

[0015] S52: For each batch, a set number of images are randomly selected from the training set and input into the pre-built Lenet-5 neural network model. The loss function is calculated based on the output of the Lenet-5 neural network model.

[0016] S53: Perform directional propagation based on the loss function, and update the parameters of the Lenet-5 neural network model through the model optimizer;

[0017] S54: When all training set images have been processed, the test set is input into the trained model for testing; after a preset number of training and testing cycles, the model with the best test set detection results is selected to obtain the SOP chip pin defect detection model based on the Lenet-5 model.

[0018] Preferably, the method for extracting the ROI image of the chip from the acquired image is as follows:

[0019] The ROI image of the chip is extracted from the acquired chip image using a global threshold segmentation method.

[0020] Preferably, the method for tilt correction of the ROI image specifically includes:

[0021] The ROI image is binarized, and the edge feature map of the chip encapsulation is obtained through edge operators;

[0022] The corner points in the feature map are detected by fitting a straight line using the least squares method based on the coordinate information of the edge corner points, and the slope of the straight line containing the edge is calculated.

[0023] The tilt angle is calculated by the slope, and correction is performed based on the tilt angle.

[0024] Preferably, the method of selecting several image samples and cutting them to classify the cut images into different categories specifically includes:

[0025] Select several image samples and cut the image samples from left to right and from top to bottom according to a set size;

[0026] The cut images are classified according to the proportion of the white portion of the chip pins in the image, resulting in different types of images.

[0027] Preferably, the structure of the Lenet-5 neural network model is as follows: Input layer: 32×32 grayscale image; First convolutional layer: using a 5*5 convolutional kernel, stride 1, ReLU activation function, and convolution depth 16; Second pooling layer: using max pooling, pooling kernel size 2*2, stride 2; Third convolutional layer: using a 5*5 convolutional kernel, stride 1, convolution depth 32, and ReLU activation function; Fourth pooling layer: using max pooling, pooling kernel size 2*2, stride 2; Fifth fully connected layer: outputting 120 neurons, ReLU activation function; Sixth fully connected layer: outputting 84 neurons, ReLU activation function; Output layer: 9 neurons, corresponding to 9 different types, using softmax activation function.

[0028] Preferably, the loss function is expressed as follows:

[0029]

[0030] Where i and j are constants, Loss represents the loss function, batchsize is the batch size, n is the total number of categories, and y represents the true distribution. This represents the output distribution of the Lenet-5 neural network model.

[0031] Preferably, the sample is input into the SOP chip pin defect detection model based on the Lenet-5 model to obtain the detection results of the sample pins, specifically including:

[0032] The samples are input into the SOP chip pin defect detection model based on the Lenet-5 model. By identifying the image of each pin boundary of the chip, its category is determined. Based on the category, the size that needs to be adjusted when calculating the pin parameters is determined. Finally, it is determined whether there are defects in the chip pins.

[0033] This invention provides a SOP chip pin defect detection system based on the Lenet-5 model, the system comprising:

[0034] The acquisition module is used to acquire images of the chip under test.

[0035] The ROI image extraction module is used to extract the ROI image of the chip from the acquired image;

[0036] The correction module is used to correct the tilt of the ROI image and obtain a corrected image sample set;

[0037] The cutting and classification module is used to select several image samples and cut them, classify the cut images into different categories and label them to create a dataset.

[0038] The model training module is used to input the dataset into a pre-built Lenet-5 neural network model for training, so as to obtain a SOP chip pin defect detection model based on the Lenet-5 model.

[0039] The detection module is used to input the sample into the SOP chip pin defect detection model based on the Lenet-5 model to obtain the detection results of the sample pin;

[0040] The model training module specifically includes the following steps:

[0041] The dataset is divided into a training set and a test set in a ratio of 4:1.

[0042] For each batch, a set number of images are randomly selected from the training set and input into the pre-built Lenet-5 neural network model. The loss function is calculated based on the output of the Lenet-5 neural network model.

[0043] Directional propagation is performed based on the loss function, and the parameters of the Lenet-5 neural network model are updated through the model optimizer;

[0044] Once all training set images have been processed, the test set is input into the trained model for testing. After a preset number of training and testing cycles, the model with the best detection results on the test set is selected to obtain the SOP chip pin defect detection model based on the Lenet-5 model.

[0045] This invention provides a network device including a processor, a memory, and a bus system. The processor and the memory are connected through the bus system. The memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to implement the SOP chip pin defect detection method based on the Lenet-5 model described above.

[0046] This invention provides a computer storage medium storing a computer software product, the computer software product including several instructions for causing a computer device to execute the SOP chip pin defect detection method based on the Lenet-5 model described above.

[0047] As can be seen from the above technical solutions, this invention application has the following advantages:

[0048] This invention provides a method and system for detecting pin defects in SOP chips based on the Lenet-5 model. The invention utilizes an industrial camera to acquire images of the chip, extracts Region of Interest (ROI) images from the acquired images, and removes redundant space. The ROI images are then tilt-corrected to improve detection accuracy. The corrected image samples are segmented, and the resulting images are categorized and labeled to create a dataset. This dataset is then input into a pre-constructed Lenet-5 neural network model for training. The network model of this invention replaces the sigmoid activation function in the traditional Lenet-5 network model with the ReLU activation function, avoiding information loss and high computational cost during training. Simultaneously, the use of the ReLU activation function makes the network sparse, reducing parameter dependencies and mitigating overfitting. Furthermore, the depths of the two convolutional layers are changed to 16 and 32 layers, increasing the number of feature parameters and making the training results more accurate. Finally, the obtained Lenet-5-based SOP chip pin defect detection model is used to detect the samples. This invention reduces the amount of image acquisition of raw samples by using deep learning, which improves detection efficiency and accuracy compared to manual inspection of chip pin defects. Furthermore, the SOP chip pin defect detection model obtained by this invention can still be applied to the detection of images acquired by ordinary vision systems. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Referring to the accompanying drawings will provide a clearer understanding of the features and advantages of the present invention. The drawings are illustrative and should not be construed as limiting the present invention in any way. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort. Wherein:

[0050] Figure 1 This is a flowchart of a method for detecting pin defects in an SOP chip based on the Lenet-5 model, as provided in the embodiments.

[0051] Figure 2 This is a diagram of the SOP chip captured by the industrial camera of this invention;

[0052] Figure 3 for Figure 2 The grayscale histogram of the SOP chip collected in the image;

[0053] Figure 4 This is a diagram showing the missing pins of the SOP8 chip.

[0054] Figure 5 Example diagram of detection for one pin of SOP8 chip;

[0055] Figure 6 This is a diagram showing the pin bending of the SOP8 chip.

[0056] Figure 7 Diagram showing the pin length defects of the SOP8 chip;

[0057] Figure 8 This is a block diagram of a SOP chip pin defect detection system based on the Lenet-5 model provided in the embodiment. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] like Figure 1 As shown in the figure, this invention proposes a method for detecting pin defects in SOP chips based on the Lenet-5 model. The method includes:

[0060] S1: Acquire an image of the chip to be tested;

[0061] S2: Extract the ROI image of the chip from the acquired image;

[0062] S3: Perform tilt correction on the ROI image to obtain a corrected image sample set;

[0063] S4: Select several image samples and cut them into different categories. Divide the cut images into different categories and label them to create a dataset.

[0064] S5: Input the dataset into the pre-built Lenet-5 neural network model for training to obtain an SOP chip pin defect detection model based on the sample Lenet-5 model;

[0065] S6: Input the sample into the SOP chip pin defect detection model based on the Lenet-5 model to obtain the detection results of the sample pin;

[0066] Step S5 specifically includes the following steps:

[0067] S51: Divide the dataset into a training set and a test set in a ratio of 4:1;

[0068] S52: For each batch, a set number of images are randomly selected from the training set and input into the pre-built Lenet-5 neural network model. The loss function is calculated based on the output of the Lenet-5 neural network model.

[0069] S53: Perform directional propagation based on the loss function, and update the parameters of the Lenet-5 neural network model through the model optimizer;

[0070] S54: When all training set images have been processed, the test set is input into the trained model for testing; after a preset number of training and testing cycles, the model with the best test set detection results is selected to obtain the SOP chip pin defect detection model based on the Lenet-5 model.

[0071] This invention proposes a method for detecting pin defects in SOP chips based on the Lenet-5 model. It utilizes an industrial camera to acquire images of the chip, extracts Region of Interest (ROI) images from the acquired images, and removes redundant space. The ROI images are then tilt-corrected to improve detection accuracy. The corrected image samples are segmented, categorized, and labeled to create a dataset. This dataset is then input into a pre-constructed Lenet-5 neural network model for training. The network model in this invention replaces the sigmoid activation function in the traditional Lenet-5 network model with the ReLU activation function, avoiding information loss and high computational cost during training. Furthermore, the use of the ReLU activation function makes the network sparse, reducing parameter dependencies and mitigating overfitting. Additionally, the depths of the two convolutional layers are changed to 16 and 32 layers, increasing the number of feature parameters and making the training results more accurate. Finally, the obtained Lenet-5-based SOP chip pin defect detection model is used to detect the samples. This invention reduces the amount of image acquisition of raw samples by using deep learning, which improves detection efficiency and accuracy compared to manual inspection of chip pin defects. Furthermore, the SOP chip pin defect detection model obtained by this invention can still be applied to the detection of images acquired by ordinary vision systems.

[0072] Furthermore, step S1 specifically includes:

[0073] An industrial camera is used to capture a top-down view of the chip. The target size (FS), pixels, focal length (f), object distance (WD), and field of view (FOV) of the lens are determined. In this embodiment, FS = 7.6mm * 5.7mm, f = 35mm, and WD = 133mm. According to the following formula, the size of the image captured by the industrial camera in a single exposure is 40.4mm x 30.3mm. Based on the actual resolution of the industrial camera's detection array (4024 * 3036), the actual physical distance represented by each pixel in the image captured by the industrial camera is approximately 0.01mm.

[0074] FOV = WD × FS / f

[0075] Furthermore, step S2 specifically includes:

[0076] Because the images acquired by the vision system contain a large area of ​​redundant space, it is necessary to extract the ROI image of the chip from the acquired images.

[0077] Specifically, Figure 2 The image shown is taken by an industrial camera. Figure 2 There is a large area of ​​redundant space. Figure 3 Showing Figure 2 The grayscale histogram of the SOP chip collected from the image is shown below. Figure 3 It can be seen that the grayscale values ​​of the chip's encapsulation are significantly different from those of the rest of the image. The ROI (Region of Interest) of the chip can be extracted from the acquired chip image using a global thresholding method. To ensure that the chip's complete encapsulation and all pins are included within the captured ROI, the extraction area should be appropriately expanded.

[0078] Furthermore, step S3 specifically includes:

[0079] Because the chip may be tilted during sample collection, tilt correction is necessary to improve detection accuracy.

[0080] Specifically, the ROI image is first binarized, and the edge feature map of the chip encapsulation is obtained through edge operators. Then, the corner points in the feature map are detected, and the least squares method is used to fit a straight line based on the coordinate information of the edge corner points to calculate the slope of the straight line where the edge is located. Finally, the tilt angle is calculated through the slope, and the tilt angle is corrected accordingly.

[0081] Furthermore, step S4 specifically includes:

[0082] Twenty tilt-corrected image samples were selected and cut into 10*10 pixels from left to right and top to bottom. The resulting images were then classified according to the proportion of white portions of the chip pins in the image, resulting in different categories of images. These categories were labeled to create a dataset. In this implementation, the images were divided into nine categories.

[0083] Specifically, since the industrial camera used in this embodiment is a 2D camera, and the SOP chip pins are curved from top to bottom, the captured chip pin images will appear black in the middle and white at both ends. In this invention, the background of the sample image is light gray, the chip's encapsulation is black, the pin portion is white, and the black portion is treated as the encapsulation for image processing. The image classification principles are as follows: over 90% of the space is white for the pins, labeled "pin_A"; 80% of the space is white for the pins, labeled "pin_B"; 60% of the space is white for the pins, labeled "pin_C"; 40% of the space is white for the pins with the remainder being background, labeled "pin_D_bg"; 40% of the space is white for the pins with the remainder being the encapsulation, labeled "pin_D_pp"; 20% of the space is white for the pins with the remainder being background, labeled "pin_E_bg"; 20% of the space is white for the pins with the remainder being the encapsulation, labeled "pin_E_pp"; over 50% of the space is background, labeled "bg"; over 50% of the space is encapsulation, labeled "pp"; thus, the final dataset is obtained.

[0084] Furthermore, step S5 specifically includes:

[0085] The dataset is input into a pre-built Lenet-5 neural network model for training, resulting in a Lenet-5-based SOP chip pin defect detection model. The Lenet-5 neural network model has the following structure: Input layer: 32×32 grayscale image; First convolutional layer: using a 5*5 convolutional kernel, stride 1, ReLU activation function, image size changed from 32*32*1 to 28*28*16, convolution depth 16; Second pooling layer: using max pooling, 2*2 kernel size, stride 2; Third convolutional layer: using a 5*5 convolutional kernel, stride 1, convolution depth 32, activation function... The first layer uses ReLU, changing the image size from 14*14*16 to 10*10*32; the fourth pooling layer uses max pooling with a 2*2 kernel size, resulting in an output image size of 5*5*32 with a stride of 2; the fifth fully connected layer has 120 output neurons with ReLU activation; the sixth fully connected layer has 84 output neurons with ReLU activation; the output layer has 9 neurons, corresponding to 9 different categories, using the softmax activation function.

[0086] Unlike the traditional Lenet-5 network model, this invention replaces the sigmoid activation function with the ReLU activation function. The sigmoid activation function is prone to gradient vanishing during backpropagation (the transformation becomes too slow and the derivative approaches zero as the sigmoid approaches saturation), leading to information loss and hindering the training of deep networks. The ReLU activation function addresses this issue by setting some neurons' outputs to zero, resulting in network sparsity (better for feature selection) and reducing parameter dependencies, thus mitigating overfitting. In terms of performance, the sigmoid activation function is computationally expensive due to its exponential calculations, and the backpropagation gradient calculation involves division, further increasing computational cost. The ReLU activation function significantly reduces the overall computational burden.

[0087] Furthermore, in the traditional Lenet-5 network model, the depths of the two convolutional layers are 6 and 16, respectively. This invention changes the depths of the two convolutional layers to 16 and 32, thereby increasing the number of feature parameters.

[0088] The training process of the model is as follows: In the dataset, the training set has 2000 images per category, and the test set has 500 images per category. During training, 32 images are randomly selected from the training set in each batch and input into the pre-built Lenet-5 neural network model. The loss function is calculated based on the output of the Lenet-5 neural network model, and the formula for calculating the loss function is as follows. Directional propagation is performed based on the loss function, and the parameters of the Lenet-5 neural network model are updated through the model optimizer. In this invention, the model optimizer used for training is the Adam optimizer, with an initial learning rate of 0.0001 and a momentum factor of 0.9. When all training set images have been processed, the test set is input into the trained model for testing. After 30 training and testing iterations, the model with the best detection results on the test set is selected to obtain the SOP chip pin defect detection model based on the Lenet-5 model.

[0089]

[0090] Where i and j are constants, Loss represents the loss function, batchsize = 32 is the batch size, n is the total number of categories, and y represents the true distribution. This represents the output distribution of the Lenet-5 neural network model.

[0091] Furthermore, step S6 specifically includes:

[0092] The remaining samples are input into the SOP chip pin defect detection model based on the Lenet-5 model to obtain the detection results of the sample pins.

[0093] Specifically, a sample is fed into a SOP chip pin defect detection model based on the Lenet-5 model. The pins are cut and identified from top to bottom in a 10*10 dimension, starting from the columns closest to the left and right sides of the molded package. All positions of the most easily identifiable "pin_A" type in that column are recorded. "Pin_A" positions within the same pin are always adjacent. When there is a large position span, it indicates that the "pin_A" positions are from different pins. The number of adjacent "pin_A" positions on one side of the molded package is recorded. In this invention, the chip package type is SOP8, and each side of the molded package has 4 pins, therefore there are 4 sets of adjacent "pin_A" positions. If there are fewer than 4 sets, it indicates a missing pin. Figure 4 This shows a missing chip pin (indicated by a rectangle). Figure 5 The accompanying diagram illustrates how to detect the length, width, curvature, and spacing of chip pins. Figure 5 In this code, A represents "pin_A", C represents "pp" or "bg", and B represents other labels. The process involves cutting and identifying pins column by column from top to bottom, finding the upper and lower boundaries of each column's pins. Starting with a given pin, identification proceeds from top to bottom. When the first A is identified, its position is recorded, and identification continues up and down until a C is identified, ending the identification of the current column. Therefore, each column of a pin should have a pair of A and C, with the upper boundary of the pin in the current column being the position above A, and the lower boundary being the position above C. By determining and adjusting the label above A, the upper boundary of the pin in that column can be obtained; similarly, by determining and adjusting the label above C, the lower boundary can be obtained. The adjustment rules are as follows. Upper Boundary: When "pin_B" is detected, adjust upwards by 8 pixels from point A, "pin_C" by 6 pixels, "pin_D_bg" and "pin_D_pp" by 4 pixels, "pin_E_bg" and "pin_E_pp" by 2 pixels, and "bg" and "pp" are not adjusted. Lower Boundary: When "pin_A" is detected, no adjustment is made. When "pin_B" is detected, adjust upwards by 2 pixels from point C, "pin_C" by 4 pixels, "pin_D_bg" and "pin_D_pp" by 6 pixels, and "pin_E_bg" and "pin_E_pp" by 8 pixels. Each column of pins can obtain an upper boundary coordinate and a lower boundary coordinate; one pin can obtain multiple upper and lower boundary coordinates. Find the maximum difference within the upper boundary, i.e. Figure 5 The maximum difference between the gray lines T_Y2 and T_Y1 in the diagram is found at the lower boundary. Figure 5 The spacing between the gray lines B_Y2 and B_Y1 in the image. If both differences are greater than 10 pixels, the pin is considered bent. Chip width = B_Y2 - T_Y1. The column preceding the first occurrence of "pin_A" is segmented and its corresponding x-coordinate is calculated; the smallest x-coordinate represents the front end of the pin. The column following the last occurrence of "pin_A" is image-recognized and its corresponding x-coordinate is calculated; the largest x-coordinate represents the rear end of the pin. Figure 5 The red lines x1 and x2 indicate the pin length. Therefore, the chip length = x2 - x1. The pin spacing is the perpendicular distance from the center line of the current pin to the center line of the next pin. The center line is the line exactly midway between the upper and lower boundaries of the pin. Figure 5 (T_Y1+B_Y2) / 2. Figure 6 , Figure 7 The images show pin bending and pin length defects, respectively.

[0094] like Figure 8 As shown, this invention provides a SOP chip pin defect detection system based on the Lenet-5 model. The system includes:

[0095] Acquisition module 100 is used to acquire images of the chip to be tested;

[0096] ROI image extraction module 200 is used to extract the ROI image of the chip from the acquired image;

[0097] The correction module 300 is used to correct the tilt of the ROI image to obtain a corrected image sample set.

[0098] The cutting and classification module 400 is used to select several image samples and cut them, classify the cut images into different categories and label them to create a dataset.

[0099] The model training module 500 is used to input the dataset into a pre-built Lenet-5 neural network model for training, so as to obtain a SOP chip pin defect detection model based on the Lenet-5 model.

[0100] The detection module 600 is used to input the sample into the SOP chip pin defect detection model based on the Lenet-5 model to obtain the detection results of the sample pin;

[0101] The model training module 500 specifically includes the following steps:

[0102] The dataset is divided into a training set and a test set in a ratio of 4:1.

[0103] For each batch, a set number of images are randomly selected from the training set and input into the pre-built Lenet-5 neural network model. The loss function is calculated based on the output of the Lenet-5 neural network model.

[0104] Directional propagation is performed based on the loss function, and the parameters of the Lenet-5 neural network model are updated through the model optimizer;

[0105] Once all training set images have been processed, the test set is input into the trained model for testing. After a preset number of training and testing cycles, the model with the best detection results on the test set is selected to obtain the SOP chip pin defect detection model based on the Lenet-5 model.

[0106] The system described above is used to implement the SOP chip pin defect detection method based on the Lenet-5 model. To avoid redundancy, it will not be described in detail here.

[0107] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

[0108] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0109] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1A device that provides the functions specified in one or more boxes.

[0110] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0111] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for detecting pin defects in SOP chips based on the Lenet-5 model, characterized in that, include: S1: Acquire an image of the chip to be tested; S2: Extract the ROI image of the chip from the acquired image; S3: Perform tilt correction on the ROI image to obtain a corrected image sample set. Specifically, this includes: binarizing the ROI image, obtaining the edge feature map of the chip encapsulation through edge operators; detecting corner points in the feature map, fitting a straight line using the least squares method based on the coordinate information of the edge corner points, and calculating the slope of the straight line containing the edge; calculating the tilt angle based on the slope, and correcting the tilt angle accordingly. S4: Select several image samples and cut them from left to right and from top to bottom according to the set size of 10×10. Divide the cut images into different categories according to the proportion of the white part of the chip pin in the image and label them to create a dataset. S5: Input the dataset into the pre-built Lenet-5 neural network model for training to obtain an SOP chip pin defect detection model based on the Lenet-5 model. The structure of the Lenet-5 neural network model is as follows: Input layer: 32×32 grayscale image; Convolutional layer 1: using a 5*5 convolutional kernel, stride 1, ReLU activation function, and convolution depth 16; Pooling layer 2: using max pooling, pooling kernel size 2*2, stride 2; Convolutional layer 3: using a 5*5 convolutional kernel, stride 1, convolution depth 32, ReLU activation function; Pooling layer 4: using max pooling, pooling kernel size 2*2, stride 2; Fully connected layer 5: output 120 neurons, ReLU activation function; Fully connected layer 6: output 84 neurons, ReLU activation function; Output layer: 9 neurons, corresponding to 9 different types, using softmax activation function. S6: Input the sample into the SOP chip pin defect detection model based on the Lenet-5 model to obtain the detection results of the sample pin; Step S5 specifically includes the following steps: S51: Divide the dataset into a training set and a test set in a ratio of 4:1; S52: For each batch, a set number of images are randomly selected from the training set and input into the pre-built Lenet-5 neural network model. The loss function is calculated based on the output of the Lenet-5 neural network model, and the loss function is expressed as follows: Where i and j are constants, Loss represents the loss function, batchsize is the batch size, n is the total number of categories, and y represents the true distribution. This represents the output distribution of the Lenet-5 neural network model; S53: Perform directional propagation based on the loss function, and update the parameters of the Lenet-5 neural network model through the model optimizer; S54: When all training set images have been processed, the test set is input into the trained model for testing; after a preset number of training and testing cycles, the model with the best test set detection results is selected to obtain the SOP chip pin defect detection model based on the Lenet-5 model.

2. The method for detecting pin defects of SOP chips based on the Lenet-5 model according to claim 1, characterized in that, The method for extracting the ROI image of the chip from the acquired image is as follows: The ROI image of the chip is extracted from the acquired chip image using a global threshold segmentation method.

3. The method for detecting pin defects of SOP chips based on the Lenet-5 model according to claim 1, characterized in that, The sample is input into the SOP chip pin defect detection model based on the Lenet-5 model to obtain the detection results of the sample pins, specifically including: The samples are input into the SOP chip pin defect detection model based on the Lenet-5 model. By identifying the image of each pin boundary of the chip, its category is determined. Based on the category, the size that needs to be adjusted when calculating the pin parameters is determined. Finally, it is determined whether there are defects in the chip pins.

4. A pin defect detection system for SOP chips based on the Lenet-5 model, characterized in that, The system is used to implement the SOP chip pin defect detection method based on the Lenet-5 model as described in any one of claims 1 to 3, including: The acquisition module is used to acquire images of the chip under test. The ROI image extraction module is used to extract the ROI image of the chip from the acquired image; The correction module is used to correct the tilt of the ROI image and obtain a corrected image sample set; The cutting and classification module is used to select several image samples and cut them, classify the cut images into different categories and label them to create a dataset. The model training module is used to input the dataset into a pre-built Lenet-5 neural network model for training, so as to obtain a SOP chip pin defect detection model based on the Lenet-5 model. The detection module is used to input the sample into the SOP chip pin defect detection model based on the Lenet-5 model to obtain the detection results of the sample pin; The model training module specifically includes the following steps: The dataset is divided into a training set and a test set in a ratio of 4:

1. For each batch, a set number of images are randomly selected from the training set and input into the pre-built Lenet-5 neural network model. The loss function is calculated based on the output of the Lenet-5 neural network model. Directional propagation is performed based on the loss function, and the parameters of the Lenet-5 neural network model are updated through the model optimizer; Once all training set images have been processed, the test set is input into the trained model for testing. After a preset number of training and testing cycles, the model with the best detection results on the test set is selected to obtain the SOP chip pin defect detection model based on the Lenet-5 model.

5. A network device, characterized in that, The device includes a processor, a memory, and a bus system, wherein the processor and the memory are connected via the bus system, the memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to implement the SOP chip pin defect detection method based on the Lenet-5 model as described in any one of claims 1 to 3.

6. A computer storage medium, characterized in that, The computer storage medium stores a computer software product, which includes several instructions for causing a computer device to execute the SOP chip pin defect detection method based on the Lenet-5 model as described in any one of claims 1 to 3.

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