Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a plurality of light-emitting sub-pixels, a plurality of light-emitting sub-pixels in the same row are connected with two scanning signal lines respectively, and adjacent two columns of light-emitting sub-pixels are connected with the same data signal line. A data signal compensation circuit comprises a direct connection module connected between a signal fan-out line and a data signal line, and a compensation module connected between the signal fan-out line and the data signal line and used for voltage compensation of the data signal. The control end of the direct connection module and the control end of the compensation module are connected with a compensation driving signal line. The compensation driving signal line is used for providing a compensation driving signal. According to the embodiment of the application, the pixel voltage difference between two kinds of light-emitting sub-pixels receiving scanning signals in sequence can be reduced, the light-emitting brightness difference between the two kinds of light-emitting sub-pixels can be reduced, the vertical stripe phenomenon can be improved, and the display effect of the display panel can be improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, at present, the layout mode of the signal line is usually a dual-gate architecture, that is, the light-emitting sub-pixels in the same row are connected with two scanning signal lines respectively, the two scanning signal lines output scanning signals in sequence, and the two light-emitting sub-pixels in the same row connected with the two scanning signal lines can share the same data signal line, which can provide data signals for the two light-emitting sub-pixels in sequence, thereby realizing the multiplexing of the data signal line. In the improved architecture, the number of scanning signal lines is doubled, and the number of data signal lines is halved. Since the cost of the data signal line is relatively high, by reducing the number of data signal lines, the panel cost can be effectively saved, and the frame width of the display panel can be reduced.

[0003] When the scanning signal occurs non-enabled jump, the pixel voltage received by the light-emitting sub-pixel will be affected by the parasitic capacitance between the pixel electrode and the scanning signal line, a feedthrough voltage is generated, which causes the pixel voltage to decrease. For the light-emitting sub-pixels connected with the two scanning signal lines in the same row, since there is an overlap between the effective level intervals of the two scanning signal lines, part of the light-emitting sub-pixels are only affected by the parasitic capacitance between one scanning signal line and the pixel electrode, and the other part of the light-emitting sub-pixels are affected by the parasitic capacitance between the two scanning signal lines and the pixel electrode. Therefore, the feedthrough voltages generated by the two kinds of light-emitting sub-pixels in the same row are different, which causes the two kinds of light-emitting sub-pixels to receive different pixel voltages, thereby generating a brightness difference, resulting in alternating bright and dark vertical lines. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device, which can solve the technical problem that the feedthrough voltages generated by the light-emitting sub-pixels in the same row are different, and alternating bright and dark vertical lines are generated.

[0005] In a first aspect, the embodiments of the present application provide a display panel, which comprises:

[0006] a plurality of light-emitting sub-pixels arranged in an array, the light-emitting sub-pixels in the same row are connected with two scanning signal lines respectively, and adjacent two columns of light-emitting sub-pixels connected with different scanning signal lines are connected with the same data signal line; the display panel further comprises a data signal compensation circuit, the data signal compensation circuit comprises:

[0007] a direct connection module connected between a signal fan-out line and a data signal line, the signal fan-out line and the data signal line are used to provide data signals for the light-emitting sub-pixels;

[0008] The compensation module is connected between the signal fan-out line and the data signal line, and is configured to provide voltage compensation for the data signal provided by the signal fan-out line.

[0009] The control end of the direct connection module is connected with a compensation driving signal line, and the control end of the compensation module is connected with the compensation driving signal line; the compensation driving signal line is configured to provide a compensation driving signal.

[0010] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel of the first aspect.

[0011] Compared with the prior art, the display panel and the display device provided by the embodiment of the present application can drive the direct connection module and the compensation module to be alternately turned on by using the compensation driving signal line. When the same data signal line provides data signals for two light-emitting sub-pixels in each row of two columns of light-emitting sub-pixels in turn, the direct connection module and the compensation module can be driven to be alternately turned on, so that the two light-emitting sub-pixels respectively receive the uncompensated data signal and the compensated data signal. Since the two light-emitting sub-pixels connected with the two scanning signal lines in the same row are respectively affected by the once feed-through voltage and the twice feed-through voltage, by respectively providing the uncompensated data signal and the compensated data signal, the pixel voltage difference between the two light-emitting sub-pixels can be reduced, thereby reducing the light-emitting brightness difference between the two light-emitting sub-pixels, improving the vertical stripe phenomenon, and improving the display effect of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0013] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0014] Figure 2 is a circuit structural schematic diagram of a light-emitting sub-pixel receiving a scanning signal in the same row in an embodiment of the present application;

[0015] Figure 3 is a signal timing diagram of the data signal received by the light-emitting sub-pixel in the embodiment; Figure 2

[0016] Figure 4 is a circuit structural schematic diagram of a light-emitting sub-pixel receiving a scanning signal in the same row in an embodiment of the present application;​

[0017] Figure 5 is Figure 4 A signal timing diagram of a data signal received by a light-emitting sub-pixel in an embodiment;

[0018] Figure 6 is a circuit structure schematic diagram of a data signal compensation circuit provided by an embodiment of the present application;

[0019] Figure 7 is a connection schematic diagram of a data signal compensation circuit and a compensation driving signal line provided by an embodiment of the present application;

[0020] Figure 8 is a connection schematic diagram of a data signal compensation circuit and a compensation driving signal line provided by another embodiment of the present application;

[0021] Figure 9 is a signal timing diagram of a signal fan-out line and a data signal line provided by an embodiment of the present application;

[0022] Figure 10 is a structure schematic diagram of a display panel provided by another embodiment of the present application;

[0023] Figure 11 is a structure schematic diagram of a display panel provided by yet another embodiment of the present application;

[0024] Figure 12 is a structure schematic diagram of a multi-path gating module provided by an embodiment of the present application;

[0025] Figure 13 is a structure schematic diagram of a display device provided by an embodiment of the present application.

[0026] In the drawings:

[0027] 10, light-emitting sub-pixel; 20, data signal compensation circuit; 21, direct connection module; 22, compensation module; 30, driving chip; 40, multi-path gating module; V1, compensation voltage port; 221, first switch unit; 222, second switch unit; 223, voltage compensation unit; Cp, compensation driving signal line; Cp1, first driving signal line; Cp2, second driving signal line; 11, first light-emitting sub-pixel group; 12, second light-emitting sub-pixel group; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; C, first capacitor. DETAILED DESCRIPTION

[0028] The features and exemplary embodiments of the various aspects of the present application will be described in detail below with reference to the drawings. For the purpose of clarity, not all of the individual features of the application are described in detail herein. The specific embodiments described herein are intended to explain the best mode of the application, and are not intended to limit the scope of the application. The present application can be implemented without some of the specific details of the embodiments described herein. The following description of the embodiments is merely provided to give a better understanding of the present application.

[0029] It should be noted that the relative terms, such as first and second, etc., are used herein only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements recited, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the phrase "comprising" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0030] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The embodiments will be described in detail below with reference to the accompanying drawings.

[0031] With the continuous development of display technology, at present, the layout mode of the signal line is usually a dual-gate architecture, that is, the light-emitting sub-pixels in the same row are respectively connected with two scanning signal lines, and the two scanning signal lines output scanning signals in sequence. The two light-emitting sub-pixels in the same row connected with the two scanning signal lines can share the same data signal line, and the data signal line can provide data signals for the two light-emitting sub-pixels in sequence, thereby realizing multiplexing of the data signal line. In the improved architecture, the number of scanning signal lines is doubled, and the number of data signal lines is reduced to half of the original number. Since the cost of the data signal line is relatively high, by reducing the number of data signal lines, the panel cost can be effectively saved, and the frame width of the display panel can be reduced.

[0032] When the scan signal is not enabled to jump, the pixel voltage received by the light-emitting sub-pixel will be affected by the parasitic capacitance between the pixel electrode and the scan signal line, a feedthrough voltage is generated, resulting in a decrease in the pixel voltage. For the light-emitting sub-pixels connected to two scan signal lines in the same row, due to the overlap of the effective level interval of the two scan signal lines, part of the light-emitting sub-pixels are only affected by the parasitic capacitance between one scan signal line and the pixel electrode, and the other part of the light-emitting sub-pixels are affected by the parasitic capacitance between the two scan signal lines and the pixel electrode. Therefore, the feedthrough voltages generated by the two types of light-emitting sub-pixels in the same row are different, resulting in different pixel voltages received by the two types of light-emitting sub-pixels, thereby generating a brightness difference, resulting in a bright and dark alternating vertical stripe.

[0033] To solve the above technical problems, the display panel and the display device are provided. First, the display panel provided by the embodiments of the present application is introduced.

[0034] Figure 1 The structure schematic diagram of the display panel provided by an embodiment of the present application is shown. The display panel includes a plurality of light-emitting sub-pixels 10 arranged in an array.

[0035] In the plurality of light-emitting sub-pixels 10 arranged in an array, the plurality of light-emitting sub-pixels 10 in the same row are respectively connected to two scan signal lines. That is, each row of light-emitting sub-pixels 10 corresponds to two scan signal lines. When n rows of light-emitting sub-pixels 10 are arranged in an array in the display panel, the n rows of light-emitting sub-pixels 10 are connected to 2n scan signal lines. As shown, taking part of the light-emitting sub-pixels 10 of the display panel as an example, four rows of light-emitting sub-pixels are respectively connected to eight scan signal lines, and six columns of light-emitting sub-pixels are respectively connected to three data signal lines. Through the above wiring arrangement design, the doubling of the scan signal lines and the halving of the data signal lines can be realized. Figure 1

[0036] For the two adjacent columns of light-emitting sub-pixels 10, each row includes two light-emitting sub-pixels 10, and the two light-emitting sub-pixels 10 are respectively connected to different scan signal lines. The two adjacent columns of light-emitting sub-pixels 10 are connected to the same data signal line. That is, one data signal line is connected to two columns of light-emitting sub-pixels 10, and the two light-emitting sub-pixels 10 connected to the data signal line in each row are respectively connected to two scan signal lines.

[0037] The display panel can further include a data signal compensation circuit 20, and the data signal compensation circuit 20 includes a direct connection module 21 and a compensation module 22.

[0038] As shown in Figure 1 ​As shown, S1, S2, S3 and S4 are a plurality of data signal lines respectively, and Fa1, Fa2, Fa3 and Fa4 are a plurality of signal fan-out lines respectively. The direct connection module 21 is connected between the signal fan-out line and the data signal line, and the signal fan-out line can provide the data signal for the data signal line through the direct connection module 21, and the data signal line can provide the data signal for the light-emitting sub-pixel 10 connected thereto.

[0039] The compensation module 22 is connected between the signal fan-out line and the data signal line, and the compensation module 22 can perform voltage compensation on the data signal provided by the signal fan-out line, and provide the compensated data signal to the data signal line, so as to provide the compensated data signal for the light-emitting sub-pixel 10 connected to the data signal line.

[0040] The control end of the direct connection module 21 is connected with the compensation driving signal line Cp, and the control end of the compensation module 22 is also connected with the compensation driving signal line Cp. The compensation driving signal line Cp can provide a compensation driving signal to drive the direct connection module 21 and the compensation module 22 to be turned on alternately.

[0041] As shown in the figure, Figure 1 For example, as the data signal compensation circuit 20 is arranged between the signal fan-out line Fa2 and the data signal line S2, when the compensation driving signal drives the direct connection module 21 to be turned on, the data signal provided by the signal fan-out line Fa2 can be directly output to the data signal line S2 through the direct connection module 21, and provided to the light-emitting sub-pixel 10 through the data signal line S2. When the compensation driving signal drives the compensation module 22 to be turned on, the data signal provided by the signal fan-out line Fa2 can be provided to the light-emitting sub-pixel 10 through the data signal line S2 after being compensated by the compensation module 22.

[0042] In the above connection mode of the plurality of light-emitting sub-pixels 10 and the data signal line and the scan signal line, the light-emitting sub-pixels 10 in the same row are connected with two scan signal lines. A single data signal line is connected with two columns of light-emitting sub-pixels 10. The above wiring connection mode can increase the number of scan signal lines to twice the original number, and reduce the number of data signal lines to one half of the original number, thereby reducing the number of data signal lines arranged in the display panel, effectively saving the panel cost and reducing the frame width of the display panel.

[0043] In the above design, when the scan signal lines output the scan signals row by row, the light emitting sub-pixels 10 in the same row are connected to two scan signal lines respectively, so that a part of the light emitting sub-pixels 10 receive the scan signals first, and another part of the light emitting sub-pixels 10 receive the scan signals later. Taking two light emitting sub-pixels 10 in the same row as an example, the two light emitting sub-pixels 10 are connected to different scan signal lines respectively and connected to the same data signal line. One of the two light emitting sub-pixels 10 receives the scan signal first, and the driving chip 30 can provide the corresponding data signal through the signal fan-out line and the data signal line within the effective interval of the scan signal. The other light emitting sub-pixel 10 receives the scan signal later, and the driving chip 30 can also provide the corresponding data signal through the same signal fan-out line and the same data signal line within the effective interval of the scan signal. That is, the same data signal line can be used to provide the corresponding data signals to the two light emitting sub-pixels 10 in the same row in sequence within the effective intervals of the two scan signals, so as to realize the writing of the data signals.

[0044] When the scan signal occurs a non-enabling jump, that is, the scan signal jumps from the effective signal to the non-effective signal, the pixel voltage received by the light emitting sub-pixel 10 will be affected by the parasitic capacitance between the pixel electrode and the scan signal line, a feed-through voltage is generated, and the pixel voltage is reduced. For the two light emitting sub-pixels 10 in the same row connected to two scan signal lines respectively, since there is an overlap between the effective level intervals of the two scan signal lines, for the light emitting sub-pixel 10 receiving the scan signal first, when the non-enabling jump of the scan signal received by itself occurs and the non-enabling jump of the next scan signal occurs, the light emitting sub-pixel 10 is affected by the parasitic capacitance between the two scan signal lines and the pixel electrode, thereby generating two feed-through voltages. For the light emitting sub-pixel 10 receiving the scan signal later, when the non-enabling jump of the scan signal received by itself occurs, the light emitting sub-pixel 10 is only affected by the parasitic capacitance between one scan signal line and the pixel electrode. That is, for the two light emitting sub-pixels 10 connected to the same data signal line and different scan signal lines, one of the light emitting sub-pixels 10 is affected by two feed-through voltages, and the other light emitting sub-pixel 10 is only affected by one feed-through voltage. In this case, the two light emitting sub-pixels 10 will receive different pixel voltages, thereby generating a brightness difference. Since in the same row, a brightness difference occurs between every two light emitting sub-pixels 10, and in every adjacent two columns of light emitting sub-pixels 10, a brightness difference also occurs between one column of light emitting sub-pixels 10 and another column of light emitting sub-pixels 10, finally leading to the generation of bright and dark vertical stripes in the image picture displayed by the display panel, which seriously affects the display effect of the display panel.

[0045] Please refer to Figures 2 to 5 , Figure 2 FIG. 4 is a schematic diagram of a pixel circuit structure of the light emitting sub-pixel 10 receiving the scan signal later, Figure 3This is a schematic diagram of the pixel voltage affected by a first feedthrough voltage for the light-emitting sub-pixel; Figure 4 This is a schematic diagram of the pixel circuit structure of the light-emitting sub-pixel 10 that receives the scanning signal first. Figure 5 This is a schematic diagram of the pixel voltage affected by the secondary feedthrough voltage for the light-emitting sub-pixel.

[0046] like Figure 2 As shown, for the light-emitting sub-pixel 10 that receives the scanning signal later, the parasitic capacitance formed between it and the corresponding scanning signal line Gaten is Cpg. Figure 3 The diagram shows that when the scan signal undergoes a de-enable transition, the signal voltage of the data signal received by the light-emitting sub-pixel 10 is affected by the coupling of the parasitic capacitance Cpg, resulting in a voltage decrease. The magnitude of this voltage decrease is the first feedthrough voltage.

[0047] like Figure 4 As shown, for the light-emitting sub-pixel 10 that receives the scan signal first, the parasitic capacitance formed between it and the corresponding scan signal line Gaten is Cpg, and the parasitic capacitance formed between it and the scan signal line Gaten+1 of the next row is Cpg'. Figure 5 The diagram shows that when the scan signal line Gaten undergoes a de-enable transition, the signal voltage of the data signal received by the light-emitting sub-pixel 10 is affected by the coupling of the parasitic capacitance Cpg; when the scan signal line Gaten+1 undergoes a de-enable transition, the signal voltage of the data signal received by the light-emitting sub-pixel 10 is affected by the coupling of the parasitic capacitance Cpg', that is, the data signal is affected by the two feedthrough voltages.

[0048] In the above embodiments, by setting a compensation driving signal line Cp to provide a compensation driving signal, and alternately driving the direct connection module 21 and the compensation module 22 to conduct, when the data signal line provides a data signal to the light-emitting sub-pixel 10 affected by only one feedthrough voltage, the compensation driving signal can drive the direct connection module 21 to conduct, so that the light-emitting sub-pixel 10 can directly receive the data signal; while when the data signal line provides a data signal to the light-emitting sub-pixel 10 affected by two feedthrough voltages, the compensation driving signal can drive the compensation module 22 to conduct, providing the light-emitting sub-pixel 10 with a voltage-compensated data signal. This compensated data signal can compensate for the influence of two feedthrough voltages, thereby reducing the difference between the pixel voltage finally received by the light-emitting sub-pixel 10 affected by two feedthrough voltages and the pixel voltage received by the light-emitting sub-pixel 10 affected by only one feedthrough voltage, and thus reducing the difference in luminous brightness between the two light-emitting sub-pixels 10.

[0049] It should be noted that according to the influence of the single-time feed-through voltage and the twice feed-through voltage on the pixel voltage, the compensation voltage provided by the compensation module 22 when compensating the data signal can be adjusted to make the pixel voltage of the light-emitting sub-pixel 10 affected by the twice feed-through voltage consistent with the pixel voltage of the light-emitting sub-pixel 10 affected by the single-time feed-through voltage, so that the luminance of the two light-emitting sub-pixels 10 under the same data signal remains consistent, thereby avoiding the bright-dark vertical stripes of the display panel.

[0050] For the two light-emitting sub-pixels 10 in the same row in the two adjacent columns, a single data signal compensation circuit 20 can be provided to drive the direct connection module 21 and the compensation module 22 to be turned on alternately by using the compensation driving signal, so that the two light-emitting sub-pixels 10 in each row alternately receive the uncompensated data signal and the compensated data signal, thereby reducing the luminance difference between the two light-emitting sub-pixels 10 due to different degrees of feed-through voltage.

[0051] For the multiple columns of light-emitting sub-pixels 10, a data signal compensation circuit 20 can be provided between each data signal line and the signal fan-out line, that is, multiple data signal compensation circuits 20 consistent with the number of data signal lines are provided to compensate for the difference in feed-through voltage of the multiple columns of light-emitting sub-pixels 10 in the display panel, thereby reducing the luminance difference between the light-emitting sub-pixels 10 in the display panel due to different degrees of feed-through voltage and improving the display effect of the display panel.

[0052] In this embodiment, the data signal compensation circuit 20 is provided to drive the direct connection module 21 and the compensation module 22 to be turned on alternately by using the compensation driving signal. When the same data signal line provides data signals for the two light-emitting sub-pixels 10 in each row in the two adjacent columns, the direct connection module 21 and the compensation module 22 can be driven to be turned on alternately, so that the two light-emitting sub-pixels 10 receive the uncompensated data signal and the compensated data signal, respectively. Since the two light-emitting sub-pixels 10 are affected by the single-time feed-through voltage and the twice feed-through voltage, respectively, by providing the uncompensated data signal and the compensated data signal, respectively, the pixel voltage difference between the two light-emitting sub-pixels 10 can be reduced, thereby reducing the luminance difference between the two light-emitting sub-pixels 10, improving the vertical stripe phenomenon, and improving the display effect of the display panel.

[0053] For details, please refer to Figure 6 In some embodiments, the compensation module 22 described above can include a compensation voltage port V1, a first switch unit 221, a second switch unit 222, and a voltage compensation unit 223.

[0054] The compensation voltage port V1 can provide a first compensation voltage.

[0055] The first end of the first switch unit 221 can be connected with the compensation voltage port V1. The first end of the second switch unit 222 can be connected with the signal fan-out line, and the second end of the second switch unit 222 can be connected with the data signal line.

[0056] As shown in Figure 6 , Fan is a signal fan-out line, and Sn is a data signal line corresponding to the signal fan-out line Fan. The voltage compensation unit 223 can be connected with the second end of the first switch unit 221 and the third end of the second switch unit 222 respectively. The voltage compensation unit 223 can receive the first compensation voltage through the first switch unit 221, and the voltage compensation unit 223 can also compensate the data signal provided by the signal fan-out line Fan by the first compensation voltage, and provide the compensated data signal to the data signal line Sn.

[0057] It can be understood that the voltage compensation unit 223 can alternately perform the acquisition of the first compensation voltage and the voltage compensation of the data signal. For example, when the direct connection module 21 is turned on, the voltage compensation unit 223 can receive the first compensation voltage through the first switch unit 221, that is, the charging process; when the compensation module 22 is turned on, the voltage compensation unit 223 can compensate the first compensation voltage to the data signal through the second switch unit 222, that is, the discharging process. When the direct connection module 21 and the compensation module 22 are alternately turned on, the voltage compensation unit 223 can alternately perform charging and discharging to realize the voltage compensation of the data signal.

[0058] In some embodiments, the above-mentioned compensation driving signal can include alternately outputted first driving signal and second driving signal.

[0059] The first driving signal can drive the direct connection module 21 to be turned on and drive the first switch unit 221 to be turned on. Under the first driving signal, the direct connection module 21 is turned on, and the compensation module 22 is turned off. The voltage compensation unit 223 in the compensation module 22 can receive the first compensation voltage through the turned-on first switch unit 221.

[0060] The second driving signal can drive the direct connection module 21 to be turned off and drive the second switch unit 222 to be turned on. Under the second driving signal, the direct connection module 21 is turned off, and the compensation module 22 is turned on. The voltage compensation unit 223 in the compensation module 22 can compensate the data signal by the first compensation voltage through the turned-on second switch unit 222, and output the compensated data signal to the data signal line.

[0061] Please continue to refer to Figure 6 , in some embodiments, the above-mentioned direct connection module 21 can include a first transistor T1, and the first transistor T1 can be connected between the signal fan-out line Fan and the data signal line Sn.

[0062] The first driving signal and the second driving signal are respectively a conducting signal and a cutoff signal of the first transistor T1. The gate of the first transistor T1 is connected with the compensation driving signal line Cp, and the first transistor T1 can be turned on when receiving the first driving signal, so as to connect the signal fan-out line Fan with the data signal line Sn, so that the data signal line Sn receives the data signal without compensation. The first transistor T1 can also be turned off when receiving the second driving signal, so that the signal fan-out line Fan cannot be connected with the data signal line Sn through the direct connection module 21.

[0063] Please continue to refer to Figure 6 In some embodiments, the voltage compensation unit 223 described above can include a first capacitor C.

[0064] The first switch unit 221 can include a second transistor T2 and a third transistor T3, the second transistor T2 being connected between the first end of the first capacitor C and the compensation voltage port V1, and the third transistor T3 being connected between the second end of the first capacitor C and the ground terminal GND.

[0065] The second switch unit 222 can include a fourth transistor T4 and a fifth transistor T5, the fourth transistor T4 being connected between the first end of the first capacitor C and the data signal line Sn, and the fifth transistor T5 being connected between the second end of the first capacitor C and the signal fan-out line Fan.

[0066] Under the first driving signal, the first switch unit 221 is turned on, and the second switch unit 222 is turned off, i.e. the second transistor T2 and the third transistor T3 are turned on, at this time the two ends of the first capacitor C are connected with the compensation voltage port V1 and the ground terminal GND respectively, and the voltage difference between the compensation voltage port V1 and the ground terminal GND is the first compensation voltage. The first capacitor C can be charged under the first compensation voltage, so that the voltage difference between the two plates of the first capacitor C becomes the first compensation voltage. At this time, the direct connection module 21 is turned on under the first driving signal, and the data signal line Sn receives the data signal without compensation.

[0067] Under the second driving signal, the second switch unit 222 is turned on, and the first switch unit 221 is turned off, i.e. the fourth transistor T4 and the fifth transistor T5 are turned on. The first end of the first capacitor C is connected with the data signal line Sn, and the second end is connected with the signal fan-out line Fan, and the first capacitor C can capacitively couple the data signal provided by the signal fan-out line Fan, so that the voltage at the other end is raised to the sum of the data signal and the first compensation voltage, and is output to the corresponding light-emitting sub-pixel 10 through the data signal line Sn.

[0068] Under the alternate driving of the first driving signal and the second driving signal, different light-emitting sub-pixels 10 respectively receive the uncompensated data signal and the compensated data signal, so that the light-emitting sub-pixels 10 affected by different feedthrough voltages can reduce the difference of the received pixel voltages under targeted voltage compensation, and then reduce the difference of the light-emitting brightness, thereby improving the vertical stripe phenomenon of the display panel.

[0069] Please refer to Figure 7 In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are the same type of transistors, for example, the above-mentioned transistors can be all set as N-type transistors, or all set as P-type transistors.

[0070] The compensation driving signal line Cp can include a first driving signal line Cp1 and a second driving signal line Cp2. The first driving signal line Cp1 is connected with the control end of the first transistor T1, the control end of the second transistor T2 and the control end of the third transistor T3, and the first driving signal line Cp1 can provide the first driving signal.

[0071] The second driving signal line Cp2 is connected with the control end of the fourth transistor T4 and the control end of the fifth transistor T5, and the second driving signal line Cp2 can provide the second driving signal.

[0072] The first driving signal is an alternating high-low level signal, and the first driving signal and the second driving signal are inverse signals of each other.

[0073] As Figure 7 shown, taking the above five transistors as N-type transistors as an example, for N-type transistors, the high-level signal is a conduction signal, and the low-level signal is a cut-off signal. The first driving signal and the second driving signal alternately output high-low level signals, and when the first driving signal is a high-level signal, the second driving signal is a low-level signal. Therefore, when the first driving signal is a high-level signal, the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, and the fourth transistor T4 and the fifth transistor T5 are cut off; when the first driving signal is a low-level signal, the first transistor T1, the second transistor T2 and the third transistor T3 are cut off, and the fourth transistor T4 and the fifth transistor T5 are turned on.

[0074] Please refer to Figure 8 In some embodiments, the first transistor T1, the second transistor T2 and the third transistor T3 are one of N-type transistors or P-type transistors, and the fourth transistor T4 and the fifth transistor T5 are the other of N-type transistors or P-type transistors.

[0075] The compensation driving signal line Cp can be connected to the control end of the first transistor T1, the control end of the second transistor T2, the control end of the third transistor T3, the control end of the fourth transistor T4, and the control end of the fifth transistor T5. The compensation driving signal line Cp can provide alternating high and low level signals.

[0076] As shown in Figure 8 , taking the first transistor T1, the second transistor T2, the third transistor T3 as N-type transistors, and the fourth transistor T4 and the fifth transistor T5 as P-type transistors as an example, when the compensation driving signal line Cp outputs a high level signal, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, and the fourth transistor T4 and the fifth transistor T5 are turned off; when the compensation driving signal line Cp outputs a low level signal, the first transistor T1, the second transistor T2, and the third transistor T3 are turned off, and the fourth transistor T4 and the fifth transistor T5 are turned on.

[0077] Similarly, when the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors, and the fourth transistor T4 and the fifth transistor T5 are N-type transistors, when the compensation driving signal line Cp outputs a low level signal, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, and the fourth transistor T4 and the fifth transistor T5 are turned off; when the compensation driving signal line Cp outputs a high level signal, the first transistor T1, the second transistor T2, and the third transistor T3 are turned off, and the fourth transistor T4 and the fifth transistor T5 are turned on.

[0078] Please refer to Figure 9 , Figure 9 When the signal voltage of the data signal output by the signal fan-out line Fan remains unchanged, the compensation driving signal line Cp alternately outputs high and low level signals, which can drive the direct connection module 21 and the compensation module 22 to alternately conduct. The signal voltage of the data signal on the data signal line Sn in the t1-t3 interval is the data signal without compensation, and the signal voltage of the data signal on the data signal line Sn in the t2-t4 interval is the compensated data signal, and the compensation amplitude is the first compensation voltage V1. By providing the data signal without compensation and the compensated data signal to the two kinds of light-emitting sub-pixels 10 affected by one-time feed-through voltage and twice feed-through voltage respectively, the different feed-through voltage effects on the two kinds of light-emitting sub-pixels 10 can be compensated, thereby reducing or eliminating the pixel voltage difference between the two kinds of light-emitting sub-pixels 10 and improving the vertical stripe phenomenon.

[0079] In some embodiments, among the multiple light-emitting sub-pixels 10 located in the same row, the first light-emitting sub-pixel and the second light-emitting sub-pixel connected to the same data signal line are respectively connected to the first scan signal line and the second scan signal line.

[0080] In the same light emitting frame, the first active voltage interval of the first scan signal line is before the second active voltage interval of the second scan signal line, and the first active voltage interval at least partially overlaps with the second active voltage interval. The active voltage intervals of two adjacent scan signal lines can be referred to as Figure 3 With Figure 5 , the active voltage interval of the scan signal line Gaten-1 overlaps with that of the scan signal line Gaten, and the active voltage interval of the scan signal line Gaten overlaps with that of the scan signal line Gaten+1.

[0081] The equivalent capacitance formed between the first light emitting sub-pixel and the first scan signal line is C1, the equivalent capacitance formed between the first light emitting sub-pixel and the second scan signal line is C2, the feedthrough compensation voltage of the light emitting sub-pixel 10 is Vcom, and the first compensation voltage is V1, wherein the relationship between the feedthrough compensation voltage and the first compensation voltage satisfies the following formula:

[0082] C1: (C1+C2) = Vcom: (Vcom+V1);

[0083] Taking the first light emitting sub-pixel and the second light emitting sub-pixel as examples, in the same light emitting frame, the first light emitting sub-pixel receives an effective signal of the scan signal in the first active voltage interval, and when the scan signal jumps to an ineffective signal, the parasitic capacitance between the pixel electrode of the first light emitting sub-pixel and the first scan signal line is coupled, resulting in that the liquid crystal voltage of the first light emitting sub-pixel is affected by a first feedthrough voltage.

[0084] The second light emitting sub-pixel receives an effective signal of the scan signal in the second active voltage interval, and when the scan signal jumps to an ineffective signal, the parasitic capacitance between the pixel electrode of the second light emitting sub-pixel and the second scan signal line is coupled, resulting in that the liquid crystal voltage of the second light emitting sub-pixel is affected by a first feedthrough voltage. At the same time, the parasitic capacitance between the pixel electrode of the first light emitting sub-pixel and the second scan signal line is also coupled, resulting in that the liquid crystal voltage of the first light emitting sub-pixel is affected by a second feedthrough voltage.

[0085] Taking the first light emitting sub-pixel as an example, the equivalent parasitic capacitance formed between the first light emitting sub-pixel and the first scan signal line connected thereto is C1. It can be understood that the equivalent parasitic capacitance formed between each light emitting sub-pixel 10 and the scan signal line connected thereto is substantially equal, that is, the equivalent parasitic capacitance formed between the second light emitting sub-pixel and the second scan signal line connected thereto is also C1.

[0086] The feedthrough voltage caused by the parasitic capacitance coupling between the light emitting sub-pixel 10 and the scanning signal line has a positive correlation with the parasitic capacitance. The first light emitting sub-pixel is capacitively coupled with the first scanning signal line and the second scanning signal line respectively at two times of feedthrough voltage influence, and the shift of the liquid crystal voltage caused by the two times of feedthrough voltage influence is positively correlated with the sum (C1+C2) of the two times of parasitic capacitance coupling. The second light emitting sub-pixel is capacitively coupled with the second scanning signal line at one time of feedthrough voltage influence, and the shift of the liquid crystal voltage caused by this time of feedthrough voltage influence is correlated with the equivalent parasitic capacitance C1 formed between the second light emitting sub-pixel and the second scanning signal line to which the second light emitting sub-pixel is connected.

[0087] For the influence of single feedthrough voltage, the cathode voltage received by the light emitting sub-pixel 10 can be adjusted from 0 voltage to a feedthrough compensation voltage Vcom, which can compensate for the influence of single feedthrough voltage.

[0088] For the influence of double feedthrough voltage, the data signal can be voltage compensated by the first compensation voltage V1. That is, when affected by single feedthrough voltage, the voltage can be compensated by the feedthrough compensation voltage Vcom; and when affected by double feedthrough voltage, the voltage can be compensated by the feedthrough compensation voltage Vcom and the first compensation voltage V1 together.

[0089] In some embodiments, when the data voltage provided by the data signal line Sn is the same, the data voltage received by the light emitting sub-pixel 10 affected by single coupling will have a voltage difference with the data voltage received by the light emitting sub-pixel 10 affected by double coupling. The voltage difference is composed of two parts, one of which is the voltage difference between the voltage drop of the light emitting sub-pixel 10 affected by single feedthrough voltage and the voltage drop of the light emitting sub-pixel 10 affected by double feedthrough voltage. The other part is the on-voltage drop of the data signal flowing through the transistor. For example, as shown in the data signal compensation circuit 20, the light emitting sub-pixel 10 affected by single coupling receives the data voltage through the first transistor T1, and the light emitting sub-pixel 10 affected by double coupling receives the data voltage coupled by the fourth transistor T4 and the fifth transistor T5 and the capacitor C. Since the total on-voltage drop of the fourth transistor T4 and the fifth transistor T5 is different from the on-voltage drop of the first transistor, it will also cause the data voltage received by the two kinds of light emitting sub-pixels 10 to be different. Figure 6

[0090] ​In order to reduce the voltage difference generated by the two light-emitting sub-pixels 10 when the same data voltage is provided on the data signal line Sn, the data voltage received by the light-emitting sub-pixel 10 under the influence of twice coupling and the data voltage received by the light-emitting sub-pixel 10 under the influence of once coupling can be determined respectively, the first compensation voltage V1 is set according to the voltage difference between the two data voltages, the difference between the data voltages received by the two light-emitting sub-pixels 10 can be compensated, so as to reduce or eliminate the voltage difference between the two light-emitting sub-pixels 10, and the vertical stripe phenomenon is improved.

[0091] In some embodiments, the feedthrough compensation voltage of the light-emitting sub-pixel 10 described above is Vcom, the first compensation voltage is V1, and the relationship between the feedthrough compensation voltage and the first compensation voltage can also satisfy the following formula:

[0092] Vcom = V1.

[0093] Taking a single light-emitting sub-pixel 10 as an example, the parasitic capacitance formed between the light-emitting sub-pixel 10 and the scan signal line corresponding to the light-emitting sub-pixel 10 is approximately equal to the parasitic capacitance formed between the light-emitting sub-pixel 10 and the next scan signal line, that is, the equivalent capacitance C1 formed between the first light-emitting sub-pixel and the first scan signal line in the above embodiment is approximately equal to the equivalent capacitance C2 formed between the first light-emitting sub-pixel and the second scan signal line. Since the size of the feedthrough voltage has a positive correlation with the parasitic capacitance, when the parasitic capacitance C1 and the parasitic capacitance C2 are approximately equal, the influence of the single feedthrough voltage and the influence of the double feedthrough voltage are also approximately equal. When the data voltage is received through the two circuits of the direct connection module 21 or the compensation module 22, the total on-voltage drop of the fourth transistor T4 and the fifth transistor T5 is smaller than the on-voltage drop of the first transistor, and the on-voltage drop of the data voltage when passing through the transistor in the two circuits can be considered consistent. Therefore, the voltage drop generated by the light-emitting sub-pixel 10 under the influence of the double feedthrough voltage can be approximately considered as twice the voltage drop generated by the light-emitting sub-pixel 10 under the influence of the single feedthrough voltage.

[0094] By setting the first compensation voltage V1 to be the same as the feedthrough compensation voltage Vcom, the light-emitting sub-pixel 10 affected by the single feedthrough voltage can be compensated by adjusting the cathode voltage to the feedthrough compensation voltage Vcom; and for the light-emitting sub-pixel 10 affected by the double feedthrough voltage, compensation is performed by adjusting the cathode voltage to the feedthrough compensation voltage Vcom and superimposing the first compensation voltage V1 on the data signal.

[0095] Please refer to Figure 10 In some embodiments, the display panel can include a plurality of first light-emitting sub-pixel groups 11 and a plurality of second light-emitting sub-pixel groups 12.

[0096] The first light emitting sub-pixel group 11 and the second light emitting sub-pixel group 12 are different in polarity, and the light emitting sub-pixels 10 included in each group of light emitting sub-pixels 10 are the same in polarity.

[0097] In the plurality of light emitting sub-pixels 10 in the same row, the first light emitting sub-pixel group 11 and the second light emitting sub-pixel group 12 are arranged alternately.

[0098] In the plurality of light emitting sub-pixels 10 in the same column, the polarities of adjacent light emitting sub-pixels 10 are different. That is, in the plurality of light emitting sub-pixels 10 in the same column, any two adjacent light emitting sub-pixels 10 belong to the first light emitting sub-pixel group 11 and the second light emitting sub-pixel group 12, respectively.

[0099] It should be noted that when the data signal line provides data signals for the light emitting sub-pixels 10 in two adjacent columns, since the polarities of any two adjacent light emitting sub-pixels 10 in each column are different, the data signal line will alternately output data signals of positive polarity and data signals of negative polarity when providing data signals for the two adjacent light emitting sub-pixels 10, so that the light emitting sub-pixels 10 of different polarities can receive data signals of different polarities.

[0100] Please continue to refer to Figure 10 In some embodiments, the first light emitting sub-pixel group 11 described above can include two light emitting sub-pixels 10 of positive polarity, and the two light emitting sub-pixels 10 of positive polarity are connected to two scanning signal lines, respectively. The second light emitting sub-pixel group 12 can include two light emitting sub-pixels 10 of negative polarity, and the two light emitting sub-pixels 10 of negative polarity are connected to two scanning signal lines, respectively.

[0101] The data signal line can include a first data signal line Sa and a second data signal line Sb. The first data signal line Sa is connected to the first light emitting sub-pixel group 11 of each row, respectively, since the light emitting sub-pixels 10 in each first light emitting sub-pixel group 11 are of positive polarity, the first data signal line Sa can provide positive polarity data signals to each light emitting sub-pixel 10 in turn when providing data signals in cooperation with the row-by-row output scanning signal.

[0102] Similarly, the second data signal line Sb is connected to the second light emitting sub-pixel group 12 of each row, respectively, since the light emitting sub-pixels 10 in each second light emitting sub-pixel group 12 are of negative polarity, the second data signal line Sb can provide negative polarity data signals to each light emitting sub-pixel 10 in turn when providing data signals in cooperation with the row-by-row output scanning signal.

[0103] It is understandable that each data signal line can provide data signals for two columns of luminous sub-pixels 10. Taking the first data signal line Sa as an example, since the polarities of two adjacent luminous sub-pixels 10 in the same column are different, the two adjacent luminous sub-pixels 10 belong to the first luminous sub-pixel group 11 and the second luminous sub-pixel group 12, respectively. That is, the left and right sides of each first luminous sub-pixel group 11 are the second luminous sub-pixel group 12, and the top and bottom sides of each first luminous sub-pixel group 11 are also the second luminous sub-pixel group 12.

[0104] like Figure 10 As shown, the first data signal line Sa can be alternately electrically connected to the first light-emitting sub-pixel groups 11 on the left and right sides during its extension. For example, when the first data signal line Sa extends into the display panel, taking the nth row of light-emitting pixels as an example, in the nth row of light-emitting sub-pixels 10, the two light-emitting sub-pixels 10 to the right of the first data signal line Sa are two positive light-emitting sub-pixels 10 in the first light-emitting sub-pixel group 11, and the two light-emitting sub-pixels 10 to the left of the first data signal line Sa are two negative light-emitting sub-pixels 10 in the second light-emitting sub-pixel group 12. Based on the above arrangement of the first light-emitting sub-pixel group 11 and the second light-emitting sub-pixel group 12, it can be seen that in the (n+1)th row, the two light-emitting sub-pixels 10 to the left of the first data signal line Sa are two positive light-emitting sub-pixels 10 in the first light-emitting sub-pixel group 11, and the two light-emitting sub-pixels 10 to the right of the first data signal line Sa are two negative light-emitting sub-pixels 10 in the second light-emitting sub-pixel group 12. The luminous sub-pixel 10 in the (n+2)th row is the same as the luminous sub-pixel 10 in the nth row, and the luminous sub-pixel 10 in the (n+3)th row is the same as the luminous sub-pixel 10 in the (n+1)th row, and so on.

[0105] like Figure 10 As shown, the wiring method for connecting the first data signal line Sa to the first light-emitting sub-pixel group 11 in each row can be as follows: in the nth row of light-emitting sub-pixels 10, the first data signal line Sa is electrically connected to the two light-emitting sub-pixels 10 on the right; in the (n+1)th row of light-emitting sub-pixels 10, the first data signal line Sa is electrically connected to the two light-emitting sub-pixels 10 on the left; in the (n+2)th row of light-emitting sub-pixels 10, the first data signal line Sa is electrically connected to the two light-emitting sub-pixels 10 on the right; in the (n+3)th row of light-emitting sub-pixels 10, the first data signal line Sa is electrically connected to the two light-emitting sub-pixels 10 on the left, and so on.

[0106] It can be understood that the first data signal line Sa extends in the display panel and is electrically connected with two positive-polarity light-emitting sub-pixels 10 in each row, and finally is electrically connected with and provides data signals for two columns of light-emitting sub-pixels 10. In the two columns of light-emitting sub-pixels 10 connected with the first data signal line Sa, the two light-emitting sub-pixels 10 in each row are not arranged in an up-down manner, but in a left-right alternating manner.

[0107] Similarly, the second data signal line Sb also extends in the display panel and is electrically connected with two negative-polarity light-emitting sub-pixels 10 belonging to the same second light-emitting sub-pixel group 12 in each row, so as to realize data signal writing for two columns of negative-polarity light-emitting sub-pixels 10.

[0108] In some embodiments, as shown in FIG. 1, the first light-emitting sub-pixel group 11 can include two positive-polarity light-emitting sub-pixels 10, and the two positive-polarity light-emitting sub-pixels 10 are respectively connected with two scanning signal lines. The second light-emitting sub-pixel group 12 can include two negative-polarity light-emitting sub-pixels 10, and the two negative-polarity light-emitting sub-pixels 10 are respectively connected with two scanning signal lines. Figure 11

[0109] The data signal line can extend longitudinally in the display panel and is electrically connected with the light-emitting sub-pixels 10 on the left and right sides. The polarities of the light-emitting sub-pixels 10 on the left and right sides of the data signal line are different.

[0110] In the embodiment, the data signal line is electrically connected with two columns of light-emitting sub-pixels 10, and in the same row of light-emitting sub-pixels, the two light-emitting sub-pixels 10 connected with the same data signal line are a positive-polarity light-emitting sub-pixel 10 and a negative-polarity light-emitting sub-pixel 10, respectively. Therefore, when the data signal line provides data signals for the two light-emitting sub-pixels 10 in turn, the data signal line needs to alternately output positive-polarity data signals and negative-polarity data signals.

[0111] Please refer to Figure 12 In some embodiments, the display panel can further include at least one multiplexing module 40.

[0112] The multiplexing module 40 can include one input end and at least two output ends. The input end of the multiplexing module 40 is connected with the signal fan-out line, and the output end of the multiplexing module 40 is connected with the data signal line.

[0113] ​Taking an example of the multiplexing module 40 including two output ends, the multiplexing module 40 can be connected with one signal fan-out line and two data signal lines respectively. The driving chip 30 can provide data signals for the signal fan-out line in different time intervals, and control the multiplexing module 40 to respectively connect the two output ends with the input end, so as to realize that one signal fan-out line provides data signals for two data signal lines. Through one signal fan-out line providing data signals for two data signal lines, data signal writing of four columns of light-emitting sub-pixels 10 can be realized. At this time, the number of signal fan-out lines needed to be arranged in the display panel is one fourth of the number of columns of light-emitting sub-pixels 10, and correspondingly, the number of fan-out terminals needed to be arranged in the driving chip 30 is consistent with the number of signal fan-out lines. By reducing the number of signal fan-out lines needed to be arranged, the number of fan-out terminals needed to be arranged in the driving chip 30 can also be reduced, so as to reduce the design cost and manufacturing cost of the driving chip 30.

[0114] The embodiment of the present application also provides a display device, please refer to Figure 13 The display device can be a PC, a television, a display, a mobile terminal, a tablet computer, a wearable device, etc. The display device can include the display panel provided by the embodiment of the present application.

[0115] The functional blocks shown in the above structure diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, etc. When implemented in software, the elements of the present application are program or code segments used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. The "machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segments can be downloaded via a computer network such as the Internet, an intranet, etc.

[0116] It should be noted that in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device.

[0117] The principles and implementation manners of the present application are described herein by using specific examples, and the above examples are only used to help understand the method of the present application and its core idea. The above is only the preferred implementation manner of the present application, and it should be pointed out that, due to the limitedness of the expression, there are objectively infinite specific structures, and for ordinary skilled persons in the technical field, some improvements, refinements or changes can be made without departing from the principles of the present application, and the above technical features can also be combined in an appropriate manner; the improvements, refinements, changes or combinations, or the direct application of the concepts and technical solutions of the present application to other occasions without improvement, shall be regarded as the protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a plurality of light-emitting sub-pixels arranged in an array, a plurality of light-emitting sub-pixels in the same row are connected to two scanning signal lines respectively, and adjacent two columns of light-emitting sub-pixels connected to different scanning signal lines are connected to the same data signal line; the display panel further comprises a data signal compensation circuit, the data signal compensation circuit comprises: a direct connection module connected between a signal fan-out line and a data signal line, the signal fan-out line and the data signal line being used to provide data signals for the light-emitting sub-pixels; a compensation module connected between the signal fan-out line and the data signal line, used to perform voltage compensation on the data signals provided by the signal fan-out line; a control end of the direct connection module is connected to a compensation drive signal line, and a control end of the compensation module is connected to the compensation drive signal line; the compensation drive signal line is used to provide a compensation drive signal; the compensation module comprises: a compensation voltage port used to provide a first compensation voltage; a first switch unit, a first end of the first switch unit being connected to the compensation voltage port; a second switch unit, a first end of the second switch unit being connected to the signal fan-out line, and a second end of the second switch unit being connected to the data signal line; a voltage compensation unit connected to a second end of the first switch unit and a third end of the second switch unit respectively; the voltage compensation unit is used to receive the first compensation voltage or perform voltage compensation on the data signals provided by the signal fan-out line for the data signal line.

2. The display panel of claim 1, wherein, the compensation drive signal comprises a first drive signal and a second drive signal output alternately; the first drive signal is used to drive the direct connection module to be turned on and drive the first switch unit to be turned on; the second drive signal is used to drive the direct connection module to be turned off and drive the second switch unit to be turned on.

3. The display panel of claim 1, wherein, the direct connection module comprises a first transistor connected between the signal fan-out line and the data signal line.

4. The display panel of claim 3, wherein, the voltage compensation unit comprises a first capacitor; the first switch unit comprises a second transistor and a third transistor, the second transistor being connected between a first end of the first capacitor and the compensation voltage port, and the third transistor being connected between a second end of the first capacitor and a ground terminal; the second switch unit comprises a fourth transistor and a fifth transistor, the fourth transistor being connected between the first end of the first capacitor and the data signal line, and the fifth transistor being connected between the second end of the first capacitor and the signal fan-out line.

5. The display panel of claim 4, wherein, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are transistors of the same type; the compensation drive signal line comprises a first drive signal line and a second drive signal line; the first drive signal line is connected to a control end of the first transistor, a control end of the second transistor, and a control end of the third transistor, and is used to provide the first drive signal; the second drive signal line is connected to a control end of the fourth transistor and a control end of the fifth transistor, and is used to provide the second drive signal; The first driving signal is an alternating high and low level signal, and the first driving signal and the second driving signal are complementary signals.

6. The display panel of claim 4, wherein, The first transistor, the second transistor, and the third transistor are one of an N-type transistor or a P-type transistor, and the fourth transistor and the fifth transistor are the other of an N-type transistor or a P-type transistor. The compensation driving signal line is connected to the control terminals of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor, and is configured to provide an alternating high and low level signal.

7. The display panel of claim 1, wherein, In the plurality of light emitting sub-pixels in the same row, the first light emitting sub-pixel and the second light emitting sub-pixel connected to the same data signal line are connected to the first scan signal line and the second scan signal line, respectively. In the same light emitting frame, a first effective voltage interval of the first scan signal line is before a second effective voltage interval of the second scan signal line, and the first effective voltage interval and the second effective voltage interval at least partially overlap. An equivalent capacitance formed between the first light emitting sub-pixel and the first scan signal line is C1, an equivalent capacitance formed between the first light emitting sub-pixel and the second scan signal line is C2, a feedthrough compensation voltage of the light emitting sub-pixel is Vcom, and the first compensation voltage is V1. Wherein, C1: (C1+C2)=Vcom:(Vcom+V1).

8. The display panel of claim 1, wherein, The first compensation voltage V1 is a voltage difference between a voltage value received by the light emitting sub-pixel under the influence of twice coupling and a voltage value received by the light emitting sub-pixel under the influence of once coupling.

9. The display panel of claim 8, wherein, The feedthrough compensation voltage of the light emitting sub-pixel is Vcom, and the first compensation voltage is V1; wherein, Vcom=V1.

10. The display panel of claim 1, wherein, The display panel comprises: a plurality of first light emitting sub-pixel groups and a plurality of second light emitting sub-pixel groups; the polarities of the first light emitting sub-pixel groups and the second light emitting sub-pixel groups are different; the polarities of the light emitting sub-pixels in each light emitting sub-pixel group are the same; in the plurality of light emitting sub-pixels in the same row, the first light emitting sub-pixel groups and the second light emitting sub-pixel groups are arranged alternately; in the plurality of light emitting sub-pixels in the same column, the polarities of adjacent light emitting sub-pixels are different.

11. The display panel of claim 10, wherein, The first light emitting sub-pixel group includes two light emitting sub-pixels with positive polarity, and the two light emitting sub-pixels with positive polarity are connected to two scan signal lines, respectively; the second light emitting sub-pixel group includes two light emitting sub-pixels with negative polarity, and the two light emitting sub-pixels with negative polarity are connected to two scan signal lines, respectively; The data signal line includes a first data signal line and a second data signal line, the first data signal line is connected to the first light emitting sub-pixel group of each row, and the second data signal line is connected to the second light emitting sub-pixel group of each row.

12. The display panel of claim 1, wherein, The display panel comprises: a plurality of multiplexing modules, each of the multiplexing modules including one input terminal and at least two output terminals; the input terminal of each multiplexing module is connected to a signal fan-out line, and the output terminals of each multiplexing module are connected to data signal lines.

13. A display device comprising: The display panel of any one of claims 1-12.

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