Display devices

Abstract

The present invention relates to a display device comprising: a transistor including a source electrode, a drain electrode, and a channel formation region, the channel formation region comprising an oxide semiconductor; a pixel electrode electrically connected to the source electrode or the drain electrode of the transistor; and a liquid crystal material adjacent to the pixel electrode, wherein the specific resistivity of the liquid crystal material measured at 20° C. is greater than or equal to 1×10 12 Ω·cm.

Description

[0001] This application is a divisional application filed again with respect to divisional application No. 201911225746.1. Divisional application No. 201911225746.1 is a divisional application of invention patent application No. 201080046963.5, filed on September 28, 2010, and entitled “LIQUID CRYSTAL DISPLAY DEVICE AND ELECTRONIC DEVICE HAVING THE SAME.” Technical Field

[0002] The present invention relates to a liquid crystal display device. The present invention relates to an electronic device having a liquid crystal display device. Background Art

[0003] Thin-film transistors (TFTs) formed on flat panels such as glass substrates, as commonly seen in liquid crystal display devices, have been manufactured using amorphous silicon, polycrystalline silicon, and the like. TFTs manufactured using amorphous silicon have low field-effect mobility but can be formed on larger glass substrates. On the other hand, TFTs manufactured using crystalline silicon have high field-effect mobility, but due to crystallization steps such as laser annealing, such transistors are not necessarily suitable for formation on larger glass substrates.

[0004] In view of the above, attention has been paid to a technology for manufacturing thin film transistors using oxide semiconductors, and such transistors are used in electronic devices or optical devices. For example, Patent Document 1 discloses a technology for manufacturing thin film transistors using zinc oxide or In-Ga-Zn-O-based oxide semiconductors as oxide semiconductor films, and such transistors are used as switching elements in liquid crystal display devices, for example.

[0005] [References]

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention

[0007] It is said that thin film transistors in which oxide semiconductors are used to form the channel region achieve higher field effect mobility than thin film transistors in which amorphous silicon is used to form the channel region. Pixels including such thin film transistors using oxide semiconductors are expected to be applied to display devices such as liquid crystal display devices.

[0008] Each pixel included in a liquid crystal display device is provided with a storage capacitor that holds a voltage used to control the orientation of the liquid crystal element. The off-state leakage current (hereinafter referred to as the off-state current) of the thin film transistor is a factor in determining the storage capacitance. When displaying still images, etc., reducing the off-state current (which increases the period during which the voltage is held in the storage capacitor) is important for reducing power consumption.

[0009] Furthermore, manufacturing display devices that can display moving images in addition to the low power consumption when displaying still images is important for increasing the added value of display devices. Therefore, it is important to determine whether an image is a still image or a moving image, and to further reduce power consumption by reducing power consumption when displaying still images by switching between still and moving images.

[0010] Note that in this specification, off-state current refers to the current flowing between the source and drain when a thin film transistor is in the off state (also called the non-conducting state). In the case of an n-channel thin film transistor (e.g., one having a threshold voltage of approximately 0 to 2 V), off-state current refers to the current flowing between the source and drain when a negative voltage is applied between the gate and source.

[0011] Furthermore, in liquid crystal display devices with higher added value (such as 3D displays or 4k2k displays), it is desirable to have a smaller area per pixel and to improve the aperture ratio. To improve the aperture ratio, it is important to reduce the area of ​​the storage capacitor. Therefore, it is necessary to reduce the off-state current of the thin film transistor.

[0012] In view of the foregoing, an object of one embodiment of the present invention is to provide a liquid crystal display device with reduced power consumption in which off-state current of a thin film transistor using an oxide semiconductor is reduced in a pixel.

[0013] One embodiment of the present invention is a liquid crystal display device, which includes: a display panel including a driving circuit part, and a pixel part in each pixel in which a transistor including a semiconductor layer using an oxide semiconductor is arranged; a signal generating circuit for generating a control signal for driving the driving circuit part, and an image signal supplied to the pixel part; a memory circuit for storing the image signal of each frame period; a comparison circuit for detecting the difference between image signals of a series of frame periods in the image signals of each frame period stored in the memory circuit; a selection circuit for selecting and outputting the image signals of the series of frame periods when the difference is detected in the comparison circuit; and a display control circuit for supplying the control signal and the image signal output from the selection circuit to the driving circuit part when the difference is detected in the comparison circuit, and stopping the supply of the control signal to the driving circuit part when the difference is not detected in the comparison circuit.

[0014] The control signal in the liquid crystal display device may be any one of a high power supply potential, a low power supply potential, a clock signal, a start pulse signal, and a reset signal.

[0015] The oxide semiconductor in the liquid crystal display device may have a carbon monoxide content less than or equal to 1×10 16 / cm 3of hydrogen concentration.

[0016] The oxide semiconductor in the liquid crystal display device may have a thickness of less than 1×10 14 / cm 3 carrier density.

[0017] According to the present invention, in a pixel including a thin film transistor using an oxide semiconductor, off-state current can be reduced. Consequently, the period during which the voltage is maintained in the storage capacitor can be extended, thereby enabling the provision of a liquid crystal display device in which power consumption when displaying a still image, etc., can be reduced. Furthermore, the aperture ratio can be improved, thereby enabling the provision of a liquid crystal display device including a high-resolution display portion.

[0018] Furthermore, a display device that displays not only still images but also moving images can be provided, thereby increasing the added value of the display device. By determining whether an image is a still image or a moving image and switching between the still and moving images for display, power consumption when displaying still images can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a diagram showing one example of a block diagram of a liquid crystal display device;

[0020] Figures 2A to 2C is a diagram showing one example of a driving circuit.

[0021] Figure 3 It is the timing diagram of the driving circuit.

[0022] Figures 4A to 4C is a diagram showing one example of a driving circuit.

[0023] Figure 5A and 5B A thin film transistor is shown.

[0024] Figures 6A to 6E A method for manufacturing a thin film transistor is shown.

[0025] Figure 7A and 7B A thin film transistor is shown.

[0026] Figures 8A to 8E A method for manufacturing a thin film transistor is shown.

[0027] Figure 9A and 9B Each shows a thin film transistor.

[0028] Figures 10A to 10E A method for manufacturing a thin film transistor is shown.

[0029] Figures 11A to 11E A method for manufacturing a thin film transistor is shown.

[0030] Figures 12A to 12D A method for manufacturing a thin film transistor is shown.

[0031] Figures 13A to 13D A method for manufacturing a thin film transistor is shown.

[0032] Figure 14 A thin film transistor is shown.

[0033] Figures 15A to 15C A liquid crystal panel is shown.

[0034] Figures 16A to 16C Each shows an electronic device.

[0035] Figures 17A to 17C Each shows an electronic device.

[0036] Figure 18A and 18B A display panel and thin film transistors are shown.

[0037] Figure 19 It is a diagram for describing Example 13.

[0038] Figure 20A and 20B It is a diagram for describing Example 13.

[0039] Figure 21A and 21B It is a diagram for describing Example 13.

[0040] Figure 22 It is a diagram for describing Example 13.

[0041] Figure 23 is a graph for describing Example 14.

[0042] Figure 24A and 24B These are photos used to describe Example 14.

[0043] Figure 25A and 25B is a graph for describing Example 14.

[0044] Figures 26A to 26D It is a diagram for describing Embodiment 1.

[0045] Figure 27 This is a photo used to describe Example 1.

[0046] Figure 28 is a graph for describing Example 1.

[0047] Figure 29 This is a photo used to describe Example 2.

[0048] Figure 30 is a graph for describing Example 2.

[0049] Figure 31 This is a photo used to describe Example 3.

[0050] Figure 32 is a graph for describing Example 3.

[0051] Figure 33 This is a photo used to describe Example 4.

[0052] Figure 34 is a diagram for describing Example 5. DETAILED DESCRIPTION

[0053] Hereinafter, embodiments and examples of the present invention will be described with reference to the accompanying drawings. However, it will be readily understood by those skilled in the art that the modes and details disclosed herein may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments and examples. Note that in the structure of the present invention described below, identical parts are indicated by identical reference numerals in all drawings.

[0054] Note that the dimensions, thickness of layers, or regions of each structure shown in the drawings and the like in the embodiments are exaggerated for simplicity in some cases, and therefore, the embodiments of the present invention are not limited to such scaling.

[0055] In this specification, ordinal numbers such as “first,” “second,” and “third” are used to avoid confusion between components, and these terms do not limit the components in numerical value.

[0056] (Example 1)

[0057] In this embodiment, a block diagram of a display device and a stop sequence and a start sequence of operations in a drive circuit are described. First, use Figure 1 To describe the block diagram of the display device.

[0058] The liquid crystal display device 1000 described in Embodiment 1 includes a display panel 1001 , a signal generating circuit 1002 , a memory circuit 1003 , a comparison circuit 1004 , a selection circuit 1005 , and a display control circuit 1006 .

[0059] The display panel 1001 includes, for example, a driver circuit portion 1007 and a pixel portion 1008. The display panel 1001 includes a gate line driver circuit 1009A and a signal line driver circuit 1009B, which are driver circuits for driving the pixel portion 1008 including a plurality of pixels. The gate line driver circuit 1009A, the signal line driver circuit 1009B, and the pixel portion 1008 can be formed using transistors formed on a single substrate.

[0060] The gate line driver circuit 1009A, the signal line driver circuit 1009B, and the pixel portion 1008 can be formed using n-channel transistors, each of which has a semiconductor layer formed using an oxide semiconductor. The gate line driver circuit 1009A and / or the signal line driver circuit 1009B can be formed on the same substrate as the pixel portion or on a different substrate.

[0061] The pixel portion 1008 can employ a progressive scanning method, an interlaced scanning method, or other display methods. The color components controlled in a pixel during color display are not limited to the three colors R, G, and B (R, G, and B correspond to red, green, and blue, respectively); for example, R, G, B, and W (W corresponds to white), or R, G, B and one or more of yellow, cyan, and magenta, can be used. Furthermore, the size of the display area can vary depending on the corresponding point of the color component. The present invention is not limited to application to display devices for color display but can also be applied to display devices for monochrome display.

[0062] Next, an oxide semiconductor layer used as a semiconductor layer of a transistor included in any of the gate line driver circuit 1009A, the signal line driver circuit 1009B, and the pixel portion 1008 is described.

[0063] As for the oxide semiconductor used in this embodiment, the oxide semiconductor contains less than or equal to 1×10 16 / cm 3 The oxide semiconductor film has a thickness of less than 1×10 14 / cm 3 The carrier density is preferably less than or equal to 1×10 12 / cm 3 , and is used to form the channel region of a thin film transistor. In this specification, a 12 / cm 3 Oxide semiconductors with a carrier density greater than or equal to 1×10 12 / cm 3 But less than or equal to 1×10 14 / cm 3An oxide semiconductor having a carrier density of 100 Å to 100 Å is referred to as a substantially intrinsic oxide semiconductor. In this specification, the hydrogen concentration in an oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS).

[0064] When the band gap of the oxide semiconductor is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, and more preferably greater than or equal to 3 eV, the number of carriers caused by thermal excitation is negligible. Therefore, impurities (such as hydrogen that can serve as a donor) are reduced as much as possible to make the carrier density less than 1×10 14 / cm 3 , preferably less than or equal to 1×10 12 / cm 3 That is, the carrier density of the oxide semiconductor layer is reduced as much as possible to be extremely close to zero.

[0065] This oxide semiconductor, which is highly purified by removing as much hydrogen as possible from the oxide semiconductor, is used for the channel formation region of the thin film transistor, whereby even when the channel width is 10 mm, the leakage current is less than or equal to 1×10-10 V when the drain voltage is in the range of 1 V to 10 V and the gate voltage is in the range of -5 V to -20 V. -13 A.

[0066] In the case of manufacturing a display device using such a thin film transistor whose off-state current is extremely small, leakage current is reduced, so that a period for holding display data can be extended.

[0067] Specifically, in a transistor including the above-described oxide semiconductor layer having a channel width of 10 μm, the off-state current per micrometer of the channel width may be less than or equal to 10 aA / μm (1 10 17 A / μm), and further may be less than or equal to 1aA / μm (1 10 18 A / μm). Such a transistor whose off-state current is extremely small is used as a transistor included in any of the gate line driver circuit 1009A, the signal line driver circuit 1009B, and the pixel portion 1008, thereby increasing the retention time of an electrical signal such as a video signal. Since the retention time can be increased, for example, the retention time after writing the video signal is set to be greater than or equal to 10 seconds, preferably greater than or equal to 30 seconds, and more preferably greater than or equal to 1 minute and less than 10 minutes. By increasing the retention time, the interval between write timings can be increased, thereby further suppressing power consumption.

[0068] The resistance to the flow of off-state current in a transistor may be referred to as off-state resistivity. The off-state resistivity is the resistivity of the channel formation region when the transistor is off, and can be calculated based on the off-state current.

[0069] Specifically, the resistance of the transistor when it is turned off (off-state resistance R) can be calculated based on the off-state current and drain voltage using Ohm's law, which results in the off-state resistivity ρ, which is calculated based on the cross-sectional area A of the channel formation region and the length L of the channel formation region (which corresponds to the distance between the source electrode and the drain electrode) using the formula ρ = RA / L (R is the off-state resistance).

[0070] The cross-sectional area A can be calculated according to A=dW (where the thickness of the channel formation region is d and the channel width is W). The length L of the channel formation region is the channel length L. In this way, the off-state resistivity can be calculated from the off-state current.

[0071] The off-state resistivity of the transistor including the oxide semiconductor layer in this embodiment is preferably greater than or equal to 1×10 9 Ω·m, more preferably greater than or equal to 1×10 10 Ω·m.

[0072] On the other hand, for example, in the case of a transistor using low-temperature polysilicon, assuming that the off-state current is approximately 1×10 -12 Therefore, in a transistor including an oxide semiconductor, when the holding capacitance is equal to each other (about 0.1 pF), the voltage holding period can be extended to about 10 times the holding period of a transistor using low-temperature polysilicon. 5 In addition, in the case of amorphous silicon transistors, the off-state current per micron of channel width is greater than or equal to 1×10 -13 Therefore, in a transistor including a high-purity oxide semiconductor, when the holding capacitances are equal to each other (about 0.1 pF), the voltage holding period can be extended to 10 times that of a transistor using amorphous silicon. 4 times or longer periods.

[0073] For example, in the case of a pixel using a transistor using low-temperature polysilicon, image display is generally performed at 60 frames per second (16 microseconds per frame). The same rate can be applied to the case of still image display because if the rate is reduced (the interval between write timings increases), the voltage of the pixel decreases, which adversely affects the image display. On the other hand, in the case of using the above-mentioned transistor including an oxide semiconductor layer, since the off-state current is small, the holding period per signal writing can be extended to 1600 seconds, which is about 10 times the holding period of the transistor using low-temperature polysilicon. 5 times longer.

[0074] In this way, still image display can be performed on the display portion even by writing the image signal less frequently. Since the holding period can be extended, the frequency of signal writing can be reduced, especially when a still image is displayed. For example, the number of times the signal is written in a display period of one still image can be 1 or n (n is greater than or equal to 2 and less than or equal to 10). 3 ). This enables low power consumption of the display device.

[0075] Generally speaking, each pixel is provided with a storage capacitor formed by a pair of electrodes and an insulating layer provided as a dielectric between the pair of electrodes. The size of the storage capacitor can be set in consideration of the off-state current of the transistor provided in each pixel, etc. In this embodiment, since a transistor including a high-purity oxide semiconductor layer is used as the transistor provided in each pixel, it is sufficient to provide a storage capacitor having a capacitance less than or equal to 1 / 3, preferably less than or equal to 1 / 5, of the liquid crystal capacitance of each pixel.

[0076] Since the retention period can be long in the above-described transistor including a high-purity oxide semiconductor layer, the frequency of signal writing can be greatly reduced, especially when displaying a still image. Therefore, the number of times a signal is written to a pixel when displaying, for example, a still image (which involves less frequent display switching) can be reduced, thereby achieving low power consumption.

[0077] When displaying a still image, a refresh operation may be appropriately performed, taking into account the retention rate of the voltage applied to the liquid crystal element during the retention period. For example, a refresh operation may be performed when the voltage on the storage capacitor reaches a predetermined level relative to the voltage value (initial value) immediately after a signal is written to the pixel electrode of the liquid crystal element. The predetermined level of this voltage is preferably set relative to the initial value so that flicker is not detected. Specifically, a refresh operation (rewriting) is preferably performed each time this voltage reaches a voltage that is 10% (preferably 3%) lower than the initial value.

[0078] During the hold period when displaying a still image, the counter electrode (also referred to as the common electrode) may enter a floating state. Specifically, a switch may be provided between a power supply that supplies a common potential to the counter electrode and the counter electrode. During the write period, the switch is turned on to supply the common potential from the power supply to the counter electrode, and then during the hold period, the switch is turned off to place the counter electrode in a floating state. A transistor including the high-purity oxide semiconductor layer described above is preferably used as the switch.

[0079] The signal generation circuit 1002 is a circuit for generating signals for driving the gate line driver circuit 1009A and signals for driving the signal line driver circuit 1009B. The signal generation circuit 1002 is also a circuit for outputting signals for driving the driver circuit portion 1007 via wiring, and is a circuit for outputting image signals (also referred to as video voltage, video signal, or video data) to the memory circuit 1003 via wiring. In other words, the signal generation circuit 1002 is a circuit for generating and outputting control signals for controlling the driver circuit portion 1007 and image signals for supply to the pixel portion 1008.

[0080] Specifically, the signal generation circuit 1002 supplies a high power supply potential VDD and a low power supply potential VSS as control signals to the gate line driver circuit 1009A and the signal line driver circuit 1009B. It also supplies a start pulse SP and a clock pulse CK for the gate line driver circuit 1009A, and a start pulse SP and a clock pulse CK for the signal line driver circuit 1009B. Furthermore, the signal generation circuit 1002 supplies an image signal (Data) for displaying a moving image or a still image to the memory circuit 1003.

[0081] A moving image is an image that is recognized as a moving image by the human eye by rapidly switching between multiple images divided into multiple frames according to time. Specifically, a moving image is a series of image signals that are recognized as moving images with less flicker by the human eye by switching images at least 60 times (60 frames) per second. Unlike a moving image, a still image is an image signal that does not change over a series of frame periods (for example, between the nth frame and the (n+1)th frame) despite rapidly switching between multiple images divided into multiple frame periods according to time.

[0082] The signal generation circuit 1002 may also generate another signal, such as an image signal or a latch signal. The signal generation circuit 1002 may output a reset signal Res to the gate line driver circuit 1009A and / or the signal line driver circuit 1009B for stopping outputting a pulse signal to each driver circuit. Each signal may include multiple signals, such as a first clock signal and a second clock signal.

[0083] The high power supply potential VDD refers to a potential higher than the reference potential, while the low power supply potential VSS refers to a potential lower than or equal to the reference potential. It is preferred that the high power supply potential and the low power supply potential are potentials high enough to operate the transistor.

[0084] In many cases, voltage refers to the potential difference between a given potential and a reference potential (e.g., ground potential). Therefore, voltage, potential, and potential difference may also be referred to as potential, voltage, and voltage difference, respectively.

[0085] When the image signal output from the signal generating circuit 1002 to the memory circuit 1003 is an analog signal, the analog signal may be converted into a digital signal by an A / D converter or the like to be output to the memory circuit 1003 .

[0086] The memory circuit 1003 includes a plurality of frame memories 1010 for storing image signals of a plurality of frames. The frame memories may be formed using memory elements such as dynamic random access memory (DRAM) or static random access memory (SRAM).

[0087] The number of frame memories 1010 is not particularly limited as long as the image signal for each frame period can be stored. The image signal of the frame memory 1010 is selectively read out by the comparison circuit 1004 and the selection circuit 1005.

[0088] Comparison circuit 1004 selectively reads image signals stored in memory circuit 1003 over a series of frame periods, compares the image signals, and detects differences therebetween. If a difference is detected by comparing the image signals in comparison circuit 1004, the image over the series of frame periods is determined to be a moving image, while if no difference is detected by comparing the image signals in comparison circuit 1004, the image is determined to be a still image. Specifically, detection of the difference in comparison circuit 1004 determines whether the image signals over the series of frame periods are for displaying a moving image or for displaying a still image. The difference obtained through comparison can be determined as a detected difference when it exceeds a predetermined level.

[0089] The selection circuit 1005 includes a plurality of switches such as thin film transistors, and is a circuit that selects an image signal from the frame memory 1010 storing the image signal when the image signal for displaying a moving image is determined by difference detection in the comparison circuit 1004, and outputs it to the display control circuit 1006. When a difference in the image signal between a series of frames compared in the comparison circuit 1004 is not detected, the image displayed in the series of frames is a still image, and in this case, the selection circuit 1005 may not output a signal from the image signal of the subsequent frame to the display control circuit 1006.

[0090] The display control circuit 1006 is a circuit that switches between supplying image signals and control signals (such as the high power supply potential VDD, the low power supply potential VSS, the start pulse SP, the clock signal CK, and the reset signal Res) to the driver circuit section 1007 and stopping the supply of these signals to the driver circuit section 1007. Specifically, when the image is determined by the comparison circuit 1004 to be a moving image (i.e., a difference in image signals across a series of frames is detected), the image signal is supplied from the selection circuit 1005 to the driver circuit section 1007 via the display control circuit 1006, and the control signal is also supplied to the driver circuit section 1007 via the display control circuit 1006. On the other hand, when the image is determined by the comparison circuit 1004 to be a still image (i.e., a difference in image signals across a series of frames is not detected), the image signal for the subsequent frame is not supplied from the selection circuit 1005, and thus the image signal is not supplied to the driver circuit section 1007 via the display control circuit 1006. The display control circuit 1006 also stops supplying the control signal to the driver circuit section 1007.

[0091] Note that if a still image is determined, and if the image is assumed to be still for a short period, it is not necessary to stop supplying the high power supply potential VDD and the low power supply potential VSS in the control signal. This is because the increase in power consumption caused by frequently stopping and starting the supply of the high power supply potential VDD and the low power supply potential VSS can be reduced, which is preferable.

[0092] It is preferred that the supply of the image signal and the control signal is stopped completely during the period for holding the image signal in each pixel in the pixel portion 1008, and the image signal and the control signal previously supplied by the display control circuit 1006 are supplied again so that the image signal is supplied again after the holding period of each pixel.

[0093] Supplying any signal means supplying a predetermined potential to a wiring. Stopping the supply of any signal means stopping the supply of the predetermined potential to the wiring, as well as stopping the connection to the wiring to which a predetermined fixed potential is supplied, for example, the wiring to which the low power supply potential VSS is supplied. Stopping the supply of any signal also means severing the electrical connection to the wiring to which the predetermined potential is supplied, thereby entering a floating state.

[0094] As described above, in the thin film transistor including the oxide semiconductor layer, the off-state current is reduced to less than or equal to 1×10 -12 Therefore, in this embodiment, it is expected that an enhanced effect will be produced in reducing the power consumption when displaying a still image.

[0095] In this way, image signals are compared to determine whether their images are moving images or still images, and supply of control signals such as clock signals or start pulses is selectively performed or stopped, whereby power consumption can be reduced.

[0096] Next, use Figures 2A to 2C An example of the structure of a shift register included in each of the gate line driver circuit 1009A and the signal line driver circuit 1009B of the driver circuit portion 1007 will be described.

[0097] Figure 2A The shift register shown includes first to N-th pulse output circuits 10_1 to 10_N (N is a natural number greater than or equal to 3). A first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14 are supplied to the first to N-th pulse output circuits 10_1 to 10_N. Figure 2A The first to N-th pulse output circuits 10_1 to 10_N of the shift register shown. The start pulse SP1 (first start pulse) from the fifth wiring 15 is input to the first pulse output circuit 10_1. The signal from the pulse output circuit in the previous stage (referred to as the previous stage signal OUT(n-1) (n is a natural number greater than or equal to 2 and less than or equal to N)) is input to the N-th pulse output circuit 10_N in the second or later stage. The signal from the third pulse output circuit 10_3 in the stage two stages after the first pulse output circuit 10_1 is input to the first pulse output circuit 10_1; similarly, the signal from the (N+2)-th pulse output circuit 10_(n+2) in the stage two stages after the N-th pulse output circuit 10_N (referred to as the subsequent stage signal OUT(n+2)) is input to the n-th pulse output circuit. In this way, each pulse output circuit outputs a first output signal (corresponding to one of OUT(1)(SR) to OUT(N)(SR)) to be input to the pulse output circuit of the next stage and / or the stage two stages before, and a second output signal (corresponding to one of OUT(1) to OUT(N)) to be input to another circuit or the like. Note that, as Figure 2A As shown, the subsequent stage signal OUT(n+2) is not input to the last two stages of the shift register; therefore, as an example, the second start pulse SP2 may be input to one of the last two stages of the shift register, and the third start pulse SP3 may be input to the other of the last two stages. Alternatively, the signal to be input may be generated internally. For example, the (N+1)th pulse output circuit 10 may be provided which does not contribute to the pulse output to the display portion. (N+1) and the (N+2)th pulse output circuit 10 (N+2) (These circuits are also referred to as dummy stages), and signals corresponding to the second start pulse (SP2) and the third start pulse (SP3) can be generated in the dummy stages.

[0098] Note that each of the first to fourth clock signals (CK1) to (CK4) is a signal that oscillates between an H-level signal and an L-level signal at a constant cycle. The first to fourth clock signals (CK1) to (CK4) are sequentially delayed by a quarter cycle. In this embodiment, the first to fourth clock signals (CK1) to (CK4) are used to control the drive pulse output circuit and the like. Note that the clock signal is also referred to as GCK or SCK, depending on the drive circuit to which the clock signal is input; however, in this embodiment, description is made using CK as the clock signal.

[0099] Note that when it is explicitly stated that "A and B are connected," this includes cases where A and B are electrically connected, cases where A and B are functionally connected, and cases where A and B are directly connected. Here, A and B each correspond to an object (e.g., a device, element, circuit, wiring, electrode, terminal, conductive film, or layer). Therefore, other connection relationships are included without being limited to the predetermined connection relationship, such as the connection relationship shown in the drawings and text.

[0100] The first to N-th pulse output circuits 10_1 to 10_N each include a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see Figure 2B ).

[0101] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first to fourth wirings 11 to 14. For example, in Figure 2A and 2B In the embodiment, the first input terminal 21 of the first pulse output circuit 10_1 is electrically connected to the first wiring 11, the second input terminal 22 of the first pulse output circuit 10_1 is electrically connected to the second wiring 12, and the third input terminal 23 of the first pulse output circuit 10_1 is electrically connected to the third wiring 13. In addition, the first input terminal 21 of the second pulse output circuit 10_2 is electrically connected to the second wiring 12, the second input terminal 22 of the second pulse output circuit 10_2 is electrically connected to the third wiring 13, and the third input terminal 23 of the second pulse output circuit 10_2 is electrically connected to the fourth wiring 14.

[0102] exist Figure 2A and 2B In the first pulse output circuit 10_1, the first start pulse SP1 is input to the fourth input terminal 24, the subsequent stage signal OUT(3) is input to the fifth input terminal 25, the first output signal OUT(1) (SR) is output from the first output terminal 26, and the second output signal OUT(1) is output from the second output terminal 27.

[0103] Next, refer to Figure 2C An example of a specific circuit structure of a pulse output circuit is described.

[0104] exist Figure 2C , a first terminal of the first transistor 31 is electrically connected to the power supply line 51, a second terminal of the first transistor 31 is electrically connected to the first terminal of the ninth transistor 39, and a gate electrode of the first transistor 31 is electrically connected to the fourth input terminal 24. A first terminal of the second transistor 32 is electrically connected to the power supply line 52, a second terminal of the second transistor 32 is electrically connected to the first terminal of the ninth transistor 39, and a gate electrode of the second transistor 32 is electrically connected to the gate electrode of the fourth transistor 34. A first terminal of the third transistor 33 is electrically connected to the first input terminal 21, and a second terminal of the third transistor 33 is electrically connected to the first output terminal 26. A first terminal of the fourth transistor 34 is electrically connected to the power supply line 52, and a second terminal of the fourth transistor 34 is electrically connected to the first output terminal 26. A first terminal of the fifth transistor 35 is electrically connected to the power supply line 52, a second terminal of the fifth transistor 35 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and a gate electrode of the fifth transistor 35 is electrically connected to the fourth input terminal 24. A first terminal of the sixth transistor 36 is electrically connected to the power supply line 51, a second terminal of the sixth transistor 36 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode of the sixth transistor 36 is electrically connected to the fifth input terminal 25. A first terminal of the seventh transistor 37 is electrically connected to the power supply line 51, a second terminal of the seventh transistor 37 is electrically connected to the second terminal of the eighth transistor 38, and the gate electrode of the seventh transistor 37 is electrically connected to the third input terminal 23. A first terminal of the eighth transistor 38 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode of the eighth transistor 38 is electrically connected to the second input terminal 22. A first terminal of the ninth transistor 39 is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, a second terminal of the ninth transistor 39 is electrically connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40, and the gate electrode of the ninth transistor 39 is electrically connected to the power supply line 51. A first terminal of the tenth transistor 40 is electrically connected to the first input terminal 21, a second terminal of the tenth transistor 40 is electrically connected to the second output terminal 27, and a gate electrode of the tenth transistor 40 is electrically connected to the second terminal of the ninth transistor 39. A first terminal of the eleventh transistor 41 is electrically connected to the power supply line 52, a second terminal of the eleventh transistor 41 is electrically connected to the second output terminal 27, and a gate electrode of the eleventh transistor 41 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34.

[0105] exist Figure 2C, a connection point between the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is referred to as a node NA. Also, a connection point between the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 is referred to as a node NB.

[0106] exist Figure 2C In the case where the pulse output circuit is the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, the third clock signal CK3 is input to the third input terminal 23, the start pulse SP is input to the fourth input terminal 24, the subsequent stage signal OUT(3) is input to the fifth input terminal 25, the first output signal OUT(1) (SR) is output from the first output terminal 26, and the second output signal OUT(1) is output from the second output terminal 27.

[0107] Figure 3 Shown including Figure 2C The timing diagram of the shift register of the multiple pulse output circuits shown in FIG. In the case where the shift register is a scan line driver circuit, Figure 3 The period 61 in FIG. 1 is the vertical retrace period, and the period 62 is the gate selection period.

[0108] Hereinafter, a driving circuit (described as a driving circuit) including a plurality of n-channel transistors in the case of displaying a still image and a moving image is described. Figures 2A to 2C as well as Figure 3 The order of supplying or stopping the supply of potential to the wiring in the example in ).

[0109] First, the display control circuit 1006 stops supplying the start pulse SP while stopping the operation of the driver circuit portion 1007. Next, after stopping the supply of the start pulse SP, the supply of each clock signal CK is stopped after the pulse output reaches the last stage of the shift register. Then, the supply of the high power supply potential VDD and the low power supply potential VSS of the power supply voltage (see Figure 26A ). In the case of starting the operation of the driver circuit portion 1007, first, the display control circuit 1006 supplies the high power supply potential VDD and the low power supply potential VSS of the power supply voltage to the driver circuit portion 1007. Then, each clock signal CK is supplied, and then the supply of the start pulse SP is started (see Figure 26B ).

[0110] exist Figures 2A to 2C as well as Figure 3 In the description of , the reset signal Res is not supplied to the driving circuit. Figures 4A to 4CA structure to which the reset signal Res is supplied is shown and described in FIG.

[0111] Figure 4A The shift register shown includes first to N-th pulse output circuits 10_1 to 10_N (N is a natural number greater than or equal to 3). A first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14 are supplied to the first to N-th pulse output circuits 10_1 to 10_N. Figure 4A The first to N-th pulse output circuits 10_1 to 10_N of the shift register shown. The start pulse SP1 (first start pulse) from the fifth wiring 15 is input to the first pulse output circuit 10_1. The signal from the pulse output circuit in the previous stage (referred to as the previous stage signal OUT(n-1) (n is a natural number greater than or equal to 2 and less than or equal to N)) is input to the N-th pulse output circuit 10_N in the second or later stage. The signal from the third pulse output circuit 10_3 in the stage two stages after the first pulse output circuit 10_1 is input to the first pulse output circuit 10_1; similarly, the signal from the (N+2)-th pulse output circuit 10_(N+2) in the stage two stages after the N-th pulse output circuit 10_N (referred to as the subsequent stage signal OUT(n+2)) is input to the n-th pulse output circuit. In this manner, each pulse output circuit outputs a first output signal (corresponding to one of OUT(1)(SR) to OUT(N)(SR)) to be input to the pulse output circuit of the next stage and / or the stage two stages before, and a second output signal (corresponding to one of OUT(1) to OUT(N)) to be input to another circuit, etc. A reset signal Res is supplied from the sixth wiring 16 to the pulse output circuit in each stage.

[0112] Figures 4A to 4C The pulse output circuit shown is Figures 2A to 2C The pulse output circuit shown is different in that a sixth wiring 16 for supplying a reset signal Res is provided; other parts such as Figures 2A to 2C As described in.

[0113] The first to N-th pulse output circuits 10_1 to 10_N each include a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, a second output terminal 27, and a sixth input terminal 28 (see Figure 4B ).

[0114] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first to fourth wirings 11 to 14. For example, in Figure 4Aand 4B In the embodiment, the first input terminal 21 of the first pulse output circuit 10_1 is electrically connected to the first wiring 11, the second input terminal 22 of the first pulse output circuit 10_1 is electrically connected to the second wiring 12, and the third input terminal 23 of the first pulse output circuit 10_1 is electrically connected to the third wiring 13. In addition, the first input terminal 21 of the second pulse output circuit 10_2 is electrically connected to the second wiring 12, the second input terminal 22 of the second pulse output circuit 10_2 is electrically connected to the third wiring 13, and the third input terminal 23 of the second pulse output circuit 10_2 is electrically connected to the fourth wiring 14.

[0115] exist Figure 4A and 4B In the first pulse output circuit 10_1, the first start pulse SP1 is input to the fourth input terminal 24, the subsequent stage signal OUT(3) is input to the fifth input terminal 25, the first output signal OUT(1) (SR) is output from the first output terminal 26, the second output signal OUT(1) is output from the second output terminal 27, and the reset signal Res is input from the sixth input terminal 28.

[0116] Next, refer to Figure 4C An example of a specific circuit structure of a pulse output circuit is described.

[0117] exist Figure 4C, a first terminal of the first transistor 31 is electrically connected to the power supply line 51, a second terminal of the first transistor 31 is electrically connected to the first terminal of the ninth transistor 39, and a gate electrode of the first transistor 31 is electrically connected to the fourth input terminal 24. A first terminal of the second transistor 32 is electrically connected to the power supply line 52, a second terminal of the second transistor 32 is electrically connected to the first terminal of the ninth transistor 39, and a gate electrode of the second transistor 32 is electrically connected to the gate electrode of the fourth transistor 34. A first terminal of the third transistor 33 is electrically connected to the first input terminal 21, and a second terminal of the third transistor 33 is electrically connected to the first output terminal 26. A first terminal of the fourth transistor 34 is electrically connected to the power supply line 52, and a second terminal of the fourth transistor 34 is electrically connected to the first output terminal 26. A first terminal of the fifth transistor 35 is electrically connected to the power supply line 52, a second terminal of the fifth transistor 35 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and a gate electrode of the fifth transistor 35 is electrically connected to the fourth input terminal 24. A first terminal of the sixth transistor 36 is electrically connected to the power supply line 51, a second terminal of the sixth transistor 36 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode of the sixth transistor 36 is electrically connected to the fifth input terminal 25. A first terminal of the seventh transistor 37 is electrically connected to the power supply line 51, a second terminal of the seventh transistor 37 is electrically connected to the second terminal of the eighth transistor 38, and the gate electrode of the seventh transistor 37 is electrically connected to the third input terminal 23. A first terminal of the eighth transistor 38 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode of the eighth transistor 38 is electrically connected to the second input terminal 22. A first terminal of the ninth transistor 39 is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, a second terminal of the ninth transistor 39 is electrically connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40, and the gate electrode of the ninth transistor 39 is electrically connected to the power supply line 51. A first terminal of the tenth transistor 40 is electrically connected to the first input terminal 21, a second terminal of the tenth transistor 40 is electrically connected to the second output terminal 27, and a gate electrode of the tenth transistor 40 is electrically connected to the second terminal of the ninth transistor 39. A first terminal of the eleventh transistor 41 is electrically connected to the power supply line 52, a second terminal of the eleventh transistor 41 is electrically connected to the second output terminal 27, and a gate electrode of the eleventh transistor 41 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 are electrically connected to a wiring 53 for supplying a reset signal Res.The reset signal Res is a signal for supplying a signal having a high power supply potential level to the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 to reduce the output from the pulse output circuit to a signal having a low power supply potential level.

[0118] exist Figure 4C , a connection point between the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is referred to as a node NA. Also, a connection point between the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 is referred to as a node NB.

[0119] exist Figure 4C In the case where the pulse output circuit is the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, the third clock signal CK3 is input to the third input terminal 23, the start pulse SP is input to the fourth input terminal 24, the subsequent stage signal OUT(3) is input to the fifth input terminal 25, the first output signal OUT(1) (SR) is output from the first output terminal 26, the second output signal OUT(1) is output from the second output terminal 27, and the reset signal Res is input from the sixth input terminal 28.

[0120] include Figure 4C The timing diagram of the shift register of the multiple pulse output circuit shown is Figure 3 shown Figure 2C Similar.

[0121] Hereinafter, a driving circuit (described as a driving circuit) including a plurality of n-channel transistors in the case of displaying a still image or a moving image is described. Figures 4A to 4C The order of supplying or stopping the supply of potential to the wiring in the example in ).

[0122] First, while stopping the operation of the driver circuit portion 1007, the display control circuit 1006 stops supplying the start pulse SP. Next, after stopping the supply of the start pulse SP, the supply of each clock signal CK is stopped after the pulse output reaches the last stage of the shift register. Then, the reset signal Res is supplied. Next, the supply of the high power supply potential VDD and the low power supply potential VSS of the power supply voltage (see Figure 26C). In the case of starting the operation of the driver circuit portion 1007, first, the display control circuit 1006 supplies the high power supply potential VDD and the low power supply potential VSS of the power supply voltage to the driver circuit portion 1007. Then, the reset signal Res is supplied. Next, each clock signal CK is supplied, and then the supply of the start pulse SP is started (see Figure 26D ).

[0123] Apart from Figures 2A to 2C as well as Figure 3 In addition to the structure shown, the reset signal is supplied as Figures 4A to 4C The illustrated structure is preferable because malfunctions due to signal delays and the like when switching between still images and moving images can be reduced.

[0124] When displaying a still image, the common potential electrode provided on the thin-film transistor included in the driver circuit section can be disconnected from the common potential line, causing it to enter a floating state. Then, after the still image mode, when the driver circuit resumes operation, the common potential electrode is connected to the common potential line. This prevents malfunctions of the thin-film transistor in the driver circuit section.

[0125] Figure 18A A display panel 1800 having such a structure is shown. Figure 18B 18 is a diagram illustrating a cross-sectional structure thereof. Display panel 1800 includes driver circuits 1802 and 1804, and a pixel portion 1806. Common potential electrode 1808 is provided so as to overlap driver circuit 1802. A switch 1810 for controlling connection / disconnection between common potential electrode 1808 and a common potential terminal 1812 is provided between them.

[0126] In such Figure 18B A common potential electrode 1808 is provided on the TFT 1803 of the driver circuit shown, thereby shielding the TFT 1803 from static electricity, thereby preventing a change in threshold voltage or generation of a parasitic channel.

[0127] The switch 1810 may have the same structure as the TFT 1803. This element, in which leakage current in the off state is extremely small, contributes to stable operation of the display panel. Specifically, when displaying a still image, the potential can be kept constant even when the switch 1803 is turned off to float the common potential electrode.

[0128] In this way, by using TFTs formed using wide-bandgap oxide semiconductors and providing a common potential electrode to shield against external electric fields, a still image can be displayed even when the drive circuit is stopped. Furthermore, by appropriately controlling the potential of the common potential electrode in accordance with the operation of the drive circuit, the operation of the display panel can be stabilized.

[0129] As described above, by utilizing the low off-state current characteristics of thin-film transistors using oxide semiconductors, the period during which the voltage is maintained in the storage capacitor can be extended in liquid crystal display devices, and power consumption when displaying still images, etc., can be reduced. Furthermore, power consumption can be further reduced by stopping the supply of control signals when displaying still images. Furthermore, switching between still and moving images can be performed without causing any malfunctions.

[0130] Embodiment 1 can be implemented by appropriately combining with any of the structures described in other embodiments.

[0131] (Example 2)

[0132] use Figure 5A and 5B ,as well as Figures 6A to 6E An embodiment of a thin film transistor of this embodiment and a method for manufacturing the thin film transistor will be described.

[0133] In Embodiment 2, an example of a thin film transistor applicable to the liquid crystal display device described in this specification will be described. The thin film transistor 410 described in Embodiment 2 can be used as a thin film transistor in each pixel of the pixel portion 1008 described in Embodiment 1.

[0134] Figure 5A An example of a planar structure of a thin film transistor is shown, and Figure 5B An example of its cross-sectional structure is shown. Figure 5A and 5B The illustrated thin film transistor 410 is a top-gate thin film transistor.

[0135] Figure 5A is a plan view of a top-gate thin film transistor 410, and Figure 5B It is along Figure 5A Cross-sectional view along line C1-C2 in FIG.

[0136] The thin film transistor 410 includes, over a substrate 400 having an insulating surface, an insulating layer 407, an oxide semiconductor layer 412, source and drain electrode layers 415 a and 415 b, a gate insulating layer 402, and a gate electrode layer 411. Wiring layers 414 a and 414 b are provided in contact with the source and drain electrode layers 415 a and 415 b to be electrically connected to the source and drain electrode layers 415 a and 415 b, respectively.

[0137] The thin film transistor 410 is described as a single-gate thin film transistor; a multi-gate thin film transistor including a plurality of channel formation regions can be formed when necessary.

[0138] Reference below Figures 6A to 6CA process for fabricating a thin film transistor 410 on a substrate 400 is described.

[0139] There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface as long as the substrate has sufficient heat resistance for heat treatment to be performed later.

[0140] When the temperature of the heat treatment to be performed later is high, a glass substrate having a strain point of 730°C or higher can be used as the substrate 400. For example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass can be used as the material of the glass substrate. Note that by containing more barium oxide (BaO) than boron oxide, a more practical heat-resistant glass substrate can be formed. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0141] Note that a substrate formed of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used instead of the glass substrate as the substrate 400. Alternatively, a crystallized glass substrate or the like may be used. Further alternatively, a plastic substrate or the like may be used.

[0142] First, an insulating layer 407 serving as a base film is formed over a substrate 400 having an insulating surface. An oxide insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer is preferably used as the insulating layer 407 in contact with the oxide semiconductor layer. The insulating layer 407 can be formed by a plasma CVD method, a sputtering method, or the like. In order to prevent hydrogen from being contained in the insulating layer 407, the insulating layer 407 is preferably formed by a sputtering method.

[0143] In this embodiment, a silicon oxide layer is formed by a sputtering method as the insulating layer 407. The substrate 400 is transferred into a chamber, a sputtering gas containing high-purity oxygen from which hydrogen and moisture are removed is introduced into the chamber, and a target is used, so that a silicon oxide layer is deposited on the substrate 400 as the insulating layer 407. The substrate 400 may be at room temperature or may be heated.

[0144] For example, a silicon oxide film is formed as follows: quartz (preferably synthetic quartz) is used as a target; the substrate temperature is 108°C; the distance between the target and the substrate (TS distance) is 60 mm; the pressure is 0.4 Pa; the high-frequency power is 1.5 kW; the atmosphere is oxygen and argon (the flow rate ratio of oxygen to argon is 25 sccm:25 sccm=1:1); and RF sputtering is used. In this embodiment, the thickness of the silicon oxide film is 100 nm. A silicon target can be used instead of quartz (preferably synthetic quartz) to form the silicon oxide film. In this embodiment, oxygen or a mixed gas of oxygen and argon is used as the sputtering gas.

[0145] In this case, it is preferable to remove residual moisture in the chamber when depositing the insulating layer 407. This is to prevent the insulating layer 407 from containing hydrogen, hydroxyl groups, or moisture.

[0146] In order to remove residual moisture from the chamber, an adsorption-type vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with a cold trap can be used as an exhaust unit. In the chamber exhausted by using a cryopump, for example, hydrogen molecules, compounds containing hydrogen atoms (such as water (H2O)), etc. are exhausted. Therefore, the impurity concentration included in the insulating layer 407 formed in the chamber can be reduced.

[0147] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl, or hydride are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the insulating layer 407 .

[0148] Examples of sputtering methods include RF sputtering in which a high-frequency power source is used as a sputtering power source, DC sputtering in which a DC power source is used, and pulsed DC sputtering in which a bias voltage is applied in a pulsed manner. RF sputtering is mainly used when forming an insulating film, while DC sputtering is mainly used when forming a metal film.

[0149] A multi-target sputtering apparatus can be used in which multiple targets formed of different materials can be set. With the multi-target sputtering apparatus, films of different materials to be formed can be stacked in the same chamber, or multiple materials can be deposited simultaneously by discharge in the same chamber.

[0150] Alternatively, a sputtering apparatus that has a magnet system provided inside a chamber and is used for a magnetron sputtering method, or a sputtering apparatus that is used for an ECR sputtering method that uses plasma generated by using microwaves without using glow discharge may be used.

[0151] Furthermore, as a deposition method using sputtering, a reactive sputtering method in which a target substance and a sputtering gas component chemically react with each other during deposition to form a compound thin film thereof, or a bias sputtering method in which a voltage is also applied to a substrate during deposition can be used.

[0152] The insulating layer 407 may have a stacked structure; for example, a stacked structure in which a nitride insulating layer (such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer) and the above-mentioned oxide insulating layer are stacked in this order on the substrate 400 may be used.

[0153] For example, by introducing a sputtering gas containing high-purity hydrogen from which hydrogen and moisture are removed, and using a silicon target, a silicon nitride layer is formed between the silicon oxide layer and the substrate 400. In this case as well, it is preferable to remove residual moisture in the chamber when forming the silicon nitride layer, as in the case of depositing the silicon oxide layer.

[0154] The substrate may be heated while the silicon nitride layer is being film deposited.

[0155] When a silicon nitride layer and a silicon oxide layer are stacked to form the insulating layer 407, the silicon nitride layer and the silicon oxide layer can be formed in the same chamber using the same silicon target. For example, a sputtering gas containing nitrogen is first introduced and a silicon target placed inside the chamber is used to form the silicon nitride layer. Subsequently, the sputtering gas is switched to a sputtering gas containing oxygen and the silicon oxide layer is formed using the same silicon target. Since the silicon nitride layer and the silicon oxide layer can be formed continuously without being exposed to air, impurities such as hydrogen and moisture can be prevented from being absorbed on the surface of the silicon nitride layer.

[0156] Next, over the insulating layer 407 , an oxide semiconductor film is formed to a thickness of greater than or equal to 2 nm and less than or equal to 200 nm.

[0157] In order to minimize the presence of impurities such as hydrogen, hydroxyl groups, or moisture in the oxide semiconductor film, it is preferable to preheat the substrate 400 provided with the insulating layer 407 in a preheating chamber of a sputtering apparatus before film formation to remove impurities (such as hydrogen or moisture) absorbed on the substrate 400, and then perform exhaust. A cryopump is preferably used as an exhaust unit provided in the preheating chamber. This preheating step is not necessarily performed.

[0158] Note that before forming the oxide semiconductor film by sputtering, reverse sputtering in which argon gas is introduced and plasma is generated is preferably performed to remove dust on the surface of the insulating layer 407. Reverse sputtering is a method in which a voltage is applied to the substrate side by a high-frequency power supply in an argon atmosphere to generate plasma on the substrate side without applying a voltage to the target side, thereby denaturing the surface. A nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like can be used instead of an argon atmosphere.

[0159] The oxide semiconductor film is formed by a sputtering method. An oxide semiconductor film can be formed using an In-Ga-Zn-O-based oxide semiconductor film, an In-Sn-Zn-O-based oxide semiconductor film, an In-Al-Zn-O-based oxide semiconductor film, a Sn-Ga-Zn-O-based oxide semiconductor film, an Al-Ga-Zn-O-based oxide semiconductor film, a Sn-Al-Zn-O-based oxide semiconductor film, an In-Zn-O-based oxide semiconductor film, a Sn-Zn-O-based oxide semiconductor film, an Al-Zn-O-based oxide semiconductor film, an In-O-based oxide semiconductor film, a Sn-O-based oxide semiconductor film, or a Zn-O-based oxide semiconductor film. In this embodiment, the oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Specifically, a target having a composition ratio of In2O3:Ga2O3:ZnO=1:1:1 (i.e., In:Ga:Zn=1:1:0.5 [atom%] (atomic%)) is used. Alternatively, a target with a composition ratio of In:Ga:Zn=1:1:1 [atom%] or In:Ga:Zn=1:1:2 [atom%] may be used. In this embodiment, the filling rate of the oxide semiconductor target is greater than or equal to 90% and less than or equal to 100%, preferably greater than or equal to 95% and less than or equal to 99.9%. By using an oxide semiconductor target with a high filling rate, the deposited oxide semiconductor film has a high density. The atmosphere during sputtering may be a rare gas (usually argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. The target may contain greater than or equal to 2wt% and less than or equal to 10wt% of SiO2.

[0160] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide semiconductor film.

[0161] An oxide semiconductor film is formed on the substrate 400 as follows: the substrate is held in a chamber with a reduced pressure, residual moisture in the chamber is removed, a sputtering gas for removing hydrogen and moisture is introduced, and the above-mentioned target is used. In order to remove residual moisture in the chamber, an absorption vacuum pump is preferably used. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with an added cold trap can be used as an exhaust unit. In a chamber that is exhausted using a cryogenic pump, hydrogen molecules, compounds including hydrogen atoms (such as water (H2O)), compounds including carbon atoms, etc. are exhausted. Therefore, the impurity concentration included in the oxide semiconductor film formed in the chamber can be reduced. The substrate can be heated when the silicon oxide semiconductor film is deposited.

[0162] As an example of film deposition conditions, the following conditions are used: the temperature of the substrate is room temperature; the distance between the substrate and the target is 110 mm; the pressure is 0.4 Pa; the direct current (DC) power is 0.5 kW; and the atmosphere is oxygen and argon (the flow rate ratio of oxygen to argon is 15 sccm:30 sccm). It is preferable to use a pulsed direct current (DC) power supply because it can reduce powder substances (also called particles or dust) generated during film deposition and make the film thickness uniform. The thickness of the oxide semiconductor film is greater than or equal to 2 nm and less than or equal to 200 nm, preferably greater than or equal to 5 nm and less than or equal to 30 nm. Note that the appropriate thickness of the oxide semiconductor film varies depending on its material; therefore, the thickness can be appropriately determined according to the material.

[0163] Next, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 412 by a first photolithography step (see Figure 6A ). An inkjet method can be used to form a resist mask for forming the island-shaped oxide semiconductor layer 412. Forming a resist mask by an inkjet method does not require a photomask; thus, manufacturing costs can be reduced.

[0164] For etching the oxide semiconductor film, one or both of wet etching and dry etching can be employed.

[0165] It is preferable to use a chlorine-containing gas (a chlorine-based gas such as chlorine (Cl 2 ), boron chloride (BCl 3 ), silicon chloride (SiCl 4 ), or carbon tetrachloride (CCl 4 )) as an etching gas for dry etching.

[0166] Alternatively, a fluorine-containing gas (a fluorine-based gas such as carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), or trifluoromethane (CHF3)); hydrogen bromide (HBr); oxygen (O2); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added, etc. may be used.

[0167] As a dry etching method, a parallel plate RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used. In order to etch the layer into a desired shape, the etching conditions (the amount of electric power applied to the coiled electrode, the amount of electric power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted.

[0168] As an etchant for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid, an ammonia-hydrogen peroxide mixture (hydrogen peroxide: ammonia: water = 5:2:2), an ammonium hydroxide / hydrogen peroxide mixture (31 wt % hydrogen peroxide solution: 28 wt % ammonia: water = 5:2:2), or the like can be used. ITO07N (produced by KANTO CHEMICAL CO., INC.) can be used.

[0169] After wet etching, the etchant and the etched material are removed by washing. The waste liquid containing the etchant from which the material has been removed can be purified, and the material contained in the waste liquid can be reused. By collecting and reusing the material included in the oxide semiconductor (such as indium) from the waste liquid after etching, resources can be used efficiently and costs can be reduced.

[0170] By appropriately adjusting etching conditions such as an etchant, etching time, or temperature depending on the material, the material can be etched into a desired shape.

[0171] In this embodiment, the oxide semiconductor film is processed into the island-shaped oxide semiconductor layer 412 by a wet etching method using a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid.

[0172] In this embodiment, the oxide semiconductor layer 412 is subjected to a first heat treatment. The temperature of the first heat treatment is higher than or equal to 400°C and lower than or equal to 750°C. When the strain point of the substrate 400 is lower than or equal to 750°C, the temperature is higher than or equal to 400°C and lower than the strain point of the substrate 400. In this embodiment, the substrate is placed in an electric furnace, which serves as a heat treatment apparatus, and the oxide semiconductor layer is heat treated at 450°C for one hour in a nitrogen atmosphere. The temperature is then lowered to room temperature while preventing water or hydrogen from entering the oxide semiconductor layer without exposure to air. Thus, an oxide semiconductor layer is obtained. The first heat treatment can be used to dehydrate or dehydrogenate the oxide semiconductor layer 412.

[0173] The heat treatment device is not limited to an electric furnace, and may be provided with a device for heating the object to be treated by heat conduction or heat radiation from a heater such as a resistance heater. For example, an RTA (rapid thermal annealing) device such as a GRTA (gas rapid thermal annealing) device or an LRTA (lamp rapid thermal annealing) device may be used. The LRTA device is a device for heating the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device for performing heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen or a rare gas (such as argon), is used.

[0174] For example, as the first heat treatment, GRTA can be performed as follows: the substrate is transferred into an inert gas heated to a high temperature of 650° C. to 700° C., heated for several minutes, and then transferred out of the inert gas. GRTA achieves high-temperature heat treatment in a short time.

[0175] In the first heat treatment, it is preferred that the nitrogen or rare gas (such as helium, neon, or argon) does not contain water, hydrogen, or the like. The purity of the nitrogen or rare gas (such as helium, neon, or argon) introduced into the heat treatment apparatus is preferably greater than or equal to 6N (99.9999%), more preferably greater than or equal to 7N (99.99999%) (i.e., the impurity concentration is preferably less than or equal to 1 ppm, more preferably less than or equal to 0.1 ppm).

[0176] In addition, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 can be crystallized into a microcrystalline film or a polycrystalline film. For example, the oxide semiconductor layer can be crystallized into a microcrystalline oxide semiconductor film in which the crystallinity is greater than or equal to 90%, or greater than or equal to 80%. In addition, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 can be an amorphous oxide semiconductor film that does not contain a crystalline component. The oxide semiconductor layer can become an oxide semiconductor film in which a microcrystalline portion (having a grain size greater than or equal to 1 nm and less than or equal to 20 nm, typically greater than or equal to 2 nm and less than or equal to 4 nm) is mixed into the amorphous oxide semiconductor.

[0177] Similarly, the oxide semiconductor film may be subjected to first heat treatment of the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer 412. In this case, the substrate is removed from the heating apparatus after the first heat treatment and then subjected to a photolithography step.

[0178] In the above, an example is described in which heat treatment for dehydration and / or dehydrogenation is performed on the oxide semiconductor layer after the oxide semiconductor layer 412 is formed. However, heat treatment for dehydration and / or dehydrogenation may be performed after the source electrode and the drain electrode are stacked on the oxide semiconductor layer, or after the gate insulating layer is formed on the source electrode and the drain electrode, as long as it is performed after the oxide semiconductor layer is deposited.

[0179] A conductive film is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive film can be formed by a sputtering method or a vacuum evaporation method. As the material of the conductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W; an alloy containing any one of these elements as a component; an alloy film containing any combination of these elements, etc. can be given. In addition, one or more materials selected from manganese, magnesium, zirconium, beryllium, and yttrium can be used. In addition, the conductive film can have a single-layer structure or a stacked-layer structure of more than or equal to two layers. For example, a single-layer structure of an aluminum film including silicon, a double-layer structure in which a titanium film is stacked on the aluminum film, or a three-layer structure in which a Ti film, an aluminum film, and a titanium film are stacked in this order can be given. Alternatively, a film, an alloy film, or a nitride film can be used, which contains aluminum (Al) and one or more elements selected from the following: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). In this embodiment, a titanium film with a thickness of 150 nm is formed as the conductive film by a sputtering method.

[0180] Next, a resist mask is formed on the conductive film by a second photolithography step. The resist mask can be formed using an inkjet method. Forming the resist mask by the inkjet method does not require a photomask; thus, manufacturing costs can be reduced. Thereafter, it is selectively etched to form the source and drain electrode layers 415a and 415b, and then the resist mask is removed (see Figure 6B ). It is preferable that each end portion of the source electrode layer and the drain electrode layer has a tapered shape because coverage with a gate insulating layer stacked thereon is improved.

[0181] Note that each material and etching conditions are appropriately adjusted so that etching of the conductive film does not remove the oxide semiconductor layer 412 and does not expose the insulating layer 407 under the oxide semiconductor layer 412 .

[0182] In this embodiment, since a Ti film is used as a conductive film and an In-Ga-Zn-O-based oxide semiconductor is used as the oxide semiconductor layer 412, an ammonium hydroxide / hydrogen peroxide mixture (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2) is used as an etchant.

[0183] In the second photolithography step, part of the oxide semiconductor layer 412 is etched in some cases, whereby an oxide semiconductor layer having a groove (a depressed portion) can be formed.

[0184] Ultraviolet light, KrF laser, or ArF laser can be used for exposure when forming the resist mask in the second photolithography step. The channel length L of the thin film transistor to be formed is determined by the distance between the lower end of the source electrode layer and the lower end of the drain electrode layer, and the source electrode layer and the drain electrode layer are adjacent to each other on the oxide semiconductor layer 412. In the case of exposure for a channel length L less than 25 nm, extreme ultraviolet light with an extremely short wavelength of several nanometers to tens of nanometers is used for exposure when forming the resist mask in the second photolithography step. When exposed by extreme ultraviolet light, the resolution is high and the depth of focus is large. Therefore, the channel length L of the thin film transistor can be made greater than or equal to 10 nm and less than or equal to 1000 nm, the operating rate of the circuit can be increased, and low power consumption can be achieved by an extremely small off-state current.

[0185] Next, a gate insulating layer 402 is formed over the insulating layer 407, the oxide semiconductor layer 412, and the source and drain electrode layers 415a and 415b (see Figure 6C ).

[0186] The gate insulating layer 402 can be formed into a single-layer structure or a stacked-layer structure using one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer by a plasma CVD method, a sputtering method, or the like. In order to prevent the gate insulating layer 402 from containing hydrogen as much as possible, the gate insulating layer 402 is preferably formed by a sputtering method. In the case of forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen, or a mixed gas of oxygen and argon is used as a sputtering gas. In this embodiment, a 100 nm thick silicon oxide layer is formed as follows: the pressure is 0.4 Pa; the high-frequency power is 1.5 kW; the atmosphere is oxygen and argon (the flow rate ratio of oxygen to argon is 25 sccm:25 sccm=1:1); and an RF sputtering method is used.

[0187] The gate insulating layer 402 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked in this order. For example, a gate insulating layer having a thickness of greater than or equal to 70 nm and less than or equal to 400 nm (for example, a thickness of 100 nm) is formed as follows: a silicon oxide layer (SiO2) having a thickness of greater than or equal to 5 nm and less than or equal to 300 nm is formed by a sputtering method. x (x>0)) as a first gate insulating layer, and then stacking a silicon nitride layer (SiN) with a thickness greater than or equal to 50 nm and less than or equal to 200 nm on the first gate insulating layer. y (y>0)) as the second gate insulating layer.

[0188] Next, a resist mask is formed by a third photolithography step, and portions of the gate insulating layer 402 are selectively etched to remove openings 421a and 421b reaching the source and drain electrode layers 415a and 415b (see FIG. 4 ). Figure 6D ).

[0189] Next, a conductive film is formed over the gate insulating layer 402 and the openings 421a and 421b. In this embodiment, a titanium film with a thickness of 150 nm is formed by sputtering. A fourth photolithography step is then performed to form the gate electrode layer 411 and the wiring layers 414a and 414b. Note that the resist mask can be formed by an inkjet method. Forming the resist mask by an inkjet method eliminates the need for a photomask, thereby reducing manufacturing costs.

[0190] The gate electrode layer 411, and the wiring layers 414a and 414b can each be formed to have a single layer or a stacked layer structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as its main component.

[0191] For example, as a double-layer structure of each of the gate electrode layer 411 and the wiring layers 414a and 414b, any of the following structures is preferred: a double-layer structure of an aluminum layer and a molybdenum layer stacked on the aluminum layer, a double-layer structure of a copper layer and a molybdenum layer stacked on the copper layer, a double-layer structure of a copper layer and a titanium nitride layer or a tantalum nitride layer stacked on the copper layer, and a double-layer structure of a titanium nitride layer and a molybdenum layer. As a three-layer structure, a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer is preferred. The gate electrode layer can be formed using a light-transmitting conductive film. A light-transmitting conductive oxide can be given as an example of a material for the light-transmitting conductive film.

[0192] Next, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere (preferably at a temperature of 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower). In this embodiment, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour. The second heat treatment may be performed after forming a protective insulating layer or a planarization insulating layer on the thin film transistor 410.

[0193] Furthermore, heat treatment may be performed in an air atmosphere at a temperature of 100°C or higher and 200°C or lower for 1 hour or higher and 30 hours or lower. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in heating temperature may be repeated multiple times: the heating temperature is increased from room temperature to a temperature of 100°C or higher and 200°C or lower, and then decreased to room temperature. This heat treatment may be performed under reduced pressure before forming the oxide insulating layer. Under reduced pressure, the heat treatment time can be shortened.

[0194] Through the above-described process, the thin film transistor 410 including the oxide semiconductor layer 412 (in which the concentrations of hydrogen, moisture, hydride, and hydroxide are reduced) can be formed (see FIG. Figure 6E ). The thin film transistor 410 can be used as the thin film transistor described in Embodiment 1.

[0195] A protective insulating layer or a planarization insulating layer for planarization may be provided on the thin film transistor 410. For example, the protective insulating layer may be formed to have a single-layer structure or a stacked-layer structure using one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer.

[0196] The planarization insulating layer can be formed using a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy resin. In addition to these organic materials, it is possible to use a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. The planarization insulating layer can be formed by stacking a plurality of insulating films formed using these materials.

[0197] Note that the siloxane resin corresponds to a resin including a Si-O-Si bond formed using a siloxane material as a raw material. The siloxane resin may include an organic group (eg, an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may include a fluoro group.

[0198] There is no particular limitation on the method for forming the planarized insulating layer. Depending on the material, the planarized insulating layer may be formed by a method such as sputtering, SOG coating, spin coating, dipping, spraying, or droplet jetting (e.g., inkjet, screen printing, or offset printing), or by using a tool such as a doctor blade, a roll coater, a curtain coater, or a knife coater.

[0199] By removing residual moisture in the reaction atmosphere during the deposition of the oxide semiconductor film as described above, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced, thereby stabilizing the oxide semiconductor film.

[0200] By using a thin-film transistor manufactured as described above in each of the multiple pixels in the display portion of a liquid crystal display device, leakage current from the pixel can be suppressed. Consequently, the period during which the voltage is maintained in the storage capacitor can be increased, and power consumption when displaying a still image, etc., on the liquid crystal display device can be reduced. Furthermore, power consumption can be further reduced by stopping the supply of control signals when displaying a still image. Furthermore, switching between still and moving images can be performed without causing any malfunctions.

[0201] Embodiment 2 may be implemented by appropriately combining with any of the structures described in other embodiments.

[0202] (Example 3)

[0203] In Example 3, another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification will be described. Note that Example 2 is applicable to the same parts as in Example 2, as well as parts and steps having similar functions as in Example 2, and their description will not be repeated. Detailed descriptions of the same parts will be omitted. The thin film transistor 460 described in this embodiment can be used as the thin film transistor in each pixel of the pixel portion 1008 described in Example 1.

[0204] use Figure 7A and 7B ,as well as Figures 8A to 8E An embodiment of a thin film transistor of this embodiment and a method for manufacturing the thin film transistor will be described.

[0205] Figure 7A An example of a planar structure of a thin film transistor is shown, and Figure 7B An example of its cross-sectional structure is shown. Figure 7A and 7B The illustrated thin film transistor 460 is a top-gate thin film transistor.

[0206] Figure 7A is a plan view of a top-gate thin film transistor 460, and Figure 7B It is along Figure 7A Cross-sectional view along line D1-D2 in FIG.

[0207] The thin film transistor 460 includes, over a substrate 450 having an insulating surface, an insulating layer 457, a source or drain electrode layer 465a (465a1 and 465a2), an oxide semiconductor layer 462, a source or drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, and a gate electrode layer 461 (461a and 461b). The source or drain electrode layer 465a (465a1 and 462a2) is electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown in the drawings, the source or drain electrode layer 465b is also electrically connected to the wiring layer in an opening formed in the gate insulating layer 452.

[0208] Reference below Figures 8A to 8E A process for fabricating thin film transistor 460 on substrate 450 is described.

[0209] First, an insulating layer 457 serving as a base film is formed over a substrate 450 having an insulating surface.

[0210] In this embodiment, a silicon oxide layer is formed by a sputtering method as the insulating layer 457. The substrate 450 is transferred into a chamber, a sputtering gas containing high-purity oxygen from which hydrogen and moisture are removed is introduced into the chamber, and a target or quartz (preferably synthetic quartz) is used, so that a silicon oxide layer is deposited on the substrate 450 as the insulating layer 457. In this embodiment, oxygen gas or a mixed gas of oxygen and argon gas is used as the sputtering gas.

[0211] For example, in this embodiment, a silicon oxide film is formed as follows: quartz (preferably synthetic quartz) with a purity of 6N is used as a target; the substrate temperature is 108°C; the distance between the target and the substrate (TS distance) is 60 mm; the pressure is 0.4 Pa; the high-frequency power is 1.5 kW; the atmosphere is oxygen and argon (the flow rate ratio of oxygen to argon is 25 sccm:25 sccm = 1:1); and RF sputtering is used. In this embodiment, the thickness of the silicon oxide film is 100 nm. A silicon target can be used instead of quartz (preferably synthetic quartz) to form the silicon oxide film.

[0212] In this case, it is preferable to remove residual moisture in the chamber when depositing the insulating layer 457. This is to prevent the insulating layer 457 from containing hydrogen, hydroxyl groups, and / or moisture. In the chamber evacuated by using a cryopump, for example, hydrogen molecules, compounds containing hydrogen atoms (such as H2O), and the like are exhausted. As a result, the impurity concentration included in the insulating layer 457 formed in the chamber can be reduced.

[0213] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl, or hydride are removed to less than or equal to 1 ppm, preferably less than or equal to 10 ppb is used as a sputtering gas for depositing the insulating layer 457 .

[0214] The insulating layer 457 may have a stacked structure; for example, a stacked structure in which a nitride insulating layer (such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer) and the above-mentioned oxide insulating layer are stacked in this order on the substrate 450 may be used.

[0215] For example, by introducing a sputtering gas containing high-purity hydrogen from which hydrogen and moisture are removed, and using a silicon target, a silicon nitride layer is formed between the silicon oxide layer and the substrate 450. In this case as well, it is preferable to remove residual moisture in the chamber when forming the silicon nitride layer, as in the case of depositing the silicon oxide layer.

[0216] A conductive film is formed on the insulating layer 457. As the material of the conductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W; an alloy containing any one of these elements as a component; an alloy film containing any combination of these elements, etc. can be given. In addition, one or more materials selected from manganese, magnesium, zirconium, beryllium, and yttrium can be used. In addition, the conductive film can have a single-layer structure or a stacked-layer structure of two or more layers. For example, a single-layer structure of an aluminum film including silicon, a double-layer structure in which a titanium film is stacked on the aluminum film, or a three-layer structure in which a Ti film, an aluminum film, and a titanium film are stacked in this order can be given. Alternatively, a film, an alloy film, or a nitride film containing aluminum (Al) and one or more elements selected from the following: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) can be used. In this embodiment, a titanium film with a thickness of 150 nm is formed as the conductive film by sputtering. Next, a resist mask is formed over the conductive film by a first photolithography step, which is selectively etched to form source and drain electrode layers 465a1 and 465a2, and then the resist mask is removed (see FIG. Figure 8A ). The source electrode layer and the drain electrode layer 465a1 and 465a2 shown as cut in the cross-sectional view are one film having a toroidal portion, such as Figure 7A It is preferable that each end portion of the source and drain electrode layers 465a1 and 465a2 have a tapered shape because coverage with a gate insulating layer stacked thereover is improved.

[0217] Next, an oxide semiconductor film having a thickness greater than or equal to 2 nm and less than or equal to 200 nm (for example, greater than or equal to 5 nm and less than or equal to 30 nm) is formed. Note that the appropriate thickness of the oxide semiconductor film varies depending on its material; therefore, the thickness can be appropriately determined depending on the material. In this embodiment, the oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target.

[0218] An oxide semiconductor film is formed on the substrate 450 as follows: the substrate is held in a chamber with a reduced pressure, residual moisture in the chamber is removed, a sputtering gas for removing hydrogen and moisture is introduced, and a target is used. In order to remove residual moisture in the chamber, an absorption vacuum pump is preferably used. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with an added cold trap can be used as an exhaust unit. In a chamber that is exhausted using a cryogenic pump, hydrogen molecules, compounds including hydrogen atoms (such as water (H2O)), compounds including carbon atoms, etc. are exhausted. Therefore, the impurity concentration included in the oxide semiconductor film formed in the chamber can be reduced. The substrate can be heated when the silicon oxide semiconductor film is deposited.

[0219] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide semiconductor film.

[0220] As an example of film deposition conditions, the following conditions are adopted: the temperature of the substrate is room temperature; the distance between the substrate and the target is 110 mm; the pressure is 0.4 Pa; the direct current (DC) power supply is 0.5 kW; and the atmosphere is oxygen and argon (the flow rate ratio of oxygen to argon is 15 sccm:30 sccm).

[0221] Next, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 462 by a second photolithography step (see Figure 8B In this embodiment, the oxide semiconductor film is processed into the island-shaped oxide semiconductor layer 462 by a wet etching method using a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid.

[0222] In this embodiment, the oxide semiconductor layer 462 is subjected to a first heat treatment. The temperature of the first heat treatment is higher than or equal to 400°C and lower than or equal to 750°C. When the strain point of the substrate 450 is lower than or equal to 750°C, the temperature is higher than or equal to 450°C and lower than the strain point of the substrate 450. In this embodiment, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heat treated at 450°C for one hour in a nitrogen atmosphere. The temperature is then lowered to room temperature without exposure to air and without water or hydrogen entering the oxide semiconductor layer. Thus, an oxide semiconductor layer is obtained. The first heat treatment can be used to dehydrate or dehydrogenate the oxide semiconductor layer 462.

[0223] The heat treatment apparatus is not limited to an electric furnace and may be provided with a device that heats the object to be treated by heat conduction or heat radiation from a heater such as a resistance heater. For example, an RTA (rapid thermal annealing) apparatus such as a GRTA (gas rapid thermal annealing) apparatus or an LRTA (lamp rapid thermal annealing) apparatus may be used. For example, as the first heat treatment, GRTA may be performed as follows: the substrate is transferred to an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then transferred to and removed from the inert gas heated to a high temperature. GRTA achieves high-temperature heat treatment for a shorter time.

[0224] In the first heat treatment, it is preferred that the nitrogen or rare gas (such as helium, neon, or argon) does not contain water, hydrogen, or the like. The purity of the nitrogen or rare gas (such as helium, neon, or argon) introduced into the heat treatment apparatus is preferably greater than or equal to 6N (99.9999%), more preferably greater than or equal to 7N (99.99999%) (i.e., the impurity concentration is preferably less than or equal to 1 ppm, more preferably less than or equal to 0.1 ppm).

[0225] Note that the oxide semiconductor layer 462 can be crystallized into a microcrystalline film or a polycrystalline film depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer.

[0226] Similarly, the oxide semiconductor film may be subjected to first heat treatment of the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer 462. In this case, the substrate is removed from the heating apparatus after the first heat treatment and then subjected to a photolithography step.

[0227] In the above, an example is described in which heat treatment for dehydration and / or dehydrogenation is performed on the oxide semiconductor layer after the oxide semiconductor layer 462 is formed. However, heat treatment for dehydration and / or dehydrogenation may be performed after the source and drain electrode layers 465 b are stacked over the oxide semiconductor layer, or after the gate insulating layer 452 is formed over the source and drain electrode layers 465 b, as long as it is performed after the oxide semiconductor layer is deposited.

[0228] Next, a conductive film is formed over the insulating layer 457 and the oxide semiconductor layer 462. After that, a resist mask is formed over the conductive film by a third photolithography step, the conductive film is selectively etched to form a source electrode layer or drain electrode layer 465b and a wiring layer 468, and then the resist mask is removed (see FIG. Figure 8C ). The source electrode layer or drain electrode layer 465b and the wiring layer 468 can each be formed using a material and a process similar to those of the source electrode layer or drain electrode layers 465a1 and 465a2.

[0229] In this embodiment, a 150 nm thick titanium film is formed by sputtering as each of the source or drain electrode layer 465 b and the wiring layer 468. In this embodiment, since the source or drain electrode layers 465 a 1 and 465 a 2 and the source or drain electrode layer 465 b are made of the same titanium film, etching selectivity between the source or drain electrode layer 465 b and each of the source or drain electrode layers 465 a 1 and 465 a 2 is not improved. Therefore, in order to prevent the source or drain electrode layers 465 a 1 and 465 a 2 from being etched when the source or drain electrode layer 465 b is etched, the wiring layer 468 is provided on the source or gate electrode layer 465 a 2 that is not covered by the oxide semiconductor layer 462. In the case where different materials having high selectivity during etching are used to form the source electrode layer 465a1 and 465a2, and the source electrode layer 465b, the wiring layer 468 that protects the source electrode layer 465a2 during etching is not necessarily provided.

[0230] The oxide semiconductor layer 462 can be partially etched away by etching the conductive film. The material and etching conditions are appropriately controlled so that the oxide semiconductor layer 462 is not removed unnecessarily.

[0231] In this embodiment, since a Ti film is used as a conductive film and an In-Ga-Zn-O-based oxide semiconductor is used as the oxide semiconductor layer 462, an ammonium hydroxide / hydrogen peroxide mixture (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2) is used as an etchant.

[0232] In the third photolithography step, a portion of the oxide semiconductor layer 462 may be etched, thereby forming an oxide semiconductor layer having a groove (recessed portion). The resist mask for forming the source or drain electrode layer 465b and the wiring layer 468 may be formed by an inkjet method. Forming the resist mask by an inkjet method eliminates the need for a photomask; thus, manufacturing costs can be reduced.

[0233] Next, the gate insulating layer 452 is formed over the insulating layer 457 , the oxide semiconductor layer 462 , the source or drain electrode layers 465 a 1 and 465 a 2 , and the source or drain electrode layer 465 b .

[0234] The gate insulating layer 452 can be formed to have a single-layer structure or a stacked-layer structure using one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer by plasma CVD, sputtering, etc. In order to minimize the inclusion of hydrogen in the gate insulating layer 452, the gate insulating layer 452 is preferably formed by sputtering. When forming a silicon oxide film by sputtering, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

[0235] The gate insulating layer 452 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked in this order on the source or drain electrode layers 465a1 and 465a2, and the source or drain electrode layer 465b. In this embodiment, a 100 nm thick silicon oxide film is formed as follows: pressure of 0.4 Pa; high frequency power of 1.5 kW; atmosphere of oxygen and argon (oxygen to argon flow rate ratio of 25 sccm:25 sccm=1:1); and using RF sputtering.

[0236] Next, a resist mask is formed by a fourth photolithography step, and etching is selectively performed to remove a portion of the gate insulating layer 452, thereby forming an opening 423 reaching the wiring layer 438 (see FIG. 4 ). Figure 8DAlthough not shown, an opening that reaches the source electrode layer or the drain electrode layer 465 b may be formed when forming the opening 423. In this embodiment, an opening that reaches the source electrode layer or the drain electrode layer 465 b is formed after stacking an interlayer insulating layer, and a wiring layer for electrical connection is formed in the opening.

[0237] Next, a conductive film is formed over the gate insulating layer 452 and the opening 423. After that, a fifth photolithography step is performed to form the gate electrode layer 461 (461a and 461b) and the wiring layer 464. Note that the resist mask can be formed by an inkjet method. Forming the resist mask by an inkjet method eliminates the need for a photomask, thereby reducing manufacturing costs.

[0238] The gate electrode layer 461 (461a and 461b) and the wiring layer 464 can each be formed into a single layer or a stacked layer structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as its main component.

[0239] In this embodiment, a 150 nm thick titanium film is formed as each of the gate electrode layer 461 (461a and 461b) and the wiring layer 464 by a sputtering method. Figure 8E The gate electrode layer 461 (461a and 461b) is shown as being divided, but the gate electrode layer 461 (461a and 461b) is formed to overlap with a ring-shaped gap formed by the source electrode layer or drain electrode layer 465a1 and 465a2, and the source electrode layer or drain electrode layer 465b, as shown in FIG. Figure 7A shown.

[0240] Next, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere (preferably at a temperature of 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower). In this embodiment, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour. The second heat treatment may be performed after forming a protective insulating layer or a planarization insulating layer over the thin film transistor 460.

[0241] Furthermore, heat treatment may be performed in an air atmosphere at a temperature of 100°C or higher and 200°C or lower for 1 hour or higher and 30 hours or lower. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in heating temperature may be repeated multiple times: the heating temperature is increased from room temperature to a temperature of 100°C or higher and 200°C or lower, and then decreased to room temperature. This heat treatment may be performed under reduced pressure before forming the oxide insulating layer. Under reduced pressure, the heat treatment time can be shortened.

[0242] Through the above-described process, the thin film transistor 460 including the oxide semiconductor layer 462 in which the concentrations of hydrogen, moisture, hydride, and hydroxide are reduced can be formed (see FIG. Figure 8E ). The thin film transistor 460 can be used as the thin film transistor used in each pixel of the pixel portion 1008 described in Embodiment 1.

[0243] A protective insulating layer or a planarization insulating layer for planarization may be provided over the thin film transistor 460. Although not shown, in this embodiment, an opening reaching the source electrode layer or the drain electrode layer 465 b is formed in the gate insulating layer 452 and the protective insulating layer and / or the planarization insulating layer, and a wiring layer electrically connected to the source electrode layer or the drain electrode layer 465 b is formed in the opening.

[0244] By removing residual moisture in the reaction atmosphere during the deposition of the oxide semiconductor film as described above, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced, thereby stabilizing the oxide semiconductor film.

[0245] In this way, in a plurality of pixels included in a display portion of a liquid crystal display device including a thin film transistor using an oxide semiconductor layer, the off-state current can be suppressed. Therefore, the period for maintaining the voltage in the storage capacitor can be extended, and the power consumption when displaying a still image, etc. in the liquid crystal display device can be reduced. In addition, by stopping the supply of the control signal when displaying a still image, the power consumption can be further reduced. In addition, the still image and the moving image can be switched without malfunction. In this embodiment, the shape of the channel is circular, and different layers are used to form the source electrode layer and the drain electrode layer, thereby reducing the channel length and increasing the channel width. In this way, a thin film transistor with a large channel width can be formed even in a relatively small area, which enables switching for large currents. In addition, although the channel width is large, the off-state current is extremely small because the oxide semiconductor is highly purified.

[0246] Embodiment 3 may be implemented by appropriately combining with any of the structures described in other embodiments.

[0247] (Example 4)

[0248] use Figure 9A and 9B4 to describe the thin film transistors in this embodiment. In Example 4, other examples of thin film transistors that can be applied to the liquid crystal display device disclosed in this specification will be described. Note that Example 2 is applicable to the same parts as in Example 2, as well as parts and steps having similar functions as in Example 2, and their descriptions will not be repeated. In addition, the detailed descriptions of the same parts are omitted. The thin film transistors 425 and 426 described in this embodiment can each be used as a thin film transistor in each pixel of the pixel portion 1008 described in Example 1.

[0249] Figure 9A and 9B An example of a cross-sectional structure of a thin film transistor is shown. Figure 9A and 9B Each of the illustrated thin film transistors 425 and 426 is a thin film transistor having a structure in which an oxide semiconductor layer is interposed between a conductive layer and a gate electrode layer.

[0250] exist Figure 9A and 9B In the embodiment, a silicon substrate 420 is used, and thin film transistors 425 and 426 are respectively provided on an insulating layer 422 (provided on the silicon substrate 420).

[0251] exist Figure 9A In the embodiment, the conductive layer 427 is provided between the insulating layer 422 (provided on the silicon substrate 420 ) and the insulating layer 407 so as to completely overlap with at least the oxide semiconductor layer 412 .

[0252] Figure 9B This is an example in which the conductive layer between the insulating layer 422 and the insulating layer 407 is processed into the conductive layer 424 by etching and overlaps with at least part of the channel region including the oxide semiconductor layer 412 .

[0253] Conductive layers 427 and 424 are each formed of a metal material that can withstand the temperature of a subsequent heat treatment. An element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) can be used; an alloy containing any of these elements as a component; an alloy film containing any combination of these elements; a nitride containing any of the above elements as a component; and the like can be used. A single-layer structure or a stacked-layer structure can be used; for example, a single tungsten layer, a stacked layer of a tungsten nitride layer, and the like can be used.

[0254] The conductive layers 427 and 424 may each have a potential equal to or different from the potential of the gate electrode layer 411 of each of the thin film transistors 425 and 426, and each of the conductive layers 427 and 424 may function as a second gate electrode layer. The potential of each of the conductive layers 427 and 424 may be a fixed potential such as GND or 0 V.

[0255] The electrical characteristics of the thin film transistors 425 and 426 can be controlled by the conductive layers 427 and 424, respectively.

[0256] Embodiment 4 can be implemented by appropriately combining with any of the structures described in other embodiments.

[0257] (Example 5)

[0258] In Embodiment 5, an example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification will be described.

[0259] use Figures 10A to 10E An embodiment of a thin film transistor of this embodiment and a method for manufacturing the thin film transistor will be described.

[0260] Figures 10A to 10E An example of a cross-sectional structure of a thin film transistor is shown. Figures 10A to 10E The thin film transistor 390 shown is a bottom-gate structure, which is also called an inverted staggered thin film transistor.

[0261] Although the thin film transistor 390 is described using a single-gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions can be formed as needed.

[0262] In the following, use Figures 10A to 10E A process for fabricating thin film transistor 390 on substrate 394 will be described.

[0263] First, a conductive film is formed over a substrate 394 having an insulating surface, and then a first photolithography step is performed thereon to form a gate electrode layer 391. The ends of the gate electrode layer preferably have a tapered shape because coverage with the gate insulating layer stacked thereon is improved. Note that the resist mask can be formed by an inkjet method. Forming the resist mask by an inkjet method eliminates the need for a photomask; thus, manufacturing costs can be reduced.

[0264] Although there is no particular limitation on a substrate that can be used as the substrate 394 having an insulating surface, the substrate 394 must at least have heat resistance high enough to withstand heat treatment to be performed later.

[0265] For example, when a glass substrate is used as the substrate 394, if the temperature of the heat treatment to be performed later is high, it is preferable to use a glass substrate having a strain point of 730°C or higher. For example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used as the glass substrate. Note that by containing a larger amount of barium oxide (BaO) than boron oxide, the glass substrate becomes heat-resistant and more practical. Therefore, it is preferable to use a glass substrate containing a larger amount of BaO than B2O3.

[0266] Note that a substrate formed of an insulator such as a ceramic substrate, a quartz glass substrate, or a sapphire substrate may be used instead of a glass substrate as the substrate 394. Alternatively, a crystallized glass substrate or the like may be used. Further alternatively, a plastic substrate or the like may be used as appropriate.

[0267] An insulating film serving as a base film may be provided between the substrate 394 and the gate electrode layer 391. This base film has a function of preventing diffusion of impurity elements from the substrate 394 and may be formed to have a single-layer structure or a stacked-layer structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.

[0268] The gate electrode layer 391 can be formed to have a single-layer structure or a stacked-layer structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as a main component.

[0269] For example, as a double-layer structure of the gate electrode layer 391, any of the following structures is preferred: a double-layer structure of an aluminum layer and a molybdenum layer stacked on the aluminum layer, a double-layer structure of a copper layer and a molybdenum layer stacked on the copper layer, a double-layer structure of a copper layer and a titanium nitride layer or a tantalum nitride layer stacked on the copper layer, a double-layer structure of a titanium nitride layer and a molybdenum layer, and a double-layer structure of a tungsten nitride layer and a tungsten layer. As a three-layer structure, a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer is preferred. The gate electrode layer can also be formed using a light-transmitting conductive film. Light-transmitting conductive oxides and the like can be given as examples of materials for the light-transmitting conductive film.

[0270] Next, a gate insulating layer 397 is formed over the gate electrode layer 391 .

[0271] The gate insulating layer 397 can be formed to have a single-layer structure or a stacked-layer structure using one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer by a plasma CVD method, a sputtering method, etc. In order to prevent the gate insulating layer 397 from containing hydrogen as much as possible, the gate insulating layer 397 is preferably formed by a sputtering method. In the case of forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

[0272] The gate insulating layer 397 may have a structure in which a silicon nitride layer and a silicon oxide layer are stacked in this order on the gate electrode layer 391. For example, a 100 nm thick gate insulating layer is formed as follows: a silicon nitride layer (SiN2O3) having a thickness of greater than or equal to 50 nm and less than or equal to 200 nm is formed by a sputtering method. y (y>0)) as a first gate insulating layer, and then a silicon oxide layer (SiO2) having a thickness greater than or equal to 5 nm and less than or equal to 300 nm is stacked on the first gate insulating layer.x (x>0)) as the second gate insulating layer.

[0273] In order to prevent the oxide semiconductor film from containing hydrogen, hydroxyl groups, or moisture as much as possible in the gate insulating layer 397 and the oxide semiconductor film 393, it is preferred to preheat the substrate 394 provided with the gate electrode layer 391, or the substrate 394 provided with the gate electrode layer 391 and the gate insulating layer 397 in a preheating chamber of the sputtering device before the film is formed to eliminate impurities (such as hydrogen or moisture) absorbed on the substrate 394, and to exhaust. The preheating temperature is higher than or equal to 100°C and lower than or equal to 400°C, preferably higher than or equal to 150°C and lower than or equal to 300°C. As an exhaust unit provided in the preheating chamber, a cryogenic pump is preferred. This preheating step is not necessarily performed. Before forming the oxide insulating layer 396, this preheating step can be performed in a similar manner on the substrate 394 provided with the gate electrode layer 391 and the gate insulating layer 397. Figure 10C The source electrode layer 395a and the drain electrode layer 395b are shown implemented on a substrate 394.

[0274] Next, an oxide semiconductor film 393 having a thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less, is formed over the gate insulating layer 397 by a sputtering method (see FIG. Figure 10A ).

[0275] Before forming the oxide semiconductor film 393 by sputtering, reverse sputtering in which argon gas is introduced and plasma is generated is preferably performed to remove dust on the surface of the gate insulating layer 397. Reverse sputtering refers to a method in which an RF power source is used to apply a voltage to the substrate side in an argon atmosphere without applying a voltage to the target side to modify the surface. A nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like can be used instead of the argon atmosphere.

[0276] The oxide semiconductor film 393 can be formed using an In-Ga-Zn-O-based oxide semiconductor film, an In-Sn-Zn-O-based oxide semiconductor film, an In-Al-Zn-O-based oxide semiconductor film, a Sn-Ga-Zn-O-based oxide semiconductor film, an Al-Ga-Zn-O-based oxide semiconductor film, a Sn-Al-Zn-O-based oxide semiconductor film, an In-Zn-O-based oxide semiconductor film, a Sn-Zn-O-based oxide semiconductor film, an Al-Zn-O-based oxide semiconductor film, an In-O-based oxide semiconductor film, a Sn-O-based oxide semiconductor film, or a Zn-O-based oxide semiconductor film. In this embodiment, the oxide semiconductor film 393 is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Specifically, a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 (i.e., In:Ga:Zn = 1:1:0.5 [atom %]) is used. Alternatively, a target with a composition ratio of In:Ga:Zn=1:1:1 [atom%] or In:Ga:Zn=1:1:2 [atom%] can be used. In this embodiment, the filling rate of the oxide semiconductor target is greater than or equal to 90% and less than or equal to 100%, preferably greater than or equal to 95% and less than or equal to 99.9%. By using an oxide semiconductor target with a high filling rate, the deposited oxide semiconductor film has a high density. The atmosphere when sputtering the oxide semiconductor film 393 can be a rare gas (usually argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (usually argon) and oxygen. The target may contain greater than or equal to 2wt% and less than or equal to 10wt% of SiO2.

[0277] An oxide semiconductor film 393 is formed on a substrate 394 as follows: the substrate is held in a chamber with a reduced pressure, and the substrate is heated to room temperature or a temperature below 400°C; and residual moisture in the chamber is removed, a sputtering gas that removes hydrogen and moisture is introduced, and the above-mentioned target is used. In order to remove residual moisture in the chamber, an absorption vacuum pump is preferably used. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with an added cold trap can be used as an exhaust unit. In a chamber that is exhausted using a cryogenic pump, hydrogen molecules, compounds including hydrogen atoms (such as water (H2O)), compounds including carbon atoms, etc. are discharged. Therefore, the impurity concentration included in the oxide semiconductor film formed in the chamber can be reduced. The remaining moisture in the chamber is removed by a cryogenic pump during sputtering film deposition, and the substrate temperature during film deposition of the oxide semiconductor film 393 can have a temperature higher than or equal to room temperature and less than 400°C.

[0278] As an example of film deposition conditions, the following conditions are employed: the distance between the substrate and the target is 100 mm; the pressure is 0.6 Pa; the DC power supply is 0.5 kW; and the atmosphere is oxygen (the flow rate ratio of oxygen is 100%). A pulsed DC power supply is preferably used because it can reduce powdery substances (also called particles or dust) generated during film deposition and can make the film thickness uniform.

[0279] Examples of sputtering methods include RF sputtering in which a high-frequency power source is used as a sputtering power source, DC sputtering in which a DC power source is used, and pulsed DC sputtering in which a bias voltage is applied in a pulsed manner. RF sputtering is mainly used when forming an insulating film, while DC sputtering is mainly used when forming a metal film.

[0280] A multi-target sputtering apparatus can be used in which multiple targets formed of different materials can be set. With the multi-target sputtering apparatus, films of different materials to be formed can be stacked in the same chamber, or multiple materials can be deposited simultaneously by discharge in the same chamber.

[0281] Alternatively, a sputtering apparatus that has a magnet system provided inside a chamber and is used for a magnetron sputtering method, or a sputtering apparatus that is used for an ECR sputtering method that uses plasma generated by using microwaves without using glow discharge may be used.

[0282] Furthermore, as a deposition method using sputtering, a reactive sputtering method in which a target substance and a sputtering gas component chemically react with each other during deposition to form a compound thin film thereof, or a bias sputtering method in which a voltage is also applied to a substrate during deposition can be used.

[0283] Next, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 399 (see FIG. 1 ) by a second photolithography step. Figure 10B ). An inkjet method can be used to form a resist mask for forming the island-shaped oxide semiconductor layer 399. Forming a resist mask by an inkjet method does not require a photomask; thus, manufacturing costs can be reduced.

[0284] In the case of forming a contact hole in the gate insulating layer 397 , this step can be performed when the oxide semiconductor layer 399 is formed.

[0285] For etching the oxide semiconductor film 393, one or both of wet etching and dry etching can be employed.

[0286] It is preferable to use a chlorine-containing gas (a chlorine-based gas such as chlorine (Cl 2 ), boron chloride (BCl 3 ), silicon chloride (SiCl 4 ), or carbon tetrachloride (CCl 4 )) as an etching gas for dry etching.

[0287] Alternatively, a fluorine-containing gas (a fluorine-based gas such as carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), or trifluoromethane (CHF3)); hydrogen bromide (HBr); oxygen (O2); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added, etc. may be used.

[0288] As a dry etching method, a parallel plate RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used. In order to etch the layer into a desired shape, the etching conditions (the amount of electric power applied to the coiled electrode, the amount of electric power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted.

[0289] As the wet etching etchant, a mixed solution of phosphoric acid, acetic acid, and nitric acid, an ammonium hydroxide / hydrogen peroxide mixture (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2) can be used. ITO07N (produced by KANTO Chemical Co., Ltd.) can be used.

[0290] After wet etching, the etchant and the etched material are removed by washing. The waste liquid containing the etchant from which the material has been removed can be purified, and the material contained in the waste liquid can be reused. By collecting and reusing the material included in the oxide semiconductor (such as indium) from the waste liquid after etching, resources can be used efficiently and costs can be reduced.

[0291] By appropriately adjusting etching conditions such as an etchant, etching time, or temperature depending on the material, the material can be etched into a desired shape.

[0292] Note that in this case, before forming a conductive film by the following steps, reverse sputtering is preferably performed to remove resist residues and the like from the surfaces of the oxide semiconductor layer 399 and the gate insulating layer 397 .

[0293] Next, a conductive film is formed on the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive film can be formed by sputtering or vacuum evaporation. As the material of the conductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo and W; an alloy containing any one of these elements as a component; an alloy film containing any combination of these elements, etc. can be given. In addition, one or more materials selected from manganese, magnesium, zirconium, beryllium and yttrium can be used. In addition, the conductive film can have a single-layer structure or a stacked structure of more than or equal to two layers. For example, a single-layer structure of an aluminum film including silicon, a double-layer structure in which a titanium film is stacked on the aluminum film, or a three-layer structure in which a Ti film, an aluminum film, and a titanium film are stacked in this order can be given. Alternatively, a film, an alloy film, or a nitride film can be used, which contains aluminum (Al) and one or more elements selected from the following: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

[0294] Next, a resist mask is formed on the conductive film by a third photolithography step. Thereafter, it is selectively etched to form source and drain electrode layers 395a and 395b, and then, the resist mask is removed (see FIG. Figure 10C ).

[0295] Ultraviolet light, KrF laser, or ArF laser can be used for exposure when forming the resist mask in the third photolithography step. The channel length L of the thin film transistor to be formed is determined by the distance between the lower end of the source electrode layer and the lower end of the drain electrode layer, and the source electrode layer and the drain electrode layer are adjacent to each other on the oxide semiconductor layer 399. In the case of exposure for a channel length L less than 25 nm, far ultraviolet light with an extremely short wavelength of several nanometers to tens of nanometers is used for exposure when forming the resist mask in the third photolithography step. When exposed by far ultraviolet light, the resolution is high and the depth of focus is large. Therefore, the channel length L of the thin film transistor can be made greater than or equal to 10 nm and less than or equal to 1000 nm, the operation rate of the circuit can be increased, and low power consumption can be achieved by an extremely small off-state current.

[0296] The oxide semiconductor layer 399 can be partially etched away by etching the conductive film. The material and etching conditions are appropriately controlled so that the oxide semiconductor layer 399 is not removed when the conductive film is etched.

[0297] In this embodiment, since a Ti film is used as a conductive film and an In-Ga-Zn-O-based oxide semiconductor is used as the oxide semiconductor layer 399, an ammonium hydroxide / hydrogen peroxide mixture (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.

[0298] In the third photolithography step, in some cases, a portion of the oxide semiconductor layer 399 is etched, thereby forming an oxide semiconductor layer having a groove (recessed portion). The resist mask for forming the source and drain electrode layers 395a and 395b can be formed by an inkjet method. Forming the resist mask by the inkjet method does not require a photomask; thus, manufacturing costs can be reduced.

[0299] To reduce the number of photomasks and steps in the photolithography process, etching can be performed using a resist mask formed using a multi-tone mask. This multi-tone mask is an exposure mask that transmits light with multiple intensities. Because a resist mask formed using a multi-tone mask has multiple thicknesses and its shape can be further modified by etching, it can be used to provide different patterns in multiple etching steps. Therefore, a resist mask corresponding to at least two different patterns can be formed using a single multi-tone mask. This reduces the number of exposure masks and the corresponding number of photolithography steps, thereby simplifying the manufacturing process.

[0300] After removing the resist mask, plasma treatment using a gas such as N2O, N2, or Ar may be performed to remove water or the like absorbed on the surface of the exposed oxide semiconductor layer 399. The plasma treatment may be performed using a mixed gas of oxygen and argon.

[0301] Next, an oxide insulating layer 396 is formed as an oxide insulating layer serving as a protective insulating layer in contact with part of the oxide semiconductor layer (see Figure 10D When plasma treatment is performed, the oxide insulating layer 396 can be formed continuously after the plasma treatment without exposing the oxide semiconductor layer 399 to air. In this embodiment, the oxide semiconductor layer 399 is in contact with the oxide insulating layer 396 in a region where the oxide semiconductor layer 399 is not in contact with either the source electrode layer 395 a or the drain electrode layer 395 b.

[0302] In this embodiment, as the oxide insulating layer 396, a silicon oxide layer including defects is formed as follows: the substrate 394 on which the island-shaped oxide semiconductor layer 399, the source electrode layer 395a, and the drain electrode layer 395b are formed is heated at a temperature from room temperature to below 100°C; a sputtering gas containing high-purity oxygen that removes hydrogen and moisture is introduced; and a silicon semiconductor target is used.

[0303] For example, in this embodiment, a silicon oxide film is formed as follows: a boron-doped silicon target with a purity of 6N (whose resistivity is 0.01 Ω·cm) is used; the distance between the target and the substrate (TS distance) is 89 mm; the pressure is 0.4 Pa; the direct current (DC) power supply is 6 kW; the atmosphere is oxygen (the oxygen flow rate ratio is 100%); and a pulsed DC sputtering method is used. In this embodiment, the thickness of the silicon oxide film is 300 nm. Quartz (preferably synthetic quartz) can be used instead of the silicon target to form the silicon oxide film.

[0304] In this case, it is preferable to remove residual moisture in the chamber when depositing the oxide insulating layer 396. This is to prevent the oxide semiconductor layer 399 and the oxide insulating layer 396 from containing hydrogen, hydroxyl groups, and / or moisture.

[0305] In order to remove residual moisture in the chamber, an absorption vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with a cold trap can be used as an exhaust unit. In a chamber that is exhausted using a cryopump, hydrogen molecules, compounds containing hydrogen atoms (such as H2O), etc. are exhausted. Therefore, the impurity concentration included in the oxide insulating layer 396 formed in the chamber can be reduced.

[0306] As the oxide insulating layer 396 , a silicon oxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer, or the like can be used instead of the silicon oxide layer.

[0307] Furthermore, after the oxide insulating layer 396 is formed, heat treatment may be performed at 100° C. to 400° C. while the oxide insulating layer 396 is in contact with the oxide semiconductor layer 399. Since the oxide insulating layer 396 in this embodiment includes many defects, impurities (such as hydrogen, moisture, hydroxyl groups, or hydrides) included in the oxide semiconductor layer 399 are diffused into the oxide insulating layer 396 by this heat treatment, thereby further reducing the impurities included in the oxide semiconductor layer 399.

[0308] Through the above-described process, a thin film transistor 390 including an oxide semiconductor layer 392 in which the concentration of hydrogen, moisture, hydroxyl group, and / or hydride is reduced can be formed (see FIG. Figure 10E ).

[0309] By removing residual moisture in the reaction atmosphere during the deposition of the oxide semiconductor film as described above, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced, thereby stabilizing the oxide semiconductor film.

[0310] A protective insulating layer may be provided over the oxide insulating layer. In this embodiment, a protective insulating layer 398 is formed over the oxide insulating layer 396. As the protective insulating layer 398, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like can be used. In this embodiment, the protective insulating layer 398 is formed using a silicon nitride film.

[0311] A silicon nitride film is formed as the protective insulating layer 398 by heating the substrate 394 on which the layers up to and including the oxide insulating layer 396 are formed to a temperature of 100° C. to 400° C., introducing a sputtering gas containing high-purity nitrogen that removes hydrogen and moisture, and using a silicon semiconductor target. In this case as well, it is preferable to remove residual moisture from the process chamber when forming the protective insulating layer 398, as in the case of the oxide insulating layer 396.

[0312] When forming the protective insulating layer 398, the substrate 394 is heated to a temperature of 100° C. to 400° C. during the formation of the protective insulating layer 398. This allows hydrogen and / or moisture contained in the oxide semiconductor layer to diffuse into the oxide insulating layer. In this case, heat treatment after the formation of the oxide insulating layer 396 is not necessarily performed.

[0313] In the case of forming a silicon oxide layer as the oxide insulating layer 396 and stacking a silicon nitride layer as the protective insulating layer 398, the silicon oxide layer and the silicon nitride layer can be formed in the same chamber using a common silicon target. First, an oxygen-containing sputtering gas is introduced and a silicon oxide layer is formed using a silicon target placed inside the chamber; and then, the sputtering gas is switched to a nitrogen-containing sputtering gas and a silicon nitride layer is formed using the same silicon target. Since the silicon oxide layer and the silicon nitride layer can be formed continuously without being exposed to the air, impurities such as hydrogen or moisture can be prevented from being absorbed on the surface of the silicon oxide layer. In this case, after forming the silicon oxide layer as the oxide insulating layer 396 and stacking the silicon nitride layer as the protective insulating layer 398, heat treatment (at a temperature of 100°C to 400°C) for diffusing hydrogen or moisture included in the oxide semiconductor layer into the oxide insulating layer can be performed.

[0314] After forming the protective insulating layer, heat treatment may be performed in air at a temperature of 100° C. or higher and 200° C. or lower for 1 hour or higher and 30 hours or lower. The heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in heating temperature may be repeated multiple times: the heating temperature rises from room temperature to a temperature of 100° C. or higher and 200° C. or lower, and then drops to room temperature. In addition, the heat treatment may be performed under reduced pressure before forming the oxide insulating film. Under reduced pressure, the heat treatment time may be shortened. By this heat treatment, a normally cut-off thin film transistor (whose threshold voltage is positive in the case of an n-channel transistor) may be obtained. Therefore, the reliability of the liquid crystal display device may be improved.

[0315] In addition, by removing moisture in a reaction atmosphere when forming an oxide semiconductor layer (in which a channel formation region is to be formed) over the gate insulating layer, the concentration of hydrogen or hydride in the oxide semiconductor layer can be reduced.

[0316] The above process can be used to manufacture rear panels (substrates on which thin film transistors are formed) of liquid crystal display panels, electroluminescent display panels, display devices using electronic ink, etc. Since the above process is performed at a temperature of 400°C or less, it can be applied to manufacturing processes using glass substrates with a side length of 1 meter or more and a thickness of 1 mm or less. In addition, since the entire process can be performed at a processing temperature of 400°C or less, display panels can be manufactured without consuming too much energy.

[0317] In thin-film transistors using an oxide semiconductor layer fabricated as described above, off-state current can be reduced. Therefore, by using thin-film transistors in each of the multiple pixels in the display portion of a liquid crystal display device, the period during which the voltage is maintained in the storage capacitor can be extended, and power consumption when displaying a still image, etc., in the liquid crystal display device can be reduced. Furthermore, power consumption can be further reduced by stopping the supply of control signals when displaying a still image. Furthermore, switching between still and moving images can be performed without causing any malfunctions.

[0318] Embodiment 5 may be implemented by appropriately combining with any of the structures described in other embodiments.

[0319] (Example 6)

[0320] use Figures 11A to 11E An embodiment of a thin film transistor of this embodiment and a method for manufacturing the thin film transistor will be described.

[0321] In Embodiment 6, another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification will be described. The thin film transistor 310 described in this embodiment can be used as a thin film transistor in each pixel of the pixel portion 1008 described in Embodiment 1.

[0322] Figures 11A to 11E An example of a cross-sectional structure of a thin film transistor is shown. Figures 11A to 11E The thin film transistor 310 shown is a bottom-gate structure, which is also called an inverted staggered thin film transistor.

[0323] Although the thin film transistor 310 is described using a single-gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions may be formed as needed.

[0324] In the following, use Figures 11A to 11EA process for manufacturing the thin film transistor 310 on the substrate 300 will be described.

[0325] First, a conductive film is formed over a substrate 300 having an insulating surface, and then a first photolithography step is performed thereon to form a gate electrode layer 311. Note that the resist mask can be formed by an inkjet method. Forming the resist mask by the inkjet method eliminates the need for a photomask; thus, manufacturing costs can be reduced.

[0326] Although there is no particular limitation on a substrate that can be used as the substrate 300 having an insulating surface, the substrate 300 must at least have heat resistance high enough to withstand heat treatment to be performed later.

[0327] For example, when a glass substrate is used as the substrate 300, if the temperature of the heat treatment to be performed later is high, it is preferable to use a glass substrate having a strain point of 730°C or higher. For example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used as the glass substrate. Note that by containing a larger amount of barium oxide (BaO) than boron oxide, the glass substrate becomes heat-resistant and more practical. Therefore, it is preferable to use a glass substrate containing a larger amount of BaO than B2O3.

[0328] Note that a substrate formed of an insulator such as a ceramic substrate, a quartz glass substrate, or a sapphire substrate may be used instead of a glass substrate as the substrate 300. Alternatively, a crystallized glass substrate or the like may be used.

[0329] An insulating film serving as a base film may be provided between the substrate 300 and the gate electrode layer 311. The base film has a function of preventing impurity elements from diffusing from the substrate 300 and may be formed to have a single-layer structure or a stacked-layer structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.

[0330] The gate electrode layer 311 can be formed to have a single-layer structure or a stacked-layer structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as a main component.

[0331] For example, as a double-layer structure of the gate electrode layer 311, any of the following structures is preferable: a double-layer structure of an aluminum layer and a molybdenum layer stacked on the aluminum layer, a double-layer structure of a copper layer and a molybdenum layer stacked on the copper layer, a double-layer structure of a copper layer and a titanium nitride layer or a tantalum nitride layer stacked on the copper layer, a double-layer structure of a titanium nitride layer and a molybdenum layer, and a double-layer structure of a tungsten nitride layer and a tungsten layer. As a three-layer structure, a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer is preferable.

[0332] Next, a gate insulating layer 302 is formed over the gate electrode layer 311 .

[0333] The gate insulating layer 302 can be formed into a single layer of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or aluminum oxide, or a stack thereof, by plasma CVD, sputtering, or the like. For example, a silicon oxynitride layer can be formed by plasma CVD using SiH4, oxygen, and nitrogen as deposition gases. In this embodiment, the thickness of the gate insulating layer 302 is greater than or equal to 100 nm and less than or equal to 500 nm. In the case of a stacked structure, a first gate insulating layer having a thickness greater than or equal to 50 nm and less than or equal to 200 nm and a second gate insulating layer having a thickness greater than or equal to 5 nm and less than or equal to 300 nm are stacked on the first gate insulating layer.

[0334] In this embodiment, a silicon oxynitride layer is formed to a thickness of 100 nm or less as the gate insulating layer 302 by a plasma CVD method.

[0335] Next, an oxide semiconductor film 330 having a thickness of greater than or equal to 2 nm and less than or equal to 200 nm, preferably greater than or equal to 5 nm and less than or equal to 30 nm, is formed on the gate insulating layer 302 by a sputtering method. Note that the appropriate thickness varies depending on the oxide semiconductor material, and the thickness can be appropriately set depending on the material. The cross-sectional view in this step is Figure 11A .

[0336] Before forming the oxide semiconductor film 330 by a sputtering method, reverse sputtering in which argon gas is introduced and plasma is generated is preferably performed to remove dust on the surface of the gate insulating layer 302. A nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like can be used instead of the argon atmosphere.

[0337] The oxide semiconductor film 330 can be formed using an In-Ga-Zn-O-based oxide semiconductor film, an In-Sn-Zn-O-based oxide semiconductor film, an In-Al-Zn-O-based oxide semiconductor film, a Sn-Ga-Zn-O-based oxide semiconductor film, an Al-Ga-Zn-O-based oxide semiconductor film, a Sn-Al-Zn-O-based oxide semiconductor film, an In-Zn-O-based oxide semiconductor film, a Sn-Zn-O-based oxide semiconductor film, an Al-Zn-O-based oxide semiconductor film, an In-O-based oxide semiconductor film, a Sn-O-based oxide semiconductor film, or a Zn-O-based oxide semiconductor film. In this embodiment, the oxide semiconductor film 330 is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Specifically, a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 (i.e., In:Ga:Zn = 1:1:0.5 [atom %]) is used. Alternatively, a target with a composition ratio of In:Ga:Zn=1:1:1 [atom%] or In:Ga:Zn=1:1:2 [atom%] may be used. In this embodiment, the filling rate of the oxide semiconductor target is greater than or equal to 90% and less than or equal to 100%, preferably greater than or equal to 95% and less than or equal to 99.9%. By using an oxide semiconductor target with a high filling rate, the deposited oxide semiconductor film has a high density. The target may contain greater than or equal to 2wt% and less than or equal to 10wt% SiO2. The atmosphere when sputtering the oxide semiconductor film 330 may be a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen.

[0338] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide semiconductor film 330 .

[0339] Sputtering is performed by holding the substrate in a chamber with a reduced pressure at a substrate temperature of greater than or equal to 100° C. and less than or equal to 600° C., preferably greater than or equal to 200° C. and less than or equal to 400° C. By heating the substrate during film deposition, the concentration of impurities contained in the oxide semiconductor film can be reduced. In addition, damage caused by sputtering can be suppressed. Then, residual moisture in the chamber is removed, a sputtering gas that removes hydrogen and moisture is introduced, and the above-mentioned target is used to form an oxide semiconductor film 330 on the substrate 300. In order to remove residual moisture in the chamber, an absorption vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with an added cold trap can be used as an exhaust unit. In a chamber that is exhausted using a cryopump, hydrogen molecules, compounds including hydrogen atoms (such as water (H2O)), compounds including carbon atoms, etc. are discharged. Therefore, the concentration of impurities included in the oxide semiconductor film formed in the chamber can be reduced.

[0340] As an example of film deposition conditions, the following conditions are employed: the distance between the substrate and the target is 100 mm; the pressure is 0.6 Pa; the DC power supply is 0.5 kW; and the atmosphere is oxygen (the flow rate ratio of oxygen is 100%). A pulsed DC power supply is preferably used because it can reduce powdery substances (also called particles or dust) generated during film deposition and can make the film thickness uniform.

[0341] Next, the oxide semiconductor film 330 is processed into an island-shaped oxide semiconductor layer 331 by a second photolithography step. An inkjet method can be used to form a resist mask for forming the island-shaped oxide semiconductor layer. Forming the resist mask by an inkjet method eliminates the need for a photomask, thereby reducing manufacturing costs.

[0342] Next, the oxide semiconductor layer 331 is subjected to a first heat treatment. The oxide semiconductor layer 331 can be dehydrated or dehydrogenated by the first heat treatment. The temperature of the first heat treatment is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. In this embodiment, the substrate is placed in an electric furnace as a heat treatment device and the oxide semiconductor layer is heat-treated at 450° C. for 1 hour in a nitrogen atmosphere, and then the temperature is lowered to room temperature without being exposed to air and preventing water or hydrogen from entering the oxide semiconductor layer; thereby, the oxide semiconductor layer 331 (see Figure 11B ).

[0343] The heat treatment device is not limited to an electric furnace, and may be provided with a device for heating the object to be treated by heat conduction or heat radiation from a heater such as a resistance heater. For example, an RTA (rapid thermal annealing) device such as a GRTA (gas rapid thermal annealing) device or an LRTA (lamp rapid thermal annealing) device may be used. The LRTA device is a device for heating the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device for performing heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen or a rare gas (such as argon), is used.

[0344] For example, as the first heat treatment, GRTA can be performed as follows: the substrate is transferred into an inert gas heated to a high temperature of 650° C. to 700° C., heated for several minutes, and then transferred out of the inert gas. GRTA achieves high-temperature heat treatment in a short time.

[0345] In the first heat treatment, it is preferred that the nitrogen or rare gas (such as helium, neon, or argon) does not contain water, hydrogen, or the like. The nitrogen or rare gas (such as helium, neon, or argon) introduced into the heat treatment apparatus preferably has a purity of 6N (99.9999%) or greater, more preferably 7N (99.99999%) or greater (i.e., the impurity concentration is preferably 1 ppm or less, more preferably 0.1 ppm or less).

[0346] By the first heat treatment, hydrogen and the like contained in the oxide semiconductor layer 331 can be removed, and oxygen loss can be generated, so that the oxide semiconductor layer 331 becomes an n-type semiconductor (a semiconductor with reduced resistance). In addition, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 331, the oxide semiconductor layer 331 can be crystallized into a microcrystalline film or a polycrystalline film. For example, the oxide semiconductor layer can be crystallized into a microcrystalline oxide semiconductor film in which the crystallinity is greater than or equal to 90%, or greater than or equal to 80%. In addition, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 331, the oxide semiconductor layer 331 can be an amorphous oxide semiconductor film that does not contain a crystalline component. The oxide semiconductor layer 331 can become an oxide semiconductor film in which a microcrystalline portion (whose grain size is greater than or equal to 1 nm and less than or equal to 20 nm, typically greater than or equal to 2 nm and less than or equal to 4 nm) is mixed into the amorphous oxide semiconductor.

[0347] Similarly, the oxide semiconductor film 330 may be subjected to first heat treatment of the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer 331. In this case, the substrate is removed from the heating apparatus after the first heat treatment and then subjected to a photolithography step.

[0348] Heat treatment for dehydration and / or dehydrogenation may be performed after stacking the source electrode and the drain electrode on the oxide semiconductor layer or after forming a protective insulating film on the source electrode and the drain electrode, as long as it is performed after depositing the oxide semiconductor layer.

[0349] In the case of forming a contact hole in the gate insulating layer 302 , this step may be performed before or after heat treatment for dehydration and / or dehydrogenation is performed on the oxide semiconductor film 330 or the oxide semiconductor layer 331 .

[0350] For etching the oxide semiconductor film, wet etching and dry etching can be used.

[0351] By appropriately adjusting etching conditions such as an etchant, etching time, or temperature depending on the material, the material can be etched into a desired shape.

[0352] Next, a conductive film is formed over the gate insulating layer 302 and the oxide semiconductor layer 331. The conductive film can be formed by sputtering or vacuum evaporation. As the material of the conductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W; an alloy containing any one of these elements as a component; an alloy film containing any combination of these elements, etc. can be given. In addition, one or more materials selected from manganese, magnesium, zirconium, beryllium, and yttrium can be used. In addition, the conductive film can have a single-layer structure or a stacked-layer structure of two or more layers. For example, a single-layer structure of an aluminum film including silicon, a double-layer structure in which a titanium film is stacked on the aluminum film, or a three-layer structure in which a Ti film, an aluminum film, and a titanium film are stacked in this order can be given. Alternatively, a film, an alloy film, or a nitride film can be used, which contains aluminum (Al) and one or more elements selected from the following: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

[0353] In the case where heat treatment is performed after the conductive film is deposited, it is preferred that the conductive film have heat resistance high enough to withstand the heat treatment.

[0354] Next, a resist mask is formed on the conductive film by a third photolithography step. Thereafter, it is selectively etched to form source and drain electrode layers 315a and 315b, and then, the resist mask is removed (see FIG. Figure 11C ).

[0355] Ultraviolet light, KrF laser, or ArF laser can be used for exposure when forming the resist mask in the third photolithography step. The channel length L of the thin film transistor to be formed is determined by the distance between the lower end of the source electrode layer and the lower end of the drain electrode layer, and the source electrode layer and the drain electrode layer are adjacent to each other on the oxide semiconductor layer 331. In the case of exposure for a channel length L less than 25 nm, extreme ultraviolet light with an extremely short wavelength of several nanometers to tens of nanometers is used for exposure when forming the resist mask in the third photolithography step. When exposed by extreme ultraviolet light, the resolution is high and the depth of focus is large. Therefore, the channel length L of the thin film transistor can be made greater than or equal to 10 nm and less than or equal to 1000 nm, the operating rate of the circuit can be increased, and low power consumption can be achieved by an extremely small off-state current.

[0356] The material and etching conditions are appropriately controlled so that the oxide semiconductor layer 331 is not removed when the conductive film is etched.

[0357] In this embodiment, since a Ti film is used as a conductive film and an In-Ga-Zn-O-based oxide semiconductor is used as the oxide semiconductor layer 331, an ammonium hydroxide / hydrogen peroxide mixture (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.

[0358] In the third photolithography step, in some cases, a portion of the oxide semiconductor layer 331 is etched, thereby forming an oxide semiconductor layer having a groove (recessed portion). The resist mask for forming the source and drain electrode layers 315a and 315b can be formed by an inkjet method. Forming the resist mask by the inkjet method does not require a photomask; thus, manufacturing costs can be reduced.

[0359] In addition, an oxide conductive layer may be formed between the oxide semiconductor layer and the source and drain electrode layers. The oxide conductive layer and the metal layer used to form the source and drain electrode layers may be formed continuously. The oxide conductive layer may serve as the source and drain regions.

[0360] By providing an oxide conductive layer as a source region and a drain region between the oxide semiconductor layer and the source and drain electrode layers, the resistance of the source and drain regions can be reduced, and the transistor can be operated at high speed.

[0361] To reduce the number of photomasks and steps in the photolithography process, etching can be performed using a resist mask formed using a multi-tone mask. This multi-tone mask is an exposure mask that transmits light with multiple intensities. Because a resist mask formed using a multi-tone mask has multiple thicknesses and its shape can be further modified by etching, it can be used to provide different patterns in multiple etching steps. Therefore, a resist mask corresponding to at least two different patterns can be formed using a single multi-tone mask. This reduces the number of exposure masks and the corresponding number of photolithography steps, thereby simplifying the manufacturing process.

[0362] Next, plasma treatment using a gas such as N2O, N2, or Ar may be performed to remove water or the like absorbed on the surface of the exposed oxide semiconductor layer. The plasma treatment may be performed using a mixed gas of oxygen and argon.

[0363] After the plasma treatment, the oxide insulating layer 316 which functions as a protective insulating film and is in contact with part of the oxide semiconductor layer is formed without being exposed to air.

[0364] The oxide insulating layer 316 can be formed to a thickness of at least 1 nm by a method (such as a sputtering method) that prevents impurities such as water or hydrogen from entering the oxide insulating layer 316. When hydrogen is contained in the oxide insulating layer 316, hydrogen may enter the oxide semiconductor layer or hydrogen may extract oxygen from the oxide semiconductor layer, thereby causing the back channel of the oxide semiconductor layer to become n-type (lowering its resistance), thereby forming a parasitic channel. Therefore, it is important to adopt a formation method that minimizes the use of hydrogen so that the oxide insulating layer 316 contains as little hydrogen as possible.

[0365] In this embodiment, a 200 nm thick silicon oxide film is deposited as the oxide insulating layer 316 by sputtering. The substrate temperature during film deposition may be higher than or equal to room temperature and lower than or equal to 300° C., and is 100° C. in this embodiment. The silicon oxide film can be formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas and oxygen. A silicon oxide target or a silicon target can be used as a target. For example, by using a silicon target, silicon oxide can be deposited by sputtering in an atmosphere of oxygen and nitrogen. Using an atmosphere that does not contain gases such as moisture, hydrogen ions, and OH - The oxide insulating layer 316 is formed in contact with the oxide semiconductor layer having reduced resistance and is an inorganic insulating film that removes impurities such as α-H and blocks the entry of these impurities from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0366] In this case, it is preferable to remove residual moisture in the chamber when depositing the oxide insulating layer 316. This is to prevent the oxide semiconductor layer 331 and the oxide insulating layer 316 from containing hydrogen, hydroxyl groups, or moisture.

[0367] In order to remove residual moisture from the chamber, an adsorption type vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with a cold trap can be used as an exhaust unit. In the chamber that is exhausted by using a cryopump, for example, hydrogen molecules, compounds containing hydrogen atoms (such as H2O), etc. are exhausted. Therefore, the impurity concentration included in the oxide insulating layer 316 formed in the chamber can be reduced.

[0368] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl, or hydride are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide insulating layer 316 .

[0369] Next, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere (preferably at a temperature of 200° C. or higher and 400° C. or lower, for example, at a temperature of 250° C. or higher and 350° C. or lower). For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. By the second heat treatment, heat is applied while a portion of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 316.

[0370] Through the above process, the deposited oxide semiconductor film is subjected to a heat treatment for dehydration and / or dehydrogenation to reduce resistance, and then, a portion of the oxide semiconductor film is selectively made to include excess oxygen. As a result, the channel formation region 313 overlapping with the gate electrode layer 311 becomes i-type, and a high-resistance source region 314a formed of a low-resistance oxide semiconductor and overlapping with the source electrode layer 315a, and a high-resistance drain region 314b formed of a low-resistance oxide semiconductor and overlapping with the drain electrode layer 315b are formed in a self-aligned manner. Through the above steps, the thin film transistor 310 (see Figure 11D ).

[0371] Furthermore, heat treatment may be performed in air at a temperature of 100°C or higher and 200°C or lower for 1 hour or higher and 30 hours or lower. In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in heating temperature may be repeated multiple times: the heating temperature is increased from room temperature to a temperature of 100°C or higher and 200°C or lower, and then decreased to room temperature. Furthermore, this heat treatment may be performed under reduced pressure before forming the oxide insulating film. Under reduced pressure, the heat treatment time can be shortened. Through this heat treatment, hydrogen is introduced from the oxide semiconductor layer into the oxide insulating layer; thereby, a normally-off thin film transistor can be obtained. Therefore, the reliability of the liquid crystal display device can be improved. Furthermore, by using a silicon oxide layer containing many defects as the oxide insulating layer, impurities contained in the oxide semiconductor layer (such as hydrogen, moisture, hydroxyl groups, or hydrides) are diffused into the oxide insulating layer through heat treatment, thereby further reducing the impurities contained in the oxide semiconductor layer.

[0372] A high-resistance drain region 314b (or a high-resistance source region 314a) is formed in a portion where the oxide semiconductor layer overlaps the drain electrode layer 315b (or the source electrode layer 315a), thereby increasing the reliability of the thin film transistor. Specifically, by forming the high-resistance drain region 314b, conductivity can gradually change from the drain electrode layer 315b to the high-resistance drain region 314b and the channel formation region 313 in the transistor. Therefore, in the case where the thin film transistor operates using the drain electrode layer 315b connected to the wiring for supplying a high power supply potential VDD, the high-resistance drain region serves as a buffer zone, and even if a high electric field is applied between the gate electrode layer 311 and the drain electrode layer 315b, a high electric field is not locally applied, thereby improving the withstand voltage of the transistor.

[0373] When the oxide semiconductor layer is as thin as less than or equal to 15 nm, a high-resistance source region and a high-resistance drain region can be formed at all depths in the oxide semiconductor layer in the film thickness direction; and when the oxide semiconductor layer is as thick as greater than or equal to 30 nm and less than or equal to 50 nm, the resistance of each portion (i.e., each region) of the oxide semiconductor layer in contact with the source electrode layer and the drain electrode layer and the vicinity thereof can be reduced, thereby forming a high-resistance source region and a high-resistance drain region, and the region of the oxide semiconductor layer close to the gate insulating layer can be made i-type.

[0374] A protective insulating layer can be formed on the oxide insulating layer 316. For example, a silicon nitride film is formed by RF sputtering. RF sputtering is preferred as a method for forming the protective insulating layer because it has high productivity. As the protective insulating layer, a film that does not contain materials such as moisture, hydrogen ions, and OH is used. -An inorganic insulating film that can remove impurities such as impurities and prevent them from entering from the outside; a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like is used. In this embodiment, a silicon nitride film is used to form the protective insulating layer 303 as the protective insulating layer (see Figure 11E ).

[0375] In this embodiment, a silicon nitride film is formed as the protective insulating layer 303 by heating the substrate 300 on which the layers up to and including the oxide insulating layer 316 are formed to a temperature of 100° C. to 400° C., introducing a sputtering gas containing high-purity nitrogen that removes hydrogen and moisture, and using a silicon semiconductor target. In this case as well, it is preferable to remove residual moisture from the process chamber when forming the protective insulating layer 303, as in the case of the oxide insulating layer 316.

[0376] A planarization insulating layer for planarization may be provided on the protective insulating layer 303 .

[0377] In each of the multiple pixels in the display portion of a liquid crystal display device employing a thin-film transistor using an oxide semiconductor layer as described above, off-state current can be reduced. Consequently, the period during which the voltage is maintained in the storage capacitor can be extended, and power consumption when displaying a still image, etc., in the liquid crystal display device can be reduced. Furthermore, power consumption can be further reduced by stopping the supply of control signals when displaying a still image. Furthermore, switching between still and moving images can be performed without causing any malfunctions.

[0378] Embodiment 6 may be implemented by appropriately combining with any of the structures described in other embodiments.

[0379] (Example 7)

[0380] use Figures 12A to 12D An embodiment of a thin film transistor of this embodiment and a method for manufacturing the thin film transistor will be described.

[0381] In Embodiment 7, another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification will be described. The thin film transistor 360 described in this embodiment can be used as a thin film transistor in each pixel of the pixel portion 1008 described in Embodiment 1.

[0382] Figures 12A to 12D An example of a cross-sectional structure of a thin film transistor is shown. Figures 12A to 12D The illustrated thin film transistor 360 is a bottom-gate structure called a channel protection structure (also called a channel blocking structure), and is also called an inverted staggered thin film transistor.

[0383] Although the thin film transistor 360 is described using a single-gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions can be formed as needed.

[0384] In the following, use Figures 12A to 12D A process for manufacturing the thin film transistor 360 on the substrate 320 will be described.

[0385] First, a conductive film is formed over a substrate 320 having an insulating surface. A first photolithography step is performed to form a resist mask. The conductive film is selectively etched using the resist mask to form a gate electrode layer 361. The resist mask is then removed. Note that the resist mask can be formed using an inkjet method. Forming the resist mask using an inkjet method eliminates the need for a photomask, thereby reducing manufacturing costs.

[0386] The gate electrode layer 361 can be formed to have a single-layer structure or a stacked-layer structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as a main component.

[0387] Next, a gate insulating layer 322 is formed over the gate electrode layer 361 .

[0388] In this embodiment, a silicon oxynitride layer is formed to a thickness of less than or equal to 100 nm as the gate insulating layer 322 by a plasma CVD method.

[0389] Next, an oxide semiconductor film having a thickness of greater than or equal to 2 nm and less than or equal to 200 nm is formed over the gate insulating layer 322 and processed by a second photolithography step into an island-shaped oxide semiconductor layer 332. In this embodiment, the oxide semiconductor film is formed by a sputtering method using an In—Ga—Zn—O-based oxide semiconductor target.

[0390] In this case, it is preferable to remove residual moisture in the chamber during the deposition of the oxide semiconductor film in order to prevent the oxide insulating film from containing hydrogen, hydroxyl groups, or moisture.

[0391] In order to remove residual moisture from the chamber, an adsorption type vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with a cold trap can be used as an exhaust unit. In the chamber that is exhausted by using a cryopump, for example, hydrogen molecules, compounds containing hydrogen atoms (such as H2O), etc. are exhausted. Therefore, the impurity concentration included in the oxide semiconductor film formed in the chamber can be reduced.

[0392] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide semiconductor film.

[0393] Next, dehydration and / or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration and / or dehydrogenation is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. In this embodiment, the substrate is placed in an electric furnace as a heat treatment device and the oxide semiconductor layer is heat-treated at 450° C. for 1 hour in a nitrogen atmosphere, and then, water or hydrogen is prevented from entering the oxide semiconductor layer without being exposed to air; thereby, the oxide semiconductor layer 332 (see Figure 12A ).

[0394] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar. This plasma treatment removes water and the like absorbed on the surface of the exposed oxide semiconductor layer. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0395] Next, an oxide insulating layer is formed over the gate insulating layer 322 and the oxide semiconductor layer 332. After that, a resist mask is formed by a third photolithography step and selectively etched, thereby forming the oxide insulating layer 366. Thereafter, the resist mask is removed.

[0396] In this embodiment, a 200 nm thick silicon oxide film is deposited as the oxide insulating layer 366 by sputtering. The substrate temperature during film deposition may be higher than or equal to room temperature and lower than or equal to 300° C., and is 100° C. in this embodiment. A silicon oxide film can be formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas and oxygen. A silicon oxide target or a silicon target can be used as a target. For example, by using a silicon target, silicon oxide can be deposited by sputtering in an atmosphere of oxygen and nitrogen. Using an atmosphere that does not contain gases such as moisture, hydrogen ions, and OH groups, it is not advisable to deposit silicon oxide by sputtering. - The oxide insulating layer 366 is formed in contact with the oxide semiconductor layer and is an inorganic insulating film that removes impurities such as α-H and blocks the entry of these impurities from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0397] In this case, it is preferable to remove residual moisture in the chamber when depositing the oxide insulating layer 366. This is to prevent the oxide semiconductor layer 332 and the oxide insulating layer 366 from containing hydrogen, hydroxyl groups, or moisture.

[0398] In order to remove residual moisture from the chamber, an adsorption type vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with a cold trap can be used as an exhaust unit. In the chamber that is exhausted by using a cryopump, for example, hydrogen molecules, compounds containing hydrogen atoms (such as H2O), etc. are exhausted. Therefore, the impurity concentration included in the oxide semiconductor film formed in the chamber can be reduced.

[0399] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide semiconductor film.

[0400] Next, second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere (preferably at a temperature of 200° C. or higher and 400° C. or lower, for example, at a temperature of 250° C. or higher and 350° C. or lower). For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. By the second heat treatment, heat is applied while a portion of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 366.

[0401] In this embodiment, the oxide semiconductor layer 332, which is partially exposed and provided with the oxide insulating layer 366, is further subjected to heat treatment in a nitrogen atmosphere or an inert gas atmosphere, or under reduced pressure. Heat treatment in a nitrogen atmosphere or an inert gas atmosphere, or under reduced pressure, can reduce the resistance of the exposed region of the oxide semiconductor layer 332 that is not covered by the oxide insulating layer 366. For example, heat treatment is performed at 250° C. for one hour in a nitrogen atmosphere.

[0402] By heat treatment of the oxide semiconductor layer 332 provided with the oxide insulating layer 366 in a nitrogen atmosphere, the resistance of the exposed region of the oxide semiconductor layer 332 is reduced, thereby forming a region including different resistances (indicated by Figure 12B 3. The oxide semiconductor layer 362 includes the shaded area and the white area in FIG.

[0403] Next, a conductive film is formed over the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. Thereafter, a resist mask is formed by a fourth photolithography step and selectively etched to form a source electrode layer 365a and a drain electrode layer 365b. Thereafter, the resist mask is removed (see Figure 12C ).

[0404] The source electrode layer 365a and the drain electrode layer 365b are each formed using an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy including any one of the above elements as a component, an alloy film including a combination of any one of these elements, or the like. A single-layer structure or a stacked-layer structure including two or more layers can be used as the conductive film.

[0405] Through the above process, excess oxygen is selectively added to a portion of the oxide semiconductor film. Consequently, the channel formation region 363 overlapping the gate electrode layer 361 becomes i-type, and a high-resistance source region 364a overlapping the source electrode layer 365a and a high-resistance drain region 364b overlapping the drain electrode layer 365b are formed in a self-aligned manner. Through the above steps, the thin film transistor 360 is formed.

[0406] In addition, heat treatment may be performed in air at a temperature of 100°C or higher and 200°C or lower for 1 hour or higher and 30 hours or lower. In the present embodiment, heat treatment is performed at 150°C for 10 hours. The heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in heating temperature may be repeated multiple times: the heating temperature is increased from room temperature to a temperature of 100°C or higher and 200°C or lower, and then decreased to room temperature. In addition, the heat treatment may be performed under reduced pressure before the oxide insulating film is formed. Under reduced pressure, the heat treatment time can be shortened. Through the heat treatment, hydrogen is introduced from the oxide semiconductor layer into the oxide insulating layer; thereby, a normally-off thin film transistor can be obtained. Therefore, the reliability of the liquid crystal display device can be improved.

[0407] A high-resistance drain region 364b (or a high-resistance source region 364a) is formed in a portion where the oxide semiconductor layer overlaps the drain electrode layer 365b (or the source electrode layer 365a), thereby increasing the reliability of the thin film transistor. Specifically, by forming the high-resistance drain region 364b, conductivity can gradually change from the drain electrode layer 365b to the high-resistance drain region 364b and the channel formation region 363 in the transistor. Therefore, when the thin film transistor operates using the drain electrode layer 365b connected to the wiring for supplying a high power supply potential VDD, the high-resistance drain region serves as a buffer zone, and even if a high electric field is applied between the gate electrode layer 361 and the drain electrode layer 315b, a high electric field is not locally applied, thereby improving the withstand voltage of the transistor.

[0408] A protective insulating layer 323 is formed over the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film (see FIG. Figure 12D ).

[0409] An oxide insulating layer may be formed over the source electrode layer 362 a , the drain electrode layer 365 b , and the oxide insulating layer 366 , and a protective insulating layer 323 may be stacked over the oxide insulating layer.

[0410] In each of the multiple pixels in the display portion of a liquid crystal display device employing a thin-film transistor using an oxide semiconductor layer as described above, off-state current can be reduced. Consequently, the period during which the voltage is maintained in the storage capacitor can be extended, and power consumption when displaying a still image, etc., in the liquid crystal display device can be reduced. Furthermore, power consumption can be further reduced by stopping the supply of control signals when displaying a still image. Furthermore, switching between still and moving images can be performed without causing any malfunctions.

[0411] Embodiment 7 can be implemented by appropriately combining with any of the structures described in other embodiments.

[0412] (Example 8)

[0413] In Embodiment 8, another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification will be described. The thin film transistor 350 described in this embodiment can be used as a thin film transistor in each pixel of the pixel portion 1008 described in Embodiment 1.

[0414] use Figures 13A to 13D An embodiment of a thin film transistor of this embodiment and a method for manufacturing the thin film transistor will be described.

[0415] Although the thin film transistor 350 is described using a single-gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions may be formed as needed.

[0416] In the following, use Figures 13A to 13D A process for manufacturing the thin film transistor 350 on the substrate 340 will be described.

[0417] First, a conductive film is formed over a substrate 340 having an insulating surface and a first photolithography step is performed to form a gate electrode layer 351. In this embodiment, a 150 nm thick tungsten film is formed as the gate electrode layer 351 by a sputtering method.

[0418] Next, the gate insulating layer 342 is formed over the gate electrode layer 351. In this embodiment, a silicon oxynitride layer is formed to a thickness of 100 nm or less as the gate insulating layer 342 by a plasma CVD method.

[0419] Next, a conductive film is formed over the gate insulating layer 342 and a resist mask is formed over the conductive film by a second photolithography step, and selective etching is performed thereon to form a source electrode layer 355a and a drain electrode layer 355b. Thereafter, the resist mask is removed (see FIG. Figure 13A ).

[0420] Next, an oxide semiconductor film 345 is formed (see Figure 13BIn this embodiment, the oxide semiconductor film 345 is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. The oxide semiconductor film 345 is processed into an island-shaped oxide semiconductor layer by a third photolithography step.

[0421] In this case, it is preferable to remove residual moisture in the chamber when depositing the oxide semiconductor film 345. This is to prevent the oxide semiconductor film 345 from containing hydrogen, hydroxyl groups, or moisture.

[0422] In order to remove residual moisture from the chamber, an adsorption type vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with a cold trap can be used as an exhaust unit. In the chamber that is exhausted by using a cryopump, for example, hydrogen molecules, compounds containing hydrogen atoms (such as H2O), etc. are exhausted. Therefore, the impurity concentration included in the oxide semiconductor film 345 formed in the chamber can be reduced.

[0423] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide semiconductor film 345 .

[0424] Next, dehydration and / or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration and / or dehydrogenation is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. In this embodiment, the substrate is placed in an electric furnace as a heat treatment device and the oxide semiconductor layer is heat-treated at 450° C. for 1 hour in a nitrogen atmosphere, and then, water or hydrogen is prevented from entering the oxide semiconductor layer without being exposed to air; thereby, the oxide semiconductor layer 346 (see Figure 13C ).

[0425] For example, as the first heat treatment, GRTA can be performed as follows: the substrate is transferred into an inert gas heated to a high temperature of 650° C. to 700° C., heated for several minutes, and then transferred out of the inert gas. GRTA achieves high-temperature heat treatment in a short time.

[0426] Next, the oxide insulating layer 356 serving as a protective insulating film is formed in contact with the oxide semiconductor layer 346 .

[0427] The oxide insulating layer 356 can be formed to a thickness of at least 1 nm by a method (such as a sputtering method) that prevents impurities such as water or hydrogen from entering the oxide insulating layer 356. When hydrogen is contained in the oxide insulating layer 356, hydrogen may enter the oxide semiconductor layer or hydrogen may extract oxygen from the oxide semiconductor layer, thereby causing the back channel of the oxide semiconductor layer to become n-type (low in resistance), thereby forming a parasitic channel. Therefore, it is important to adopt a formation method that uses as little hydrogen as possible so that the oxide insulating layer 356 contains as little hydrogen as possible.

[0428] In this embodiment, a 200 nm thick silicon oxide film is deposited as the oxide insulating layer 356 by sputtering. The substrate temperature during film deposition may be higher than or equal to room temperature and lower than or equal to 300° C., and is 100° C. in this embodiment. A silicon oxide film can be formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas and oxygen. A silicon oxide target or a silicon target can be used as a target. For example, by using a silicon target, silicon oxide can be deposited by sputtering in an atmosphere of oxygen and nitrogen. Using an atmosphere that does not contain gases such as moisture, hydrogen ions, and OH groups, it is not advisable to deposit silicon oxide by sputtering. - The oxide insulating layer 356 is formed in contact with the oxide semiconductor layer and is an inorganic insulating film that removes impurities such as α-H and blocks the entry of these impurities from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0429] In this case, it is preferable to remove residual moisture in the chamber when depositing the oxide insulating layer 356. This is to prevent the oxide semiconductor layer 346 and the oxide insulating layer 356 from containing hydrogen, hydroxyl groups, or moisture.

[0430] In order to remove residual moisture from the chamber, an adsorption type vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with a cold trap can be used as an exhaust unit. In the chamber that is exhausted by using a cryopump, for example, hydrogen molecules, compounds containing hydrogen atoms (such as H2O), etc. are exhausted. Therefore, the impurity concentration included in the oxide insulating layer 356 formed in the chamber can be reduced.

[0431] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl, or hydride are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide insulating layer 356 .

[0432] Next, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere (preferably at a temperature of 200° C. or higher and 400° C. or lower, for example, at a temperature of 250° C. or higher and 350° C. or lower). For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. By the second heat treatment, heat is applied while a portion of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 356.

[0433] Through the above process, the oxide semiconductor film selectively contains excess oxygen, thereby forming the i-type oxide semiconductor layer 352. Through the above steps, the thin film transistor 350 is formed.

[0434] In addition, heat treatment may be performed in air at a temperature of 100°C or higher and 200°C or lower for 1 hour or higher and 30 hours or lower. In the present embodiment, heat treatment is performed at 150°C for 10 hours. The heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in heating temperature may be repeated multiple times: the heating temperature is increased from room temperature to a temperature of 100°C or higher and 200°C or lower, and then decreased to room temperature. In addition, the heat treatment may be performed under reduced pressure before the oxide insulating film is formed. Under reduced pressure, the heat treatment time can be shortened. Through the heat treatment, hydrogen is introduced from the oxide semiconductor layer into the oxide insulating layer; thereby, a normally-off thin film transistor can be obtained. Therefore, the reliability of the liquid crystal display device can be improved.

[0435] A protective insulating layer can be formed over the oxide insulating layer 356. For example, a silicon nitride film is formed by an RF sputtering method. In this embodiment, the protective insulating layer 343 is formed using a silicon nitride film as the protective insulating layer (see Figure 13D ).

[0436] A planarization insulating layer for planarization may be provided on the protective insulating layer 343 .

[0437] In thin-film transistors using an oxide semiconductor layer fabricated as described above, off-state current can be reduced. Therefore, by using thin-film transistors in each of the multiple pixels in the display portion of a liquid crystal display device, the period during which the voltage is maintained in the storage capacitor can be extended, and power consumption when displaying a still image, etc., in the liquid crystal display device can be reduced. Furthermore, power consumption can be further reduced by stopping the supply of control signals when displaying a still image. Furthermore, switching between still and moving images can be performed without causing any malfunctions.

[0438] Embodiment 8 can be implemented by appropriately combining with any of the structures described in other embodiments.

[0439] (Example 9)

[0440] In Example 9, we will use Figure 14 An example of a manufacturing process of a thin film transistor that is different from that of embodiment 6 is described below. Figure 14 Except for some steps Figures 11A to 11E The same components are identical, so the same reference numerals are used for the same components, and the detailed description of the same components will not be repeated.

[0441] In Embodiment 9, another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification will be described. The thin film transistor 380 described in this embodiment can be used as a thin film transistor in each pixel of the pixel portion 1008 described in Embodiment 1.

[0442] According to Embodiment 6, a gate electrode layer 381 is formed on a substrate 370, and a first gate insulating layer 372a and a second gate insulating layer 372b are stacked. In this embodiment, the gate insulating layer has a double-layer structure in which a nitride insulating layer is used as the first gate insulating layer 372a, and an oxide insulating layer is used as the second gate insulating layer 372b.

[0443] As the oxide insulating layer, a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer, etc. can be used. As the nitride insulating layer, a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, an aluminum nitride oxide layer, etc. can be used.

[0444] In this embodiment, the gate insulating layer has a structure in which a silicon nitride layer and a silicon oxide layer are stacked in this order on the gate electrode layer 381. For example, a 150 nm thick gate insulating layer is formed as follows: a silicon nitride layer (SiN2O3) having a thickness of greater than or equal to 50 nm and less than or equal to 200 nm is formed by a sputtering method. y (y>0)) as the first gate insulating layer 372a, and then a silicon oxide layer (SiO) having a thickness greater than or equal to 5 nm and less than or equal to 300 nm (100 nm in this embodiment) is stacked on the first gate insulating layer 372a. x (x>0)) as the second gate insulating layer 372b.

[0445] Next, an oxide semiconductor film is formed and processed into an island-shaped oxide semiconductor layer by a photolithography step. In this embodiment, the oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target.

[0446] In this case, it is preferable to remove residual moisture in the chamber when depositing the oxide insulating film in order to prevent the oxide semiconductor film from containing hydrogen, hydroxyl groups, or moisture.

[0447] In order to remove residual moisture from the chamber, an adsorption type vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with a cold trap can be used as an exhaust unit. In the chamber that is exhausted by using a cryopump, for example, hydrogen molecules, compounds containing hydrogen atoms (such as H2O), etc. are exhausted. Therefore, the impurity concentration included in the oxide semiconductor film formed in the chamber can be reduced.

[0448] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide semiconductor film.

[0449] Next, dehydration and / or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is higher than or equal to 400°C and lower than or equal to 750°C, preferably higher than or equal to 425°C. The heat treatment time is shorter than or equal to 1 hour at a temperature higher than or equal to 425°C, and longer than 1 hour at a temperature lower than 425°C. In this embodiment, the substrate is placed in an electric furnace as a heat treatment device and the oxide semiconductor layer is heat-treated in a nitrogen atmosphere, and then, water or hydrogen is prevented from entering the oxide semiconductor layer without being exposed to the air; thereby, the oxide semiconductor layer is obtained. Thereafter, cooling is performed by introducing high-purity oxygen, high-purity N2O gas, or ultra-dry air (having a dew point lower than or equal to -40°C, preferably lower than or equal to -60°C) into the same furnace. Preferably, the oxygen and N2O gases do not contain water, hydrogen, etc. Alternatively, the purity of the oxygen or N2O gas introduced into the heat treatment device is preferably higher than or equal to 6N (99.9999%), more preferably higher than or equal to 7N (99.99999%) (i.e., the impurity concentration of the oxygen gas or N2O gas is preferably lower than or equal to 1ppm, more preferably lower than or equal to 0.1ppm).

[0450] The heat treatment device is not limited to an electric furnace. For example, an RTA (rapid thermal annealing) device such as a GRTA (gas rapid thermal annealing) device or an LRTA (lamp rapid thermal annealing) device can be used. The LRTA device is a device for heating the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The LRTA device can be provided with not only a lamp, but also a device for heating the object to be treated by heat conduction or heat radiation from a heater (such as a resistance heater). GRTA is a method for performing heat treatment using a high-temperature gas. An inert gas (such as nitrogen or a rare gas (such as argon)) that does not react with the object to be treated by the heat treatment is used as the gas. The RTA method can be used to perform heat treatment at 600°C to 750°C for several minutes.

[0451] After the first heat treatment for dehydration and / or dehydrogenation, heat treatment may be performed in an oxygen atmosphere or an N2O gas atmosphere at a temperature higher than or equal to 200°C and lower than or equal to 400°C, preferably higher than or equal to 200°C and lower than or equal to 300°C.

[0452] Alternatively, the oxide semiconductor film may be subjected to first heat treatment of the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer. In this case, the substrate is removed from the heating apparatus after the first heat treatment and then subjected to a photolithography step.

[0453] Through the above steps, the entire oxide semiconductor film contains excess oxygen, so that the oxide semiconductor film has higher resistance, that is, becomes i-type. Therefore, the entire oxide semiconductor layer 382 is formed to be i-type.

[0454] Next, a resist mask is formed over the oxide semiconductor layer 382 by a photolithography step, and etching is selectively performed to form a source electrode layer 385 a and a drain electrode layer 385 b , and then an oxide insulating layer 386 is formed by a sputtering method.

[0455] In this case, it is preferable to remove residual moisture in the chamber when depositing the oxide insulating layer 386. This is to prevent the oxide semiconductor layer 382 and the oxide insulating layer 386 from containing hydrogen, hydroxyl groups, and / or moisture.

[0456] In order to remove residual moisture in the chamber, an absorption vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. A turbomolecular pump with a cold trap can be used as an exhaust unit. In a chamber that is exhausted using a cryopump, hydrogen molecules, compounds containing hydrogen atoms (such as H2O), etc. are exhausted. Therefore, the impurity concentration included in the oxide insulating layer 386 formed in the chamber can be reduced.

[0457] It is preferable that a high-purity gas in which impurities such as hydrogen, water, hydroxyl, or hydride are removed to 1 ppm or less, preferably 10 ppb or less is used as a sputtering gas for depositing the oxide insulating layer 386 .

[0458] Through the above steps, the thin film transistor 380 can be manufactured.

[0459] Next, heat treatment may be performed in an inert gas atmosphere or a nitrogen atmosphere (preferably at a temperature higher than or equal to 150°C and lower than 350°C) to suppress changes in the electrical characteristics of the thin film transistor. For example, heat treatment may be performed at 250°C for 1 hour in a nitrogen atmosphere.

[0460] In addition, heat treatment may be performed in air at a temperature of 100°C or higher and 200°C or lower for 1 hour or higher and 30 hours or lower. In the present embodiment, heat treatment is performed at 150°C for 10 hours. The heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in heating temperature may be repeated multiple times: the heating temperature is increased from room temperature to a temperature of 100°C or higher and 200°C or lower, and then decreased to room temperature. In addition, the heat treatment may be performed under reduced pressure before the oxide insulating film is formed. Under reduced pressure, the heat treatment time can be shortened. Through the heat treatment, hydrogen is introduced from the oxide semiconductor layer into the oxide insulating layer; thereby, a normally-off thin film transistor can be obtained. Therefore, the reliability of the liquid crystal display device can be improved.

[0461] A protective insulating layer 373 is formed over the oxide insulating layer 386. In this embodiment, a 100-nm-thick silicon nitride film is formed as the protective insulating layer 373 by a sputtering method.

[0462] The protective insulating layer 373 and the first gate insulating layer 372a, which are nitride insulating layers, do not contain impurities such as moisture, hydrogen, hydride, or hydroxide, and prevent them from entering from the outside.

[0463] Therefore, in the manufacturing process after forming the protective insulating layer 373, impurities such as moisture can be prevented from entering from the outside. In addition, even after the device is completed as a semiconductor device such as a liquid crystal display device, impurities such as moisture can be prevented from entering from the outside for a long time; therefore, the long-term reliability of the device can be improved.

[0464] The insulating layer disposed between the protective insulating layer 373 , which is a nitride insulating layer, and the first gate insulating layer 372 a may be removed to make contact with the protective insulating layer 373 and the first gate insulating layer 372 a .

[0465] Therefore, impurities (such as moisture, hydrogen, hydride, and hydroxide) in the oxide semiconductor layer can be reduced and prevented from entering, so that the impurity concentration in the oxide semiconductor layer can be kept low.

[0466] A planarization insulating layer for planarization may be provided on the protective insulating layer 373 .

[0467] In each of the multiple pixels in the display portion of a liquid crystal display device employing a thin-film transistor using an oxide semiconductor layer as described above, off-state current can be reduced. Consequently, the period during which the voltage is maintained in the storage capacitor can be extended, and power consumption when displaying a still image, etc., in the liquid crystal display device can be reduced. Furthermore, power consumption can be further reduced by stopping the supply of control signals when displaying a still image. Furthermore, switching between still and moving images can be performed without causing any malfunctions.

[0468] Embodiment 9 can be implemented by appropriately combining with any of the structures described in other embodiments.

[0469] (Example 10)

[0470] In Example 10, another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification will be described. The thin film transistor described in this embodiment can be used as the thin film transistor in any of Examples 2 to 8, and can be used as the thin film transistor in Example 1.

[0471] In Example 10, an example will be described in which a conductive material having a light-transmitting property is used as any one of the gate electrode layer, the source electrode layer, and the drain electrode layer. Note that the above embodiment is applicable to the same parts as those in the above embodiment, as well as parts and steps having similar functions to those in this embodiment, and their description will not be repeated. Detailed descriptions of the same parts will be omitted.

[0472] A conductive material that transmits visible light can be used as a material for any one of the gate electrode layer, the source electrode layer, and the drain electrode layer. For example, any one of the following metal oxides can be used: In-Sn-O based metal oxide; In-Sn-Zn-O based metal oxide; In-Al-Zn-O based metal oxide; Sn-Ga-Zn-O based metal oxide; Al-Ga-Zn-O based metal oxide; Sn-Al-Zn-O based metal oxide; In-Zn-O based metal oxide; Sn-Zn-O based metal oxide; Al-Zn-O based metal oxide; In-O based metal oxide; Sn-O based metal oxide; and Zn-O based metal oxide. Its thickness is appropriately set within a range of greater than or equal to 50 nm and less than or equal to 300 nm. Sputtering, vacuum evaporation (electron beam evaporation, etc.), arc discharge ion plating, and spraying are used as deposition methods for the metal oxide for any one of the gate electrode layer, the source electrode layer, and the drain electrode layer. In the case of sputtering, it is preferable to use a target containing 2 wt% or more and 10 wt% or less of SiO2 for deposition, and to suppress the crystallization of SiO2. x (x>0) is contained in the light-transmitting conductive film, thereby preventing crystallization during heat treatment in a subsequent step.

[0473] Note that the unit of the composition percentage in the light-transmitting conductive film is atomic percentage, and the composition percentage is evaluated by analysis using an electron probe X-ray microanalyzer (EPMA).

[0474] In a pixel provided with a thin film transistor, when a pixel electrode layer, another electrode layer (such as a capacitor electrode layer), or a wiring layer (such as a capacitor wiring layer) is formed using a conductive film that transmits visible light, a display device with a high aperture ratio can be realized. Needless to say, it is preferable that the gate insulating layer, oxide insulating layer, protective insulating layer, and planarization insulating layer in the pixel are each formed using a film that transmits visible light.

[0475] In this specification, a film that transmits visible light refers to a film having such a thickness as to have a visible light transmittance of 75% to 100%. When the film is conductive, the film is also referred to as a transparent conductive film. Furthermore, a conductive film that is semi-transmissive with respect to visible light can be used as a metal oxide applied to a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, another electrode layer, or another wiring layer. A conductive film that is semi-transmissive with respect to visible light refers to a film having a visible light transmittance of 50% to 75%.

[0476] When the thin film transistor has a light-transmitting property, the aperture ratio can be increased. Specifically, for a small liquid crystal display panel less than or equal to 10 inches, for example, a high aperture ratio can be achieved even when the size of the pixel is reduced by increasing the number of gate wirings to achieve a higher resolution of the displayed image. In addition, by using a film with a light-transmitting property for the components of the thin film transistor, a high aperture ratio can be achieved even when a pixel is divided into multiple sub-pixels to achieve a wide viewing angle. That is, even when a group of high-density thin film transistors is provided, a high aperture ratio can be maintained, thereby ensuring a sufficient area of ​​the display area. For example, in the case where a pixel includes 2 to 4 sub-pixels, the aperture ratio can be improved because the thin film transistor has a light-transmitting property. In addition, the storage capacitor can be formed using the same material and by the same steps as the components in the thin film transistor, so that the storage capacitor can have a light-transmitting property, thereby further improving the aperture ratio.

[0477] Embodiment 10 can be implemented in appropriate combination with any of the structures described in other embodiments.

[0478] (Example 11)

[0479] refer to Figures 15A to 15C An appearance and a cross section of a liquid crystal display panel as one embodiment of a liquid crystal display device will be described. Figure 15A and 15C Each is a top view of a panel in which thin film transistors 4010 and 4011 formed over a first substrate 4001 and a liquid crystal element 4013 are sealed between a first substrate 4001 and a second substrate 4006 by a sealant 4005 . Figure 15B Corresponding to Figure 15A Or the cross-section along line MN in 15C.

[0480] A sealant 4005 is provided so as to surround the pixel portion 4002 and the scan line driver circuit 4004 provided on the first substrate 4001. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Thus, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003, which is formed on a separately prepared substrate using a single crystal semiconductor film or a polycrystalline semiconductor film, is mounted on the first substrate 4001 in a region different from the region surrounded by the sealant 4005.

[0481] Note that the connection method of the separately formed driver circuits is not particularly limited; a COG method, a wire bonding method, a TAB method, or the like can be used. Figure 15A 4 shows an example in which the signal line driver circuit 4003 is mounted by a COG method. Figure 15C An example in which the signal line driver circuit 4003 is mounted by a TAB method is shown.

[0482] In addition, the pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 each include a plurality of thin film transistors. Figure 15B Detailed description is given of a thin film transistor 4010 included in the pixel portion 4002 and a thin film transistor 4011 included in the scan line driver circuit 4004. Insulating layers 4041, 4042, 4020, and 4021 are provided over the thin film transistors 4010 and 4011.

[0483] Any of the thin film transistors described in Embodiments 2 to 9 can be appropriately used as each of the thin film transistors 4010 and 4011, and can be formed using similar processes and similar materials. Hydrogen or water is reduced in the oxide semiconductor layer of each of the thin film transistors 4010 and 4011. As a result, the thin film transistors 4010 and 4011 have high reliability. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

[0484] A conductive layer 4040 is provided over a portion of the insulating layer 4021, overlapping with a channel formation region of the oxide semiconductor layer in the thin film transistor 4011 used in the driver circuit. Providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer can reduce the amount of change in the threshold voltage of the thin film transistor 4011 that passes the BT test. The potential of the conductive layer 4040 can be the same as or different from the potential of the gate electrode layer of the thin film transistor 4011. The conductive layer 4040 can also function as a second gate electrode layer. Alternatively, the potential of the conductive layer 4040 can be GND or 0 V, or the conductive layer 4040 can be in a floating state.

[0485] The pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4010. A counter electrode layer 4031 of the liquid crystal element 4013 is provided on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap with each other corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are respectively provided with an insulating layer 4032 and an insulating layer 4033, each serving as an alignment film, and the liquid crystal layer 4008 is sandwiched between the pixel electrode layer 4030 and the counter electrode layer 4031 with the insulating layers 4032 and 4033 interposed therebetween.

[0486] A light-transmitting substrate can be used as each of the first substrate 4001 and the second substrate 4006; glass, ceramic, or plastic can be used. As the plastic, a fiberglass reinforced plastic (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used.

[0487] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating film, and is used to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Alternatively, a spherical spacer can be used. In addition, the counter electrode layer 4031 is electrically connected to a common potential line formed on the same substrate as the thin film transistor 4010. By using a common connection portion, the counter electrode layer 4031 and the common potential line can be electrically connected to each other by conductive particles arranged between a pair of substrates. These conductive particles are included in the sealant 4005.

[0488] Liquid crystals include thermotropic liquid crystals, low-molecular liquid crystals, high-molecular liquid crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric, smectic, stereoscopic, chiral nematic, and isotropic phases depending on the conditions.

[0489] Alternatively, a liquid crystal exhibiting a blue phase that does not require an alignment film can be used. The blue phase is one of the liquid crystal phases that occurs just before the cholesteric phase changes to the isotropic phase when the temperature of the cholesteric liquid crystal increases. Because the blue phase occurs only within a narrow temperature range, a liquid crystal composition containing 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to widen the temperature range. The liquid crystal composition including the liquid crystal exhibiting the blue phase and the chiral agent has a short response time of less than or equal to 1 millisecond, has optical isotropy that does not require an alignment process, and has low viewing angle dependence. No alignment film is required, and thus, rubbing treatment is unnecessary; thus, electrostatic discharge damage caused by the rubbing treatment can be prevented, and defects and damage to the liquid crystal display device can be reduced during the manufacturing process. This improves the productivity of the liquid crystal display device. Thin-film transistors including an oxide semiconductor layer are particularly prone to the possibility that the electrical characteristics of the thin-film transistor may be significantly altered by static electricity and deviate from the designed range. Therefore, it is more effective to use a blue-phase liquid crystal material in a liquid crystal display device having a thin-film transistor including an oxide semiconductor layer.

[0490] The specific resistivity of the liquid crystal material in this embodiment is greater than or equal to 1×10 12 Ω·cm, preferably greater than or equal to 1×10 13 Ω·cm, more preferably greater than or equal to 1×10 14 Ω·cm. The resistivity in the case where impurities from the alignment film or sealant can enter the liquid crystal cell using the liquid crystal material is greater than or equal to 1×10 11 Ω·cm, and preferably more than 1×10 12 Ωcm. The specific resistivity values ​​in this specification are measured at 20°C.

[0491] As the specific resistivity of the liquid crystal material increases, the amount of charge leaking through the liquid crystal material can be reduced, thereby suppressing the decrease in the voltage used to maintain the operating state of the liquid crystal element over time. As a result, the retention period can be extended, the frequency of signal writing can be reduced, and low power consumption of the display device can be achieved.

[0492] This embodiment of the present invention can also be applied to a semi-transmissive (transmissive reflective) or reflective liquid crystal display device, as well as a transmissive liquid crystal display device. The display device of this embodiment is not limited to a liquid crystal display device, and can be an EL display device using a light-emitting element such as an electroluminescent element (also referred to as an EL element) as a display element.

[0493] An example of a liquid crystal display device is shown in which a polarizing plate is provided on the outer surface of a substrate (on the observer side) and a coloring layer and an electrode layer for a display element are provided in this order on the inner surface of the substrate; however, the polarizing plate may be provided on the inner surface of the substrate. The stacked structure of the polarizing plate and the coloring layer is not limited to the structure described in this embodiment and may be appropriately provided depending on the materials of the polarizing plate and the coloring layer or the conditions of the manufacturing process. In addition, a light-blocking film serving as a black matrix may be provided in the non-display area.

[0494] An insulating layer 4041 is formed over the thin film transistors 4011 and 4010 in contact with the oxide semiconductor layer. The insulating layer 4041 can be formed using a material similar to that of the oxide insulating layer 416 described in Example 2 and by a method similar thereto. In this embodiment, a silicon oxide layer is formed as the insulating layer 4041 by a sputtering method using Example 2. Furthermore, a protective insulating layer 4042 is formed over the insulating layer 4041 and in contact with the insulating layer 4041. The protective insulating layer 4042 can be formed in a manner similar to that of the protective insulating layer 403 described in Example 2; for example, a silicon nitride film can be used. In order to reduce the surface roughness of the thin film transistor, the protective insulating layer 4042 is covered with the insulating layer 4021 serving as a planarization insulating film.

[0495] The insulating layer 4021 is formed as a planarizing insulating film. A heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy resin can be used as the insulating layer 4021. In addition to these organic materials, a low-dielectric constant material (low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like can also be used. The insulating layer 4021 can be formed by stacking a plurality of insulating films formed using these materials.

[0496] There is no particular limitation on the method for forming the insulating layer 4021. Depending on the material, the insulating layer 4021 can be formed by a method such as sputtering, SOG, spin coating, dipping, spraying, or a droplet discharge method (for example, an inkjet method, screen printing, or offset printing), or by using a tool (equipment) such as a doctor blade, a roll coater, a curtain coater, or a knife coater. The baking step of the insulating layer 4021 also serves as annealing of the semiconductor layer, whereby a liquid crystal display device can be efficiently manufactured.

[0497] The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a light-transmitting conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO) mixed with zinc oxide (ZnO) and indium oxide, a conductive material mixed with silicon oxide (SiO2) and indium oxide, organic indium, organic tin, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or indium tin oxide containing titanium oxide. Alternatively, when the pixel electrode layer 4030 or the counter electrode layer 4031 in a reflective liquid crystal display device does not require light-transmitting properties or requires reflective properties, the pixel electrode layer 4030 or the counter electrode layer 4031 can be formed using one or more selected from metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), or silver (Ag), alloys thereof, and nitrides thereof.

[0498] A conductive composition containing a conductive high molecule (also called a conductive polymer) can be used for the pixel electrode layer 4030 and the counter electrode layer 4031. The pixel electrode formed using the conductive composition preferably has a sheet resistance of less than or equal to 10,000 ohms / square and a transmittance of greater than or equal to 70% at a wavelength of 550 nm. In addition, the resistivity of the conductive high molecule contained in the conductive composition is preferably less than or equal to 0.1 Ω·cm.

[0499] As the conductive high molecule, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, copolymers of two or more of these materials, and the like can be given.

[0500] In addition, various signals and potentials are supplied from the FPC 4018 to the signal line driver circuit 4003 , the scan line driver circuit 4004 , or the pixel portion 4002 which are separately formed.

[0501] The connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013 , and the terminal electrode 4016 is formed of the same conductive film as the source and drain electrode layers of the thin film transistors 4010 and 4011 .

[0502] The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 via an anisotropic conductive film 4019 .

[0503] Figures 15A to 15CIn the example shown, the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, the present embodiment is not limited to this structure. The scan line driver circuit may be formed separately and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be formed separately and then mounted.

[0504] A black matrix (light blocking layer), an optical member (optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member, etc. are appropriately provided. For example, circular polarization can be adopted by using a polarizing substrate and a retardation substrate. In addition, a backlight, a side light, etc. can be used as a light source.

[0505] In an active-matrix liquid crystal display (LCD), a display pattern is formed on the screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between a selected pixel electrode and the corresponding counter electrode layer, optically modulating the liquid crystal layer interposed between the pixel and counter electrodes. This optical modulation is perceived by the viewer as the display pattern.

[0506] In addition, since thin film transistors are easily damaged by static electricity, the protection circuit is preferably provided on the same substrate as the pixel portion or the driving circuit portion. The protection circuit is preferably formed by a nonlinear element including an oxide semiconductor layer. For example, the protection circuit is provided between the pixel portion and the scan line input terminal and the signal line input terminal. In this embodiment, a plurality of protection circuits are provided so as not to damage the pixel transistors, etc. even when a surge voltage caused by static electricity, etc. is applied to the scan line, signal line, or capacitor bus. Therefore, the protection circuit is configured to release the charge to the common wiring when a surge voltage is applied to the protection circuit. The protection circuit includes nonlinear elements arranged in parallel between the common wiring and the scan line, signal line, or capacitor bus. Each nonlinear element includes a two-terminal element such as a diode, or a three-terminal element such as a transistor. For example, the nonlinear element can be formed by the same steps as the thin film transistor of the pixel portion. For example, a diode-like characteristic can be achieved by connecting the gate terminal to the drain terminal.

[0507] In addition, for liquid crystal display modules, twisted nematic (TN) mode, in-plane switching (IPS) mode, fringe field switching (FFS) mode, axisymmetrically aligned microcell (ASM) mode, optically compensated birefringence (OCB) mode, ferroelectric liquid crystal (FLC) mode, antiferroelectric liquid crystal (AFLC) mode, etc. can be used.

[0508] The liquid crystal display device disclosed in this specification is not particularly limited; TN liquid crystal, OCB liquid crystal, STN liquid crystal, VA liquid crystal, ECB liquid crystal, GH liquid crystal, polymer dispersed liquid crystal, discotic liquid crystal, and the like can be used. Specifically, a normally black liquid crystal panel, such as a transmissive liquid crystal display device using a vertical alignment (VA) mode, is preferred. There are several examples of vertical alignment modes; for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an ASV mode, and the like can be employed.

[0509] Furthermore, this embodiment can be applied to VA liquid crystal display devices. VA liquid crystal display devices have a form in which the orientation of the liquid crystal molecules of the liquid crystal display panel is controlled. In VA liquid crystal display devices, when no voltage is applied, the liquid crystal molecules are oriented in a vertical direction relative to the panel surface. In addition, it is possible to use a method called domain multiplication or multi-domain design, in which the pixel is divided into a number of regions (sub-pixels) and the molecules are oriented in different directions in their respective regions.

[0510] Embodiment 11 can be implemented by appropriately combining with any of the structures described in other embodiments.

[0511] (Example 12)

[0512] In Embodiment 12, an example of an electronic device including any of the liquid crystal display devices of the above-described embodiments will be described.

[0513] Figure 16A A portable game machine is shown which can include a housing 9630, a display portion 9631, a speaker 9633, operation keys 9635, a connection terminal 9636, a recording medium reading portion 9672, and the like. Figure 16A The illustrated portable game machine may have a function of reading a program or data stored in a recording medium to display on a display portion, a function of sharing information with another portable game machine through wireless communication, and the like. Figure 16A The portable game machine shown in can have various functions in addition to the functions given above.

[0514] Figure 16B 96. A digital camera is shown which may include a housing 9630, a display portion 9631, a speaker 9633, operation keys 9635, a connection terminal 9636, a shutter button 9676, an image receiving portion 9677, and the like. Figure 16B A digital camera with a television reception function may have the function of shooting still images and / or moving images, the function of automatically or manually correcting the shot images, the function of acquiring various information from an antenna, the function of storing the shot images or the information acquired from the antenna, and the function of displaying the shot images or the information acquired from the antenna on a display portion. Figure 16BThe digital camera with a television reception function may have various functions in addition to the functions given above.

[0515] Figure 16C 9630, a display portion 9631, speakers 9633, operation keys 9635, a connection terminal 9636, and the like are shown. Figure 16C The television in the present invention may have the function of processing television waves and converting them into image signals, the function of processing image signals and converting them into signals suitable for display, the function of converting the frame frequency of image signals, etc. Figure 16C The television set in the may have various functions in addition to the functions given above.

[0516] Figure 17A The computer shown may include a housing 9630, a display portion 9631, speakers 9633, operation keys 9635, a connection terminal 9636, a pointing device 9681, an external connection port 9680, and the like. Figure 17A The computer may have a function of displaying various information (for example, still images, moving images, and text images) on a display portion, a function of controlling processing through various software (programs), a communication function such as wireless communication or wired communication, a function of connecting to various computer networks through the communication function, a function of transmitting or receiving various data through the communication function, and the like. Figure 17A The computer in may have various functions in addition to the functions given above.

[0517] Figure 17B The diagram shows a mobile phone which can include a housing 9630, a display portion 9631, a speaker 9633, operation keys 9635, a microphone 9638, and the like. Figure 17B The mobile phone in the present invention may have the function of displaying various information (for example, still images, moving images, and text images) on the display part, the function of displaying the calendar, date, time, etc. on the display part, the function of operating or editing the information displayed on the display part, the function of controlling processing through various software (programs), etc. Figure 17B The mobile phone in may have various functions in addition to the functions given above.

[0518] Figure 17C The electronic paper (also referred to as an electronic book) shown may include a housing 9630, a display portion 9631, operation keys 9635, and the like. Figure 17C The electronic paper may have the function of displaying various information (for example, still images, moving images, and text images) on the display part, the function of displaying the calendar, date, time, etc. on the display part, the function of operating or editing the information displayed on the display part, the function of controlling the processing through various software (programs), etc. Figure 17CThe electronic paper in the present invention may have various functions in addition to the functions given above.

[0519] In each of the electronic devices described in this embodiment, the off-state current in each of the multiple pixels in the display portion of the liquid crystal display device can be reduced. Consequently, the period during which the voltage is maintained in the storage capacitor can be increased, and an electronic device can be manufactured that reduces power consumption when displaying a still image, etc., on the liquid crystal display device. Furthermore, power consumption can be further reduced by stopping the supply of control signals when displaying a still image. Furthermore, switching between still and moving images can be performed without causing any malfunctions.

[0520] Embodiment 12 can be implemented by appropriately combining with any of the structures described in other embodiments.

[0521] (Example 13)

[0522] In Embodiment 13, an operation principle of a bottom-gate transistor including an oxide semiconductor will be described.

[0523] Figure 19 This is a cross-sectional view of an inverted staggered insulated gate transistor including an oxide semiconductor. An oxide semiconductor layer (OS) is provided on a gate electrode (G1) via a first gate insulating film (GI1), while a source electrode (S) and a drain electrode (D) are provided on the oxide semiconductor layer. Furthermore, a second gate insulating film (GI2) is provided on the source electrode (S) and the drain electrode (D), while a second gate electrode (G2) is provided on the second gate insulating film. G2 is maintained at ground potential.

[0524] In the following, descriptions are made using energy band diagrams, which are simplified as much as possible to understand that the energy band diagrams described are not strict. Figure 20A and 20B It is along Figure 19 The energy band diagram of the AA' section is shown (schematic diagram). Figure 20A shows a case where the voltage potential applied to the source is equal to the voltage potential applied to the drain (VD=0V), while Figure 20B A case is shown in which a positive potential with respect to the source is applied to the drain (VD>0).

[0525] Figure 21A and 21B It is along Figure 19 The energy band diagram of the BB' section is shown (schematic diagram). Figure 21A An on-state is shown in which a positive potential (+VG) is applied to the gate ( G1 ) and carriers (electrons) flow between the source and the drain. Figure 21B An off-state is shown in which a negative potential (-VG) is applied to the gate (G1) and minority carriers do not flow.

[0526] Figure 22 The relationship between the vacuum level and the work function (φM) of a metal, and the relationship between the vacuum level and the electron affinity (χ) of an oxide semiconductor are shown.

[0527] Due to metal degeneracy, the conduction band and the Fermi level correspond to each other. On the other hand, conventional oxide semiconductors are generally n-type semiconductors, in which case the Fermi level (Ef) is located away from the intrinsic Fermi level (Ei) located in the middle of the band gap and is located closer to the conduction band. Note that hydrogen is known to be a donor in oxide semiconductors and is one factor that makes oxide semiconductors n-type semiconductors.

[0528] On the other hand, the oxide semiconductor of the present invention is an intrinsic (i-type) or substantially intrinsic oxide semiconductor, which is obtained by removing hydrogen as an n-type impurity from the oxide semiconductor and purifying the oxide semiconductor to prevent the inclusion of impurities other than its main component in the oxide semiconductor as much as possible. In other words, the characteristic is that the purified i-type (intrinsic) semiconductor, or a semiconductor close to it, is obtained not by adding impurities, but by removing impurities (such as hydrogen or water) as much as possible. This allows the Fermi level (Ef) to be at the same energy level as the intrinsic Fermi level (Ei).

[0529] When the band gap (Eg) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is 4.3 eV. The work function of titanium (Ti) included in the source and drain electrodes is substantially equal to the electron affinity (χ) of the oxide semiconductor. In this case, a Schottky barrier for electrons is not formed at the interface between the metal and the oxide semiconductor.

[0530] In other words, in the case where the work function (φM) of the metal and the electron affinity (χ) of the oxide semiconductor are equal to each other and the metal and the oxide semiconductor are in contact with each other, a state such as Figure 20A The energy band diagram (schematic diagram) is shown.

[0531] exist Figure 20B In the figure, black circles (·) represent electrons, and when a positive potential is applied to the gate and drain, electrons are injected into the oxide semiconductor on the barrier (h) and flow toward the drain. In this case, the height of the barrier (h) changes according to the gate voltage and drain voltage; when a positive drain voltage is applied, the height of the barrier (h) is less than Figure 20A The height of the potential barrier when no voltage is applied (i.e., 1 / 2 of the band gap (Eg)).

[0532] At this time, the electrons injected into the oxide semiconductor flow in the oxide semiconductor, such as Figure 21A In addition, Figure 21BIn the embodiment, when a negative potential (reverse bias) is applied to the gate electrode (G1), the current value is extremely close to zero because the number of holes as minority carriers is substantially zero.

[0533] For example, even when the insulated gate transistor as described above has a 1×10 4 When the channel width W is 3 μm and the channel length is 3 μm, the off-state current is less than or equal to 10 -13 A, and the sub-threshold swing (S value) can be 0.1 V / dec (thickness of the gate insulating film: 100 nm).

[0534] Note that the intrinsic carrier density of silicon semiconductor is 1.45×10 10 / cm 3 (300K), and carriers exist even at room temperature. This means that thermally excited carriers exist even at room temperature. In practice, silicon wafers to which impurities such as phosphorus or boron are added are used. In addition, even in so-called intrinsic silicon wafers, there are uncontrollable impurities. Therefore, in practice, there are greater than or equal to 1×10 14 / cm 3 This contributes to the conduction between the source and drain. In addition, the band gap of a silicon semiconductor is 1.12 eV, and thus the off-state current of a transistor including a silicon semiconductor significantly changes depending on the temperature.

[0535] Therefore, instead of simply using an oxide semiconductor having a wide band gap for a transistor, the oxide semiconductor is purified to prevent the inclusion of impurities other than the main component as much as possible so that the carrier concentration becomes less than 1×10 14 / cm 3 (Preferably less than or equal to 1×10 12 / cm 3 ), thermally excited carriers can be eliminated at practical operating temperatures, and the transistor can operate only with carriers injected from the source side. This reduces the off-state current to less than or equal to 1×10 -13 A and it becomes possible to obtain a transistor whose off-state current hardly changes with changes in temperature and which can operate extremely stably.

[0536] The technical concept of the present invention is to purify the oxide semiconductor itself by removing impurities (such as water or hydrogen) that are not desired to be present therein, without adding impurities. In other words, one embodiment of the present invention is characterized in that the oxide semiconductor itself is purified by removing water or hydrogen that form donor levels and further by sufficiently supplying oxygen to eliminate oxygen defects.

[0537] In oxide semiconductors, even immediately after deposition, 1020 / cm 3 One technical idea of ​​the present invention is to purify an oxide semiconductor and obtain an electrically i-type (intrinsic) semiconductor by intentionally removing impurities (such as water or hydrogen) that form donor energy levels and further adding oxygen (one of the components of the oxide semiconductor) that is reduced when water or hydrogen is removed to the oxide semiconductor.

[0538] Therefore, it is preferable that the amount of hydrogen is as small as possible, and it is also preferable that the number of carriers in the oxide semiconductor is as small as possible. An oxide semiconductor is a purified i-type (intrinsic) semiconductor that has eliminated carriers when used in an insulated gate transistor and has the meaning of a carrier path like a semiconductor (rather than intentionally including carriers like a semiconductor).

[0539] Therefore, by completely eliminating carriers from the oxide semiconductor or significantly reducing the carriers therein, the off-state current of the insulated gate transistor can be reduced, which is a technical idea of ​​one embodiment of the present invention. In other words, as a guideline, the hydrogen concentration is less than or equal to 1×10 16 / cm 3 , and the carrier concentration is less than 1×10 14 / cm 3 , preferably less than or equal to 1×10 12 / cm 3 According to the technical concept of the present invention, the ideal hydrogen concentration and carrier concentration are zero or close to zero.

[0540] In addition, the oxide semiconductor serves as a path, and the oxide semiconductor itself is an i-type (intrinsic) semiconductor that has been purified to contain no carriers or contain very few carriers, and carriers are supplied from the electrode on the source side. The degree of supply is determined by the barrier height obtained from the electron affinity x of the oxide semiconductor, the Fermi level that ideally corresponds to the intrinsic Fermi level, and the work function of the source electrode or drain electrode.

[0541] Therefore, it is preferred that the off-state current is as small as possible, and one embodiment of the present invention is characterized in that, in the characteristics of the insulated gate transistor to which a drain voltage of 1V to 10V is applied, the off-state current per micron of the channel width is less than or equal to 100aA / μm, preferably less than or equal to 10aA / μm, and more preferably less than or equal to 1aA / μm.

[0542] (Example 14)

[0543] In Example 14, an off-state current value measured using a test element group (also referred to as TEG) will be described below.

[0544] Figure 23The initial characteristics of a thin film transistor with L / W=3μm / 10000μm are shown, where 200 thin film transistors each with L / W=3μm / 50μm are connected in parallel. In addition, the top view is Figure 24A , and its partially enlarged top view is Figure 24B . Figure 24B The area surrounded by the dotted line in is a thin film transistor with a level of L / W=3μm / 50μm and Lov=1.5μm. In order to measure the initial characteristics of the thin film transistor, the change characteristics of the source-drain current (hereinafter referred to as leakage current or Id) are measured under the conditions that the substrate temperature is set to room temperature, the voltage between the source and the drain (hereinafter referred to as drain voltage or Vd) is set to 10V, and the voltage between the source and the gate (hereinafter referred to as gate voltage or Vg) is changed from -20V to +20V, that is, the Vg-Id characteristics. Note that Figure 23 Vg is shown in the range from -20V to +5V.

[0545] like Figure 23 As shown, a thin film transistor with a channel width W of 10000 μm has a voltage less than or equal to 1×10 -13 The off-state current is less than or equal to the resolution (100 fA) of the measuring device (Agilent 4156C, a semiconductor parameter analyzer manufactured by Agilent Technologies).

[0546] A method for fabricating a thin film transistor for measurement is described.

[0547] First, a silicon nitride layer is formed on a glass substrate by CVD as a base layer, and a silicon oxynitride layer is formed on the silicon nitride layer. A tungsten layer is formed on the silicon oxynitride layer by sputtering as a gate electrode layer. In this embodiment, the tungsten layer is selectively etched to form the gate electrode layer.

[0548] Then, a silicon oxynitride layer was formed as a gate insulating layer with a thickness of 100 nm on the gate electrode layer by a CVD method.

[0549] Then, a 50 nm thick oxide semiconductor layer was formed on the gate insulating layer by sputtering using an In—Ga—Zn—O-based oxide semiconductor target (molar ratio of In 2 O 3 : Ga 2 O 3 : ZnO = 1:1:2). Here, the oxide semiconductor layer was selectively etched into island-shaped oxide semiconductor layers.

[0550] Then, the oxide semiconductor layer is subjected to first heat treatment in a clean oven at 450° C. for 1 hour in a nitrogen atmosphere.

[0551] Then, a titanium layer (150 nm thick) was formed on the oxide semiconductor layer by sputtering to serve as source and drain electrode layers. Here, the source and drain electrode layers were selectively etched to connect 200 thin-film transistors, each with a channel length L of 3 μm and a channel width W of 50 μm, in parallel to obtain a thin-film transistor with L / W = 3 μm / 10,000 μm.

[0552] Next, a 300nm-thick silicon oxide layer was formed by reactive sputtering as a protective insulating layer in contact with the oxide semiconductor layer. The protective silicon oxide layer was selectively etched to form openings in the gate, source, and drain electrode layers. A second heat treatment was then performed in a nitrogen atmosphere at 250°C for one hour.

[0553] Then, heat treatment was performed at 150° C. for 10 hours before measuring Vg-Id characteristics.

[0554] Through the above process, a bottom-gate thin film transistor is manufactured.

[0555] like Figure 23 The thin film transistor shown has a -13 The reason for the off-state current of A is that the hydrogen concentration in the oxide semiconductor layer may be sufficiently reduced in the above manufacturing process. The hydrogen concentration in the oxide semiconductor layer is less than or equal to 1×10 16 / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS).

[0556] Although an example of using an In-Ga-Zn-O based oxide semiconductor is described, the present embodiment is not particularly limited thereto. Another oxide semiconductor material such as an In-Sn-Zn-O based oxide semiconductor, a Sn-Ga-Zn-O based oxide semiconductor, an Al-Ga-Zn-O based oxide semiconductor, a Sn-Al-Zn-O based oxide semiconductor, an In-Zn-O based oxide semiconductor, an In-Sn-O based oxide semiconductor, a Sn-Zn-O based oxide semiconductor, an Al-Zn-O based oxide semiconductor, an In-O based oxide semiconductor, a Sn-O based oxide semiconductor, or a Zn-O based oxide semiconductor may also be used. AlO mixed with 2.5 wt % to 10 wt % may be used. x In-Al-Zn-O based oxide semiconductor, or mixed with 2.5 wt% to 10 wt% of SiO x An In-Zn-O-based oxide semiconductor is used as the oxide semiconductor material.

[0557] The carrier concentration of the oxide semiconductor layer measured by a carrier measurement device is less than 1×1014 / cm 3 , preferably less than or equal to 1×10 12 / cm 3 In other words, the carrier concentration of the oxide semiconductor layer can be made as close to zero as possible.

[0558] The channel length L of the thin film transistor can also be greater than or equal to 10 nm and less than or equal to 1000 nm, which enables the circuit operation speed to be increased, while the off-state current is extremely small, which enables the power consumption to be further reduced.

[0559] In addition, in circuit design, the oxide semiconductor layer can be considered as an insulator when the thin film transistor is in the off state.

[0560] Next, the temperature characteristics of the off-state current of the thin-film transistors manufactured in this example were evaluated. Temperature characteristics are important for considerations such as the environmental resistance and performance maintenance of the final product in which the thin-film transistor is used. It should be understood that smaller changes are more preferable, as they increase the degree of freedom in product design.

[0561] For temperature characteristics, Vg-Id characteristics were obtained using a constant temperature chamber under the conditions that the substrate provided with the thin film transistor was maintained at corresponding constant temperatures of -30°C, 0°C, 25°C, 40°C, 60°C, 80°C, 100°C and 120°C, the drain voltage was set to 6V, and the gate voltage was changed from -20V to +20V.

[0562] Figure 25A The Vg-Id characteristics measured at the above temperatures and superimposed on each other are shown, and Figure 25B Show Figure 25A This is an enlarged view of the range of the off-state current surrounded by the dotted line in the figure. The rightmost curve indicated by the arrow in the figure is the curve obtained at -30°C; the leftmost curve is the curve obtained at 120°C, and the curves obtained at other temperatures are located between them. It may be difficult to observe the temperature dependence of the on-state current. On the other hand, as Figure 25B As clearly shown in the enlarged figure, except for the gate voltage near -20V, the off-state current is less than or equal to 1×10 -12 A (which is close to the resolution of the measurement equipment), and its temperature dependence is not observed. In other words, even at a high temperature of 120°C, the off-state current is maintained at less than or equal to 1×10 -12 A, and assuming that the channel width W is 10000 μm, it can be seen that the off-state current is quite small.

[0563] The thin film transistor including the purified oxide semiconductor (purified OS) as described above shows that the off-state current has almost no dependence on temperature. It can be said that the oxide semiconductor does not show temperature dependence when it is purified because the conductivity type becomes very close to the intrinsic type and the Fermi level is located in the middle of the band gap, as shown in FIG. Figure 19 This is also due to the fact that the oxide semiconductor has an energy gap greater than or equal to 3 eV and includes very few thermally excited carriers. In addition, the source region and the drain region are in a degenerate state, which is also a factor showing no temperature dependence. The thin film transistor mainly operates with carriers injected into the oxide semiconductor from the degenerate source region, and the above characteristics (no dependence of the off-state current on temperature) can be explained by the fact that the carrier concentration is independent of temperature.

[0564] In the case of manufacturing a display device using such a thin film transistor whose off-state current is extremely small, leakage current is reduced, so that a period for holding display data can be extended.

[0565] [Example 1]

[0566] In Example 1, the evaluation results of the image signal retention characteristics of the liquid crystal display device described in the above embodiments and actually manufactured when displaying a still image will be described.

[0567] First, regarding the upper layout diagram of a plurality of pixels included in the pixel portion, Figure 27 , a photograph of an element such as a thin film transistor formed on a substrate taken from the back side is shown.

[0568] from Figure 27 As can be seen from the photograph of the pixel shown, rectangular pixels are arranged, and the gate line 2701 and the signal line 2702 are arranged at right angles to each other. It can also be seen that the capacitor line 2703 is arranged in parallel with the gate line 2701. In the area where the gate line 2701 and the capacitor line 2703, as well as the signal line 2702, overlap each other, an insulating film is provided to reduce parasitic capacitance, and the insulating film can be observed as Figure 27 The liquid crystal display device described in this example is a reflective liquid crystal display device, and a red (R) color filter 2704R, a green (G) color filter 2704G, and a blue (B) color filter 2704B are observed. Figure 27 In the embodiment, in a region controlled by the gate line 2701, an In-Ga-Zn-O-based non-single-crystal film as an oxide semiconductor is provided as a light-transmitting semiconductor layer, and a thin film transistor is formed.

[0569] Figure 28 According to the above embodiment, when displaying a still image, Figure 27 A graph showing the luminance of each pixel changing over time.

[0570] from Figure 28 It can be seen that in Figure 27 In the case of a layout on the upper side of the pixels, the image signal holding period is about 1 minute long. Therefore, when displaying a still image, a constant luminance can be maintained by regularly supplying the same image signal ("refresh" in the diagram). Therefore, the length of time that the voltage is applied to the transistors included in the drive circuit portion can be drastically shortened. In addition, the degradation of the drive circuit over time can be drastically slowed, which produces advantageous effects such as improved reliability of the liquid crystal display device.

[0571] [Example 2]

[0572] In Example 2, the following description will be given of the Figure 1 Shown are evaluation results of image signal retention characteristics of a liquid crystal display device described in the above embodiment and actually manufactured to have a structure different from that of Example 1.

[0573] First, regarding the upper layout diagram of a plurality of pixels included in the pixel portion, Figure 29 , a photograph of an element such as a thin film transistor formed on a substrate taken from the back side is shown.

[0574] from Figure 29 As can be seen from the photograph of the pixel shown, rectangular pixels are arranged, and the gate line 2901 and the signal line 2902 are arranged at right angles to each other. It can also be seen that the capacitor line 2903 is arranged at a position parallel to the gate line 2901. In the area where the gate line 2901 and the capacitor line 2903, as well as the signal line 2902, overlap each other, an insulating film is provided to reduce parasitic capacitance, and the insulating film can be observed as Figure 29 The liquid crystal display device described in this example is a reflective liquid crystal display device, and a reflective electrode 2904R overlapping with a red (R) color filter, a reflective electrode 2904G overlapping with a green (G) color filter, and a reflective electrode 2904B overlapping with a blue (B) color filter are observed. Figure 29 In the embodiment, in a region controlled by the gate line 2901, an In-Ga-Zn-O-based non-single-crystal film as an oxide semiconductor is provided as a light-transmitting semiconductor layer, and a thin film transistor is formed.

[0575] Figure 30 According to the above embodiment, when displaying a still image, Figure 29 A graph showing the luminance of each pixel changing over time.

[0576] from Figure 30 It can be seen that in Figure 29In the case of a layout on the upper side of the pixels, the image signal holding period is about 1 minute long. Therefore, when displaying a still image, a constant luminance can be maintained by regularly supplying the same image signal ("refresh" in the diagram). Therefore, the length of time that the voltage is applied to the transistors included in the drive circuit portion can be drastically shortened. In addition, the degradation of the drive circuit over time can be drastically slowed, which produces advantageous effects such as improved reliability of the liquid crystal display device.

[0577] [Example 3]

[0578] In Example 3, the following description will be given of the Figure 1 Shown are evaluation results of image signal retention characteristics of the liquid crystal display devices described in the above embodiments and actually manufactured to have structures different from Examples 1 and 2.

[0579] First, regarding the upper layout diagram of a plurality of pixels included in the pixel portion, Figure 31 , a photograph of an element such as a thin film transistor formed on a substrate taken from the back side is shown.

[0580] from Figure 31 As can be seen from the photograph of the pixel shown, rectangular pixels are arranged, and the gate line 3101 and the signal line 3102 are arranged at right angles to each other. It can also be seen that the capacitor line 3103 is arranged at a position parallel to the gate line 3101. In the area where the gate line 3101 and the capacitor line 3103 and the signal line 3102 overlap with each other, an insulating film is provided to reduce parasitic capacitance, and the insulating film can be observed as Figure 31 The liquid crystal display device described in this example is a liquid crystal display device using polymer dispersed liquid crystal, and the reflective electrode 3104 is observed. Figure 31 In the embodiment, in a region controlled by the gate line 3101, an In-Ga-Zn-O-based non-single-crystal film as an oxide semiconductor is provided as a light-transmitting semiconductor layer, and a thin film transistor is formed.

[0581] Figure 32 According to the above embodiment, when displaying a still image, Figure 31 A graph showing the luminance of each pixel changing over time.

[0582] from Figure 32 It can be seen that in Figure 31In the case of a top-side pixel layout, the image signal retention period can be longer than that of Examples 1 and 2 because the polymer-dispersed liquid crystal has the property of retaining image signals. Therefore, when displaying a still image, the interval between operations in which the same image signal is supplied can be extended. Consequently, the duration of time during which voltage is applied to transistors included in the driver circuit can be drastically shortened. Furthermore, the degradation of the driver circuit over time can be significantly slowed, resulting in advantageous effects such as improved reliability of the liquid crystal display device.

[0583] [Example 4]

[0584] In Example 4, the following description will be given of the Figure 1 The results of the evaluation of the image signal retention characteristics of the liquid crystal display device described in the above embodiment and actually manufactured to have a structure different from Examples 1 to 3 are shown. Specifically, in this example, an example of a top layout diagram of a plurality of pixels different from that described in any one of Examples 1 to 3 will be described. Figure 33 , a photograph of an element such as a thin film transistor formed on a substrate taken from the back side is shown.

[0585] from Figure 33 As can be seen from the photograph of the pixel shown, rectangular pixels are arranged, and the gate line 3301 and the signal line 3302 are arranged at right angles to each other. Unlike the photograph of the pixel described in any of Examples 1 to 3, the upper side layout diagram in which the capacitor line is omitted is described. The liquid crystal display device described in this example is a transmissive liquid crystal display device, and the pixel electrode 3304 is observed. Figure 33 In the embodiment, in a region controlled by the gate line 3301, an In-Ga-Zn-O-based non-single-crystal film as an oxide semiconductor is provided as a light-transmitting semiconductor layer, and a thin film transistor is formed.

[0586] [Example 5]

[0587] In Example 5, the Figure 1 An example of an operating method of a liquid crystal display device shown in FIG and described in the above embodiments. Figure 34 A process of supplying or stopping a potential to each wiring of a driver circuit portion in a driver circuit manufactured using a plurality of n-channel transistors during an operation of displaying a still image and a moving image or an operation of rewriting a voltage applied to a liquid crystal element (hereinafter also referred to as a refresh operation) is described and given as Figures 2A to 2C ,as well as Figure 3 Note that Figure 34The changes in the potential of the wiring for supplying a high power supply potential (VDD) to the shift register, the wiring for supplying a low power supply potential (VSS), the wiring for supplying a start pulse (SP), and the wiring for supplying the first to fourth clock signals (CK1 to CK4) before and after period T1 are shown.

[0588] The liquid crystal display device of this embodiment can display a still image without constantly operating the drive circuit portion. Figure 34 As shown, there are periods in which control signals such as a high power supply potential (VDD), first to fourth clock signals (CK1 to CK4), and a start pulse are supplied to the shift register, and periods in which control signals are not supplied. Note that Figure 34 The illustrated period T1 corresponds to a period in which a control signal is supplied, in other words, a period in which a moving image is displayed, and a period in which a refresh operation is performed. Figure 34 The illustrated period T2 corresponds to a period during which no control signal is supplied, in other words, a period during which a still image is displayed.

[0589] exist Figure 34 In the embodiment, the period for supplying the high power supply potential (VDD) is provided not only in the period T1 but also in a part of the period T2. Figure 34 In the embodiment, the first to fourth clock signals (CK1 to CK4) are supplied at periods set between the start of supply of the high power supply potential (VDD) and the stop of supply of the high power supply potential (VDD).

[0590] In addition, if Figure 34 As shown, the first to fourth clock signals (CK1 to CK4) may be set to start oscillating at a constant frequency once set to a high level before the start of period T1, and stop oscillating after being set to a low level after the end of period T1.

[0591] As described above, in the liquid crystal display device of this example, the supply of control signals to the shift register, such as the high power supply potential (VDD), the first to fourth clock signals (CK1 to CK4), and the start pulse, is stopped during period T2. Then, during the period in which the supply of control signals is stopped, each transistor is controlled to be turned on or off, and the output of pulse signals from the shift register is also stopped. Therefore, the power consumption of the shift register and the power consumption of the pixel portion driven by the shift register can be reduced.

[0592] The above-mentioned refresh operation must be performed regularly because there is a possibility that the quality of the displayed still image may deteriorate. In the liquid crystal display device of this example, the above-mentioned transistor including an oxide semiconductor is used as a switching element for controlling the voltage applied to the liquid crystal element of each pixel. Therefore, the off-state current can be sharply reduced, and the change in the voltage applied to the liquid crystal element of each pixel can be reduced. In other words, even when the cycle of stopping the operation of the shift register is long due to the display of a still image, the degradation of the image quality can be suppressed. For example, even when the cycle is 3 minutes long, the quality of the displayed still image can be maintained. For example, if a liquid crystal display device that is rewritten 60 times per second is compared with a liquid crystal display device that performs a refresh operation once every 3 minutes, the power consumption can be reduced to about 1 / 10000.

[0593] Note that the high power supply potential (VDD) is set to a potential equal to the low power supply potential (VSS) when the supply is stopped. Figure 34 In addition, the supply of the high power supply potential (VDD) can be stopped to set the potential of the wiring to which the high power supply potential is supplied in a floating state.

[0594] Note that when the potential of the wiring to which the high power supply potential (VDD) is supplied increases (this means that the potential increases from the low power supply potential (VSS) to the high power supply potential (VDD) before period T1), it is preferable to control the potential of the wiring to change gradually. If the gradient of the potential change of the wiring is steep, there is a possibility that the change in potential may become noise and a fault pulse may be output from the shift register. In the case where a shift register is included in the gate line driver circuit, the fault pulse is used as a signal for turning on the transistor. Thus, there is a possibility that the voltage applied to the liquid crystal element may be changed by the fault pulse and the quality of the still image may change. Therefore, it is preferable to control the potential change of the wiring as described above. In view of the above, Figure 34 An example is shown in which a signal rises to a high power supply potential (VDD) more slowly than it falls. Specifically, in the liquid crystal display device of this embodiment, when a still image is displayed in a pixel portion, the supply of the high power supply potential (VDD) to the shift register is stopped and the high power supply potential is re-supplied to the shift register as appropriate. In other words, when a potential change of the wiring for supplying the high power supply potential (VDD) adversely affects the pixel portion as noise, the noise directly causes degradation of the displayed image. Therefore, it is important to control the liquid crystal display device of this embodiment to prevent a potential change of the wiring (specifically, an increase in potential) from entering the pixel portion as noise.

[0595] This application is based on Japanese patent application serial numbers 2009-238916, 2009-273913, and 2009-278999 filed with the Japan Patent Office on October 16, 2009, December 1, 2009, and December 8, 2009, respectively, the entire contents of which are incorporated herein by reference.

Claims

1. A display device, comprising: a pixel portion including a transistor; as well as a gate line driving circuit electrically connected to the pixel portion, wherein the transistor of the pixel portion includes an oxide semiconductor layer, the oxide semiconductor layer including a channel formation region, wherein the pixel portion is configured to display in a first mode and a second mode, a start pulse is supplied to the gate line driving circuit during the first mode, and the second mode includes a period in which the supply of the start pulse to the gate line driving circuit is stopped, The transistor of the pixel portion further includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer. wherein the oxide semiconductor layer includes a region located on the first conductive layer, wherein the second conductive layer includes a region located on the oxide semiconductor layer, The third conductive layer includes a region located on the oxide semiconductor layer. The fourth conductive layer includes a region located on the oxide semiconductor layer through an insulating layer. Wherein, the fifth conductive layer includes a region located on the insulating layer, wherein the second conductive layer includes a region in contact with the oxide semiconductor layer, wherein the third conductive layer includes a region in contact with the oxide semiconductor layer, The third conductive layer includes a region in contact with the first conductive layer. The third conductive layer includes a region in contact with the fifth conductive layer. wherein the fourth conductive layer is configured to function as a gate electrode of the transistor in the pixel portion, Wherein, in a cross-sectional view, the oxide semiconductor layer includes a region located between the first conductive layer and the third conductive layer, wherein, in a plan view, the oxide semiconductor layer overlaps with an edge of the first conductive layer, and In the plan view, the channel formation region overlapping with the fourth conductive layer is surrounded by the edge of the first conductive layer.

2. A display device comprising: a pixel portion including a transistor; as well as a gate line driving circuit electrically connected to the pixel portion, wherein the transistor of the pixel portion includes an oxide semiconductor layer, the oxide semiconductor layer including a channel formation region, wherein the pixel portion is configured to display in a first mode and a second mode, a start pulse is supplied to the gate line driving circuit during the first mode, and the second mode includes a period in which the supply of the start pulse to the gate line driving circuit is stopped, The transistor of the pixel portion further includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer. wherein the oxide semiconductor layer includes a region located on the first conductive layer, wherein the second conductive layer includes a region located on the oxide semiconductor layer, The third conductive layer includes a region located on the oxide semiconductor layer. The fourth conductive layer includes a region located on the oxide semiconductor layer through an insulating layer. Wherein, the fifth conductive layer includes a region located on the insulating layer, wherein the second conductive layer includes a region in contact with the oxide semiconductor layer, wherein the third conductive layer includes a region in contact with the oxide semiconductor layer, The third conductive layer includes a region in contact with the first conductive layer. The third conductive layer includes a region in contact with the fifth conductive layer. wherein the fourth conductive layer is configured to function as a gate electrode of the transistor in the pixel portion, Wherein, in a cross-sectional view, the oxide semiconductor layer includes a region located between the first conductive layer and the third conductive layer, wherein, in a plan view, the oxide semiconductor layer overlaps with an edge of the first conductive layer, wherein, in the plan view, the channel formation region overlapping with the fourth conductive layer is surrounded by the edge of the first conductive layer, wherein the oxide semiconductor layer includes indium, gallium, and zinc, and When the drain voltage is 1V, the off-state current of the transistor in the pixel portion is 1×10 -13 A or smaller.

3. A display device comprising: a pixel portion including a transistor; as well as A gate line driving circuit electrically connected to the pixel portion wherein the transistor of the pixel portion includes an oxide semiconductor layer, the oxide semiconductor layer including a channel formation region, wherein the pixel portion is configured to display in a first mode and a second mode, a start pulse is supplied to the gate line driving circuit during the first mode, and the second mode includes a period in which the supply of the start pulse to the gate line driving circuit is stopped, The transistor of the pixel portion further includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer. wherein the oxide semiconductor layer includes a region located on the first conductive layer, wherein the second conductive layer includes a region located on the oxide semiconductor layer, The third conductive layer includes a region located on the oxide semiconductor layer. The fourth conductive layer includes a region located on the oxide semiconductor layer through an insulating layer. Wherein, the fifth conductive layer includes a region located on the insulating layer, wherein the second conductive layer includes a region in contact with the oxide semiconductor layer, wherein the third conductive layer includes a region in contact with the oxide semiconductor layer, The third conductive layer includes a region in contact with the first conductive layer. The third conductive layer includes a region in contact with the fifth conductive layer. wherein the fourth conductive layer is configured to function as a gate electrode of the transistor in the pixel portion, Wherein, in a cross-sectional view, the oxide semiconductor layer includes a region located between the first conductive layer and the third conductive layer, wherein, in a plan view, the oxide semiconductor layer overlaps with an edge of the first conductive layer, wherein, in the plan view, the channel formation region overlapping with the fourth conductive layer is surrounded by the edge of the first conductive layer, Wherein, the gate line driving circuit includes a first transistor, a second transistor and a third transistor, wherein the potential of the first power line is provided to a node connecting the first transistor, the second transistor, and the third transistor through the first transistor, wherein the potential of the first power line is provided to the node through the second transistor, and The potential of the second power line is provided to the node through the third transistor.

4. A display device comprising: a pixel portion including a transistor; as well as a gate line driving circuit electrically connected to the pixel portion, wherein the transistor of the pixel portion includes an oxide semiconductor layer, the oxide semiconductor layer including a channel formation region, wherein the pixel portion is configured to display in a first mode and a second mode, a start pulse is supplied to the gate line driving circuit during the first mode, and the second mode includes a period in which the supply of the start pulse to the gate line driving circuit is stopped, The transistor of the pixel portion further includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer. wherein the oxide semiconductor layer includes a region located on the first conductive layer, wherein the second conductive layer includes a region located on the oxide semiconductor layer, The third conductive layer includes a region located on the oxide semiconductor layer. The fourth conductive layer includes a region located on the oxide semiconductor layer through an insulating layer. Wherein, the fifth conductive layer includes a region located on the insulating layer, wherein the second conductive layer includes a region in contact with the oxide semiconductor layer, wherein the third conductive layer includes a region in contact with the oxide semiconductor layer, The third conductive layer includes a region in contact with the first conductive layer. The third conductive layer includes a region in contact with the fifth conductive layer. wherein the fourth conductive layer is configured to function as a gate electrode of the transistor in the pixel portion, Wherein, in a cross-sectional view, the oxide semiconductor layer includes a region located between the first conductive layer and the third conductive layer, wherein, in a plan view, the oxide semiconductor layer overlaps with an edge of the first conductive layer, wherein, in the plan view, the channel formation region overlapping with the fourth conductive layer is surrounded by the edge of the first conductive layer, Wherein, the oxide semiconductor layer includes indium, gallium and zinc, When the drain voltage is 1V, the off-state current of the transistor in the pixel portion is 1×10 -13 A or less, Wherein, the gate line driving circuit includes a first transistor, a second transistor and a third transistor, wherein the potential of the first power line is provided to a node connecting the first transistor, the second transistor, and the third transistor through the first transistor, wherein the potential of the first power line is provided to the node through the second transistor, and The potential of the second power line is provided to the node through the third transistor.

Images