Antifuse readout circuit, antifuse memory, and test method

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and in particular to an anti-fuse readout circuit, an anti-fuse memory, and a test method. The anti-fuse readout circuit includes: a latch module configured to latch data read from an anti-fuse memory array; a transmission module connected to the output terminal of the latch module and configured to transmit the data latched in the latch module to a data port in response to a read test command. Embodiments of the present disclosure are beneficial to improving the authenticity of test results when testing data stored in an anti-fuse programmable device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to an anti-fuse readout circuit, an anti-fuse memory, and a testing method. Background Art

[0002] One-time programmable devices based on anti-fuse technology are widely used in various chips. For example, in DRAM (Dynamic Random Access Memory) chips, anti-fuse programmable devices can be used to store address information of defective memory cells, and then redundant replacement can be achieved, such as row replacement or column replacement.

[0003] To ensure the high accuracy of the data stored in the anti-fuse programmable device, the stored data is usually tested. However, when testing the data stored in the anti-fuse programmable device currently, there is a problem that the authenticity of the test result is poor. Summary of the Invention

[0004] Embodiments of the present disclosure provide an anti-fuse readout circuit, an anti-fuse memory, and a testing method, which are at least beneficial to solving the problem that the authenticity of the test result is poor when testing the data stored in the anti-fuse programmable device.

[0005] Embodiments of the present disclosure provide an anti-fuse readout circuit, including: a latch module configured to latch data read from an anti-fuse memory array; a transmission module connected to an output end of the latch module and configured to transmit the data latched in the latch module to a data port in response to a read test command.

[0006] In some embodiments, the latch module includes: a multiplexed latch unit, where each latch unit is configured to latch one-bit data among the data read from the anti-fuse memory array; the transmission module includes: a plurality of transmission units, each transmission unit is connected to an output end of a corresponding latch unit, and each transmission unit transmits the one-bit data latched in the corresponding latch unit to the data port in response to different read test commands, and the timing of the read test commands received by each transmission unit is different.

[0007] In some embodiments, the latch unit includes: a first switching transistor that receives one-bit data and conducts in response to a position strobe signal, so that the output end of the first switching transistor outputs one-bit data; a latch circuit, an output end of the latch circuit is connected to the transmission unit, and an input end of the latch circuit is connected to the output end of the first switching transistor.

[0008] In some embodiments, the first switching transistor is a first transmission gate. The first control terminal of the first transmission gate receives a position strobe signal, and the input terminal of the first transmission gate receives one-bit data. The latch unit further includes: a first inverter, the input terminal of the first inverter receives the position strobe signal, and the output terminal of the first inverter is connected to the second control terminal of the first transmission gate.

[0009] In some embodiments, the transmission unit includes: a second switching transistor, and the second switching transistor is turned on in response to a read test command to transmit one-bit data to the data port.

[0010] In some embodiments, the second switching transistor includes a second transmission gate. The first control terminal of the second transmission gate receives the read test command, and the input terminal of the second transmission gate receives one-bit data. The transmission unit further includes: a second inverter, the input terminal of the second inverter receives the read test command, and the output terminal of the second inverter is connected to the second control terminal of the second transmission gate.

[0011] In some embodiments, it further includes: a buffer module, which is disposed between the output terminal of the transmission module and the data port.

[0012] In some embodiments, the buffer module includes an even number of inverters connected in series. The input terminal of the inverter at the first position is connected to the output terminal of the transmission module, and the output terminal of the inverter at the last position is connected to the data port.

[0013] In some embodiments, it further includes: a comparison module, the comparison module is connected to the output terminal of the latch module and is configured to compare whether the data latched by the latch module matches the current address information.

[0014] In some embodiments, the comparison module includes: an exclusive NOR gate, one input terminal of the exclusive NOR gate is connected to the output terminal of the latch module, and the other input terminal of the exclusive NOR gate receives the current address information.

[0015] In some embodiments, the transmission module is further configured to transmit the data latched in the latch module to the same data port.

[0016] In some embodiments, the antifuse readout circuit includes a plurality of latch modules and a plurality of transmission modules; it further includes: a selection module, the selection module is connected to the output terminals of the plurality of transmission modules, and the selection module is configured to select the data output by one of the transmission modules and transmit it to the data port.

[0017] In some embodiments, the selection module includes: a plurality of selection output units, each selection output unit corresponds to a transmission module, and the selection output unit outputs the data transmitted by the transmission module in response to a selection signal; a switching unit, the switching unit is connected between the output terminals of the plurality of selection output units and the data port, and the switching unit is configured to transmit the data output by the selection output unit to the data port.

[0018] In some embodiments, the selection output unit includes an AND gate circuit. One input terminal of the AND gate circuit receives a selection signal, and the other input terminal receives the data output by the transmission module.

[0019] In some embodiments, the switch unit includes: an OR gate circuit connected in multiple stages. Each stage of the OR gate circuit corresponds to a selection output unit. One input terminal of the OR gate is connected to the output terminal of the corresponding selection output unit; wherein, the other input terminal of the OR gate circuit at the first stage is grounded, the output terminal of the OR gate circuit at the last stage is connected to the data port, and the output terminal of the previous stage of the OR gate circuit is connected to one input terminal of the next stage of the OR gate circuit.

[0020] In some embodiments, the OR gate circuit includes: a NOR gate circuit, one input terminal of the NOR gate circuit is connected to the output terminal of the corresponding selection output unit; a NOT gate circuit, the input terminal of the NOT gate circuit is connected to the output terminal of the NOR gate circuit, and the output terminal of the NOT gate circuit is connected to the input terminal of the NOR gate circuit of the next stage of the OR gate.

[0021] In some embodiments, the switch unit includes: an OR gate circuit. The output terminals of multiple selection output units are all connected to the input terminal of the OR gate circuit, and the output terminal of the OR gate circuit is connected to the data port.

[0022] Correspondingly, an embodiment of the present disclosure further provides an antifuse memory, including: an antifuse storage array; the antifuse readout circuit provided in any one of the above.

[0023] Correspondingly, an embodiment of the present disclosure further provides a test method. The test method can be tested by using the antifuse readout circuit provided in any one of the above, including: reading data from the antifuse storage array and latching the data; in response to a read test command, transmitting the latched data to the data port; determining whether the data transmitted to the data port meets the expectation.

[0024] In some embodiments, transmitting the latched data to the data port includes: in response to different read test commands, transmitting one bit of the data to the data port each time.

[0025] In some embodiments, there are multiple latching modules and multiple transmission modules; transmitting the latched data to the data port includes: in response to a selection signal, transmitting the data latched by one latching module to the data port each time.

[0026] The technical solution provided by the embodiment of the present disclosure has the following advantages:

[0027] In the technical solution of the anti-fuse readout circuit provided by the embodiments of the present disclosure, it includes: a latch module for latching the data read from the anti-fuse memory array; a transmission module connected to the output end of the latch module and configured to transmit the data latched in the latch module to the data port in response to a read test command. By adding a transmission module to the readout circuit, the data latched in the latch module can be transmitted to the data port through the transmission module, that is, the data transmitted to the data port during the test stage is the data from the latch module. In this way, when the data in the data port is collected and tested during the test stage, the test result of the data in the data port can truly reflect whether the data in the latch module is accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the drawings do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 It is a functional block diagram of an anti-fuse readout circuit provided by an embodiment of the present disclosure;

[0030] Figure 2 It is a functional block diagram of another anti-fuse readout circuit provided by an embodiment of the present disclosure;

[0031] Figure 3 It is a timing diagram of a read test command provided by an embodiment of the present disclosure;

[0032] Figure 4 It is a circuit diagram of an anti-fuse readout circuit provided by an embodiment of the present disclosure;

[0033] Figure 5 It is a circuit diagram of another anti-fuse readout circuit provided by an embodiment of the present disclosure;

[0034] Figure 6 It is a structural schematic diagram of an anti-fuse memory provided by an embodiment of the present disclosure;

[0035] Figure 7 It is a flowchart of a test method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] As can be seen from the background art, when testing the data stored in an antifuse programmable device, there is a problem that the authenticity of the test results is not good enough. Through analysis, it is found that one of the reasons for the poor authenticity of the test results is that currently, the data stored in the antifuse programmable device is first latched into the latch module through the broadcast path. Subsequently, the data latched in the latch module is compared with the current address information to determine whether there are defects in the storage cells in the DRAM chip. When testing the accuracy of the data stored in the antifuse programmable device, the data stored in the antifuse programmable device is transmitted to the data port through the antifuse read path and the FIFO (First Input First Output) circuit, and then the data in the data port is read and tested. Since the broadcast path and the antifuse read path are two different paths, the data in the data port may be inconsistent with the data in the latch module, resulting in the test results of the data in the data port not being able to truly reflect the accuracy of the data latched in the latch module, and the authenticity of the test results is not good enough.

[0037] An embodiment of the present disclosure provides an antifuse readout circuit. A transmission module is added to the readout circuit, so that the data latched in the latch module can be transmitted to the data port through the transmission module, that is, the data transmitted to the data port during the test stage is the data from the latch module. In this way, the data collected at the data port during the test stage comes from the latch module, so that the test results of the data at the data port can truly reflect whether the data in the latch module is accurate, thereby improving the accuracy of the test.

[0038] The following will elaborate on the embodiments of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are proposed to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0039] Figure 1 It is a functional block diagram of an antifuse readout circuit provided by an embodiment of the present disclosure.

[0040] Refer to Figure 1 , the antifuse readout circuit includes: a latch module 101, which is used to latch the data read from the antifuse storage array; a transmission module 102, which is connected to the output end of the latch module 101 and is configured to transmit the data latched in the latch module 101 to the data port 103 in response to the read test command RD.

[0041] That is to say, in the test stage, the transmission module 102 is turned on in response to the read test command RD, and the data latched in the latching module 101 can be transmitted to the data port 103 through the transmission module 102. Thus, collecting the data in the data port 103 for testing is equivalent to collecting the data in the latching module 101 for testing, so that the test result of the data in the data port 103 can truly reflect whether the data in the latching module 101 is accurate.

[0042] The latching module 101 is used to latch the data read from the antifuse memory array. When the latching module 101 is turned on, the data of the antifuse memory array can be transmitted to the latching module 101 and latched. The transmission module 102 is used to transmit the data in the latching module 101. In some embodiments, when the read test command RD is at a high level, the transmission module 102 is turned on, and the data in the latching module 101 can be transmitted to the data port 103 via the transmission module 102; when the read test command RD is at a low level, the transmission module 102 is turned off, and the data in the latching module 101 cannot be transmitted to the data port 103 through the transmission module 102. Thus, the transmission module 102 can respond to the read test command RD to transmit the data in the latching module 101 to the data port 103 for testing. In other embodiments, it can also be that when the read test command RD is at a low level, the latching module 101 is turned on, and when the read test command RD is at a high level, the latching module 101 is turned off. In some embodiments, the data port 103 can be a DQ port.

[0043] Reference Figure 2 , Figure 2Another functional block diagram of the anti-fuse readout circuit provided by the embodiments of the present disclosure. In some embodiments, the number of bits of the data is multiple bits; the latch module 101 includes: a multiplexed latch unit 11, and each latch unit 11 is used to latch one bit of the data read from the anti-fuse memory array; the transmission module 102 includes: a plurality of transmission units 12, each transmission unit 12 is connected to the output end of a corresponding latch unit 11, and each transmission unit 12 responds to different read test commands RD, and respectively transmits one bit of the data latched in the corresponding latch unit 11 to the data port 103. The different read test commands RD received by each transmission unit 12 refer to different timings of the read test command RD. The multiplexed latch unit 11 is provided to latch more data in the anti-fuse memory array. By setting the corresponding connection between the multiplexed latch unit 11 and the transmission unit 12, the data in the multi-bit latch module 101 can be transmitted to the data port 103 for testing. Each time the transmission unit 12 receives a read test command RD, it transmits one bit of the data in the latch unit 11 to the data port 103, and by setting different timings of the read test commands RD received by each transmission unit 12, each transmission unit 12 transmits the data latched in the latch unit 11 to the data port 103 one by one according to different timings. In this way, the data in the data port 103 can be tested individually, making the test result more accurate.

[0044] Reference Figure 3 , Figure 3 FIG. is a timing diagram of a read test command provided by the embodiments of the present disclosure. In some embodiments, taking the number of bits of the data read from the anti-fuse memory array as 8 bits as an example, among them, the read test commands RD corresponding to different transmission units 12 are respectively denoted as: RD0, RD1,... RD7. Different timings of the read test commands RD corresponding to each transmission unit 12 can avoid the problem that different transmission units 12 simultaneously transmit one bit of data in different latch units 11 to the data port 103, so that each time only one bit of data in the data port DQ can be tested, ensuring the accuracy of the test result. Specifically, in some embodiments, the read test command RD can be provided by a read test command generation module. In other embodiments, the read test command RD can also be provided by an external circuit.

[0045] Reference Figure 4 , Figure 4A circuit diagram of the anti-fuse readout circuit provided by the embodiments of the present disclosure. In some embodiments, the latch unit 11 includes: a first switch transistor 1, which receives one-bit data and conducts in response to a position strobe signal, so that the output end of the first switch transistor 1 outputs one-bit data; a latch circuit 13, the output end of the latch circuit 13 is connected to the transmission unit 12, and the input end of the latch circuit 13 is connected to the output end of the first switch transistor 1. In some embodiments, there are multiple latch units 11. Taking the number of bits of the data read out from the anti-fuse memory array being 8 bits as an example, among them, the position strobe signals corresponding to different latch units 11 are respectively denoted as: Load<0>, Load<1>......Load<7>; the one-bit data received by different latch units 11 are respectively denoted as: FsBit<0>, FsBit<1>......FsBit<7>. The input end of the latch circuit 13 is connected to the output end of the first switch transistor 1 to receive the one-bit data output from the output end of the first switch transistor 1 and latch it. The output end of the latch circuit 13 is connected to the transmission unit 12. When the transmission unit 12 conducts, the data latched in the latch circuit 13 can be transmitted to the data port 103 via the transmission unit 12. In some embodiments, the latch circuit 13 can be composed of 2 inverters connected end to end.

[0046] In some embodiments, it further includes: a broadcast path unit. The input end of the broadcast path unit is connected to the anti-fuse memory array, and the output end of the broadcast path unit is connected to the input end of the latch unit 11. One-bit data in the anti-fuse memory array is transmitted to the first switch transistor 1 via the broadcast path unit, and the position strobe signal can be generated by the broadcast path unit. Specifically, in some embodiments, the position strobe signal is at a high level, the first switch transistor 1 conducts, and at the same time, the one-bit data corresponding to the position strobe signal is transmitted to the first switch transistor 1 via the broadcast path unit.

[0047] In some embodiments, taking the position strobe signal as Load<0> as an example, when Load<0> is at a high level, the first switch transistor 1 conducts and transmits FsBit<0> to the latch circuit 13; when Load<0> is at a low level, the first switch transistor 1 is cut off, and FsBit<0> cannot be transmitted to the latch circuit 13 through the first switch transistor 1. It can be understood that in some other embodiments, when Load<0> is at a low level, the first switch transistor 1 conducts; when Load<0> is at a high level, the first switch transistor 1 is cut off. In some embodiments, after FsBit<0> is transmitted to the latch circuit 13, when the read test signal is at a high level, the transmission module 102 conducts, and FsBit<0> can be transmitted to the data port 103 via the transmission module 102; when the read test command RD is at a low level, the transmission module 102 is cut off, and FsBit<0> cannot be transmitted to the data port 103 through the transmission module 102.

[0048] In some embodiments, the first switching transistor 1 is a first transmission gate. The first control terminal of the first transmission gate receives a position strobe signal, and the input terminal of the first transmission gate receives a single-bit data. The latch unit 11 further includes: a first inverter 2. The input terminal of the first inverter 2 receives the position strobe signal, and the output terminal of the first inverter 2 is connected to the second control terminal of the first transmission gate. The first transmission gate and the first inverter 2 together form an analog switch and conduct in response to the position strobe signal. Taking the position strobe signal as Load<0> as an example, when Load<0> is at a high level, the first control terminal of the first transmission gate receives a high level corresponding to the logic "1", the input terminal of the first inverter 2 receives a high level corresponding to the logic "1", and the output terminal of the first inverter 2 outputs a low level corresponding to the logic "0". Since the output terminal of the first inverter 2 is connected to the second control terminal of the first transmission gate, the second control terminal of the first transmission gate receives a low level corresponding to the logic "0", the first transmission gate conducts, and FsBit<0> is transmitted to the latch circuit 13. In other embodiments, the first switching transistor 1 may also be other logic gate circuits. For example, it may be a PMOS transistor or an NMOS transistor. When the logic circuit is a PMOS transistor or an NMOS transistor, the gate of the PMOS transistor or the NMOS transistor is connected to the latch circuit 13 and conducts in response to the position strobe signal.

[0049] In some embodiments, the transmission unit 12 includes: a second switching transistor 3. The second switching transistor 3 conducts in response to a read test command RD to transmit a single-bit data to the data port 103. Taking the read test command RD as RD0 as an example, when RD0 is at a high level, the second switching transistor 3 conducts and transmits FsBit<0> to the data port 103; when RD0 is at a low level, the second switching transistor 3 is cut off, and FsBit<0> cannot be transmitted to the data port 103 through the first switching transistor 1. It can be understood that in other embodiments, when RD0 is at a low level, the second switching transistor 3 conducts; when RD0 is at a high level, the second switching transistor 3 is cut off.

[0050] In some embodiments, the second switching transistor 3 includes a second transmission gate. The first control end of the second transmission gate receives a read test command RD, and the input end of the second transmission gate receives one-bit data. The transmission unit 12 further includes: a second inverter 4. The input end of the second inverter 4 receives the read test command RD, and the output end of the second inverter 4 is connected to the second control end of the second transmission gate. The second transmission gate and the second inverter 4 together form an analog switch and conduct in response to the read test command RD. Taking the read test command RD as RD0 as an example, when RD0 is at a high level, the first control end of the second transmission gate receives a high level with a corresponding logic of "1", the input end of the second inverter 4 receives a high level with a corresponding logic of "1", and the output end of the second inverter 4 outputs a low level with a corresponding logic of "0". Since the output end of the second inverter 4 is connected to the second control end of the second transmission gate, the second control end of the second transmission gate receives a low level with a corresponding logic of "0", the second transmission gate conducts, and FsBit<0> is transmitted to the data port 103. In some other embodiments, the second switching transistor 3 may also be other logic gate circuits. For example, it may be a PMOS transistor or an NMOS transistor. When the logic circuit is a PMOS transistor or an NMOS transistor, the gate of the PMOS transistor or the NMOS transistor conducts in response to the position strobe signal, and one-bit data is transmitted to the data port 103.

[0051] In some embodiments, it further includes: a buffer module 104, which is arranged between the output end of the transmission module 102 and the data port 103. The buffer module 104 plays a delaying role, that is, compared with not setting the buffer module 104, setting the buffer module 104 makes the time taken for the transmission module 102 to transmit one-bit data to the data port 103 longer. In this way, a longer time is reserved for collecting and testing one-bit data in the data port 103 during the test phase, so that the test can proceed orderly.

[0052] Specifically, in some embodiments, the buffer module 104 includes an even number of inverters connected in series. The input terminal of the first inverter is connected to the output terminal of the transmission module 102, and the output terminal of the last inverter is connected to the data port 103. Setting an even number of inverters connected in series as the buffer module 104 enables one-bit data to still be transmitted to the data port 103 after passing through the buffer module 104. For example, when the input terminal of the first inverter receives a high level with a corresponding logic of "1", the output terminal of the first inverter outputs a low level with a corresponding logic of "0". Since an even number of inverters are connected in series, thus, the logic level corresponding to the output terminal of the last inverter is still "1", that is, the input terminal of the data port 103 still receives a high level with a corresponding logic of "1". Since an even number of inverters are set, the transmission speed of one-bit data becomes slower, thereby reserving a buffer time for testing one-bit data in the data port 103 during the test phase. In addition, setting inverters in the circuit makes the circuit structure simple and occupies a relatively small chip area. It can be understood that in some embodiments, the number of inverters can be set according to different readout circuit requirements, thereby adjusting the length of the buffer time. In other embodiments, the buffer module 104 can also be set as other logic gate circuits, for example, it can be any one of PMOS transistors or NMOS transistors.

[0053] In some embodiments, it further includes: a comparison module 105. The comparison module 105 is connected to the output end of the latch module 101 and is used to compare whether the data latched by the latch module 101 matches the current address information. The input end of the comparison module 105 is connected to the output end of the latch module 101 and is used to receive one bit of data latched in the latch module 101. The other input end of the latch module 101 is further used to receive the current address information and match the one bit of data with the current address information. In some embodiments, the data in the antifuse memory array is the address information of defective memory cells, for example, it can be the address information of defective addresses in DRAM memory cells. If the comparison module 105 compares that one bit of data matches the current address information, it indicates that the address corresponding to the current address information is a defective address, so that the defective address can be replaced, enabling the memory cell to work properly. Since the transmission module 102 is provided in the antifuse readout circuit, during the test phase, the transmission module 102 can transmit the data in the latch module 101 to the data port 103 one by one, and then test the data in the data port 103 one by one to test the accuracy of the data latched in the latch module 101, making the data accuracy in the latch module 101 relatively high. Therefore, by setting the comparison module 105 in the same readout circuit and comparing the data tested in the latch module 101 with the current address information, the accuracy of the comparison result is relatively high, so that the defective address in the memory cell can be found more accurately, ensuring the normal operation of the memory cell and maintaining good performance of the memory cell.

[0054] In some embodiments, the comparison module 105 includes a plurality of comparison units 14. The input end of each comparison unit 14 is connected to the output end of a latch unit 11 and is used to receive one bit of data latched in the latch unit 11 and compare it with the current address information. A plurality of comparison units 14 are set to be connected to the latch units 11 in a one-to-one correspondence, so that each comparison unit 14 can simultaneously receive one bit of data latched in the corresponding latch unit 11, making the working efficiency of the comparison module 105 relatively high.

[0055] In some embodiments, the comparison module 105 includes: an exclusive-NOR gate, one input terminal of the exclusive-NOR gate is connected to the output terminal of the latch module 101, and the other input terminal of the exclusive-NOR gate receives the current address information. The working principle of the exclusive-NOR gate is as follows: when both input terminals of the exclusive-NOR gate receive a high level or both receive a low level, the output is high level; if one input terminal of the exclusive-NOR gate receives a high level and the other input terminal receives a low level, the output is low level. Using the working principle of the exclusive-NOR gate, when a bit of data in the latch module 101 received by one input terminal of the exclusive-NOR gate has the same logic level as the current address received by the other input terminal of the exclusive-NOR gate, the exclusive-NOR gate outputs a high level, and it is considered that a bit of data received in the latch module 101 matches the current address information; when a bit of data in the latch module 101 received by one input terminal of the exclusive-NOR gate has the opposite logic level to the current address received by the other input terminal of the exclusive-NOR gate, the exclusive-NOR gate outputs a low level, and it is considered that a bit of data received in the latch module 101 does not match the current address information. In some embodiments, the current address information received by the exclusive-NOR gate can be provided by an external circuit; in other embodiments, the current address information received by the exclusive-NOR gate can also be provided by an address signal generation module of the memory.

[0056] In some embodiments, the comparison module 105 includes a plurality of comparison units 14. The input end of each comparison unit 14 is connected to the output end of a latch unit 11. In some embodiments, taking the number of bits of the data read from the antifuse memory array as 8 bits as an example, the current address information corresponding to each comparison unit 14 is denoted as: ADDR<0>, ADDR<1>......ADDR<7>. Taking the current address information as ADDR<0> as an example, one input end of the XNOR gate receives FsBit<0> with a corresponding logic level of "1", and the other input end of the XNOR gate receives ADDR<0> with a corresponding logic level of "1". If the XNOR gate outputs a high level with a logic level of "1", then FsBit<0> matches ADDR<0>; or one input end of the XNOR gate receives FsBit<0> with a corresponding logic level of "0", and the other input end of the XNOR gate receives ADDR<0> with a corresponding logic level of "0". If the XNOR gate outputs a high level with a logic level of "1", then it is considered that FsBit<0> matches ADDR<0>; one input end of the XNOR gate receives FsBit<0> with a corresponding logic level of "0", and the other input end of the XNOR gate receives ADDR<0> with a corresponding logic level of "1". If the XNOR gate outputs a high level with a logic level of "0", then it is considered that FsBit<0> does not match ADDR<0>; one input end of the XNOR gate receives FsBit<0> with a corresponding logic level of "1", and the other input end of the XNOR gate receives ADDR<0> with a corresponding logic level of "0". If the XNOR gate outputs a high level with a logic level of "0", then it is considered that FsBit<0> does not match ADDR<0>.

[0057] It can be understood that in some other embodiments, the comparison module 105 can also be other logic gate circuits, as long as it satisfies that the comparison module 105 can compare whether the data latched by the latch module 101 matches the current address information.

[0058] In some embodiments, the transmission module 102 is further configured to transmit the data latched in the latch module 101 to the same data port 103. That is to say, when the latch module 101 includes a plurality of latch units 11 and the transmission module 102 includes a plurality of transmission units 12, each transmission unit 12 is connected to the same data port 103, and the data latched in each latch unit 11 is transmitted to the same data port 103 one by one. In this way, when it is necessary to test the data latched in the latch unit 11, it is only necessary to collect and test the data in the same data port 103 one by one.

[0059] Reference Figure 5 , Figure 5Circuit diagram of another anti-fuse readout circuit provided by an embodiment of the present disclosure. In some embodiments, the anti-fuse readout circuit includes a plurality of latch modules 101 and a plurality of transmission modules 102; it further includes: a selection module 106, the selection module 106 is connected to the output ends of the plurality of transmission modules 102, and the selection module 106 is configured to select the data output by one of the transmission modules 102 and transmit it to the data port 103. During the test phase, when the selection module 106 is turned on, the selection module 106 transmits the data output by one of the transmission modules 102 to the data port 103. By setting the selection module 106, when there are a plurality of latch modules 101 and transmission modules 102 in the circuit, during the test phase, the data in different latch modules 101 can be transmitted to the same data port 103 one by one through the transmission modules 102. In this way, not only is it beneficial to improve the accuracy of the test results, but also in the same circuit, more data in the anti-fuse memory array can be tested, which is beneficial to improving the test efficiency.

[0060] In some embodiments, the selection module 106 may include: a plurality of selection output units 15, each selection output unit 15 corresponds to a transmission module 102, and the selection output unit 15 outputs the data transmitted by the transmission module 102 in response to a selection signal; a switch unit 16, the switch unit 16 is connected between the output end of the selection output unit 15 and the data port 103, and the switch unit 16 is configured to transmit the data output by the selection output unit 15 to the data port 103. The switch unit 16 is provided between the selection transmission unit 12 and the data port 103, that is, the data transmitted by the transmission module 102 needs to pass through the selection output unit 15 and the switch unit 16 and then be transmitted to the data port 103. By setting the switch unit 16, when one of the selection transmission units 12 transmits the data in the transmission module 102 to the data port 103 based on the selection signal, the switch unit 16 connected to the selection transmission unit 12 that has not received the selection signal can filter out the logic signal corresponding to the data in the corresponding transmission module 102, so that the data currently transmitted to the data port 103 is only the data in the transmission module 102 selected based on the selection signal, enabling the data in different transmission modules 102 to be transmitted to the data port 103 one by one for testing, thus making the test results more accurate. In some embodiments, the selection signal may be provided by an external circuit; in other embodiments, the selection signal may also be provided by the internal circuit of the memory, for example, it may be provided by a selection signal generation module. It can be understood that, in other embodiments, the selection module 106 may also be other logic gate circuits, such as a MUX (Multiplexer, data selector).

[0061] In some embodiments, the selection output unit 15 includes an AND gate circuit. One input terminal of the AND gate circuit receives a selection signal, and the other input terminal receives the data output by the transmission module 102. The working principle of the AND gate circuit is as follows: when high levels are received at both input terminals of the AND gate circuit, the output is high level; if a low level is received at one of the input terminals of the AND gate circuit, the output is low level. Utilizing the working principle of the AND gate circuit, when a high-level bit of data in the transmission module 102 is received at one input terminal of the AND gate circuit, and when the selection signal is high level, a high-level selection signal is received at the other input terminal of the AND gate circuit, the AND gate circuit outputs high level, the switch unit 16 receives high level, connects the selection transmission unit 12 and the data port 103, and transmits one bit of data to the data port 103.

[0062] In some embodiments, the switch unit 16 may include: an OR gate circuit connected in multiple stages. Each stage of the OR gate circuit corresponds to a selection output unit 15. One input terminal of the OR gate circuit is connected to the output terminal of the corresponding selection output unit 15; wherein, the other input terminal of the OR gate circuit at the first stage is grounded, the output terminal of the OR gate circuit at the last stage is connected to the data port 103, and the output terminal of the previous stage of the OR gate circuit is connected to one input terminal of the next stage of the OR gate circuit. The working principle of the OR gate circuit is as follows: when a high level is received at any one of the input terminals of the OR gate circuit, the output terminal of the OR gate circuit outputs high level; if low levels are received at both input terminals of the OR gate circuit, the output terminal of the OR gate circuit outputs low level. Utilizing the working principle of the OR gate circuit, in some embodiments, when the selection output unit 15 is an AND gate, the selection signal is high level, one bit of data in the transmission module 102 is high level, and the output terminal of the selection output unit 15 outputs high level. Thus, the input terminal of the OR gate circuit receives high level, and the output terminal of the OR gate circuit outputs high level. Thus, one bit of high-level data can be transmitted to the data port 103.

[0063] A multi - level OR gate circuit is set, and the output terminal of the previous - stage OR gate circuit is connected to an input terminal of the next - stage OR gate circuit. Thus, when the selection output unit 15 connected to the input terminal of the previous - stage OR gate circuit transfers one - bit data in the transmission module 102 to the previous - stage OR gate circuit based on the selection signal, since the output terminal of the previous - stage OR gate circuit is connected to the input terminal of the next - stage OR gate circuit, the previous - stage OR gate circuit can transfer one - bit data to the data port 103 through the next - stage OR gate circuit. In other words, as long as any one of the multiple selection output units 15 receives a high - level selection signal, the OR gate circuit connected to this selection output unit 15 outputs a high level. Since the output terminal of the previous - stage OR gate circuit is connected to the input terminal of the next - stage OR gate circuit, therefore, one input terminal of each OR gate circuit receives a high - level selection signal, thereby transferring one - bit data to the data port 103. For other selection output units 15 that do not receive a high - level selection signal, the output terminal of the selection output unit 15 is at a low level. At this time, one input terminal of the OR gate circuit adjacent to this selection output unit 15 inputs a low level, and the other input terminal inputs a high level. The output terminal of the OR gate circuit still outputs a high level, that is, the logic signal output by the selection output unit 15 that does not respond to the selection signal can be filtered out, so that only one - bit data output by the selection output unit 15 that responds to the selection signal is transferred to the data port 103. Thus, when testing the data in the data port 103, the test result is more accurate.

[0064] Specifically, in some embodiments, taking the number of bits of the data read out from the antifuse memory array as 8 bits as an example, the selection output units 15 corresponding to each transmission module 102 are denoted as: SEL<0>, SEL<1>......SEL<7>, and the switch units 16 corresponding to each selection output unit 15 are denoted as: S<0>, S<1>......S<7>. Taking SEL<0> and SEL<1> as examples, one input terminal of SEL<0> receives a selection signal with a corresponding logic level of "1", the other input terminal of SEL<0> receives FsBit<0> with a corresponding logic level of "1", the output terminal of SEL<0> outputs a high level with a corresponding logic level of "1", one input terminal of S<0> receives a high level with a corresponding logic level of "1", and the output terminal of S<0> outputs a high level with a corresponding logic level of "1". One input terminal of SEL<1> receives a selection signal with a corresponding logic level of "0", the output terminal of SEL<1> outputs a selection signal with a corresponding logic level of "0", the other input terminal of S<1> receives the selection signal with a corresponding logic level of "0" from SEL<1>. Since one input terminal of S<1> receives the high level with a corresponding logic level of "1" from S<0>, the output terminal of S<1> outputs a high level with a corresponding logic of "1", that is, S<1> can filter out the low level with a corresponding logic level of "0" output from the output terminal of SEL<1>, so that the data transmitted to the data port 103 has a corresponding logic level of "1".

[0065] In some embodiments, the OR gate circuit may include: a NOR gate circuit, one input terminal of the NOR gate circuit is connected to the output terminal of the corresponding selection output unit 15; a NOT gate circuit, the input terminal of the NOT gate circuit is connected to the output terminal of the NOR gate circuit, and the output terminal of the NOT gate circuit is connected to the input terminal of the NOR gate circuit of the next-stage OR gate. The working principle of the NOR gate circuit is: when any one of the input terminals of the NOR gate circuit receives a high level, the output terminal of the NOR gate circuit outputs a low level; if both input terminals of the NOR gate circuit receive low levels, the output terminal of the NOR gate circuit outputs a high level. The working principle of the NOT gate circuit is: when the input terminal of the NOT gate circuit receives a low level, the output terminal of the NOT gate circuit outputs a high level; when the input terminal of the NOT gate circuit receives a high level, the output terminal of the NOT gate circuit outputs a low level. By using the working principles of the NOR gate circuit and the NOT gate circuit, when the OR gate circuit receives the connection of the NOR gate circuit and the NOT gate circuit, the NOR gate circuit and the NOT gate circuit together play the role of an OR gate.

[0066] In some other embodiments, the switch unit 16 may also include: an OR gate circuit, outputs of multiple selection output units 15 are all connected to an input end of the OR gate circuit, and an output end of the OR gate circuit is connected to the data port 103. That is, only one OR gate circuit can be used to function as an OR gate. The number of input ends of the OR gate circuit is the same as the number of selection output units 15, so as to connect the data port 103 to the selection output unit 15 that outputs data, enabling one bit of data in the transmission module 102 to be transmitted to the data port 103.

[0067] In the technical solution of the antifuse readout circuit provided by the above disclosed embodiments, it includes: a latch module 101, and the latch module 101 is used to latch the data read from the antifuse storage array; a transmission module 102, the transmission module 102 is connected to an output end of the latch module 101 and is configured to, in response to a read test command RD, transmit the data latched in the latch module 101 to the data port 103. By adding the transmission module 102 in the readout circuit, the data latched in the latch module 101 can be transmitted to the data port 103 through the transmission module 102. In this way, during the test phase, the data in the data port 103 comes from the latch module 101, which is equivalent to collecting the data in the latch module 101, making the test result of the data in the data port 103 can truly reflect whether the data in the latch module 101 is accurate and improving the authenticity of the test result.

[0068] Correspondingly, the present disclosure embodiments also provide an antifuse memory, referring to Figure 6 , Figure 6 is a schematic structural diagram of an antifuse memory provided by the present disclosure embodiments. The antifuse memory includes: an antifuse storage array 10; the antifuse readout circuit provided by any of the above embodiments. The antifuse storage array 10 is used to store data. Among them, the data stored in the antifuse storage array 10 may include: address information of storage units with defects. The data in the antifuse storage unit can be transmitted to the latch module 101 in the antifuse readout circuit through the broadcast path unit for latching. The transmission module 102 connected to the latch module 101 transmits the data latched in the latch module 101 to the data port 103 in response to a read test command RD. In this way, during the test phase, the data in the data port 103 comes from the latch module 101, which is equivalent to collecting the data latched in the latch module 101, making the test result of the data in the data port 103 can truly reflect the accuracy of the data latched in the latch module 101. Therefore, when the data latched in the latch module 101 is used to compare with the storage unit address information in the memory, the comparison result can be relatively accurate, enabling the memory to work properly and maintaining good performance of the memory.

[0069] Accordingly, the embodiments of the present disclosure further provide a test method. The test method can use the anti-fuse readout circuit provided in any of the above embodiments for testing. Refer to Figure 7 , Figure 7 which is a schematic flowchart of a test method provided by the embodiments of the present disclosure, including:

[0070] Step 110: Read data from the anti-fuse memory array 10 (refer to Figure 6 ) and latch the data. In some embodiments, it further includes: a broadcast path unit 20. The input end of the broadcast path unit 20 is connected to the anti-fuse memory array 10, and the output end of the broadcast path unit 20 is connected to the input end of the latch unit 11. One bit of data in the anti-fuse memory array 10 is transmitted to the latch module 101 via the broadcast path unit 20 for latching.

[0071] Step 120: In response to a read test command RD (refer to Figure 4 ), transmit the latched data to the data port 103 (refer to Figure 4 ). Specifically, in the test stage, the data in the latch module 101 (refer to Figure 4 ) can be transmitted to the data port 103 through the transmission module 102 (refer to Figure 4 ). In some embodiments, when the read test command RD is at a high level, the transmission module 102 is turned on, and the data in the latch module 101 can be transmitted to the data port 103 via the transmission module 102; when the read test command RD is at a low level, the transmission module 102 is cut off, and the data in the latch module 101 cannot be transmitted to the data port 103 through the transmission module 102. In this way, in the test stage, the transmission module 102 can respond to the read test command RD to transmit the data in the latch module 101 to the data port 103 for testing. In some other embodiments, it can also be that when the read test command RD is at a low level, the latch module 101 is turned on, and when the read test command RD is at a high level, the latch module 101 is cut off.

[0072] In some embodiments, transmitting the latched data to the data port 103 includes: in response to different read test commands RD, transmitting one bit of the data to the data port 103 each time. Specifically, in the test stage, each time the transmission module 102 receives a read test command RD, one bit of data in the latch module 101 is transmitted to the data port 103, and by setting the timing of each read test command RD received by each transmission module 102 to be different, each transmission module 102 transmits the latched data in the latch module 101 to the data port 103 one by one according to different timings. In this way, the data in the data port 103 can be tested separately, making the test result more accurate.

[0073] Step 130: Determine whether the data transmitted to data port 103 meets the expectation. In some embodiments, during the test phase, after the data in latch module 101 is transmitted to data port 103, the data in data port 103 is collected and compared with the data to be compared. Herein, the data to be compared may be correct or defective address information. If the collected data is different from the data to be compared, it is considered that the data transmitted to data port 103 does not meet the expectation. If the collected data is the same as the data to be compared, it is considered that the data transmitted to data port 103 meets the expectation. Specifically, in some embodiments, an external tester may be used to collect the data transmitted to data port 103 and compare it with the data to be compared. In other embodiments, an engineer may also manually collect the data transmitted to data port 103 and compare it with the data to be compared.

[0074] In some embodiments, there are multiple latch modules 101 and transmission modules 102; transmitting the latched data to data port 103 includes: in response to a selection signal, transmitting the data latched by one latch module 101 to data port 103 each time. In some embodiments, the antifuse readout circuit further includes: a selection module 106 (refer to Figure 5 ), and the selection module 106 responds to the selection signal and selects the data output by one of the transmission modules 102 to be transmitted to data port 103. Specifically, in some embodiments, during the test phase, when the selection signal is at a high level, the selection module 106 is turned on, and the selection module 106 transmits the data output by one of the transmission modules 102 to data port 103. Thus, when there are multiple latch modules 101 and transmission modules 102 in the circuit, the data in different latch modules 101 can be transmitted to the same data port 103 one by one through the transmission modules 102 for orderly testing, which is beneficial to improving the accuracy of the test results. In addition, it also enables more data in the antifuse memory array 10 to be tested in the same circuit, which is beneficial to improving the test efficiency.

[0075] In the test method provided by the above disclosed embodiments, the data is read from the antifuse memory array 10 and latched; in response to the read test command RD, the latched data is transmitted to data port 103; it is determined whether the data transmitted to data port 103 meets the expectation, that is, the data in data port 103 is tested. That is to say, during the test phase, it is equivalent to collecting and testing the data in latch module 101, so that the test result of the data in data port 103 during the test phase can more truly reflect the accuracy of the data in latch module 101. Thus, if the data latched in latch module 101 is subsequently used to compare with the storage unit address information in the memory, the reliability of the comparison result can be improved.

[0076] Those of ordinary skill in the art can understand that the above-described embodiments are specific examples for implementing the present disclosure. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. An anti-fuse readout circuit, characterized in that Comprising: A latch module for latching data read from an antifuse memory array; the latch module includes a multiplexed latch unit, and each latch unit is used to latch one bit of the data read from the antifuse memory array; A transmission module connected to the output end of the latch module and configured to transmit the data latched in the latch module to a data port in response to a read test command; the transmission module includes a plurality of transmission units, each transmission unit is connected to the output end of a corresponding latch unit, and each transmission unit transmits the one bit of data latched in the corresponding latch unit to the data port respectively in response to different read test commands; Wherein, the latch unit includes: A first switching transistor that receives the one bit of data and conducts in response to a position strobe signal, so that the output end of the first switching transistor outputs the one bit of data; A latch circuit, the output end of the latch circuit is connected to the transmission unit, and the input end of the latch circuit is connected to the output end of the first switching transistor.

2. The anti-fuse readout circuit according to claim 1, wherein The first switching transistor is a first transmission gate, the first control end of the first transmission gate receives the position strobe signal, and the input end of the first transmission gate receives the one bit of data; The latch unit further includes: a first inverter, the input end of the first inverter receives the position strobe signal, and the output end of the first inverter is connected to the second control end of the first transmission gate.

3. The antifuse readout circuit according to claim 1, wherein The transmission unit includes: a second switching transistor that conducts in response to the read test command to transmit the one bit of data to the data port.

4. The antifuse readout circuit according to claim 3, wherein The second switching transistor includes a second transmission gate, the first control end of the second transmission gate receives the read test command, and the input end of the second transmission gate receives the one bit of data; The transmission unit further includes: a second inverter, the input end of the second inverter receives the read test command, and the output end of the second inverter is connected to the second control end of the second transmission gate.

5. The anti-fuse readout circuit according to claim 1, characterized in that, Further comprising: A buffer module disposed between the output end of the transmission module and the data port.

6. The antifuse readout circuit according to claim 5, characterized in that, The buffer module includes an even number of inverters connected in series, and the input end of the inverter at the first position is connected to the output end of the transmission module, and the output end of the inverter at the last position is connected to the data port.

7. The anti-fuse readout circuit according to claim 1, characterized in that, Further comprising: A comparison module connected to the output end of the latch module for comparing whether the data latched by the latch module matches the current address information.

8. The anti-fuse readout circuit according to claim 7, wherein The comparison module includes: an exclusive-NOR gate, one input end of the exclusive-NOR gate is connected to the output end of the latch module, and the other input end of the exclusive-NOR gate receives the current address information.

9. The antifuse readout circuit according to claim 1, wherein, The transmission module is further configured to transmit the data latched in the latch module to the same data port.

10. The anti-fuse readout circuit according to any one of claims 1-9, characterized in that, The antifuse readout circuit includes a plurality of the latch modules and a plurality of the transmission modules; further comprising: A selection module, the selection module is connected to the output ends of a plurality of the transmission modules, and the selection module is configured to select the data output by one of the transmission modules and transmit it to the data port.

11. The anti-fuse readout circuit according to claim 10, wherein The selection module includes: a plurality of selection output units, each selection output unit corresponding to one of the transmission modules, the selection output unit outputting the data transmitted by the transmission module in response to a selection signal; a switching unit, the switching unit being connected between the output ends of the plurality of selection output units and the data port, the switching unit being configured to transmit the data output by the selection output unit to the data port.

12. The antifuse readout circuit according to claim 11, characterized in that, The selection output unit includes an AND gate circuit, one input end of the AND gate circuit receiving the selection signal, and the other input end receiving the data output by the transmission module.

13. The anti-fuse readout circuit according to claim 11, characterized in that, The switching unit includes: OR gate circuits connected in multiple stages, each stage of the OR gate circuit corresponding to one of the selection output units, one input end of the OR gate circuit being connected to the output end of the corresponding selection output unit; wherein, the other input end of the OR gate circuit at the first stage is grounded, the output end of the OR gate circuit at the last stage is connected to the data port, and the output end of the previous stage of the OR gate circuit is connected to one input end of the next stage of the OR gate circuit.

14. The antifuse readout circuit according to claim 13, characterized in that, The OR gate circuit includes: a NOR gate circuit, one input end of the NOR gate circuit being connected to the output end of the corresponding selection output unit; a NOT gate circuit, the input end of the NOT gate circuit being connected to the output end of the NOR gate circuit, and the output end of the NOT gate circuit being connected to the input end of the NOR gate circuit of the next stage of the OR gate.

15. The antifuse readout circuit according to claim 11, characterized in that, The switching unit includes: an OR gate circuit, the output ends of the plurality of selection output units being connected to the input end of the OR gate circuit, and the output end of the OR gate circuit being connected to the data port.

16. An anti-fuse memory, characterized in that, including: an anti-fuse memory array; the anti-fuse readout circuit according to any one of claims 1-15.

17. A test method using the anti-fuse readout circuit described in any one of claims 1-15 for testing, characterized in that, including: reading data from the anti-fuse memory array and latching the data; in response to a read test command, transmitting the latched data to a data port; judging whether the data transmitted to the data port meets the expectation.

18. The test method according to claim 17, characterized in that, The transmitting the latched data to the data port includes: in response to different read test commands, transmitting one bit of the data to the data port each time.

19. The test method according to claim 17, characterized in that, Both the latching module and the transmission module are multiple; the transmitting the latched data to the data port includes: in response to a selection signal, transmitting the data latched by one of the latching modules to the data port each time.

Images