Nor flash verification method, device, equipment and storage medium

Abstract

The present invention relates to the field of memory chip technology, and specifically discloses a verification method, device, equipment and storage medium for Nor flash, wherein the verification method comprises the steps of: constructing a simple storage model according to the memory array of Nor flash, wherein the simple storage model is based on the local bit line group and the storage cells corresponding to all word lines, wherein the local bit line group only includes the second bit line on each word line; i The verification method only retains the verification item simulation of the storage cells corresponding to the edge part of the storage array and the address that conforms to the growth law, ensuring that the verification process covers the checkpoints required for verification while completing more functional verification items in a limited time, greatly improving the verification efficiency.

Description

Technical Field

[0001] The present application relates to the field of memory chip technology, and in particular to a verification method, apparatus, device, and storage medium for Nor flash. Background Art

[0002] Nor flash is a non-volatile memory whose storage cells can be erased, reprogrammed, and read. During the chip design process, the designed chip undergoes multiple rigorous tests to verify its functional correctness. This verification process is generally carried out through simulation testing. The verification process must ensure that the chip can correctly execute each test command. The verification results are generally obtained based on the stored data in the chip's memory array model.

[0003] However, as chip size increases, more and more memory cells need to be verified to be fully functional, which causes the time required for verification to increase exponentially. However, in the actual verification process, it is found that when the verification results are wrong, the data of the memory cells at specific locations in the storage array model will not be wrong or will not be wrong individually. The simulation verification process of these partial memory cells is redundant work.

[0004] There is currently no effective technical solution to the above problems. Summary of the Invention

[0005] The purpose of this application is to provide a verification method, device, equipment and storage medium for Nor flash, so as to establish a simple storage model for simulation verification, thereby improving verification efficiency.

[0006] In a first aspect, the present application provides a verification method for Nor flash, which is used to simulate Nor flash to perform functional verification on a design to be tested, the method comprising the following steps:

[0007] A simple storage model is constructed based on the storage array of the Nor flash. The simple storage model is composed of storage cells corresponding to a local bit line group and all word lines. The local bit line group only includes the second bit line on each word line. i The bit lines corresponding to the first and last bytes, i = 0, 1, ..., n, where n is an integer greater than 1;

[0008] The simple storage model is used to perform functional verification on the design to be tested.

[0009] The verification method of the Nor flash of the present application constructs a simple storage model based on the specifications of the storage array, and only retains the verification item simulation for the storage cells corresponding to the edge part of the storage array and the addresses that conform to the growth law, ensuring that the verification process covers the checkpoints required for verification while greatly improving the verification efficiency.

[0010] The verification method of the Nor flash, wherein the step of performing functional verification on the design to be tested using the simple storage model comprises:

[0011] Simulating a reference model based on a preset test stimulus to generate a first test result, and simulating the design to be tested using the simple storage model based on the test stimulus to generate a second test result;

[0012] The first test result and the second test result are compared to generate a verification result.

[0013] The method of this example can determine whether the simulation of the design to be tested runs normally based on the comparison of the first test result and the second test result, that is, determine whether the corresponding verification item passes to generate a verification result.

[0014] The verification method of the Nor flash, wherein the step of simulating the reference model based on a preset test stimulus to generate a first test result includes:

[0015] Simulate the reference model based on the preset test stimulus;

[0016] According to the storage unit distribution characteristics of the simple storage model, data of corresponding storage units in the reference model after the simulation is completed is extracted as the first test result.

[0017] The method of this example obtains the first test result of the data specification and format corresponding to the simple storage model from the reference model according to the storage unit distribution characteristics of the simple storage model, so as to directly compare the data with the second test result, simplify the verification result generation process and improve the verification efficiency.

[0018] The verification method of the Nor flash, wherein each word line in the storage array has 2 n bytes of data.

[0019] The verification method of Nor flash, wherein the simple storage model includes multiple storage blocks.

[0020] The verification method of the Nor flash, wherein each of the storage blocks has 4 word lines.

[0021] In the verification method of the Nor flash, the simple storage model is a two-dimensional array model including binary data or a two-dimensional array model including threshold voltage values or a storage cell model established based on MOS tubes.

[0022] In a second aspect, the present application further provides a Nor flash verification device for simulating Nor flash to perform functional verification on a design to be tested, the device comprising:

[0023] A construction module is used to construct a simple storage model according to the storage array of the Nor flash, wherein the simple storage model is composed of storage cells corresponding to a local bit line group and all word lines, wherein the local bit line group only includes the second bit line on each word line. i The bit lines corresponding to the first and last bytes, i=0, 1, 2, ..., n-1, n, where n is an integer greater than 1;

[0024] A verification module is used to perform functional verification on the design to be tested using the simple storage model.

[0025] The verification device of the Nor flash of the present application builds a simple storage model based on the specifications of the storage array, and only retains the verification item simulation of the storage cells corresponding to the edge part of the storage array and the addresses that conform to the growth law, ensuring that the verification process covers the checkpoints required for verification while greatly improving the verification efficiency.

[0026] In a third aspect, the present application further provides an electronic device comprising a processor and a memory, wherein the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the steps of the method provided in the first aspect are executed.

[0027] In a fourth aspect, the present application further provides a storage medium having a computer program stored thereon, which, when executed by a processor, runs the steps of the method provided in the first aspect above.

[0028] As can be seen from the above, the present application provides a verification method, apparatus, device and storage medium for Nor flash, wherein the verification method constructs a simple storage model based on the specifications of the storage array, so that when the design to be tested is simulated and verified using the simple storage model, the simulation of the storage cells on most non-important bit lines is skipped, and only the verification items of the storage cells corresponding to the edge part of the storage array and the addresses that conform to the growth law are retained for simulation. This ensures that the verification process covers the checkpoints required for verification while completing more functional verification items within a limited time, greatly improving the verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a flowchart of the Nor flash verification method provided in an embodiment of the present application.

[0030] Figure 2 A schematic diagram of the structure of the Nor flash verification device provided in an embodiment of the present application.

[0031] Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0032] Reference numerals: 201, construction module; 202, verification module; 301, processor; 302, memory; 303, communication bus. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.

[0034] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0035] First, please refer to Figure 1 Some embodiments of the present application provide a Nor flash verification method for simulating Nor flash to perform functional verification on a design to be tested, the method comprising the following steps:

[0036] S1. Construct a simple storage model based on the storage array of Nor flash. The simple storage model is based on the storage cells corresponding to the local bit line group and all word lines. The local bit line group only includes the second bit line on each word line. i The bit lines corresponding to the first and last bytes, i = 0, 1, ..., n, where n is an integer greater than 1;

[0037] S2. Use a simple storage model to perform functional verification on the design under test.

[0038] Specifically, the design under test (DUT) is a chip that has not yet been tested. Generally, a test bench needs to be built to simulate the operation of the DUT to perform functional verification. The DUT is mainly for the purpose of functional verification, that is, by inputting directed or random test stimuli into the DUT, detecting the operating status of the DUT or the changes in the storage data of the storage array therein to verify whether the various functions of the DUT are operating normally. For the verification process of the DUT, the storage array model therein is used to simulate the data changes of the storage cells as the data comparison basis for functional verification. However, a storage array model that is too large seriously increases the verification efficiency of the DUT. Therefore, the verification method of the embodiment of the present application aims to propose a simple storage model for replacing the full-specification storage array model to simulate the data changes of the storage cells to reduce the verification time of the DUT.

[0039] More specifically, the design under test is the design circuit of the Nor flash in step S1 , so the simplified storage model needs to be designed corresponding to the specifications of the Nor flash storage array to be suitable for functional verification of the design under test.

[0040] More specifically, it should be noted that the storage data corresponding to the first byte and the last byte on each word line are more prone to errors than the storage data at other positions. The reason is that the word line adjustment process involves different word line voltage switching processes, which makes the storage data in these parts prone to errors. Therefore, the simple storage model constructed by the verification method of the embodiment of the present application includes the bit lines corresponding to the first byte and the last byte on each word line.

[0041] More specifically, each byte of data (byte) corresponds to 8 bits of data (bit), so each byte in the simple storage model corresponds to 8 bit lines. The construction principle of the simple storage model constructed in step S1 is to reduce the number of unimportant bit lines while keeping the bit line number unchanged to reduce the size of the entire storage array model, and only retain the storage cells corresponding to the bit lines with higher importance to form the simple storage model. In the verification process of the design to be tested, the data of the storage cells in the middle of the storage array model generally will not have errors alone, so the simple storage model retains the bit lines corresponding to the first byte (i=0) and the last byte on each word line and multiple bit lines in the middle part, so that when the design to be tested is simulated based on the simple storage model, the storage data output can reflect the data changes on the edge bit lines in the storage array and the data relationship between the edge bit lines and the middle bit lines, so as to ensure that the simulation process can complete the functional verification of the design to be tested while reducing the simulation content.

[0042] More specifically, in the embodiment of the present application, the byte reserved bit lines comply with the data read and write logic of the Nor flash, so that the verification process of step S2 can perform numerical analysis based on the byte data (0-255) to efficiently complete the functional verification.

[0043] More specifically, the storage array searches for stored data based on byte addresses, wherein the word line address corresponds to the high-order address of the byte address, and the low-order address increases according to the byte order on the word line. Therefore, the low-order addresses of the byte data occupying the same bit line on different word lines are the same. For example, assuming that the low-order address is a 4-bit address, then n=0,1,2,3,4 in the simplified storage model. The first word line corresponds to the first byte data (byte0), the second byte data (byte1), the fourth byte data (byte3), the eighth byte data (byte7) and the sixteenth byte data (byte15), and the corresponding low-order addresses are 0000, 0001, 0011, 0111 and 1111. It can be seen that the low-order address in the simplified storage model has a displacement relationship, that is, it is set based on the low-order address and gradually shifted by 1, which complies with the address growth law. Therefore, step S2 is to obtain test data based on the address that complies with the growth law for functional verification, thereby improving the reliability of the test results. In addition, the simplified storage model reduces the bit lines corresponding to 11 byte addresses. These bit lines include BL <0> -BL <7> BL <8> -BL <15> BL <24> -BL <31> BL <56> -BL <63> and BL <120> -BL <127> , which reduces the memory cells corresponding to most word lines in the memory array model, greatly shortening the time required for each verification item of the design to be tested.

[0044] It should be noted that when the second n When the last byte is the last byte, the local bit line group only includes the 1st, 2nd, ..., 2nd byte on each word line. n The bytes correspond to the bit lines.

[0045] More specifically, during the simulation verification process, the design to be tested receives test stimuli regarding specific verification items and selects the word lines, bit lines and bulk terminals of the corresponding storage cells in the simple storage model to apply corresponding voltage pulses to execute corresponding operation commands, and verifies whether the functions corresponding to the verification items are normal by analyzing the storage data of the simple storage model after the test; it should be noted that, during the simulation verification process, for storage cells that do not exist in the simple storage model, the design to be tested skips the operation processing of these storage cells.

[0046] The verification method of the Nor flash in the embodiment of the present application constructs a simple storage model based on the specifications of the storage array. When the design to be tested is simulated and verified using the simple storage model, the simulation of most non-important storage cells on bit lines is skipped, and only the verification items corresponding to the storage cells at the edge of the storage array and the addresses that conform to the growth law are simulated. This ensures that the verification process covers the checkpoints required for verification while completing more functional verification items within a limited time, greatly improving verification efficiency.

[0047] In some preferred embodiments, the steps of performing functional verification of the design under test using the simplified storage model include:

[0048] S21, simulating the reference model based on a preset test stimulus to generate a first test result, and simulating the design to be tested using a simple storage model based on the test stimulus to generate a second test result;

[0049] S22: Compare the first test result and the second test result to generate a verification result.

[0050] Specifically, the reference model is a functional model or a global model that generates a standard first test result based on the test stimulus. The first test result is the storage data in the reference model, which is regarded as the storage data result generated when the design to be tested operates normally based on the test stimulus. Therefore, the method of the embodiment of the present application can determine whether the simulation operation of the design to be tested is normal based on comparing the first test result and the second test result, that is, determine whether the corresponding verification item passes to generate a verification result.

[0051] In some preferred embodiments, the step of simulating the reference model based on a preset test stimulus to generate a first test result includes:

[0052] S211, simulating the reference model based on a preset test stimulus;

[0053] S212 . Extracting data of corresponding storage cells in the reference model after the simulation according to the storage cell distribution characteristics of the simplified storage model as a first test result.

[0054] Specifically, the reference model generates a standard result for the entire storage array based on the test stimulus. Since the verification method of the embodiment of the present application uses a simple storage model to perform functional verification on the design to be tested, the data specifications and format of the generated second test result correspond to the simple storage model. It is necessary to search for the storage data corresponding to the standard result according to the byte address for comparison, which makes the comparison process cumbersome. Therefore, the verification method of the embodiment of the present application preferably obtains the first test result with data specifications and format corresponding to the simple storage model from the reference model according to the storage unit distribution characteristics of the simple storage model, so as to directly perform data comparison with the second test result, simplify the verification result generation process, and improve verification efficiency.

[0055] In some other embodiments, the reference model can also replace its internal storage model with a simple storage model corresponding to the design to be tested, so that the storage data specifications and format of the first test result are consistent with the second test result, so as to improve the operating effect of the reference model in generating the first test result and simplify the data matching and comparison process.

[0056] In some preferred embodiments, each word line in the memory array has 2 n bytes of data.

[0057] Specifically, in this embodiment, the second n The byte data is the last byte above the byte data, so the local bit line group only includes the second byte on each word line. i The bytes correspond to the bit lines where i=0,1,…,n, where n is an integer greater than 1.

[0058] More specifically, each word line has 2 n The byte data complies with the design specifications of a general storage array, and can make the low-order address corresponding to the last byte on each word line an all-1 address.

[0059] In some preferred embodiments, the simplified storage model includes a plurality of storage blocks.

[0060] Specifically, the storage array of a large-capacity Nor flash is generally composed of multiple stacked storage blocks, and the multiple storage blocks share the same bit lines for connection. Therefore, in the embodiment of the present application, all storage blocks can be simplified based on the construction logic of the simple storage model in step S1.

[0061] More specifically, the storage capacity of different storage blocks may be consistent or inconsistent; in the embodiment of the present application, the number of bit lines occupied by different storage blocks is preferably consistent, so the inconsistent storage capacity of different storage blocks is reflected in the different number of corresponding occupied word lines, so that the corresponding storage blocks contain different numbers of storage units.

[0062] In some preferred embodiments, each memory block has four word lines.

[0063] Specifically, the number of characters of the upper address should be determined in consideration of the total number of word lines of all memory blocks.

[0064] More specifically, the verification method of the embodiment of the present application determines each storage block as 4 word lines, which is consistent with the design concept of the general Norflash storage array and can also make the storage capacity of different storage blocks consistent, so as to facilitate the establishment of a simple storage model.

[0065] In some preferred embodiments, the simplified storage model is a two-dimensional array model including binary data or a two-dimensional array model including threshold voltage values or a storage unit model based on MOS transistors.

[0066] Specifically, the two-dimensional array model including binary data is a model that represents the erase and write state of the storage unit based on the data 1 and data 0 displayed in the array, and can be used to verify the erase and write functions commonly used in the design to be tested; the two-dimensional array model including the threshold voltage value is a model that represents the voltage state of the storage unit based on the threshold voltage size displayed in the array, and can be used to verify the erase and write functions commonly used in the design to be tested and the repair functions of special states (such as over-erase repair, program strong, etc.); the storage cell model established based on the MOS tube is a model that truly imitates the specific connection structure of the MOS tube, and can be used for functional verification of all designs to be tested; different models have different simulation efficiency and application range, and users can choose to use them according to their usage requirements. The verification method of the embodiment of the present application aims to simplify the structure of the storage array model by reducing the number of storage cells, so the above models can be simplified to generate corresponding simple storage models.

[0067] Second, please refer to Figure 2 Some embodiments of the present application further provide a Nor flash verification device for simulating Nor flash to perform functional verification on a design to be tested, the device comprising:

[0068] The construction module 201 is used to construct a simple storage model based on the storage array of the Nor flash. The simple storage model is composed of storage cells corresponding to the local bit line group and all word lines. The local bit line group only includes the second bit line on each word line. i The bit lines corresponding to the first and last bytes, i=0,1,…,n, where n is an integer greater than 1;

[0069] The verification module 202 is used to perform functional verification on the design under test using a simple storage model.

[0070] The verification device of the Nor flash in the embodiment of the present application constructs a simple storage model based on the specifications of the storage array. When the design to be tested is simulated and verified using the simple storage model, the simulation of most non-important storage cells on bit lines is skipped, and only the verification items corresponding to the storage cells at the edge of the storage array and the addresses that conform to the growth law are simulated. This ensures that the verification process covers the checkpoints required for verification while completing more functional verification items within a limited time, greatly improving verification efficiency.

[0071] In some preferred implementations, the Nor flash verification device of the embodiment of the present application is used to execute the Nor flash verification method provided in the first aspect above.

[0072] Thirdly, please refer to Figure 3 Some embodiments of the present application also provide a structural diagram of an electronic device. The present application provides an electronic device, including: a processor 301 and a memory 302. The processor 301 and the memory 302 are interconnected and communicate with each other through a communication bus 303 and / or other forms of connection mechanisms (not marked). The memory 302 stores computer-readable instructions executable by the processor 301. When the electronic device is running, the processor 301 executes the computer-readable instructions to execute the method in any optional implementation of the above embodiments.

[0073] In a fourth aspect, an embodiment of the present application provides a storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method of any optional implementation of the above embodiment is executed. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0074] In summary, the embodiments of the present application provide a verification method, apparatus, device and storage medium for Nor flash, wherein the verification method constructs a simple storage model based on the specifications of the storage array, so that when the design to be tested is simulated and verified using the simple storage model, the simulation of most non-important storage cells on the bit lines is skipped, and only the verification item simulation of the storage cells corresponding to the edge part of the storage array and the addresses that conform to the growth law is retained. This ensures that the verification process covers the checkpoints required for verification while completing more functional verification items within a limited time, greatly improving the verification efficiency.

[0075] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0076] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0077] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0078] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0079] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A verification method for Nor flash, for simulating Nor flash to perform functional verification on a design to be tested, characterized in that: The method comprises the following steps: A simple storage model is constructed based on the storage array of the Nor flash. The simple storage model is composed of storage cells corresponding to a local bit line group and all word lines. The local bit line group only includes the second bit line on each word line. i The bit lines corresponding to the first and last bytes, i = 0, 1, ..., n, where n is an integer greater than 1; Performing functional verification on the design to be tested using the simple storage model; The step of performing functional verification on the design to be tested using the simple storage model includes: Simulating a reference model based on a preset test stimulus to generate a first test result, and simulating the design to be tested using the simple storage model based on the test stimulus to generate a second test result; The first test result and the second test result are compared to generate a verification result.

2. The verification method of Nor flash according to claim 1, wherein: The step of simulating the reference model based on the preset test stimulus to generate the first test result includes: Simulate the reference model based on the preset test stimulus; According to the storage unit distribution characteristics of the simple storage model, data of corresponding storage units in the reference model after the simulation is completed is extracted as the first test result.

3. The verification method of Nor flash according to claim 1, wherein: Each word line in the memory array has 2 n bytes of data.

4. The verification method of Nor flash according to claim 1, wherein: The simplified storage model includes a plurality of storage blocks.

5. The verification method of Nor flash according to claim 4, characterized in that: Each of the memory blocks has four word lines.

6. The verification method of Nor flash according to claim 1, wherein: The simple storage model is a two-dimensional array model including binary data or a two-dimensional array model including threshold voltage values or a storage unit model established based on MOS tubes.

7. A verification device for Nor flash, used for simulating Nor flash to perform functional verification on a design to be tested, characterized in that: The device comprises: A construction module is used to construct a simple storage model according to the storage array of the Nor flash, wherein the simple storage model is composed of storage cells corresponding to a local bit line group and all word lines, wherein the local bit line group only includes the second bit line on each word line. i The bit lines corresponding to the first and last bytes, i=0,1,…,n, where n is an integer greater than 1; A verification module, configured to perform functional verification on the design to be tested using the simple storage model; The step of performing functional verification on the design to be tested using the simple storage model includes: Simulating a reference model based on a preset test stimulus to generate a first test result, and simulating the design to be tested using the simple storage model based on the test stimulus to generate a second test result; The first test result and the second test result are compared to generate a verification result.

8. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the steps in the method according to any one of claims 1 to 6 are executed.

9. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are executed.

Images