A vacuum device and a preparation method thereof

Abstract

The present invention provides a vacuum device and a preparation method thereof. The method includes: patterning an SOI substrate to form a nano-narrow structure including the minimum radial dimension; wrapping the nano-narrow structure with a gate dielectric layer; performing hydrogen annealing to disconnect the minimum radial dimension, forming a cross-sectional structure that separates the top semiconductor layer into an anode region and a cathode region, and the gate dielectric layer and the nano-narrow structure form a sealed cavity to form a vacuum device. By setting the nano-narrow structure and forming the cross-sectional structure through hydrogen annealing, the present invention obtains a vacuum device with a nano-scale interval between the anode and the cathode to form a larger electric field strength and conduction current; at the same time, a fully surrounding gate vacuum device with stronger control ability is realized by using the nano-cantilever structure; in addition, a cavity under the nano-cantilever structure is only arranged in the top semiconductor layer to further reduce the interval between the anode and the cathode; finally, the nano-cantilever structure is rounded and thinned to further reduce the interval between the anode and the cathode.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a vacuum device and a preparation method thereof. Background Art

[0002] As the integrated circuit manufacturing technology enters the 5-nanometer technology node, the continuous miniaturization of the feature size of semiconductor devices has approached the physical limit in terms of size. Limited by the fact that the carrier mobility in silicon-based solid-state devices is essentially affected by lattice scattering or impurities, silicon-based devices can no longer meet the growing demands in terms of high frequency or fast response. Compared with the situation in solid-state devices, the vacuum condition enables electrons to achieve ballistic transport without collisions or scattering, resulting in faster carrier transport.

[0003] Since the nanoscale vacuum channel transistor was first proposed, the mechanisms used to realize the nanoscale vacuum channel transistor include field emission, two-dimensional electron gas emission in Schottky diodes, and thermionic emission of low-dimensional carbon materials, etc. Among them, some vacuum transistor devices formed by low-dimensional materials, such as fully surrounding gate nanovacuum channel transistors, have received extensive attention due to their characteristics of high drive current and good radiation immunity.

[0004] Vacuum devices often require an extremely short anode-cathode spacing to form a large field strength and a large conduction current. However, it is difficult to fabricate a vacuum device with a nanoscale anode-cathode spacing using the commonly used lithography technology in the prior art. Therefore, there is an urgent need for a vacuum device that can achieve a nanoscale source-drain spacing.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a vacuum device and a preparation method thereof, which are used to solve the problem that the cathode-anode spacing of the vacuum device in the prior art cannot be made small.

[0007] To achieve the above purpose, the present invention provides a preparation method of a vacuum device, and the preparation method includes:

[0008] Providing a SOI substrate, the SOI substrate sequentially includes a substrate layer, a buried oxide layer, and a top semiconductor layer from bottom to top; patterning the SOI substrate to form a nano-narrow structure, so that the nano-narrow structure has a minimum radial dimension;

[0009] A gate dielectric layer is disposed on the surface exposed by the nano-narrow structure and the surface of the top semiconductor layer. The gate dielectric layer wraps the nano-narrow structure, and a first gate electrode layer is disposed on the surface of the gate dielectric layer;

[0010] The structure obtained thus far is annealed in a hydrogen-containing atmosphere to break the nano-narrow structure at the minimum radial dimension, forming a cross-sectional structure that divides the top semiconductor layer into an anode region and a cathode region. The gate dielectric layer wrapping the cross-sectional structure and the nano-narrow structure form a sealed cavity with the cross-sectional structure;

[0011] An anode contact electrode is disposed in the anode region, a cathode contact electrode is disposed in the cathode region, and a gate contact electrode is disposed on the first gate electrode layer. Thus, a vacuum device is formed.

[0012] Optionally, the radial dimension of the nano-narrow structure gradually increases from the cross-sectional structure to both sides thereof.

[0013] Optionally, the nano-narrow structure is a nano-cantilever structure, and the position with the minimum distance from the upper surface of the nano-cantilever structure to the top semiconductor layer is the minimum radial dimension; there is a cavity below the nano-cantilever structure, and the cavity is only disposed in the top semiconductor layer; or the cavity is only disposed in the buried oxide layer; or the cavity is disposed in the top semiconductor layer and extends into the buried oxide layer.

[0014] Optionally, the nano-narrow structure is a base with a groove having a preset slope on the top semiconductor layer. The bottom surface of the groove is higher than the bottom surface of the top semiconductor layer, and the position with the minimum distance between the bottom surface of the groove and the buried oxide layer forms the minimum radial dimension of the nano-narrow structure.

[0015] Optionally, after forming the nano-narrow structure, the nano-narrow structure is annealed in a hydrogen-containing atmosphere to round and thin the nano-narrow structure and reduce the radial dimension at the minimum radial dimension.

[0016] Optionally, after forming the nano-narrow structure or / and after forming the cross-sectional structure, doping is performed on both sides of the minimum radial dimension of the nano-narrow structure to serve as the cathode region and the anode region.

[0017] Optionally, after forming the cross-sectional structure, the first gate electrode layer is removed, and a second gate electrode layer is disposed on the gate dielectric layer; or the second gate electrode layer is directly disposed on the first gate electrode layer; the gate contact electrode is disposed on the second gate electrode layer.

[0018] Optionally, the annealing temperature when annealing in a hydrogen-containing atmosphere to form the cross-sectional structure is 500 - 1300 °C.

[0019] Optionally, after forming the vacuum device, pattern the SOI substrate of the vacuum device, provide an insulating layer on the surface of the vacuum device, form a back gate electrode in the insulating layer, and pattern the insulating layer to expose the back gate electrode, the gate contact electrode, the anode contact electrode, and the cathode contact electrode. The back gate electrode cooperates with the gate electrode layer to regulate the electrical characteristics of the vacuum device.

[0020] The present invention also provides a vacuum device obtained by using any one of the above preparation methods. The vacuum device includes an SOI substrate, which includes a substrate layer, a buried oxide layer, and a top semiconductor layer;

[0021] The buried oxide layer is disposed on the substrate layer, and the top semiconductor layer is disposed on the buried oxide layer;

[0022] A nano-narrow structure is provided in the top semiconductor layer. A cross-sectional structure is provided at the smallest radial dimension of the nano-narrow structure. The cross-sectional structure divides the top semiconductor layer into a cathode region and an anode region. The cross-sectional structure is obtained by an annealing process in a hydrogen atmosphere;

[0023] The periphery of the cross-sectional structure is wrapped by a gate dielectric layer. The gate dielectric layer wrapping the cross-sectional structure and the nano-narrow structure form a sealed cavity for the cross-sectional structure. The surface of the gate dielectric layer is wrapped by a first gate electrode layer or / and a second gate electrode layer.

[0024] As described above, the vacuum device and its preparation method of the present invention have the following beneficial effects:

[0025] By providing a nano-narrow structure and forming a cross-sectional structure through hydrogen annealing, the present invention obtains a vacuum device with a nanoscale cathode-anode interval to form a larger electric field strength and conduction current;

[0026] The present invention utilizes a nano-suspension beam structure to realize a fully surrounding gate vacuum device with stronger control ability;

[0027] With the present invention, the cavity under the nano-suspension beam structure is only provided in the top semiconductor layer, further reducing the cathode-anode interval;

[0028] By rounding and thinning the nano-suspension beam structure, the present invention further reduces the cathode-anode interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It shows a top view schematic diagram of forming a nano-suspension beam structure in step 1 of Embodiment 1 of the present invention.

[0030] Figure 2 It shows a front view schematic diagram of forming a nano-suspension beam structure in step 1 of Embodiment 1 of the present invention.

[0031] Figure 3 It shows a cross-sectional view schematic diagram of forming the nano-suspension beam structure in step 1 of Embodiment 1 of the present invention.

[0032] Figure 4 It shows a top-view schematic diagram of rounding the nano-suspension beam structure in the optional example of step 1 of Embodiment 1 of the present invention.

[0033] Figure 5 It shows a front-view cross-sectional view schematic diagram of rounding the nano-suspension beam structure in the optional example of step 1 of Embodiment 1 of the present invention.

[0034] Figure 6 It shows a left-view cross-sectional view schematic diagram of rounding the nano-suspension beam structure in the optional example of step 1 of Embodiment 1 of the present invention.

[0035] Figure 7 It shows a top-view schematic diagram of setting the gate dielectric layer and the first gate electrode layer in step 2 of Embodiment 1 of the present invention.

[0036] Figure 8 It shows a front-view cross-sectional view schematic diagram of setting the gate dielectric layer and the first gate electrode layer in step 2 of Embodiment 1 of the present invention.

[0037] Figure 9 It shows a left-view cross-sectional view schematic diagram of setting the gate dielectric layer and the first gate electrode layer in step 2 of Embodiment 1 of the present invention.

[0038] Figure 10 It shows a top-view schematic diagram of forming the cross-sectional structure in step 3 of Embodiment 1 of the present invention.

[0039] Figure 11 It shows a front-view cross-sectional view schematic diagram of forming the cross-sectional structure in step 3 of Embodiment 1 of the present invention.

[0040] Figure 12 It shows a left-view cross-sectional view schematic diagram of forming the cross-sectional structure in step 3 of Embodiment 1 of the present invention.

[0041] Figure 13 It shows a top-view schematic diagram of forming the contact electrode in step 4 of Embodiment 1 of the present invention.

[0042] Figure 14 It shows a front-view cross-sectional view schematic diagram of forming the contact electrode in step 4 of Embodiment 1 of the present invention.

[0043] Figure 15 It shows a left-view cross-sectional view schematic diagram of forming the contact electrode in step 4 of Embodiment 1 of the present invention.

[0044] Figure 16 It shows a top - view schematic diagram of the groove formed in S1 in the second embodiment of the present invention.

[0045] Figure 17 It shows a front - view schematic diagram of the groove formed in S1 in the second embodiment of the present invention.

[0046] Figure 18 It shows a cross - sectional view schematic diagram of the groove formed in S1 in the second embodiment of the present invention.

[0047] Figure 19 It shows a left - hand cross - sectional view schematic diagram of the rounded base in the alternative example of S1 in the second embodiment of the present invention.

[0048] Figure 20 It shows a top - view schematic diagram of the gate dielectric layer and the first gate electrode layer provided in S2 in the second embodiment of the present invention.

[0049] Figure 21 It shows a front - view cross - sectional view schematic diagram of the gate dielectric layer and the first gate electrode layer provided in S2 in the second embodiment of the present invention.

[0050] Figure 22 It shows a left - hand cross - sectional view schematic diagram of the gate dielectric layer and the first gate electrode layer provided in S2 in the second embodiment of the present invention.

[0051] Figure 23 It shows a top - view schematic diagram of the cross - sectional structure formed in S3 in the second embodiment of the present invention.

[0052] Figure 24 It shows a front - view cross - sectional view schematic diagram of the cross - sectional structure formed in S3 in the second embodiment of the present invention.

[0053] Figure 25 It shows a left - hand cross - sectional view schematic diagram of the cross - sectional structure formed in S3 in the second embodiment of the present invention.

[0054] Figure 26 It shows a top - view schematic diagram of the contact electrode formed in S4 in the second embodiment of the present invention.

[0055] Figure 27 It shows a front - view cross - sectional view schematic diagram of the contact electrode formed in S4 in the second embodiment of the present invention.

[0056] Figure 28 It shows a left - hand cross - sectional view schematic diagram of the contact electrode formed in S4 in the second embodiment of the present invention.

[0057] Figure 29 It shows a top - view schematic diagram of the back - gate electrode provided in the alternative example of S4 in the second embodiment of the present invention.

[0058] Figure 30 It shows a schematic diagram of the main view cross-section presented when the back gate electrode is set in the optional example S4 in the second embodiment of the present invention.

[0059] Figure 31 It shows a schematic diagram of the left view cross-section presented when the back gate electrode is set in the optional example S4 in the second embodiment of the present invention.

[0060] Description of component labels

[0061] 100, substrate layer; 200, buried oxide layer; 300, top semiconductor layer; 310, nano-suspension beam structure; 321, base; 322, groove; 323, cavity; 330, minimum radial dimension; 340, cross-sectional structure; 350, sealed cavity; 411, cathode region; 412, cathode contact electrode; 421, anode region; 422, anode contact electrode; 431, gate dielectric layer; 432, first gate electrode layer; 433, second gate electrode layer; 434, gate contact electrode; 435, back gate electrode; 436, insulating layer. Detailed implementation manners

[0062] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0063] When detailing the embodiments of the present invention, for ease of description, the schematic diagrams showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0064] For the sake of convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings.

[0065] In the context of the present application, the structure where the first feature is "above" the second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0066] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0067] Embodiment 1:

[0068] As Figures 1 - 15 shown, the present invention provides a method for preparing a vacuum device, and the preparation method includes:

[0069] Step 1: Provide an SOI substrate, which sequentially includes a substrate layer 100, a buried oxide layer 200, and a top semiconductor layer 300 from bottom to top; pattern the SOI substrate to form a nano-narrow structure, so that the nano-narrow structure has a position 330 with the smallest radial dimension; the nano-narrow structure is a nano-cantilever structure 310, and the position where the distance between the nano-cantilever structure 310 and the upper surface of the top semiconductor layer 300 is the smallest is the position 330 with the smallest radial dimension, and there is a cavity 323 below the nano-cantilever structure 310;

[0070] Step 2: Set a gate dielectric layer 431 on the surface of the exposed nano-narrow structure and the surface of the top semiconductor layer 300, the gate dielectric layer 431 wraps the nano-cantilever structure 310, and set a first gate electrode layer 432 on the surface of the gate dielectric layer 431;

[0071] Step 3: Anneal the structure obtained so far in a hydrogen-containing atmosphere, so that the position 330 with the smallest radial dimension of the nano-cantilever structure 310 is disconnected to form a cross-sectional structure 340, the cross-sectional structure 340 divides the top semiconductor layer 300 into an anode region 421 and a cathode region 411, and the gate dielectric layer 431 wrapping the cross-sectional structure 340 and the nano-cantilever structure 310 form a sealed cavity 350;

[0072] Step 4: Set an anode contact electrode 422 in the anode region 421, set a cathode contact electrode 412 in the cathode region 411, and set a gate contact electrode 434 on the first gate electrode layer 432. Thus, a vacuum device is formed.

[0073] Next, the method for preparing the vacuum device of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the vacuum device protected by the present invention, and those skilled in the art can change it according to the actual preparation steps.

[0074] First, as Figures 1 - 3 shown, perform Step 1, where Figure 2is a front view sectional view obtained along the AA' line in Figure 1 , and Figure 3 is a left view sectional view obtained along the BB' line in Figure 1 . A SOI substrate is provided, which sequentially includes a substrate layer 100, a buried oxide layer 200, and a top semiconductor layer 300 from bottom to top; the SOI substrate is patterned to form a nano-narrow structure, so that the nano-narrow structure has a minimum radial dimension 330; the nano-narrow structure is a nano-cantilever structure 310, and the position with the smallest distance from the upper surface of the top semiconductor layer 300 in the nano-cantilever structure 310 is the minimum radial dimension 330, and there is a cavity 323 below the nano-cantilever structure 310.

[0075] In the present invention, by providing the nano-cantilever structure 310, the minimum radial dimension 330 thereof is in a nano-scale size, so that a subsequent extremely small anode-cathode spacing can be formed, thereby achieving a large field strength and current intensity in the vacuum device. Specifically, other structures can also be used to realize the nano-narrow structure with a small size. The nano-cantilever structure 310 here can realize a fully surrounding gate device while achieving a smaller anode-cathode spacing, thereby obtaining a high-performance device with stronger gate control ability.

[0076] In one embodiment, the cavity 323 below the nano-cantilever structure 310 is only provided in the top semiconductor layer 300; or the cavity 323 is only provided in the buried oxide layer 200; or the cavity 323 is provided in the top semiconductor layer 300 and extends into the buried oxide layer 200.

[0077] In the present invention, by providing the cavity 323 only in the top semiconductor layer 300, the size of the nano-cantilever structure 310 is further thinned, thereby further reducing the anode-cathode spacing of the vacuum device.

[0078] In one embodiment, as shown in Figures 4 - 6 , where Figure 5 is a front view sectional view obtained along the AA' line in Figure 4 , and Figure 6 is a left view sectional view obtained along the BB' line in Figure 4 . After forming the nano-cantilever structure 310, the nano-cantilever structure 310 is annealed in a hydrogen-containing atmosphere to round and thin the nano-cantilever structure 310 and reduce the radial dimension of the minimum radial dimension 330.

[0079] In the present invention, by annealing the nano-cantilever structure 310 in a hydrogen-containing atmosphere to round and thin the nano-cantilever structure 310, the anode-cathode spacing of the vacuum device can be further reduced.

[0080] Then, as shown in Figures 7 - 9As shown, step 2 is performed, where Figure 8 is a front view sectional view obtained along line AA' in Figure 7 , Figure 9 is a left view sectional view obtained along line BB' in Figure 7 . A gate dielectric layer 431 is provided on the surface of the exposed nano-narrow structure and the surface of the top semiconductor layer 300. The gate dielectric layer 431 wraps the nano-cantilever structure 310, and a first gate electrode layer 432 is provided on the surface of the gate dielectric layer 431.

[0081] Next, as shown in Figures 10 - 12 , step 3 is performed, where Figure 11 is a front view sectional view obtained along line AA' in Figure 10 , Figure 12 is a left view sectional view obtained along line BB' in Figure 10 . The structure obtained so far is annealed in a hydrogen-containing atmosphere to break the nano-cantilever structure 310 at the minimum radial dimension 330 to form a cross-sectional structure 340. The cross-sectional structure 340 separates the top semiconductor layer 300 into an anode region 421 and a cathode region 411. The gate dielectric layer 431 wrapping the cross-sectional structure 340 and the nano-cantilever structure 310 form a sealed cavity 350 for the cross-sectional structure 340.

[0082] In one embodiment, the radial dimension of the nano-cantilever structure 310 gradually increases from the cross-sectional structure 340 to both sides thereof.

[0083] Specifically, the nano-cantilever structure 310 is formed by the previous process here to achieve the form that the radial dimension of the nano-cantilever structure 310 gradually increases from the minimum radial dimension 330 to both sides, so as to obtain a small radial dimension, and then a sealed cavity 350 formed by the subsequent small-sized cross-sectional structure 340 is obtained, and its dimension is the anode-cathode spacing of this vacuum device.

[0084] In one embodiment, after forming the nano-cantilever structure 310 or / and after forming the cross-sectional structure 340, doping is performed on both sides of the minimum radial dimension 330 of the nano-cantilever structure 310 to serve as the cathode region 411 and the anode region 421.

[0085] In one embodiment, after forming the cross-sectional structure 340, the first gate electrode layer 432 is removed, and a second gate electrode layer 433 is provided on the gate dielectric layer 431; or the second gate electrode layer 433 is directly provided on the first gate electrode layer 432; the gate contact electrode 434 is provided on the second gate electrode layer 433.

[0086] Specifically, the material of the first gate electrode layer 432 is a material through which hydrogen can easily permeate, and the material of the second gate electrode layer 433 is used to improve the performance of the vacuum device, such as protecting the vacuum degree of the sealed cavity 350 and improving the electrical performance, etc.

[0087] By replacing or adding the second gate electrode layer 433, the present invention realizes that while ensuring the smooth progress of the hydrogen annealing process for forming the cross-sectional structure 340, the device performance is excellent after the annealing process.

[0088] In one embodiment, after forming the first gate electrode layer 432 or / and the second gate electrode layer 433, a passivation layer can be provided in the area outside the nano-beam structure 310.

[0089] In one embodiment, when annealing in a hydrogen-containing atmosphere to form the cross-sectional structure 340, the annealing temperature is 500 - 1300 °C.

[0090] In one embodiment, the annealing time for forming the cross-sectional structure 340 can be 10 seconds - 1 hour, and specific adjustment is made according to parameters such as the material type and thickness of the gate dielectric layer 431, the size of the smallest radial dimension 330, and the hydrogen concentration.

[0091] Finally, as Figures 13 - 15 shown, step 4 is performed, where Figure 14 is a front view cross-sectional view obtained along the AA' line in Figure 13 , Figure 15 is a left view cross-sectional view obtained along the BB' line in Figure 13 . An anode contact electrode 422 is provided in the anode region 421, a cathode contact electrode 412 is provided in the cathode region 411, and a gate contact electrode 434 is provided in the first gate electrode layer 432. Thus, a vacuum device is formed.

[0092] Specifically, when the second gate electrode layer 433 is provided, the gate contact electrode 434 is provided on the second gate electrode layer 433.

[0093] The present invention also provides a vacuum device, which is obtained by using any of the above preparation methods. The vacuum device includes an SOI substrate, and the SOI substrate includes a substrate layer 100, a buried oxide layer 200, and a top semiconductor layer 300;

[0094] The buried oxide layer 200 is provided on the substrate layer 100, and the top semiconductor layer 300 is provided on the buried oxide layer 200;

[0095] A nano-cantilever structure 310 is provided in the top semiconductor layer 300. A cross-sectional structure 340 is provided at the smallest radial dimension 330 of the nano-cantilever structure 310. The cross-sectional structure 340 divides the top semiconductor layer 300 into a cathode region 411 and an anode region 421. The cross-sectional structure 340 is obtained by an annealing process in a hydrogen atmosphere.

[0096] The periphery of the cross-sectional structure 340 is wrapped by a gate dielectric layer 431. The gate dielectric layer 431 wrapping the cross-sectional structure 340 and the nano-cantilever structure 310 form a sealed cavity 350 for the cross-sectional structure 340. The surface of the gate dielectric layer 431 is wrapped by a first gate electrode layer 432 and / or a second gate electrode layer 433.

[0097] Embodiment 2:

[0098] The present invention provides a method for manufacturing a vacuum device. The manufacturing method is similar to the manufacturing method in Embodiment 1 in other features and will not be elaborated here. The difference lies in that the manufacturing method includes:

[0099] S1: Provide a SOI substrate. The SOI substrate includes a substrate layer 100, a buried oxide layer 200, and a top semiconductor layer 300 from bottom to top. Pattern the SOI substrate to form a nano-narrow structure, so that the nano-narrow structure has a smallest radial dimension 330. The nano-narrow structure is a base 321 of a groove 322 with a preset slope provided on the top semiconductor layer 300. The bottom surface of the groove 322 is higher than the bottom surface of the top semiconductor layer 300. The smallest distance between the bottom surface of the groove 322 and the buried oxide layer 200 forms the smallest radial dimension 330 of the base 321.

[0100] S2: Set a gate dielectric layer 431 on the surface exposed by the nano-narrow structure and the surface of the top semiconductor layer 300. The gate dielectric layer 431 wraps the base 321. Set a first gate electrode layer 432 on the surface of the gate dielectric layer 431.

[0101] S3: Anneal the structure obtained so far in a hydrogen-containing atmosphere, so that the smallest radial dimension 330 of the base 321 is disconnected to form a cross-sectional structure 340. The cross-sectional structure 340 divides the top semiconductor layer 300 into an anode region 421 and a cathode region 411. The gate dielectric layer 431 wrapping the cross-sectional structure 340 and the base 321 form a sealed cavity 350 for the cross-sectional structure 340.

[0102] S4: Set an anode contact electrode 422 in the anode region 421, set a cathode contact electrode 412 in the cathode region 411, and set a gate contact electrode 434 on the first gate electrode layer 432. Thus, a vacuum device is formed.

[0103] The preparation method of the vacuum device of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the vacuum device protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0104] First, as Figures 16 - 18 shown, perform S1, where Figure 17 is a front view sectional view obtained along the AA' line in Figure 16 , Figure 18 is a left view sectional view obtained along the BB' line in Figure 16 . Provide a SOI substrate, which sequentially includes a substrate layer 100, a buried oxide layer 200, and a top semiconductor layer 300 from bottom to top; pattern the SOI substrate to form a nano-narrow structure, so that the nano-narrow structure has a minimum radial dimension 330; the nano-narrow structure is a base 321 provided with a groove 322 with a preset slope on the top semiconductor layer 300, the bottom surface of the groove 322 is higher than the bottom surface of the top semiconductor layer 300, and the minimum distance between the bottom surface of the groove 322 and the buried oxide layer 200 forms the minimum radial dimension 330 of the nano-narrow structure.

[0105] By setting the base 321 in the present invention, the minimum radial dimension 330 thereof is in a nano-scale size, so that a subsequent extremely small anode-cathode spacing can be formed to achieve a large field strength and current intensity of the vacuum device.

[0106] Specifically, the cross-section of the groove 322 with a preset slope can be in different forms such as V-shaped, semi-circular, semi-elliptical, etc., so that the base 321 under the groove 322 can form the structure of the minimum radial dimension 330.

[0107] In one embodiment, as Figure 19 shown, Figure 19 is a left view sectional view obtained along the BB' line. After forming the base 321, anneal the base 321 in a hydrogen-containing atmosphere to round and thin the base 321 and reduce the radial dimension of the minimum radial dimension 330.

[0108] Then, as Figures 20 - 22 shown, perform S2, where Figure 21 is a front view sectional view obtained along the AA' line in Figure 20 , Figure 22 is a left view sectional view obtained along the BB' line in Figure 20The left view cross-sectional view obtained from the BB' line in [reference], a gate dielectric layer 431 is provided on the exposed surface of the nano-narrow structure and the surface of the top semiconductor layer 300. The gate dielectric layer 431 wraps the base 321, and a first gate electrode layer 432 is provided on the surface of the gate dielectric layer 431.

[0109] Next, as Figures 23 - 25 shown, perform S3, where Figure 24 is the front view cross-sectional view obtained from the AA' line in Figure 23 [reference], Figure 25 is the left view cross-sectional view obtained from the BB' line in Figure 23 [reference]. Anneal the structure obtained so far in a hydrogen-containing atmosphere to break the minimum radial dimension 330 of the base 321, forming a cross-sectional structure 340. The cross-sectional structure 340 divides the top semiconductor layer 300 into an anode region 421 and a cathode region 411. The gate dielectric layer 431 wrapping the cross-sectional structure 340 and the base 321 form a sealed cavity 350 for the cross-sectional structure 340.

[0110] In one embodiment, after forming the cross-sectional structure 340, remove the first gate electrode layer 432, and provide a second gate electrode layer 433 on the gate dielectric layer 431; or directly provide the second gate electrode layer 433 on the first gate electrode layer 432; the gate contact electrode 434 is provided on the second gate electrode layer 433.

[0111] Finally, as Figures 26 - 28 shown, perform S4, where Figure 27 is the front view cross-sectional view obtained from the AA' line in Figure 26 [reference], Figure 28 is the left view cross-sectional view obtained from the BB' line in Figure 26 [reference]. An anode contact electrode 422 is provided in the anode region 421, a cathode contact electrode 412 is provided in the cathode region 411, and a gate contact electrode 434 is provided on the first gate electrode layer 432. Thus, a vacuum device is formed.

[0112] In one embodiment, as Figures 29 - 31 shown, where Figure 30 is the front view cross-sectional view obtained from the AA' line in Figure 29 [reference], Figure 31 is the front view cross-sectional view obtained from the AA' line in Figure 29The left view sectional view obtained from the line BB' in [description], after forming the vacuum device, pattern the SOI substrate of the vacuum device, provide an insulating layer 436 on the surface of the vacuum device, form a back gate electrode 435 within the insulating layer 436, pattern the insulating layer 436 to expose the back gate electrode 435, the gate contact electrode 434, the anode contact electrode 422, and the cathode contact electrode 412. The back gate electrode 435 cooperates with the gate electrode layer to regulate the electrical characteristics of the vacuum device.

[0113] By additionally providing the back gate electrode 435, the present invention can assist in controlling and regulating the device to improve the control ability of the gate over the operation of the device.

[0114] In summary, for the vacuum device and its manufacturing method of the present invention, a cross-sectional structure can be obtained by setting a nano-narrow structure and performing hydrogen annealing, resulting in a vacuum device with a nanoscale anode-cathode spacing to form a larger electric field strength and conduction current. At the same time, a fully surrounding gate vacuum device with stronger control ability is realized using a nano-cantilever structure. Additionally, by arranging the cavity under the nano-cantilever structure only in the top semiconductor layer, the anode-cathode spacing is further reduced. Finally, by rounding and thinning the nano-cantilever structure, the anode-cathode spacing is further reduced.

[0115] Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0116] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a vacuum device, characterized in that, The preparation method includes: Providing an SOI substrate, which sequentially includes a substrate layer, a buried oxide layer, and a top semiconductor layer from bottom to top; patterning the SOI substrate to form a nano-narrow structure, such that there is a position with the minimum radial dimension in the nano-narrow structure; Setting a gate dielectric layer on the surface of the nano-narrow structure and the surface of the top semiconductor layer, the gate dielectric layer wrapping the nano-narrow structure, and setting a first gate electrode layer on the surface of the gate dielectric layer; Annealing the structure obtained so far in a hydrogen-containing atmosphere, such that the position with the minimum radial dimension of the nano-narrow structure is disconnected to form a cross-sectional structure, the cross-sectional structure separating the top semiconductor layer into an anode region and a cathode region, and the gate dielectric layer wrapping the cross-sectional structure and the nano-narrow structure forming a sealed cavity for the cross-sectional structure; Setting an anode contact electrode in the anode region, setting a cathode contact electrode in the cathode region, and setting a gate contact electrode on the first gate electrode layer, thus forming a vacuum device.

2. The manufacturing method of the vacuum device according to claim 1, characterized in that The radial dimension of the nano-narrow structure gradually increases from the cross-sectional structure to both sides thereof.

3. The manufacturing method of the vacuum device according to claim 1, characterized in that, The nano-narrow structure is a nano-cantilever structure, and the position with the minimum distance from the upper surface of the nano-cantilever structure to the top semiconductor layer is the position with the minimum radial dimension; There is a cavity below the nano-cantilever structure, and the cavity is only provided in the top semiconductor layer; or the cavity is only provided in the buried oxide layer; or the cavity is provided in the top semiconductor layer and extends into the buried oxide layer.

4. The preparation method of the vacuum device according to claim 1, characterized in that, The nano-narrow structure is a base with a groove having a preset slope provided on the top semiconductor layer, the bottom surface of the groove being higher than the bottom surface of the top semiconductor layer, and the position with the minimum distance between the bottom surface of the groove and the buried oxide layer forms the position with the minimum radial dimension of the nano-narrow structure.

5. The manufacturing method of the vacuum device according to claim 1, characterized in that, The preparation method further includes: after forming the nano-narrow structure, annealing the nano-narrow structure in a hydrogen-containing atmosphere to round and thin the nano-narrow structure and reduce the radial dimension of the position with the minimum radial dimension.

6. The manufacturing method of the vacuum device according to claim 1, characterized in that, After forming the nano-narrow structure or / and after forming the cross-sectional structure, doping both sides of the position with the minimum radial dimension of the nano-narrow structure as the cathode region and the anode region.

7. The manufacturing method of the vacuum device according to claim 1, characterized in that, The preparation method further includes: after forming the cross-sectional structure, removing the first gate electrode layer, and setting a second gate electrode layer on the gate dielectric layer; or Directly setting the second gate electrode layer on the first gate electrode layer; The gate contact electrode is set on the second gate electrode layer.

8. The manufacturing method of the vacuum device according to claim 1, characterized in that, The annealing temperature when annealing in a hydrogen-containing atmosphere to form the cross-sectional structure is 500 - 1300 °C.

9. The manufacturing method of the vacuum device according to claim 1, characterized in that, The preparation method further includes: after forming the vacuum device, patterning the SOI substrate of the vacuum device, setting an insulating layer on the surface of the vacuum device, forming a back gate electrode in the insulating layer, and patterning the insulating layer to expose the back gate electrode, the gate contact electrode, the anode contact electrode, and the cathode contact electrode, and the back gate electrode cooperates with the gate electrode layer to regulate the electrical characteristics of the vacuum device.

10. A vacuum device is prepared by using the preparation method of the vacuum device according to any one of the above claims 1-9, characterized in that, The vacuum device includes an SOI substrate, which includes a substrate layer, a buried oxide layer, and a top semiconductor layer; The buried oxide layer is disposed on the substrate layer, and the top semiconductor layer is disposed on the buried oxide layer; A nano-narrow structure is disposed in the top semiconductor layer. A cross-sectional structure is disposed at the smallest radial dimension of the nano-narrow structure. The cross-sectional structure divides the top semiconductor layer into a cathode region and an anode region. The cross-sectional structure is obtained by an annealing process in a hydrogen atmosphere; The periphery of the cross-sectional structure is wrapped by a gate dielectric layer. The gate dielectric layer wrapping the cross-sectional structure and the nano-narrow structure form a sealed cavity for the cross-sectional structure. The surface of the gate dielectric layer is wrapped by a first gate electrode layer or / and a second gate electrode layer.

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