A method for diagnosing wafer failure causes

Abstract

The application provides a wafer failure cause diagnosis method, which comprises the following steps: performing data detection on a wafer group to be detected which comprises a plurality of abnormal wafers with different yields and a plurality of normal wafers and collecting wafer data; randomly extracting data from the wafer data, performing cleaning and feature extraction processing on the data to obtain a to-be-detected module, performing rapid iteration prediction analysis on the to-be-detected module, comprehensively analyzing analysis results, determining whether there is a correlation between the yield of the abnormal wafer and corresponding module parameters according to R 2 , and positioning a failure position of the to-be-detected module and analyzing a failure cause. The application can realize comprehensive analysis of the correlation between the low yield of the abnormal wafer and each process flow module through a linear regression automatic algorithm, can quickly position an abnormal point and analyze a cause, and thus can take relevant avoidance or blocking measures to avoid the occurrence of the same type of situation again, and can effectively improve the wafer yield and reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a wafer failure cause diagnosis method. BACKGROUND

[0002] As a silicon wafer indispensable for manufacturing semiconductor integrated circuits, after a series of front-end and back-end process treatments are completed, due to manufacturing process, material, environment and other problems, yield testing for screening good and bad silicon wafers is still needed, and the yield result determines the quality and reliability of the silicon wafer. When the yield of the silicon wafer is low or abnormal, production process problem screening and analysis of the silicon wafer with abnormal yield is needed, that is, semiconductor failure analysis. Semiconductor failure analysis is to use various test analysis tools and analysis processes to confirm the failure phenomenon inside the chip, distinguish the failure mode and failure mechanism, and determine the final failure cause. And measures are taken to avoid or block the problem points to avoid subsequent silicon wafers from repeating the same mistake, so as to improve the yield and reliability of the silicon wafer.

[0003] At present, when the silicon wafer with abnormal yield is found, the possible abnormal points of each node in the process flow need to be found, including Flow version, Inline, WAT, Machine, Materials, etc. The process nodes that the silicon wafer needs to go through from delivery to production completion are as long as thousands of processes, including process, machine, material, etc. If each process, machine, etc. is checked, the process flow is complex, and there are many hardware devices, so it is very difficult to quickly locate the abnormal point, and a lot of manpower and material resources are needed, which affects the efficiency of cause investigation and prolongs the time to solve the problem. Therefore, if the abnormal cause point cannot be found in time and timely measures are taken to avoid or block, it will bring potential risks to the subsequent production of silicon wafers, leading to the occurrence of this type of situation again, which is very unfavorable for ensuring the quality and reliability of the silicon wafer, and will also cause huge economic losses to the silicon wafer manufacturer. SUMMARY

[0004] The purpose of the present application is to provide a wafer failure cause diagnosis method to solve the problem that due to the complex and diverse process flow that the silicon wafer needs to go through from delivery to production completion, manual work cannot quickly and timely find the abnormal cause point and take timely measures to avoid or block, which brings potential risks to the subsequent production of silicon wafers, leads to the occurrence of low yield of silicon wafers again, reduces the quality and reliability of the silicon wafers, and thus causes huge economic losses to the silicon wafer manufacturer.

[0005] To solve the above technical problems, the present application provides a wafer failure cause diagnosis method, which comprises the following steps:

[0006] A wafer group to be tested is provided, the wafer group to be tested including a plurality of abnormal wafers and a plurality of normal wafers with different yields, data of the wafer group to be tested is detected and wafer data is collected;

[0007] Random data is extracted from the wafer data, and the extracted wafer data is cleaned and processed to extract features, so as to obtain a plurality of processed wafer data as test modules;

[0008] The test modules are subjected to rapid iterative prediction analysis, and analysis results are outputted;

[0009] According to the analysis results, a comprehensive statistical analysis is performed, and a correlation value R of the yield of the abnormal wafer and the corresponding module parameter is outputted 2 ;

[0010] According to the correlation value R 2 , a failure position of the test module is located.

[0011] Further, the proportion of the random data to the collected wafer data can be 80% to 100%.

[0012] Further, the wafer data cleaning method can be information denoising.

[0013] Further, the linear regression algorithm is used to determine the number of rapid iterations of the test module.

[0014] Further, the linear regression algorithm R 2

[0015]

[0016] wherein y n is the yield of the normal wafer, y a is the yield of the abnormal wafer, and y^ is the average yield of the wafer.

[0017] Further, the module includes at least two of process, wafer acceptance test, machine, and production version.

[0018] Further, in the iterative analysis results, when the R 2 >0.8, it is determined that the parameter corresponding to the module has a correlation with the low yield reason.

[0019] Further, in the iterative analysis results, when the R 2 <0.8, it is determined that the parameter corresponding to the module has no correlation with the low yield reason.

[0020] Further, according to the correlation determination result, the failure position of the wafer to be tested is located.​

[0021] Further, the positioned abnormal wafer is subjected to failure analysis, and reasons for low yield of the abnormal wafer are listed.

[0022] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0023] In the diagnostic method for wafer failure reasons provided by the present application, first, the wafer group to be tested including several abnormal wafers with different yields and several normal wafers is subjected to data detection and wafer data collection; second, data are randomly extracted from the wafer data, and the extracted wafer data are subjected to cleaning and feature extraction processing, so as to take the processed wafer data as test modules, and all the test modules are subjected to fast iterative prediction analysis and output of analysis results; finally, comprehensive statistical analysis is performed according to the analysis results, and a correlation value R of the yield of the abnormal wafer and corresponding module parameters is output 2 ; and the failure position of the test module is positioned according to the correlation value R 2 . Through the linear regression automatic algorithm, the present application realizes comprehensive analysis of the correlation between the reasons for low yield of abnormal silicon wafers and process flow modules, can quickly locate abnormal points and perform reason analysis, so as to take relevant avoidance or blocking measures to avoid the recurrence of this type of situation, and thus can effectively improve the yield and reliability of silicon wafers. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 Fig. 1 is a flowchart of the diagnostic method for wafer failure reasons in an embodiment of the present application;

[0025] Figure 2 Fig. 2 is a model analysis flowchart in the diagnostic method for wafer failure reasons in an embodiment of the present application;

[0026] Figure 3 Fig. 3 is a fitting analysis result comprehensive analysis flowchart in the diagnostic method for wafer failure reasons in an embodiment of the present application. DETAILED DESCRIPTION

[0027] As described in the background, as the silicon wafer indispensable for manufacturing semiconductor integrated circuits, after a series of front-end and back-end process treatments are completed, due to manufacturing process, material, environment and other problems, yield testing for screening good and bad silicon wafers is still needed, and the yield result determines the quality and reliability of the silicon wafer. When the yield of the silicon wafer is low or abnormal, the production process problem of the abnormal silicon wafer needs to be screened and analyzed, that is, semiconductor failure analysis. Semiconductor failure analysis is to use various test analysis tools and analysis processes to confirm the failure phenomenon inside the chip, determine the failure mode and failure mechanism, and determine the final failure cause. And take evasive or blocking measures for the problem point to avoid the subsequent silicon wafer from repeating the same mistake, so as to improve the yield and reliability of the silicon wafer.

[0028] At present, when the yield of the silicon wafer is abnormal, the process flow nodes that may be abnormal need to be found out, including Flow version, Inline, WAT, Machine, Materials, etc. The process nodes that the silicon wafer needs to go through from delivery to production completion are as long as thousands of processes, including process, machine, material, etc. If each process, machine, etc. is checked, the process flow is complex, the hardware equipment is much, it is very difficult to quickly locate the abnormal point, and a lot of manpower and material resources are needed, which affects the efficiency of cause investigation and prolongs the time to solve the problem. Therefore, if the abnormal cause point cannot be found out in time and evasive or blocking measures are not taken in time, it will bring potential risks to the on-line or subsequent production of the silicon wafer, leading to the occurrence of this type of situation again. This is very unfavorable to guarantee the quality and reliability of the silicon wafer, and will also cause huge economic losses to the silicon wafer manufacturer.

[0029] For example, as shown in Figure 1 The surface solder bump removal method comprises the following steps:

[0030] Step S100, providing a to-be-tested wafer group, the to-be-tested wafer group including a plurality of abnormal wafers with different yields and a plurality of normal wafers, performing data detection on the to-be-tested wafers and collecting wafer data;

[0031] Step S200, randomly extracting data from the wafer data, and performing cleaning, feature extraction processing on the extracted wafer data, so as to take the processed wafer data as to-be-tested modules;

[0032] Step S300, performing fast iterative prediction analysis on all the to-be-tested modules obtained, and outputting an analysis result;

[0033] Step S400, performing comprehensive statistical analysis according to the analysis result, and outputting a correlation value R of the yield of the abnormal wafer and the corresponding module parameter 2 ;

[0034] Step S500, according to the correlation value R 2 locating the failure position of the to-be-tested module.

[0035] That is, in the wafer failure cause diagnosis method provided by the present application, first, the to-be-tested wafer group including a plurality of abnormal wafers with different yields and a plurality of normal wafers is subjected to data detection and wafer data is collected; second, data is randomly extracted from the wafer data, and the extracted wafer data is subjected to cleaning and feature extraction processing, so as to take the processed wafer data as to-be-tested modules, and all the to-be-tested modules are subjected to fast iterative prediction analysis, and an analysis result is output; finally, comprehensive statistical analysis is performed according to the analysis result, and a correlation value R 2 of the yield of the abnormal wafer and the corresponding module parameter is output, so as to locate the failure position of the to-be-tested module according to the correlation value R 2 . The present application realizes comprehensive analysis of the correlation between the cause of low yield of abnormal silicon wafers and each process flow module through a linear regression automatic algorithm, can quickly locate abnormal points and perform cause analysis, so as to take relevant measures to avoid or block, avoid the occurrence of this type of situation again, and thus can effectively improve the yield and reliability of silicon wafers.

[0036] The wafer failure cause diagnosis method provided by the present application will be further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be clearer according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clarifying the description of the embodiments of the present application. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and therefore the present application is not limited to the specific embodiments disclosed below.

[0037] As shown in the present application and claims, unless the context clearly indicates otherwise, "one", "a", "an", and / or "the" do not refer to the singular, but also include the plural. Generally speaking, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements. In the detailed description of the embodiments of the present application, the cross-sectional view showing the device structure will be partially enlarged without general proportion, and the described schematic diagram is only an example, which should not limit the scope of protection of the present application. In addition, three-dimensional spatial dimensions including length, width and depth should be included in actual manufacture.

[0038] First, the wafer failure cause diagnosis method provided by the present application will be described in detail below. Specifically, reference can be made to Figures 2-3 shown,Figures 2-3 respectively are a model analysis flow chart and a fitting analysis result comprehensive analysis flow chart of a wafer failure cause diagnosis method provided in an embodiment of the present application; wherein the wafer failure cause diagnosis method can comprise the following steps:

[0039] Embodiment 1:

[0040] In step S100, referring to Figure 2 , a wafer group to be tested is provided, and the wafer group to be tested includes a plurality of abnormal wafers with different yields and a plurality of normal wafers. Specifically, in the embodiment, the material of the wafer is selected from single crystal silicon, polycrystalline silicon or amorphous silicon; the wafer can also be at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors; the wafer can also be a ceramic substrate such as aluminum oxide, a quartz or glass substrate or other semiconductor materials. For example, in the embodiment of the present application, the wafer is silicon. The abnormal wafer is a wafer that frequently fails during the manufacturing process.

[0041] In step S200, continuing to refer to Figure 2 , data detection is performed on the plurality of abnormal wafers with different yields and the plurality of normal wafers included in the wafer group to be tested, and the detected wafer data information is collected. Specifically, in the embodiment, the collected wafer data information is stored in a model, and in the embodiment, the stored model is a data pool; for example, the abnormal wafer contains abnormal data, and the normal wafer contains normal data, in order to improve the breadth of the collected data, the number of abnormal wafers and normal wafers included in the wafer group to be tested is uncertain.

[0042] In step S300, continuing to refer to Figure 2 , data is randomly extracted from the collected wafer data. Specifically, in the embodiment, in order to reduce the randomness of abnormal data, the wafer data collected in the data pool is extracted in a random mode; for example, the proportion of the randomly extracted data in all the collected wafer data is 80% to 100%. For example, in the embodiment, the proportion of the randomly extracted data in all the collected wafer data is more than 80%.

[0043] In step S400, continuing to refer to Figure 2The extracted wafer data within a specified range is cleaned. Specifically, in this embodiment, the randomly extracted wafer data is cleaned to achieve noise reduction. There are typically three methods for data cleaning: binning, clustering, and regression. Each method has its own advantages and can comprehensively remove noise. For example, in this embodiment, regression is used for data cleaning.

[0044] In step S500, continue to refer to Figure 2 Feature extraction processing is performed to use the processed wafer data as modules under test. Specifically, feature extraction processing is performed on the data after data information denoising and cleaning, and wafer data with different extracted features are defined as different modules, i.e., modules under test. Specifically, in this embodiment, the modules under test include at least two or more of the following: process technology, wafer acceptance testing, equipment, and production version.

[0045] In step S600, continue to refer to Figure 2 The system performs rapid iterative predictive analysis on all the modules to be tested and outputs the analysis results. Specifically, low yield is correlated with various modules in the wafer fabrication process. For example, in this embodiment, the principle of linear regression algorithm is used to perform rapid iterative predictive analysis on each module to determine whether there is a correlation between the modules to be tested. The linear regression algorithm is an automatic algorithm that can determine the number of rapid iterations for the modules to be tested. For example, in this embodiment, if a correlation exists, a result set is generated for each analysis until the Nth result set is generated through rapid iteration, in order to avoid randomness in the analysis results.

[0046] Determine whether a process node or parameter is likely related to a general rule by assessing its degree of conformity with it.

[0047] In step S700, please refer to the following for details. Figure 3 Based on the analysis results, a comprehensive statistical analysis is performed, and the correlation value R between the abnormal wafer yield and the corresponding module parameters is output. 2 Specifically, a linear regression algorithm is used to perform comprehensive statistical analysis on the analysis results. The linear regression algorithm R... 2 The formula is

[0048]

[0049] Among them, y n For the yield of a normal wafer, y a Let y represent the yield of defective wafers, and y^ represent the average yield of wafers. For example, in this embodiment, according to the linear regression algorithm R... 2The formula calculates the correlation between the abnormal wafer yield and the corresponding module parameter to be tested. Specifically, in the iteration analysis result, the critical value for determining whether the abnormal wafer yield and the corresponding module parameter to be tested have correlation is 0.8 according to the degree of coincidence with the general rule; when the R 2 >0.8, it is determined that the parameter corresponding to the module to be tested has correlation with the cause of low yield; when the R 2 <0.8, it is determined that there is no correlation between the parameter corresponding to the module and the cause of low yield. For example, in this embodiment, the R 2 >0.8, therefore, according to the comprehensive analysis, it is determined that there is a greater correlation between the abnormal wafer yield and the parameter of the module to be tested.

[0050] In step S800, continuing to refer to Figure 3 , the failure position of the module to be tested is located according to the correlation value R 2 . Specifically, in this embodiment, the failure position of the wafer to be tested is located according to the correlation determination result, and the located abnormal wafer is analyzed for failure, the correlation between the cause of low yield of the abnormal wafer and the corresponding module is listed, and the entire analysis process is ended.

[0051] Embodiment 2:

[0052] In this embodiment, steps S100-S500 are the same as the above steps in embodiment 1.

[0053] In step S600, continuing to refer to Figure 2 , the obtained all the modules to be tested are analyzed by fast iteration prediction, and the analysis result is output. Specifically, there is a certain correlation between the low yield and the modules in the wafer production process. For example, in this embodiment, the linear regression algorithm is used to analyze the fast iteration prediction of each module to determine whether there is correlation between the modules to be tested; and the linear regression algorithm is an automatic algorithm which can determine the number of fast iterations of the modules to be tested. For example, in this embodiment, if there is no correlation, it indicates that the correlation between the randomly selected data information is small, and it has no significance for subsequent analysis, then it returns to step S300 to randomly select wafer data above the specified range from the collected wafer data pool.

[0054] Embodiment 3:

[0055] In this embodiment, steps S100-S600 are the same as the above steps in embodiment 1.

[0056] In step S700, specifically referring to Figure 3, and output a correlation value R between the abnormal wafer yield and the corresponding module parameter according to the analysis result 2 . Specifically, a linear regression algorithm R 2 is used to perform comprehensive statistical analysis on the analysis result, and the formula of the linear regression algorithm R

[0057]

[0058] wherein y n is the yield of a normal wafer, y a is the yield of an abnormal wafer, and y^ is the average yield of the wafer. In this embodiment, the correlation between the abnormal wafer yield and the corresponding to-be-tested module parameter is calculated according to the linear regression algorithm R 2 . Specifically, in the iterative analysis result, the critical value for determining whether the abnormal wafer yield and the corresponding to-be-tested module parameter have a correlation is 0.8; when R 2 >0.8, it is determined that the parameter corresponding to the to-be-tested module has a correlation with the low yield reason; and when R 2 <0.8, it is determined that the parameter corresponding to the module has no correlation with the low yield reason. In this embodiment, R 2 <0.8, and therefore, it is determined that the abnormal wafer yield and the parameter corresponding to the to-be-tested module have no great correlation according to the comprehensive analysis, and the entire correlation analysis process is ended.

[0059] In summary, in the wafer failure reason diagnosis method provided by the present application, firstly, the to-be-tested wafer group including a plurality of abnormal wafers with different yields and a plurality of normal wafers is subjected to data detection and wafer data collection; secondly, data is randomly extracted from the wafer data, and the extracted wafer data is subjected to cleaning and feature extraction processing, so as to take the processed wafer data as to-be-tested modules, and all the to-be-tested modules are subjected to rapid iterative prediction analysis and output analysis result; finally, comprehensive statistical analysis is performed according to the analysis result, and a correlation value R 2 between the abnormal wafer yield and the corresponding module parameter is output; and the failure position of the to-be-tested module is located according to the correlation value R 2 . Through the linear regression automatic algorithm, the present application realizes comprehensive analysis of the correlation between the low yield reason of an abnormal wafer and each process flow module, can quickly locate the abnormal point and perform reason analysis, so as to take relevant avoidance or blocking measures to avoid the occurrence of this type of situation again, and thus the wafer yield and reliability can be effectively improved.

[0060] It should be noted that, although the present application has been described in terms of the preferred embodiments, the embodiments disclosed are not intended to define the scope of the present application. Those skilled in the art will be able to devise many alternative means and embodiments that, although not explicitly denoted in the above disclosure, nevertheless fall within the scope of the present application. Accordingly, all such modifications and variations are intended to be included within the scope of the present application as defined in the following claims in which:

[0061] It should also be understood that, unless specifically stated otherwise, the terms "first", "second", "third" and the like, in the description and in the claims, merely indicate different instances of elements, elements with a certain property, and do not imply a logical or chronological order of elements, steps, and / or sequences.

[0062] In addition, it is to be appreciated that the terms "comprises", "comprising", "includes", "including", "contains", "containing" or variations thereof do not specify a limited number of elements but encompass the same with eligibility to a plurality of elements. It is to be further understood that the terms "comprises", "comprising", "includes", "including", "contains", "containing" or variations thereof, when used in this specification and in the following claims, shall be construed as specifying the presence of stated features, regions, integers, steps or components but do not preclude the presence or addition of one or more other features, regions, integers, steps, components or groups thereof. In addition, it is to be understood that the use of certain terms, for example "one", "another", "at least one" and the like, can not imply that the terminology connotes a single element, unless the context clearly indicates otherwise. Furthermore, the use of certain terms in various places in the specification is merely for the sake of convenience of the description and does not necessarily have a corresponding limitation on the scope of the present application.

Claims

1. A method of diagnosing a wafer failure cause, characterized by, The method comprises the following steps: providing a wafer group to be tested, the wafer group to be tested comprising a plurality of abnormal wafers and a plurality of normal wafers with different yields, performing data detection on the wafer group to be tested and collecting wafer data; randomly extracting data from the wafer data, and performing cleaning and feature extraction processing on the extracted wafer data, so as to take the processed wafer data as a module to be tested; performing rapid iteration prediction analysis on all the modules to be tested, and outputting an analysis result; According to the analysis result, a comprehensive statistical analysis is performed, and a correlation value R of an abnormal wafer yield and a corresponding module parameter is output 2 ; According to the correlation value R 2 The failure position of the to-be-tested module is located.

2. The wafer failure cause diagnosis method according to claim 1, wherein the proportion of the randomly extracted data to the collected wafer data is 80% to 100%.

3. The wafer failure cause diagnostic method of claim 1, wherein The cleaning method of the wafer data is information denoising.

4. The wafer failure cause diagnostic method of claim 1, wherein The rapid iteration number of the module to be tested is determined by using a linear regression algorithm.

5. The wafer failure cause diagnostic method of claim 1, wherein, The correlation value R 2 is R 2 =1- ； where y n is the yield of normal wafers, y a is the yield of abnormal wafers, y ˄ is the average yield of wafers, i is the index of each wafer, RMSE is the root mean square error, and Var is the variance.

6. The wafer failure cause diagnostic method of claim 1, wherein, The module to be tested comprises at least two of process, wafer acceptance test, machine, and production version.

7. The wafer failure cause diagnostic method of claim 5, wherein, In the iterative analysis result, when the correlation value R 2 >0.8, it is determined that the parameter corresponding to the to-be-tested module is correlated with the low yield cause.

8. The wafer failure cause diagnostic method of claim 5, wherein, In the iterative analysis result, when the correlation value R 2 <0.8, it is determined that the parameter corresponding to the to-be-tested module is not correlated with the low yield cause.

9. The wafer failure cause diagnostic method according to Claim 7, wherein The failure position of the module to be tested is located according to the correlation determination result.

10. The wafer failure cause diagnostic method according to Claim 9, wherein The method further comprises performing failure analysis on the located abnormal wafer, and listing the reasons for the low yield of the abnormal wafer.

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