Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate, the substrate including an active region and an isolation region arranged along a first direction, the substrate including a substrate and a fin protruding from the substrate and extending along the first direction; forming a buried power rail in the substrate on the sides of the fin in the active region and the isolation region, the buried power rail for applying a first potential; forming a gate dielectric layer on the sidewalls and bottom of a gate opening and on the top and sidewalls of the fin; forming a contact hole in the isolation region, through the gate dielectric layer and the isolation layer, on top of the buried power rail; forming a gate electrode layer in the gate opening and the contact hole, the gate electrode layer electrically connected to the buried power rail in the isolation region; and forming a gate plug on top of the gate electrode layer in the active region, the gate plug for applying a second potential, the second potential being opposite to the first potential. This simplifies the process steps and reduces the probability of shorting between the gate electrode layer in the isolation region and adjacent components in the active region.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to advance towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, as functional density (i.e., the number of interconnect structures per chip) increases, geometric dimensions (i.e., the minimum component size that can be produced using process steps) decrease. The design of three-dimensional structures, such as fin field-effect transistors (FinFETs), has become a hot topic in the field. Furthermore, to create smaller and more densely distributed fins, existing technologies have introduced single diffusion break (SDB) structures. These SDB structures are typically distributed along the extension direction of the fin. Certain areas of the fin are removed through an etching process, forming one or more break trenches in the fin. The break trenches are then filled with insulating material to segment the fin along its extension direction, thereby preventing bridging between adjacent source and drain doping regions. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising an active region and an isolation region arranged along a first direction, the substrate comprising a substrate, and a fin protruding from the substrate and extending along the first direction; a buried power rail located in the substrate on the side of the fin in the active region and the isolation region, the buried power rail extending along the first direction, and being used to load a first potential; a first dielectric layer located on top of the substrate and the buried power rail and covering part of the sidewalls of the fin; a first opening located in the isolation region, the first opening being surrounded by the sidewalls of the first dielectric layer and the top of the buried power rail, and the first opening exposing the top surface of the buried power rail; a gate structure spanning the fins of the active region and the isolation region respectively, and the gate structure of the isolation region being used as a partition structure, the gate structure comprising a gate dielectric layer covering part of the top and part of the sidewalls of the fin and the top of the first dielectric layer, and also comprising a gate electrode layer covering the gate dielectric layer, wherein in the isolation region, projections of the gate electrode layer and the buried power rail on the substrate have an overlapping portion, and the gate The electrode layer is located in the first opening, and the gate electrode layer located in the isolation area penetrates the gate dielectric layer and the first dielectric layer at the top of the buried power rail and is electrically connected to the buried power rail; the sidewalls are located on the sidewalls of the gate structure; the source and drain doped layers are located in the fins on both sides of the gate structure and away from the sidewalls; the second dielectric layer is located on the substrate exposed by the gate structure, the second dielectric layer covers the sidewalls of the gate structure, and the top of the second dielectric layer is flush with the top of the gate structure; the second opening penetrates the second dielectric layer at the top of the source and drain doped layer, and the second opening exposes the top surface of the source and drain doped layer; the source and drain interconnection layer is located in the second opening, and the source and drain interconnection layer is electrically connected to the source and drain doped layer; the third dielectric layer is located on top of the gate structure and the second dielectric layer; the third opening is located in the working area, the third opening penetrates the third dielectric layer at the top of the gate structure and exposes the top surface of the gate structure; the gate plug is located in the third opening, the gate plug is electrically connected to the gate structure, and the gate plug is used to load a second potential, which is opposite to the first potential.

[0006] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an active region and an isolation region arranged along a first direction, the substrate comprising a substrate, and a fin protruding from the substrate and extending along the first direction, a buried power rail formed in the substrate on the side of the fin in the active region and the isolation region, the buried power rail extending along the first direction, an isolation layer formed on top of the buried power rail and the substrate, the isolation layer covering a portion of the sidewall of the fin, the buried power rail being used to load a first potential; forming a dummy gate layer on top of the substrate in the active region and the isolation region, spanning the fin and covering a portion of the top and sidewall of the fin, in the isolation region, the dummy gate layer and The projection of the buried power rail on the substrate has an overlapping portion; an interlayer dielectric layer is formed on the isolation layer exposed by the dummy gate layer; the dummy gate layer is removed, and a gate opening is formed in the interlayer dielectric layer; a gate dielectric layer is formed on the sidewalls and bottom of the gate opening, and on the top and sidewalls of the fin; in the isolation region, a contact hole is formed on the top of the buried power rail, penetrating the gate dielectric layer and the isolation layer; a gate electrode layer is formed in the gate opening and the contact hole, the gate electrode layer covers the gate dielectric layer, and the gate electrode layer is electrically connected to the buried power rail located in the isolation region; a gate plug is formed on the top of the gate electrode layer in the working region, the gate plug is used to load a second potential, and the second potential is opposite to the first potential.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] An embodiment of the present invention provides a semiconductor structure, wherein a buried power rail is located in a substrate on the side of a fin in an active region and an isolation region. The buried power rail extends along a first direction, and in the isolation region, a gate electrode layer in a gate structure is electrically connected to the buried power rail. Therefore, a first potential can be directly applied to the gate structure in the isolation region via the buried power rail, enabling the gate structure in the isolation region to serve as a partition structure. This eliminates the need to form a gate plug on top of the gate structure in the isolation region. Since the gate plug is omitted, the probability of a short circuit between the gate structure in the isolation region and adjacent components in the active region is reduced, thereby improving the performance of the semiconductor structure.

[0009] An embodiment of the present invention provides a method for forming a semiconductor structure. In the step of providing a base, a buried power rail is formed in the substrate on the side of the fin in the working area and the isolation area; then, a gate dielectric layer and a gate electrode layer are formed in the working area and the isolation area, wherein the gate electrode layer in the isolation area is electrically connected to the buried power rail. Therefore, a first potential can be directly applied to the gate electrode layer in the isolation area through the buried power rail, so that the gate electrode layer and the gate dielectric layer in the isolation area can serve as a partition structure. This eliminates the need for the subsequent step of forming a gate plug on top of the gate electrode layer in the isolation area. Since the need for forming a gate plug on top of the gate electrode layer in the isolation area is eliminated, the probability of short circuit between the gate electrode layer in the isolation area and adjacent components in the working area is reduced, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural diagram of a semiconductor structure;

[0011] Figures 2 to 4 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0012] Figures 5 to 22 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in conjunction with a method for forming a semiconductor structure.

[0014] Figure 1 It is a structural diagram of a semiconductor structure.

[0015] refer to Figure 1 The semiconductor structure includes: a substrate, the substrate including a first direction (such as Figure 1The substrate includes an active area 10A and an isolation area 10B arranged along the X direction (shown in the middle X direction), the substrate includes a substrate (not shown) and a fin 10 protruding from the substrate and extending along the first direction; a gate structure 11 spanning the fins 10 in the active area 10A and the isolation area 10B respectively; a source-drain doped layer (not shown) located in the substrate on both sides of the gate structure 11; a source-drain interconnect layer 12 located on both sides of the gate structure 11 and covering the top of the source-drain doped layer; a first gate plug 13 located on top of the gate structure 11 in the isolation area 10B, the first gate plug 13 being electrically connected to the gate structure 11 and configured to apply a first potential; and a second gate plug 16 located on top of the gate structure 11 in the active area 10A, the second gate plug 16 being electrically connected to the gate structure 11 and configured to apply a second potential, the second potential being opposite to the first potential.

[0016] The second potential and the first potential are opposite potentials, so the gate structure 11 of the isolation region 10B can be used as a partition structure.

[0017] However, under current development trends, the increase in device density has brought about numerous problems. Specifically, due to limitations in lithography equipment, the first gate plug 13 located at the top of the gate structure 11 in the isolation region 10B is too large. This cannot meet the process requirements for smaller first gate plugs 13 or the smaller spacing between adjacent gate structures 11. This increases the probability of shorting between the first gate plug 13 and the adjacent source-drain interconnect layer 12, and correspondingly increases the probability of shorting between the first gate plug 12 and the adjacent source-drain doped layer.

[0018] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an active region and an isolation region arranged along a first direction, the substrate comprising a substrate, and a fin protruding from the substrate and extending along the first direction, a buried power rail formed in the substrate on the side of the fin in the active region and the isolation region, the buried power rail extending along the first direction, an isolation layer formed on top of the buried power rail and the substrate, the isolation layer covering a portion of the sidewall of the fin, the buried power rail being used to load a first potential; forming a dummy gate layer on top of the substrate in the active region and the isolation region, spanning the fin and covering a portion of the top and sidewall of the fin, in the isolation region, the dummy gate layer The projections of the gate layer and the buried power rail on the substrate have overlapping parts; an interlayer dielectric layer is formed on the isolation layer exposed by the dummy gate layer; the dummy gate layer is removed, and a gate opening is formed in the interlayer dielectric layer; a gate dielectric layer is formed on the sidewalls and bottom of the gate opening, and on the top and sidewalls of the fin; in the isolation region, a contact hole is formed on the top of the buried power rail, penetrating the gate dielectric layer and the isolation layer; a gate electrode layer is formed in the gate opening and the contact hole, the gate electrode layer covers the gate dielectric layer, and the gate electrode layer is electrically connected to the buried power rail located in the isolation region; a gate plug is formed on the top of the gate electrode layer in the working region, the gate plug is used to load a second potential, and the second potential is opposite to the first potential.

[0019] In the formation method provided by an embodiment of the present invention, in the step of providing a substrate, a buried power rail is formed in the substrate on the side of the fin in the working area and the isolation area; then, a gate dielectric layer and a gate electrode layer are formed in the working area and the isolation area, wherein the gate electrode layer located in the isolation area is electrically connected to the buried power rail, so that a first potential can be directly applied to the gate electrode layer in the isolation area through the buried power rail, so that the gate electrode layer and the gate dielectric layer in the isolation area can serve as a partition structure, which eliminates the subsequent step of forming a gate plug on top of the gate electrode layer in the isolation area. Since the formation of the gate plug on top of the gate electrode layer in the isolation area is eliminated, the probability of short circuit between the gate electrode layer in the isolation area and the adjacent components in the working area is reduced, thereby improving the performance of the semiconductor structure.

[0020] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0021] Figures 2 to 4 1 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention, wherein: Figure 2 It is a top view. Figure 3 yes Figure 2 Cross-sectional view along the ab direction, Figure 4 yes Figure 2 Cross-sectional view along the ab direction.

[0022] For the convenience of illustration, Figure 2 Only the gate electrode layer 218 , the buried power rail 200 , the fin 202 , the isolation structure 219 , the source-drain interconnect layer 290 and the gate plug 220 are illustrated.

[0023] The semiconductor structure includes: a substrate, the substrate including a first direction (such as Figure 2The substrate includes an active area 200A and an isolation area 200B arranged in a direction (shown in the X direction in the figure), the substrate includes a substrate 203, and a fin 202 protruding from the substrate 203 and extending along a first direction; a buried power rail 200 is located in the substrate 203 on the side of the fin 202 in the active area 200A and the isolation area 200B, the buried power rail 200 extends along the first direction, and is used to apply a first potential; a first dielectric layer 201 is located on top of the substrate 203 and the buried power rail 200 and covers a portion of the sidewall of the fin 202; a first opening (not shown) is located in the isolation area 200B, and the first opening is formed by the sidewall of the first dielectric layer 201. and the top of the buried power rail 200, and the first opening exposes the top surface of the buried power rail 200; the gate structure 260 spans the fins 202 of the working area 200A and the isolation area 200B respectively, and the gate structure 260 of the isolation area 200B is used as a partition structure, the gate structure 260 includes a gate dielectric layer 212 covering a portion of the top and a portion of the sidewall of the fin 202 and the top of the first dielectric layer 201, and also includes a gate electrode layer 218 covering the gate dielectric layer 212. In the isolation area 200B, the gate electrode layer 218 and the projection of the buried power rail 200 on the substrate 203 have an overlapping portion, and the gate electrode layer 218 is located at the first dielectric layer 201. The gate electrode layer 218 in the opening and located in the isolation region 200B penetrates the gate dielectric layer 212 and the first dielectric layer 201 at the top of the buried power rail 200 and is electrically connected to the buried power rail 200; the sidewall 208 is located on the sidewall of the gate structure 260; the source and drain doped layers (not shown) are located in the fins 202 on both sides of the gate structure 260 and away from the side of the sidewall 208; the second dielectric layer 209 is located on the substrate 203 exposed by the gate structure 260, the second dielectric layer 209 covers the sidewall of the gate structure 260, and the top of the second dielectric layer 209 is flush with the top of the gate structure 260; the second opening (not shown) penetrates the sidewalls of the source and drain A second dielectric layer 209 is formed on top of the doped layer, and a second opening exposes the top surface of the source-drain doped layer; a source-drain interconnection layer 290 is located in the second opening, and the source-drain interconnection layer 290 is electrically connected to the source-drain doped layer; a third dielectric layer 221 is located on top of the gate structure 260 and the second dielectric layer 209; a third opening is located in the working area 200A, and the third opening penetrates the third dielectric layer 221 on top of the gate structure 260 and exposes the top surface of the gate structure 260; a gate plug 220 is located in the third opening, and the gate plug 220 is electrically connected to the gate structure 260. The gate plug 220 is used to load a second potential, and the second potential is opposite to the first potential.

[0024] In this embodiment, the buried power rail 200 is located in the substrate 203 on the sides of the fin 202 in the active region 200A and the isolation region 200B. The buried power rail 200 extends along a first direction. In the isolation region 200B, the gate electrode layer 218 in the gate structure 260 is electrically connected to the buried power rail 200. Therefore, a first potential can be directly applied to the gate structure 260 in the isolation region 200B via the buried power rail 200, enabling the gate structure 260 in the isolation region 200B to serve as a partition structure. This eliminates the need to form a gate plug 220 on top of the gate structure 260 in the isolation region 200B. Since the gate plug 220 is omitted, the probability of shorting between the gate structure 260 in the isolation region 200B and adjacent components in the active region 200A is reduced, thereby improving the performance of the semiconductor structure.

[0025] In this embodiment, the substrate is used to form a fin field effect transistor (FinFET), and includes a substrate 203 and a fin 202 protruding from the substrate 203. In other embodiments, when the substrate is used to form a planar field effect transistor, the substrate is correspondingly a planar substrate.

[0026] In this embodiment, the material of the fin 202 is the same as that of the substrate 203, both being silicon. In other embodiments, the substrate may be made of germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0027] The buried power rail 200 is used to achieve electrical connection with the gate electrode layer 218 in the isolation region 200B. The first potential can be directly applied to the gate electrode layer in the isolation region 200B through the buried power rail 200 .

[0028] In this embodiment, in the step of providing a substrate, the substrate includes a device cell region 200C, and the device cell region 200C includes an active region 200A and an isolation region 200B arranged along a first direction. In the device cell region 200C, the active region 200A shares a gate structure 260 .

[0029] In this embodiment, in the second direction (such as Figure 2 At the boundary of the device unit area 200C on the substrate 200 (as shown in the Y direction), the buried power rail 200 extending along the first direction is formed in the substrate 200, and the second direction is perpendicular to the first direction.

[0030] It should be noted that the external interconnection structure connected to the buried power rail 200 in the isolation area 200B is usually located at the boundary of the device unit area 200C in the second direction. Therefore, in order to reduce the impact on traditional circuit design, the buried power rail 200 is located at the boundary of the device unit area 200C in the second direction.

[0031] In this embodiment, the buried power rail 200 is made of tungsten. Tungsten has a low resistivity, which helps improve signal delay in the downstream RC circuit and increase chip processing speed. It also helps reduce the resistance of the buried power rail 100, thereby reducing power consumption. In other embodiments, the buried power rail can also be made of conductive materials such as cobalt, ruthenium, or nickel.

[0032] It should be noted that, with the lateral dimension of the buried power rail 200 perpendicular to the extension direction of the fin 202 (i.e., the second direction) being defined as the lateral dimension, the lateral dimension of the buried power rail 200 should be neither too large nor too small. If the lateral dimension of the buried power rail 200 is too large, given a given lateral dimension of the semiconductor structure, the device density per unit area in the active region 200A may be reduced, thereby affecting the performance of the semiconductor structure. If the lateral dimension of the buried power rail 200 is too small, during the formation process of the semiconductor structure, the process window for forming a contact hole on top of the buried power rail 200 in the isolation region 200B may be reduced, thereby increasing the difficulty of forming the contact hole. Furthermore, the process window for electrically connecting the gate electrode layer in the isolation region 200B to the buried power rail 200 may also be reduced. Furthermore, the probability of damage to the substrate 203 in contact with the buried power rail 200 may be increased, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, with the direction perpendicular to the extending direction of the fin 202 as the lateral direction, the lateral dimension of the buried power rail 200 is 30 nm to 100 nm.

[0033] In this embodiment, the semiconductor structure further includes an insulating layer 206 located between the substrate 203 and the buried power rail 200 .

[0034] The insulating layer 206 is used to electrically isolate the substrate 203 from the buried power rail 200 , thereby reducing the risk of a short circuit between the buried power rail 200 and the substrate 203 .

[0035] In this embodiment, the material of the insulating layer 206 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0036] The isolation layer 201 is used to isolate adjacent devices. The isolation layer 201 is used as a shallow trench isolation structure. In this embodiment, the isolation layer 201 is made of silicon oxide.

[0037] The second dielectric layer 209 is used to isolate adjacent devices. The material of the second dielectric layer 209 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second dielectric layer 209 is silicon oxide.

[0038] Specifically, the second dielectric layer 209 serves as the first second dielectric layer.

[0039] When the transistor device is operating, the gate structure 260 in the device region 200A is used to control the on or off of the conductive channel.

[0040] The gate structure 260 of the isolation region 200B is used as a partition structure to electrically isolate the transistors in the adjacent working region 200A.

[0041] It should be noted that the gate structure 260 formed in the isolation region 200B is used as a partition structure. Compared with the existing solution of cutting fins and forming a partition structure in the fins of the isolation region, this embodiment omits the process step of cutting the fins 200 in the isolation region 200B, reduces the impact of the cutting process on the conductive channel in the fins 200, and at the same time, reduces the probability of other process defects during the cutting process.

[0042] The first opening (not shown) provides a space for the gate electrode layer 218 located in the isolation region 200B.

[0043] In this embodiment, the gate structure 260 is a metal gate structure, and the device gate structure 202 includes a gate dielectric layer 212 and a gate electrode layer 218 covering the gate dielectric layer 212 .

[0044] In this embodiment, the material of the gate dielectric layer 212 includes one or more of HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 and La 2 O 3 .

[0045] The gate electrode layer 218 is used for subsequent electrical connection to external interconnect structures. The material of the gate electrode layer 218 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0046] It should be noted that, in order to electrically connect the gate electrode layer 218 formed in the isolation region 200B to the buried power rail 200 , in the isolation region 200B, the projections of the gate electrode layer 218 and the buried power rail 200 on the substrate 203 have an overlapping portion.

[0047] The gate electrode layer 218 in the isolation region 200B is electrically connected to the buried power rail 200 , and the buried power rail 200 is used to load a first potential, so that the gate structure 260 in the isolation region 200B is loaded with the first potential through the buried power rail 200 .

[0048] In this embodiment, the gate structure 260 further includes a work function layer 211 located between the gate dielectric layer 212 and the gate electrode layer 218 . The gate electrode layer 218 located in the isolation region 200B also penetrates the work function layer 211 .

[0049] The work function layer 211 is used to adjust the threshold voltage of the formed transistor.

[0050] In this embodiment, the material of the work function layer 211 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0051] In this embodiment, the gate electrode layer 218 located in the isolation region 200B penetrates the work function layer 211, which is conducive to the electrical connection between the gate electrode layer 218 and the top surface of the buried power rail 200. At the same time, the gate electrode layer 218 is in contact with and directly electrically connected to the buried power rail 200, thereby reducing the contact resistance between the gate electrode layer 218 and the buried power rail 200, thereby improving the performance of the semiconductor structure.

[0052] In this embodiment, the semiconductor structure further includes a sidewall spacer 208 located on a sidewall of the gate structure 260 .

[0053] The sidewall spacer 208 is used to protect the sidewalls of the gate structure 260. The sidewall spacer 208 can have a single-layer structure or a stacked-layer structure. The material of the sidewall spacer 208 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacer 208 has a single-layer structure and is made of silicon nitride.

[0054] In this embodiment, the semiconductor structure further includes an isolation structure 219 located in the isolation region 200B and penetrating the gate structure 260 . The isolation structure 219 is used to divide the gate structure 260 in the extension direction of the gate structure 260 .

[0055] The isolation structure 219 is arranged along the second direction (eg Figure 2 The gate structure 260 in the isolation region 200B is divided in the Y direction (as shown in FIG. 2 ), thereby achieving the requirement of separately controlling the gate structure 260 in the isolation region 200B.

[0056] The material of the isolation structure 219 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. As an example, the material of the isolation structure 219 is silicon nitride.

[0057] Silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride are all insulating materials that can effectively isolate adjacent devices.

[0058] In this embodiment, the semiconductor structure further includes source and drain doping layers (not shown), which are located in the substrate on both sides of the device gate structure 260. The source and drain doping layers are used as source regions or drain regions of the transistor.

[0059] In this embodiment, the semiconductor structure further includes a source-drain interconnection layer 290 located between adjacent gate structures 260 and covering the top of the source-drain doped layer. Specifically, the source-drain interconnection layer 290 penetrates the second dielectric layer 209 between adjacent gate structures 260.

[0060] The source-drain interconnection layer 290 is electrically connected to the source-drain doping layer (not shown) to achieve electrical connection between the source-drain doping layer and an external circuit or other interconnection structure.

[0061] Since the step of forming a gate plug on the top of the gate structure 260 in the isolation region 200B is omitted, the probability of short circuit between the gate structure 260 in the isolation region 200B and the adjacent source-drain interconnection layer 290 in the working region 200A is reduced, thereby improving the performance of the semiconductor structure.

[0062] The second opening exposes the top surface of the source-drain doped layer, and the second opening provides a spatial position for the source-drain interconnection layer 290 .

[0063] In this embodiment, the semiconductor structure further includes a third dielectric layer 221 located on top of the gate structure 260 , the spacer 208 and the second dielectric layer 209 .

[0064] The third dielectric layer 221 is used to isolate the gate plug 220 located in the active area 200A.

[0065] The material of the third dielectric layer 221 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the third dielectric layer 221 is silicon oxide.

[0066] The third opening is located in the active area 200A and exposes the top surface of the gate structure 260 . The third opening provides a space for the gate plug 220 .

[0067] The gate plug 220 is used to realize electrical connection between the gate electrode layer 218 in the active area 200A and external circuits or other interconnection structures.

[0068] In this embodiment, in the working area 200A, the gate plug 220 penetrates the third dielectric layer 221 located on the top of the gate structure 260 .

[0069] In this embodiment, the gate plug 220 is made of tungsten. Tungsten has a low resistivity, which helps improve signal delay in the back-end RC circuit and increase chip processing speed. It also helps reduce the resistance of the gate plug 220, thereby reducing power consumption. In other embodiments, the gate plug can also be made of conductive materials such as cobalt, ruthenium, or nickel.

[0070] In this embodiment, the gate electrode layer 218 formed in the isolation region 200B serves to electrically isolate the adjacent working region 200A.

[0071] Specifically, the buried power rail 200 is used to load a first potential, and the gate plug 220 is used to load a second potential, where the second potential is opposite to the first potential.

[0072] In this embodiment, the gate electrode layer 218 in the isolation region 200B is electrically connected to the buried power rail 200, and a first potential is applied to the gate structure 260 in the isolation region 200B through the buried power rail 200. Therefore, by making the second potential and the first potential opposite potentials, no current is conducted between the device regions 200A on both sides of the isolation region 200B, thereby enabling the gate structure 260 in the isolation region 200B to serve as a partition structure.

[0073] Specifically, when the device region 200A is used as an NMOS transistor, in order to be able to electrically isolate the adjacent NMOS transistor, the first potential loaded on the gate electrode layer 218 in the isolation region 200B is used as a cutoff gate voltage. Since the NMOS transistor in the device region 200A needs to be loaded with a positive second potential to be turned on, the gate electrode layer 218 in the isolation region 200B needs to be loaded with a negative voltage, so that no current is conducted between the device regions 200A on both sides of the isolation region 200B, and thus the gate electrode layer 218 in the isolation region 200B can achieve the effect of electrical isolation.

[0074] When the device region 200A is used as a PMOS transistor, in order to electrically isolate the adjacent PMOS transistor, the gate electrode layer 218 located in the isolation region 200B has a first potential loaded on the gate electrode layer 218 in the isolation region 100B and is used as a cutoff gate voltage. Since the PMOS transistor in the device region 100A needs to be loaded with a negative second potential to be turned on, the gate electrode layer 118 in the isolation region 100B needs to be loaded with a positive voltage, so that no current is conducted between the device regions 200A on both sides of the isolation region 200B, and thus the gate electrode layer 218 located in the isolation region 200B can achieve an electrical isolation effect.

[0075] Figures 5 to 22 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0076] refer to Figures 5 and 6 ,in, Figure 5 It is a top view. Figure 6 yes Figure 5 A cross-sectional view along the AB direction provides a substrate, wherein the substrate includes a first direction (such as Figure 5 The base includes an active area 100A and an isolation area 100B arranged along the first direction (as shown in the X direction in FIG). The base includes a substrate 103 and a fin 102 protruding from the substrate 103 and extending along the first direction. A buried power rail 100 is formed in the substrate 103 on the side of the fin 102 in the active area 100A and the isolation area 100B. The buried power rail 100 extends along the first direction. An isolation layer 101 is formed on top of the buried power rail 100 and the substrate 103. The isolation layer 101 covers a portion of the sidewall of the fin 102. The buried power rail 100 is used to apply a first potential.

[0077] The substrate is used to provide a process platform for subsequent process steps.

[0078] In this embodiment, the substrate is used to form a fin field effect transistor (FinFET), and includes a substrate 103 and a fin 102 protruding from the substrate 103. In other embodiments, when the substrate is used to form a planar field effect transistor, the substrate is correspondingly a planar substrate.

[0079] In this embodiment, the material of the fin 102 is the same as that of the substrate 103, both being silicon. In other embodiments, the substrate may be made of germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0080] The buried power rail 100 is used to subsequently achieve electrical connection with a gate electrode layer formed in the isolation region 100B. The first potential can be directly applied to the gate electrode layer in the isolation region 100B through the buried power rail 100, eliminating the need for a subsequent step of forming a gate plug on top of the gate electrode layer in the isolation region 100B. This simplifies the process steps and reduces the complexity of the process steps. At the same time, since the formation of a gate plug on top of the gate electrode layer in the isolation region 100B is omitted, the probability of short circuit between the gate electrode layer in the isolation region 100B and adjacent components in the working region 100A is reduced, thereby improving the performance of the semiconductor structure.

[0081] In this embodiment, in the step of providing a substrate, the substrate includes a device cell region 100C, and the device cell region 100C includes an active region 100A and an isolation region 100B arranged along a first direction. In the device cell region 100C, the active region 100A shares a gate structure.

[0082] In this embodiment, in the second direction (such as Figure 5 At the boundary of the device unit area 100C on the substrate 100 (as shown in the Y direction), the buried power rail 100 extending along the first direction is formed in the substrate 100, and the second direction is perpendicular to the first direction.

[0083] It should be noted that, in the isolation region 100B, the interconnection structure subsequently connected to the buried power rail 100 is generally located at the boundary of the device unit region 100C in the second direction. Therefore, in order to reduce the impact on the traditional circuit design, the buried power rail 100 is located at the boundary of the device unit region 100C in the second direction.

[0084] In this embodiment, the step of forming the buried power rail 100 includes: forming an opening (not shown) extending along the first direction in the substrate 103 at the side of the fin 102; and forming the buried power rail 100 in the opening.

[0085] The opening provides a space for the subsequent formation of an insulating layer and a buried power rail 100 .

[0086] Specifically, the step of forming the buried power rail 100 in the opening includes: forming a conductive material layer (not shown) in the opening and on the substrate 103 where the fin 102 is exposed; etching back the conductive material layer on the substrate 103, and the conductive material layer in the opening serves as the buried power rail 100.

[0087] In this embodiment, the buried power rail 100 is made of tungsten. Tungsten has a low resistivity, which helps improve signal delay in the downstream RC circuit and increase chip processing speed. It also helps reduce the resistance of the buried power rail 100, thereby reducing power consumption. In other embodiments, the buried power rail can also be made of conductive materials such as cobalt, ruthenium, or nickel.

[0088] It should be noted that, with the lateral dimension of the buried power rail 100 perpendicular to the extension direction of the fin 102 (i.e., the second direction) being defined as the lateral dimension, the lateral dimension of the buried power rail 100 should be neither too large nor too small. If the lateral dimension of the buried power rail 100 is too large, given a given lateral dimension of the semiconductor structure, the device density per unit area in the active region 100A may be reduced, thereby affecting the performance of the semiconductor structure. If the lateral dimension of the buried power rail 100 is too small, the subsequent process window for forming a contact hole on top of the buried power rail 100 in the isolation region 100B may be reduced, thereby increasing the difficulty of forming the contact hole. Furthermore, the process window for achieving electrical connection between the gate electrode layer subsequently formed in the isolation region 100B and the buried power rail 100 is correspondingly reduced. Furthermore, the probability of damage to the substrate 103 in contact with the buried power rail 100 is increased, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, with the direction perpendicular to the extending direction of the fin 102 as the lateral direction, the lateral dimension of the buried power rail 100 is 30 nm to 100 nm.

[0089] In this embodiment, before forming the buried power rail 100 in the opening, the method further includes: forming an insulating layer 106 on the sidewall of the opening.

[0090] The insulating layer 106 is used to electrically isolate the substrate 103 from the buried power rail 100 , thereby reducing the risk of a short circuit between the buried power rail 100 and the substrate 103 .

[0091] In this embodiment, the material of the insulating layer 106 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0092] Specifically, the step of forming an insulating layer 106 on the side wall of the opening includes: forming an insulating material layer (not shown) on the side wall and bottom of the opening, the top of the substrate 103, and the side wall of the fin 102; removing the insulating material layer on the top of the substrate 103 and the side wall of the fin 102, and the remaining insulating material layer located on the side wall of the opening serves as the insulating layer 106.

[0093] In this embodiment, the method for forming the semiconductor structure further includes: after forming the buried power rail 100 , forming an isolation layer 101 on top of the substrate 100 , the insulating layer 106 and the buried power rail 100 exposed by the fin 102 , wherein the isolation layer covers a portion of the sidewall of the fin 102 .

[0094] The isolation layer 101 is used to isolate adjacent devices. The isolation layer 201 is used as a shallow trench isolation structure. In this embodiment, the isolation layer 101 is made of silicon oxide.

[0095] refer to Figures 7 and 8 ,in, Figure 7 It is a top view. Figure 8 yes Figure 7 In the cross-sectional view along the AB direction, a dummy gate layer 107 is formed on the top of the substrate of the working area 100A and the isolation area 100B, spanning the fin 102 and covering part of the top and part of the sidewall of the fin 102. In the isolation area 100B, the projection of the dummy gate layer 107 and the buried power rail 100 on the substrate 103 has an overlapping portion.

[0096] The dummy gate layer 107 occupies space for the gate electrode layer and gate dielectric layer to be formed subsequently.

[0097] In this embodiment, the dummy gate layer 107 is made of polysilicon. In other embodiments, the dummy gate layer may be made of amorphous carbon, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbon oxynitride.

[0098] It should be noted that, since the dummy gate layer 107 occupies a spatial position for the subsequent formation of a gate electrode layer, and at the same time, in order to electrically connect the gate electrode layer formed in the isolation region 100B to the buried power rail 100, the top of the buried power rail 100 in the isolation region 100B is covered with a gate electrode layer, that is, the top of the buried power rail 100 in the isolation region 100B is covered with a dummy gate layer 107. Therefore, the projections of the dummy gate layer 107 and the buried power rail 100 on the substrate 103 have an overlapping part.

[0099] In this embodiment, the method for forming the semiconductor structure further includes: after forming the dummy gate layer 107 , forming source and drain doping layers (not shown) in the fins 102 on both sides of the dummy gate layer 107 .

[0100] The source-drain doped layer is used as a source region or a drain region of a transistor.

[0101] refer to Figure 9 An interlayer dielectric layer 109 is formed on the isolation layer 101 exposed by the dummy gate layer 107 .

[0102] Specifically, the interlayer dielectric layer 109 serves as a first interlayer dielectric layer.

[0103] The interlayer dielectric layer 109 is used to isolate adjacent devices. The material of the interlayer dielectric layer 109 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 109 is silicon oxide.

[0104] In this embodiment, after forming the dummy gate layer 107 and before forming the interlayer dielectric layer 109 , the process further includes forming a spacer 108 on the sidewall of the dummy gate layer 107 .

[0105] The sidewall spacers 108 are used to protect the sidewalls of the subsequently formed gate structure. The sidewall spacers 108 may be a single-layer structure or a stacked-layer structure, and the material of the sidewall spacers 108 may include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacers 108 are a single-layer structure, and the material of the sidewall spacers 108 is silicon nitride.

[0106] refer to Figures 10 and 11 ,in, Figure 10 It is a top view. Figure 11 yes Figure 10 In the cross-sectional view along the AB direction, the dummy gate layer 107 is removed, and a gate opening 110 is formed in the interlayer dielectric layer 109 .

[0107] The gate opening 110 provides a space for the subsequent formation of a gate dielectric layer and a gate electrode layer.

[0108] In this embodiment, the process of removing the dummy gate layer 107 includes a dry etching process.

[0109] refer to Figure 12 A gate dielectric layer 112 is formed on the sidewalls and bottom of the gate opening 110 and the top and sidewalls of the fin 102 .

[0110] In this embodiment, the gate dielectric layer 112 is made of one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. Specifically, the gate dielectric layer 112 is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.

[0111] It should be noted that, in the step of forming the gate dielectric layer 112 , the gate dielectric layer 112 is also formed on top of the interlayer dielectric layer 109 .

[0112] In this embodiment, the process of forming the gate dielectric layer 112 includes an atomic layer deposition process.

[0113] Specifically, the atomic layer deposition process includes multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the gate dielectric layer 112, so that the gate dielectric layer 112 can cover the sidewalls and bottom of the gate opening 110, the top and sidewalls of the fin 102, and the top of the interlayer dielectric layer 109; in addition, the atomic layer deposition process has good gap filling performance and step coverage, which correspondingly improves the conformal coverage capability of the gate dielectric layer 112.

[0114] Continue to refer Figure 12 After forming the gate dielectric layer 112 , a work function layer 111 covering the gate dielectric layer 112 is formed.

[0115] The work function layer 111 is used to adjust the threshold voltage of the formed transistor.

[0116] In this embodiment, the material of the work function layer 111 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0117] In this embodiment, the process of forming the work function layer 111 includes an atomic layer deposition process.

[0118] refer to Figures 13 to 15 ,in, Figure 14 It is a top view. Figure 15 yes Figure 14 In the cross-sectional view along the AB direction, a contact hole 117 is formed on the top of the buried power rail 100 in the isolation region 100B, penetrating the gate dielectric layer 112 and the isolation layer 101 .

[0119] The contact hole 117 provides a spatial location for the subsequent formation of a gate electrode layer, so that the subsequently formed gate electrode layer can be electrically connected to the buried power rail 100, thereby directly applying a first potential to the gate electrode layer in the isolation region 100B through the buried power rail 100, eliminating the step of forming a gate plug on top of the gate electrode layer in the isolation region 100B, thereby reducing the probability of short circuit between the gate electrode layer in the isolation region 100B and adjacent components (for example, source and drain doping layers) in the active region 100A.

[0120] Combined with reference Figures 13 to 15 , the step of forming a contact hole 117 on the top of the buried power rail 100 that penetrates the gate dielectric layer 112 and the isolation layer 101 is described in detail.

[0121] refer to Figure 13 A mask layer 113 having a mask opening 116 is formed on the top of the substrate 103 . The mask layer 113 covers the top and sidewalls of the fin 102 . The mask opening 116 is located at the top of the buried power rail 100 .

[0122] The mask layer 113 serves as an etching mask for forming the contact hole 117 .

[0123] In this embodiment, the mask layer 113 includes a filling layer, an anti-reflection coating layer on the filling layer, and a photoresist layer on the anti-reflection coating layer.

[0124] The material of the filling layer includes an organic material. In this embodiment, the material of the filling layer is spin-on carbon (SOC). In other embodiments, the material of the filling layer can also be other organic materials, such as: one or more of: ODL (organic dielectric layer) material, DUO (Deep UV Light Absorbing Oxide) material and APF (Advanced Patterning Film) material.

[0125] The material of the anti-reflective coating includes a BARC (bottom anti-reflective coating) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

[0126] In this embodiment, during the process of forming the mask layer 113 , the anti-reflective coating layer and the organic material layer are sequentially etched using the photoresist layer as a mask.

[0127] It should be noted that, in other embodiments, the photoresist layer will be consumed during the etching of the anti-reflective coating and the organic material layer, and the mask layer may accordingly only include the organic material layer and the anti-reflective coating on the organic material layer.

[0128] In this embodiment, in the step of forming a mask layer 113 having a mask opening 116 on the top of the substrate 103 , the mask opening 116 also exposes the gate dielectric layer 112 on the top of the interlayer dielectric layer 109 .

[0129] The mask opening 116 exposes the gate dielectric layer 112 on the top of the interlayer dielectric layer 109, which is beneficial to increasing the process window of the photolithography process used to form the mask opening 116. Moreover, when the contact hole 116 is formed, the gate dielectric layer 112 on the top of the interlayer dielectric layer 109 is also removed, eliminating the subsequent process step of planarizing the gate dielectric layer 112 on the top of the interlayer dielectric layer 109, thereby simplifying the process steps and reducing the process cost.

[0130] refer to Figures 14 and 15 Using the mask layer 113 as a mask, the gate dielectric layer 112 and the isolation layer 101 exposed by the mask opening 116 are etched to form a contact hole 117 exposing the buried power rail 100 .

[0131] In this embodiment, the process of etching the gate dielectric layer 112 and the isolation layer 101 using the mask layer 113 as a mask includes an anisotropic dry etching process.

[0132] The anisotropic dry etching process has anisotropic etching characteristics, and its longitudinal etching rate is much greater than the lateral etching rate. It can obtain quite accurate pattern transfer, improve the morphology quality of the sidewall of the contact hole 117, and facilitate precise control of the size of the contact hole 117 along the second direction. At the same time, the dry etching process has high process controllability, and during the process of forming the contact hole 117, the probability of damaging the adjacent structures on the side of the buried power rail 100 is reduced.

[0133] It should be noted that, in the step of forming the contact hole 117 , the contact hole 117 also penetrates the work function layer 111 .

[0134] Specifically, the contact hole 117 penetrates the work function layer 111, and the contact hole 117 exposes the top surface of the buried power rail 100, which is conducive to the electrical connection between the subsequently formed gate electrode layer and the top surface of the buried power rail 100. At the same time, the gate electrode layer is directly electrically connected to the buried power rail 100, reducing the contact resistance between the gate electrode layer and the buried power rail 100, thereby improving the performance of the semiconductor structure.

[0135] It should be noted that the size of the contact hole 117 along the second direction should not be too large or too small. If the size of the contact hole 117 along the second direction is too large, the probability of the gate electrode layer subsequently formed in the contact hole 117 contacting the fin 102 increases, increasing the probability of the gate electrode layer and the fin 102 being short-circuited, thereby affecting the performance of the semiconductor structure. If the size of the contact hole 117 along the second direction is too small, it is likely that the size of the gate electrode layer subsequently formed in the contact hole 117 will not meet the process requirements, resulting in a decrease in the electrical isolation effect of the gate structure subsequently formed in the isolation region 100B, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, the size of the contact hole 117 along the second direction is 15 nanometers to 30 nanometers.

[0136] It should also be noted that, after forming the contact hole 117 , the method for forming the semiconductor structure further includes: removing the mask layer 113 .

[0137] Specifically, the process of removing the mask layer 113 includes an ashing process.

[0138] refer to Figures 16 to 18 ,in, Figure 16 It is a top view. Figure 17 yes Figure 16 Cross-sectional view along AB direction, Figure 18 yes Figure 16 In the cross-sectional view along the CD direction, a gate electrode layer 118 is formed in the gate opening 110 and the contact hole 117 . The gate electrode layer 118 covers the gate dielectric layer 112 , and the gate electrode layer 118 is electrically connected to the buried power rail 100 in the isolation region 100B.

[0139] In this embodiment, the gate electrode layer 118 and the gate dielectric layer 112 are used to form a gate structure 160 .

[0140] Specifically, the gate structure 160 further includes a work function layer 111 located between the gate electrode layer 118 and the gate dielectric layer 112 .

[0141] The gate electrode layer 118 in the active area 100A is used to achieve electrical connection with a gate plug formed subsequently, and the gate electrode layer 118 in the isolation area 100B is electrically connected with the buried power rail 100 .

[0142] Specifically, the material of the gate electrode layer 118 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0143] In this embodiment, the step of forming a gate electrode layer 118 in the gate opening 110 and the contact hole 117 includes: forming a conductive material layer (not shown) in the gate opening 110 and the contact hole 117, and the conductive material layer also covers the top of the interlayer dielectric layer 109; with the top of the interlayer dielectric layer 109 as the stopping position, the conductive material layer above the top of the interlayer dielectric layer 109 is flattened, and the remaining conductive material layer in the gate opening 110 and the contact hole 117 serves as the gate electrode layer 118.

[0144] In this embodiment, the gate structure 160 of the isolation region 100B is used as a partition structure to electrically isolate the transistors in the adjacent working region 100A.

[0145] It should be noted that the gate structure 160 formed in the isolation region 100B is used as a partition structure. Compared with the existing solution of cutting fins and forming a partition structure in the fins of the isolation region, this embodiment omits the process step of cutting the fins 102 in the isolation region 100B, reduces the impact of the cutting process on the conductive channel in the fins 102, and at the same time, reduces other process defects generated during the cutting process.

[0146] The gate electrode layer 118 in the isolation region 100B is electrically connected to the buried power rail 100 , and the buried power rail 100 is used to load a first potential, so that the gate structure 160 in the isolation region 100B is loaded with the first potential through the buried power rail 100 .

[0147] refer to Figures 19 to 21 ,in, Figure 19 It is a top view. Figure 20 yes Figure 19 Cross-sectional view along AB direction, Figure 21 yes Figure 19 In the cross-sectional view along the CD direction, after the gate electrode layer 118 is formed, an isolation structure 119 is formed in the isolation region 100B, which penetrates the gate electrode layer 118 and the gate dielectric layer 112 . The isolation structure 119 is used to divide the gate structure 160 in the extension direction of the gate structure 160 .

[0148] The isolation structure 119 is arranged along the second direction (eg Figure 19 The gate structure 160 in the isolation region 100B is divided in the Y direction (as shown in FIG. 1 ), thereby achieving the requirement of separately controlling the gate structure 160 in the isolation region 100B.

[0149] The material of the isolation structure 119 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. As an example, the material of the isolation structure 119 is silicon nitride.

[0150] Silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride are all insulating materials that can effectively isolate adjacent devices.

[0151] It should be noted that in this embodiment, after forming the gate structure 160 and before forming the gate plug 120, the process further includes forming a source-drain interconnection layer 190 on top of the source-drain doped layer. Specifically, the source-drain interconnection layer 190 penetrates the first interlayer dielectric layer 109 between adjacent gate structures 160.

[0152] The source-drain interconnection layer 190 is electrically connected to the source-drain doping layer (not shown) to achieve electrical connection between the source-drain doping layer and an external circuit or other interconnection structure.

[0153] Since the subsequent process omits the step of forming a gate plug on top of the gate structure 160 in the isolation region 100B, the probability of short circuit between the gate structure 160 in the isolation region 100B and the adjacent source-drain interconnection layer 190 in the working region 100A is correspondingly reduced, thereby improving the performance of the semiconductor structure.

[0154] refer to Figure 22 A gate plug 120 is formed on top of the gate electrode layer 118 in the working area 100A. The gate plug 120 is used to load a second potential, and the second potential is opposite to the first potential.

[0155] The gate plug 120 is used to achieve electrical connection between the gate electrode layer 118 in the active area 100A and external circuits or other interconnect structures.

[0156] In this embodiment, the step of forming a gate plug 120 on top of the gate electrode layer 118 in the working area 100A includes: forming a second interlayer dielectric layer (not shown) on top of the gate electrode layer 118, the gate dielectric layer 112, the work function layer 111, the sidewall layer 108 and the interlayer dielectric layer 109; forming a conductive through-hole penetrating the second interlayer dielectric layer on top of the gate electrode layer 118 in the working area 100A; forming a conductive material in the conductive through-hole and on top of the second interlayer dielectric layer; after forming the conductive material, planarizing the conductive material above the second interlayer dielectric layer with the top of the second interlayer dielectric layer as a stop position, and the conductive material remaining in the conductive through-hole serves as the gate plug 120.

[0157] In this embodiment, the gate plug 120 is made of tungsten. Tungsten has a low resistivity, which helps improve signal delay in the back-end RC circuit and increase chip processing speed. It also helps reduce the resistance of the gate plug 120, thereby reducing power consumption. In other embodiments, the gate plug can also be made of conductive materials such as cobalt, ruthenium, or nickel.

[0158] In this embodiment, the gate electrode layer 118 formed in the isolation region 100B serves to electrically isolate the adjacent active region 100A.

[0159] Specifically, the buried power rail 100 is used to load a first potential, and the gate plug 120 is used to load a second potential, where the second potential is opposite to the first potential.

[0160] In this embodiment, the gate electrode layer 118 in the isolation region 100B is electrically connected to the buried power rail 100, and a first potential is applied to the gate structure 160 in the isolation region 100B through the buried power rail 100. Therefore, by making the second potential and the first potential opposite to each other, no current is conducted between the device regions 100A on both sides of the isolation region 100B, thereby enabling the gate structure 160 in the isolation region 100B to serve as a partition structure.

[0161] Specifically, when the device region 100A is used as an NMOS transistor, in order to be able to electrically isolate the adjacent NMOS transistor, the first potential loaded on the gate electrode layer 118 in the isolation region 100B is used as a cutoff gate voltage. Since the NMOS transistor in the device region 100A needs to be loaded with a positive second potential to be turned on, the gate electrode layer 118 in the isolation region 100B needs to be loaded with a negative voltage, so that no current is conducted between the device regions 100A on both sides of the isolation region 100B, and thus the gate electrode layer 118 in the isolation region 100B can achieve the effect of electrical isolation.

[0162] When the device region 100A is used as a PMOS transistor, in order to electrically isolate the adjacent PMOS transistor, the first potential loaded on the gate electrode layer 118 in the isolation region 100B is used as a cutoff gate voltage. Since the PMOS transistor in the device region 100A needs to be loaded with a negative second potential to be turned on, the gate electrode layer 118 in the isolation region 100B needs to be loaded with a positive voltage, so that no current is conducted between the device regions 100A on both sides of the isolation region 100B, and the gate electrode layer 118 in the isolation region 100B can achieve the effect of electrical isolation.

[0163] It should be noted that the formation method generally further comprises: forming a source-drain plug (not shown) penetrating the second interlayer dielectric layer on top of the source-drain interconnection layer.

[0164] The source-drain plugs are electrically connected to the source-drain interconnection layer, and are used to achieve electrical connection between the source-drain doped layer and an external circuit or other interconnection structures.

[0165] The description of the source-drain plugs will not be repeated here.

[0166] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate, comprising a working area and an isolation area arranged along a first direction, the substrate comprising a substrate, and a fin protruding from the substrate and extending along the first direction; a buried power rail located in the substrate at a side of the fin portion in the working area and the isolation area, the buried power rail extending along the first direction, and configured to apply a first potential; a first dielectric layer, located on top of the substrate and the buried power rail, and covering a portion of the sidewalls of the fin; a first opening located in the isolation region, the first opening being surrounded by sidewalls of the first dielectric layer and a top of the buried power rail, and the first opening exposing a top surface of the buried power rail; a gate structure, spanning the fins of the active region and the isolation region, respectively, and the isolation region gate structure serving as a partition structure, the gate structure comprising a gate dielectric layer covering a portion of the top and sidewalls of the fin and a top of the first dielectric layer, and further comprising a gate electrode layer covering the gate dielectric layer; in the isolation region, projections of the gate electrode layer and the buried power rail on the substrate have an overlapping portion, the gate electrode layer is located in the first opening, and the gate electrode layer in the isolation region penetrates the gate dielectric layer and the first dielectric layer on top of the buried power rail and is electrically connected to the buried power rail; A sidewall spacer, located on a sidewall of the gate structure; A source-drain doped layer is located in the fins on both sides of the gate structure and away from one side of the sidewall; a second dielectric layer, located on the substrate where the gate structure is exposed, the second dielectric layer covering the sidewalls of the gate structure, and the top of the second dielectric layer being flush with the top of the gate structure; a second opening penetrating through the second dielectric layer located on top of the source / drain doped layer, and exposing the top surface of the source / drain doped layer; a source-drain interconnection layer, located in the second opening, and electrically connected to the source-drain doped layer; a third dielectric layer, located on top of the gate structure and the second dielectric layer; a third opening, located in the working area, wherein the third opening penetrates the third dielectric layer on the top of the gate structure and exposes the top surface of the gate structure; A gate plug is located in the third opening, the gate plug is electrically connected to the gate structure, and the gate plug is used to load a second potential, where the second potential is opposite to the first potential.

2. The semiconductor structure according to claim 1, wherein The gate structure further includes a work function layer located between the gate dielectric layer and the gate electrode layer. The gate electrode layer located in the isolation region also penetrates the work function layer.

3. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes an isolation structure located in the isolation region and penetrating the gate structure, wherein the isolation structure is used to divide the gate structure in an extension direction of the gate structure.

4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes an insulating layer located between the substrate and the buried power rail.

5. The semiconductor structure according to claim 1, wherein The substrate includes a device unit area, and the device unit area includes a working area and an isolation area arranged along a first direction; The buried power rail is located at a boundary of the device unit region in a second direction, which is perpendicular to the first direction.

6. The semiconductor structure according to claim 1, wherein The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

7. The semiconductor structure according to claim 2, wherein: The material of the work function layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

8. The semiconductor structure according to claim 3, wherein: The material of the isolation structure includes one or more of silicon oxide, silicon carbonitride, silicon nitride and silicon oxynitride.

9. The semiconductor structure according to claim 1, wherein: The material of the buried power rail includes one or more of tungsten, cobalt, ruthenium and nickel.

10. The semiconductor structure according to claim 4, wherein: The insulating layer may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

11. The semiconductor structure according to claim 1, wherein: Taking a direction perpendicular to an extending direction of the fin as a lateral direction, a lateral dimension of the buried power rail is 30 nanometers to 100 nanometers.

12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an active region and an isolation region arranged along a first direction, the substrate comprising a substrate, and a fin protruding from the substrate and extending along the first direction, a buried power rail formed in the substrate on sides of the fin in the active region and the isolation region, the buried power rail extending along the first direction, an isolation layer formed on top of the buried power rail and the substrate, the isolation layer covering a portion of a sidewall of the fin, and the buried power rail being used to apply a first potential; forming a dummy gate layer on top of the substrate in the active region and the isolation region, the dummy gate layer spanning the fin and covering a portion of the top and a portion of the sidewall of the fin, wherein in the isolation region, projections of the dummy gate layer and the buried power rail on the substrate have an overlapping portion; forming an interlayer dielectric layer on the isolation layer exposed by the dummy gate layer; removing the dummy gate layer and forming a gate opening in the interlayer dielectric layer; forming a gate dielectric layer on the sidewalls and bottom of the gate opening and the top and sidewalls of the fin; In the isolation region, forming a contact hole penetrating the gate dielectric layer and the isolation layer on top of the buried power rail; forming a gate electrode layer in the gate opening and the contact hole, the gate electrode layer covering the gate dielectric layer, and the gate electrode layer being electrically connected to the buried power rail located in the isolation region; A gate plug is formed on the top of the gate electrode layer in the active region, and the gate plug is used to load a second potential, where the second potential is opposite to the first potential.

13. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming a contact hole penetrating the gate dielectric layer and the isolation layer on the top of the buried power rail includes: forming a mask layer having a mask opening on the top of the substrate, the mask layer covering the top and sidewalls of the fin, and the mask opening being located on the top of the buried power rail; using the mask layer as a mask, etching the gate dielectric layer and the isolation layer exposed by the mask opening to form a contact hole exposing the buried power rail.

14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming a gate dielectric layer on the sidewalls and bottom of the gate opening and the top and sidewalls of the fin, the gate dielectric layer is also formed on top of the interlayer dielectric layer; In the step of forming a mask layer having a mask opening on the top of the substrate, the mask opening also exposes the gate dielectric layer on the top of the interlayer dielectric layer; The process of etching the gate dielectric layer and the isolation layer exposed by the mask opening using the mask layer as a mask further includes: removing the gate dielectric layer formed on the top of the interlayer dielectric layer.

15. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming a gate electrode layer in the gate opening and the contact hole includes: forming a conductive material layer in the gate opening and the contact hole, wherein the conductive material layer also covers the top of the interlayer dielectric layer; taking the top of the interlayer dielectric layer as the stopping position, flattening the conductive material layer above the top of the interlayer dielectric layer, and using the remaining conductive material layer in the gate opening and the contact hole as the gate electrode layer.

16. The method for forming a semiconductor structure according to claim 12, wherein: In the step of providing a substrate, the step of forming the buried power rail includes: forming an opening extending along the first direction in the substrate at a side of the fin; and forming the buried power rail in the opening.

17. The method for forming a semiconductor structure according to claim 16, wherein: Before forming the buried power rail in the opening, the method further includes: forming an insulating layer on the sidewall of the opening.

18. The method for forming a semiconductor structure according to claim 16, wherein: The step of forming a buried power rail in the opening includes: forming a conductive material layer in the opening; etching back a portion of the conductive material layer, and the remaining conductive material layer in the opening serves as the buried power rail.

19. The method for forming a semiconductor structure according to claim 12, wherein: In the step of providing a substrate, the substrate includes a device cell area, the device cell area includes a working area and an isolation area arranged along a first direction, and at a boundary of the device cell area in a second direction, the buried power rail extending along the first direction is formed in the substrate, and the second direction is perpendicular to the first direction.

20. The method for forming a semiconductor structure according to claim 12, wherein: After forming the gate dielectric layer and before forming the contact hole, the method further includes: forming a work function layer covering the gate dielectric layer; In the step of forming the contact hole, the contact hole also penetrates the work function layer.

21. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming a gate electrode layer in the gate opening and the contact hole, the gate electrode layer and the gate dielectric layer are used to constitute a gate structure; Before forming a gate plug on top of the gate electrode layer in the working area, the method further includes: forming an isolation structure penetrating the gate electrode layer and the gate dielectric layer in the isolation area, wherein the isolation structure is used to divide the gate structure in an extension direction of the gate structure.

22. The method for forming a semiconductor structure according to claim 12, wherein: The process of forming a contact hole on the top of the buried power rail and penetrating the gate dielectric layer and the isolation layer includes a dry etching process.

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