Field effect transistor and manufacturing method thereof

Abstract

According to the field effect transistor, a first JFET is formed in a first epitaxial layer, and a second MOSFET is formed in a second epitaxial layer. The forbidden band width of the material of the first epitaxial layer is greater than that of the material of the second epitaxial layer; the second epitaxial layer is formed on the top surface of the first epitaxial layer, and the contact surface of the first epitaxial layer and the second epitaxial layer is heterojunction; a first source region of the first JFET and a second drain region of the second MOSFET are connected through a first floating metal contact hole penetrating through the heterojunction. A first gate region of the first JFET is connected to a source consisting of a front metal layer through a deep contact hole penetrating through the heterojunction; the second source region is connected with the source electrode. The back face of the first drain region is connected to a drain electrode composed of a back face metal layer. The invention further discloses a manufacturing method of the field effect transistor. The invention has the advantages of a wide bandgap semiconductor material device, and can overcome the problems of high channel carrier mobility, high driving voltage and poor reliability of the gate dielectric layer of the wide bandgap semiconductor material device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a field effect transistor; the present invention also relates to a method for manufacturing the field effect transistor. Background Art

[0002] Wide bandgap semiconductor material SiC is an ideal material for preparing high voltage power electronic devices. Compared with Si material, SiC material has a high breakdown electric field strength (4×10 6 V / cm), high carrier saturation drift velocity (2×10 7 cm / s), high thermal conductivity, good thermal stability, etc., so it is particularly suitable for use in high-power, high-voltage, high-temperature and radiation-resistant electronic devices.

[0003] SiC VDMOS is the most widely used voltage-controlled device among SiC power devices. Compared to bipolar devices (such as IGBTs), SiC VDMOS has no charge storage effect, resulting in better frequency characteristics and lower switching losses. The wide bandgap of SiC material also allows SiC VDMOS to operate at temperatures as high as 300°C.

[0004] However, planar SiC VDMOS suffers from three issues: 1) The channel mobility of SiC VDMOS using existing processes is too low, severely impacting the device's conduction capability; 2) The drive voltage of existing SiC VDMOS is too high, typically requiring a gate voltage greater than 18V. This makes many applications originally designed for Si devices unsuitable for SiC VDMOS. 3) The gate oxide layer reliability of SiC VDMOS is poor, primarily due to the large tunneling current between SiC and SiO2. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a field-effect transistor that combines the advantages of wide-bandgap semiconductor devices while overcoming the problems of wide-bandgap semiconductor devices, such as high channel carrier mobility, high drive voltage, and poor gate dielectric layer reliability. To this end, the present invention also provides a method for manufacturing the field-effect transistor.

[0006] To solve the above technical problems, the field effect transistor provided by the present invention includes: a first epitaxial layer doped with a first conductive type composed of a first semiconductor material and a second epitaxial layer doped with a first conductive type composed of a second semiconductor material, the band gap width of the first semiconductor material is greater than the band gap width of the second semiconductor material, the second epitaxial layer is formed on the top surface of the first epitaxial layer and the contact surface between the first epitaxial layer and the second epitaxial layer is a heterojunction.

[0007] A first JFET is formed in the first epitaxial layer, and a second MOSFET is formed in the second epitaxial layer.

[0008] The first JFET includes a first drain region heavily doped with a first conductivity type, a first gate region, and a first source region heavily doped with a first conductivity type.

[0009] The first drain region is formed on the back side of the first epitaxial layer.

[0010] The first source region is formed on the front surface of the first epitaxial layer.

[0011] The first gate region is composed of a second conductive type doped region formed in the first epitaxial layer. The first epitaxial layer surrounded by the first gate region constitutes a first channel region. The first channel region is located between the first source region and the first drain region.

[0012] The second MOSFET includes: a second source region heavily doped with the first conductivity type, a second gate structure, and a second drain region heavily doped with the first conductivity type.

[0013] The second gate structure includes a gate dielectric layer and a gate conductive material layer sequentially stacked on the surface of the second epitaxial layer.

[0014] The second source region and the second drain region are formed on both sides of the second gate structure in a self-aligned manner.

[0015] A second channel region doped with a second conductive type is formed in the region covered by the second gate structure.

[0016] The first source region and the second drain region are connected via a first floating metal contact hole passing through the heterojunction; a first dielectric layer is provided between the first floating metal contact hole and the second channel region passed through and the second epitaxial layer at the bottom of the second channel region.

[0017] The first gate region is connected to a source composed of a front metal layer through a deep contact hole passing through the heterojunction; the second source region is connected to the source; a first dielectric layer is provided between the deep contact hole and the second channel region passed through and the second epitaxial layer at the bottom of the second channel region.

[0018] The back side of the first drain region is connected to a drain electrode formed by a back side metal layer.

[0019] A further improvement is that the first semiconductor material includes SiC.

[0020] A further improvement is that the second semiconductor material includes Si.

[0021] A further improvement is that the first gate region comprises two first buried layers and one second buried layer.

[0022] The second buried layer is formed in a top surface region of the first epitaxial layer.

[0023] A top surface of each of the first buried layers is located below a bottom surface of the second buried layers.

[0024] A first lateral spacing region is provided between the two first buried layers, and the first lateral spacing region serves as a longitudinal extension region of the first channel region.

[0025] The second buried layer and the first buried layer at the bottom have a first intersection region, and the first intersection region serves as a lateral extension region of the first channel region.

[0026] The first gate region is connected to the source through the deep contact hole formed on the top of the second buried layer.

[0027] A further improvement is that the second source region is also connected to the source electrode through the deep contact hole on the top of the second buried layer.

[0028] A further improvement is that above the top surface of the second epitaxial layer, the width of the first floating metal contact hole increases and extends above the top surface of the second drain region and the width of the deep contact hole increases and extends above the top surface of the second source region.

[0029] Ohmic contact alloys are formed at the contact positions of the first floating metal contact hole and the top surface of the second drain region, the contact positions of the first floating metal contact hole and the top surface of the first source region, the contact positions of the deep contact hole and the top surface of the second source region, and the contact positions of the deep contact hole and the top surface of the second buried layer.

[0030] A further improvement is that the gate dielectric layer includes a gate oxide layer, and the gate conductive material layer includes a polysilicon gate;

[0031] A further improvement is that the material of the first dielectric layer includes an oxide layer.

[0032] A further improvement is that the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the field effect transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0033] To solve the above technical problems, the present invention provides a method for manufacturing a field effect transistor, comprising the following steps:

[0034] A first epitaxial layer doped with a first conductivity type and composed of a first semiconductor material is formed on a first semiconductor material substrate. The first semiconductor substrate has a heavily doped region of the first conductivity type and serves as a first drain region of a first JFET.

[0035] A first gate region of a first JFET consisting of a second conductivity type doped region is formed in the first epitaxial layer.

[0036] A first source region of the first JFET that is heavily doped with a first conductivity type is formed in the front surface area of ​​the first epitaxial layer; the first epitaxial layer surrounded by the first gate region constitutes a first channel region of the first JFET, and the first channel region is located between the first source region and the first drain region.

[0037] A second epitaxial layer doped with a first conductive type and composed of a second semiconductor material is formed on the top surface of the first epitaxial layer. The band gap width of the first semiconductor material is greater than the band gap width of the second semiconductor material. The contact surface between the first epitaxial layer and the second epitaxial layer forms a heterojunction.

[0038] A second channel region doped with the second conductivity type of the second MOSFET is formed in the second epitaxial layer by using a well region forming process.

[0039] Etching is performed simultaneously to form contact hole trenches penetrating the second epitaxial layer on the top of the first source region and the top of the lead-out region of the first gate region.

[0040] A first dielectric layer is formed on the inner surface of the contact hole trench, and the first dielectric layer also extends to the surface of the second epitaxial layer outside the contact hole trench.

[0041] A gate dielectric layer and a gate conductive material layer of a second gate structure of the second MOSFET are sequentially formed on the top surface of the second channel region.

[0042] A second source region and a second drain region heavily doped with the first conductivity type are formed on both sides of the second gate structure in a self-aligned manner.

[0043] The first dielectric layer on the bottom surface of each contact hole trench is removed, and the first dielectric layer or the gate dielectric layer on the top of the contact region between the second source region and the second drain region outside the contact hole trench is removed.

[0044] An ohmic contact alloy is formed on the bottom surface of each of the contact hole trenches and the top surface of the contact region of the second source region and the second drain region.

[0045] A metal layer is filled in each contact hole trench and the filled metal layer also extends to the surface of the ohmic contact alloy outside the contact hole trench to form a contact hole, and the contact hole on the top of the first source region constitutes a first floating metal contact hole.

[0046] An interlayer film is formed, a through hole passes through the interlayer film, the through hole is formed on the top of the contact hole located at the top of the lead-out region of the first gate region, and the contact hole located at the top of the lead-out region of the first gate region and the through hole at the top are connected to form a deep contact hole.

[0047] A front metal layer is formed and patterned to form a source electrode, and the top of the deep contact hole is connected to the source electrode.

[0048] A drain electrode composed of a back metal layer is formed on the back side of the first drain region.

[0049] A further improvement is that the first semiconductor material includes SiC.

[0050] A further improvement is that the second semiconductor material includes Si.

[0051] A further improvement is that the steps of forming the first gate region include:

[0052] Two first buried layers are formed at a selected depth of the first epitaxial layer, with a first lateral spacing region between the two first buried layers, and the first lateral spacing region serves as a longitudinal extension region of the first channel region.

[0053] A second buried layer is formed in the top surface area of ​​the first epitaxial layer; the top surface of each first buried layer is located at the bottom of the bottom surface of the second buried layer; the second buried layer and the first buried layer at the bottom have a first intersection area and the first intersection area serves as a lateral extension area of ​​the first channel region; the first gate region is connected to the source through the deep contact hole formed on the top of the second buried layer.

[0054] A further improvement is that the gate dielectric layer includes a gate oxide layer, and the gate conductive material layer includes a polysilicon gate.

[0055] A further improvement is that the material of the first dielectric layer includes an oxide layer formed by a thermal oxidation process.

[0056] A further improvement is that the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the field effect transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0057] The field effect transistor of the present invention comprises a first JFET formed in a first epitaxial layer and a second MOSFET formed in a second epitaxial layer, which are connected to form a common source and common gate structure. The first epitaxial layer is composed of a first semiconductor material with a wide bandgap width, such as SiC, so that the first JFET has the advantages of a wide bandgap semiconductor material device, such as the ability to achieve high power, high voltage, high temperature and radiation resistance.

[0058] The second epitaxial layer is made of a second semiconductor material with a lower bandgap width, such as silicon, and a second MOSFET is used to control the channel conduction current of the entire field effect transistor, thereby avoiding the high interface state density problem of the channel of wide bandgap semiconductor material devices and improving the channel mobility of the device.

[0059] Furthermore, in the present invention, a second MOSFET is used to control the conduction of the field-effect transistor, making the device fully compatible with the drive scheme of a low-bandgap semiconductor device, namely, the second MOSFET. Simultaneously, the second MOSFET is used to control the field-effect transistor's off-state. Therefore, the portion directly performing voltage drive is the low-bandgap semiconductor device corresponding to the second MOSFET, thus avoiding the low reliability of gate dielectric layers, such as gate oxide layers, in wide-bandgap semiconductor devices.

[0060] In addition, in the present invention, the first source region of the first JFET and the second drain region of the second MOSFET are connected through a first floating metal contact hole. Since the first floating metal contact hole passes through the heterojunction formed by the first epitaxial layer and the second epitaxial layer, the forward conduction current does not cross the potential barrier of the heterojunction, thereby avoiding the adverse effects of the heterojunction on the conduction characteristics of the device.

[0061] At the same time, the deep contact hole at the top of the first gate region also passes through the heterojunction. When the device is reversely cut off, the first JFET bears the high voltage, and the reverse leakage current will pass through the first gate region and the deep contact hole and the source contact at the top of the deep contact hole. Therefore, the reverse leakage current will not pass through the heterojunction, thereby avoiding the problem of increased leakage caused by heterogeneous crystal lattice mismatch.

[0062] Therefore, the present invention can have the advantages of wide bandgap semiconductor material devices while overcoming the problems of high channel carrier mobility, high driving voltage and poor gate dielectric layer reliability of wide bandgap semiconductor material devices; it can also avoid the adverse effects of heterojunction barriers on forward conduction current and reverse current. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0064] Figure 1 1 is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention;

[0065] Figure 2 Schematic diagram of the flow direction of source-drain current of the field effect transistor when it is forward-conducting according to an embodiment of the present invention;

[0066] Figure 3 1 is a schematic diagram of the distribution of the depletion region of the first JFET of the source-drain current of the field effect transistor when it is turned off according to an embodiment of the present invention;

[0067] Figure 4 1 is a schematic diagram of an equivalent circuit of a field effect transistor according to an embodiment of the present invention;

[0068] Figures 5A-5L It is a schematic diagram of the device structure in each step of the method for manufacturing a field effect transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0069] like Figure 1 As shown in FIG, it is a schematic diagram of the structure of the field effect transistor according to an embodiment of the present invention; Figure 4 As shown in FIG, is a schematic diagram of an equivalent circuit of a field effect transistor according to an embodiment of the present invention; the field effect transistor according to the embodiment of the present invention comprises: a first epitaxial layer 2 doped with a first conductive type composed of a first semiconductor material and a second epitaxial layer 5 doped with a first conductive type composed of a second semiconductor material, the band gap width of the first semiconductor material is greater than the band gap width of the second semiconductor material, the second epitaxial layer 5 is formed on the top surface of the first epitaxial layer 2 and the contact surface between the first epitaxial layer 2 and the second epitaxial layer 5 is a heterojunction.

[0070] The first JFET 202 is formed in the first epitaxial layer 2 , and the second MOSFET 201 is formed in the second epitaxial layer 5 .

[0071] The first JFET 202 includes a first drain region 1 heavily doped with the first conductivity type, a first gate region 3, and a first source region 4 heavily doped with the first conductivity type. In this embodiment of the present invention, a first epitaxial layer 2 is formed on the top surface of a first semiconductor material substrate. The first drain region 1 is formed by the first semiconductor material substrate. In other embodiments, the first drain region 1 can also be formed by backside ion implantation of the first epitaxial layer 2.

[0072] The first drain region 1 is formed on the back side of the first epitaxial layer 2 .

[0073] The first source region 4 is formed on the front surface of the first epitaxial layer 2 .

[0074] The first gate region 3 is composed of a second conductivity type doped region formed in the first epitaxial layer 2 . The first epitaxial layer 2 surrounded by the first gate region 3 forms a first channel region, which is located between the first source region 4 and the first drain region 1 .

[0075] The second MOSFET 201 includes a second source region 11 a heavily doped with the first conductivity type, a second gate structure, and a second drain region 11 b heavily doped with the first conductivity type.

[0076] The second gate structure includes a gate dielectric layer 9 and a gate conductive material layer 10 sequentially stacked on the surface of the second epitaxial layer 5 .

[0077] In the embodiment of the present invention, the gate dielectric layer 9 includes a gate oxide layer, and the gate conductive material layer 10 includes a polysilicon gate.

[0078] The second source region 11 a and the second drain region 11 b are formed on both sides of the second gate structure in a self-aligned manner.

[0079] A second channel region doped with the second conductivity type is formed in the region covered by the second gate structure. In the embodiment of the present invention, the second channel region is composed of a well region 6 doped with the second conductivity type and covered by the second gate structure. The well region 6 is formed in the surface region of the second epitaxial layer 5.

[0080] The first source region 4 and the second drain region 11b are connected via a first floating metal contact hole 13a that passes through the heterojunction. A first dielectric layer 8 is provided between the first floating metal contact hole 13a and the second channel region and the second epitaxial layer 5 at the bottom of the second channel region. Figure 1 As shown, the first floating metal contact hole 13a is not connected to the external electrode and is only used to achieve the connection between the first source region 4 and the second drain region 11b. The purpose is to pass through the heterojunction to prevent the heterojunction from adversely affecting the electrical connection between the first source region 4 and the second drain region 11b.

[0081] The first gate region 3 is connected to the source electrode composed of the front metal layer 16 through a deep contact hole passing through the heterojunction. Figure 1 In the cross-sectional structure shown, only the front metal layer 16 corresponding to the source is shown. At other locations, the front metal layer includes a gate for connecting to the second gate structure. The deep contact hole and the second channel region passed through and the second epitaxial layer 5 at the bottom of the second channel region are separated by a first dielectric layer 8. In an embodiment of the present invention, the deep hole contact is formed by superimposing a contact hole 13b made with the same process as the first floating metal contact hole 13a and a through hole 15 passing through the interlayer film 14. The first floating metal contact hole 13a and the contact hole 13b are both formed in the contact hole trench 7 of the same layer. The first dielectric layer 8 is formed on the side of the contact hole trench 7.

[0082] In some embodiments, the material of the first dielectric layer 8 includes an oxide layer.

[0083] The back side of the first drain region 1 is connected to a drain electrode formed by a back side metal layer 17 .

[0084] In the embodiment of the present invention, the first semiconductor material includes SiC. The second semiconductor material includes Si. Therefore, Figure 4 In the figure, the second MOSFET 201 is also represented by Si MOSFET. Compared with the existing SiC MOSFET, Si MOSFET can overcome various defects of SiC MOSFET, such as: low channel interface density, so the channel mobility is high; only the driving scheme of Si MOSFET, such as driving voltage, is required for driving, and the driving voltage of more than 18V required by SiC MOSFET is not required; the tunneling current between Si and SiO2 is smaller than the tunneling current between SiC and SiO2, so the reliability of the gate dielectric layer, such as the gate oxide layer, is improved. Figure 4 In the example, the first JFET 202 is also represented by SiC JFET. Figure 1 As shown, the first JFET 202 is at the drain end, so the characteristics of the SiC material can be used to improve the performance of the device, making it suitable for high power, high voltage, high temperature and radiation resistance conditions.

[0085] In other embodiments, specific materials of the first semiconductor material and the second semiconductor material can also be selected as needed.

[0086] like Figure 1 As shown, in the embodiment of the present invention, the components of the first gate region 3 include two first buried layers 3a and one second buried layer 3b.

[0087] The second buried layer 3 b is formed in the top surface region of the first epitaxial layer 2 .

[0088] The top surface of each first buried layer 3a is located below the bottom surface of the second buried layer 3b.

[0089] A first lateral spacing region is provided between the two first buried layers 3 a , and the first lateral spacing region serves as a longitudinal extension region of the first channel region.

[0090] The second buried layer 3 b and the bottom first buried layer 3 a have a first intersection region, and the first intersection region serves as a lateral extension region of the first channel region.

[0091] The first gate region 3 is connected to the source through a deep contact hole formed on the top of the second buried layer 3b. The second source region 11a is also connected to the source through a deep contact hole formed on the top of the second buried layer 3b.

[0092] In the embodiment of the present invention, above the top surface of the second epitaxial layer 5, the width of the first floating metal contact hole 13a increases and extends above the top surface of the second drain region 11b, and the width of the deep contact hole increases and extends above the top surface of the second source region 11a.

[0093] Ohmic contact alloy 12 is formed at the contact position of the first floating metal contact hole 13a and the top surface of the second drain region 11b, the contact position of the first floating metal contact hole 13a and the top surface of the first source region 4, the contact position of the deep contact hole and the top surface of the second source region 11a, and the contact position of the deep contact hole and the top surface of the second buried layer 3b.

[0094] In other embodiments, the first gate region 3 can also be adjusted as needed, as long as it is ensured that the first channel region can be controlled.

[0095] In some embodiments, the material of the ohmic contact alloy 12 includes a nickel (Ni) alloy.

[0096] In the embodiment of the present invention, the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the field effect transistor can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0097] like Figure 2 As shown, it is a schematic diagram of the flow direction of the source-drain current of the field effect transistor of an embodiment of the present invention when it is forward-conducted; when the gate conductive material layer 10 increases the positive voltage greater than the threshold voltage, the second MOSFET 201 is turned on, the source-drain current is turned on, and the current flows in the direction as shown by the arrow line 101, that is, starting from the drain corresponding to the back metal layer 17, passing through the first channel region corresponding to the first epitaxial layer 2 to reach the first source region 4, passing through the first floating metal contact hole 13a to reach the second drain region 11b, passing through the second channel region to reach the second source region 9b and finally passing through the deep contact hole to reach the source composed of the front metal layer 16.

[0098] like Figure 3 , which is a schematic diagram of the depletion region distribution of the first JFET 202 of the field effect transistor when it is turned off according to an embodiment of the present invention; when a potential of 0 or a negative voltage less than the threshold voltage is applied to the gate conductive material layer 10, the second MOSFET 201 is turned off, and the entire field effect transistor is turned off and is in a reverse cutoff state; for the first JFET 202, the second buried layer 3b is connected to the source potential through a deep contact hole, and the drain potential is a high potential, so the first buried layer 3a and the second buried layer 3b will deplete the first epitaxial layer 2 and form a depletion region, Figure 3The middle dotted line 102 represents the boundary of the corresponding depletion region. It can be seen that the depletion region between the two first buried layers 3a is connected together, and the depletion region between the second buried layer 3b and the bottom first buried layer 3a is also connected together. Therefore, the longitudinal extension area and the lateral extension area of ​​the first channel region are both turned off, which can reduce the reverse leakage of the device; at the same time, the depletion region is mainly located in the first epitaxial layer 2, and the depletion region in the first epitaxial layer 2 will be subjected to high voltage; the reverse leakage enters the first epitaxial layer 2 through the drain, and finally connects to the source through the deep contact hole at the top of the second buried layer 3b, and will not pass through the heterojunction, which can avoid the risk of increased leakage caused by the lattice mismatch of the heterojunction.

[0099] The field effect transistor in an embodiment of the present invention is composed of a first JFET202 formed in the first epitaxial layer 2 and a second MOSFET201 formed in the second epitaxial layer 5, which are connected to form a common source and common gate structure. The first epitaxial layer 2 is composed of a first semiconductor material with a wide bandgap width, such as SiC, and the second MOSFET201 is used as a switch and the first JFET202 is used as a reverse voltage-bearing end, so that the first JFET202 has the advantages of a wide bandgap semiconductor material device, such as the ability to achieve high power, high voltage, high temperature and radiation resistance.

[0100] The second epitaxial layer 5 is made of a second semiconductor material with a lower bandgap width, such as silicon, and a second MOSFET201 is used to control the channel conduction current of the entire field effect transistor, thereby avoiding the high interface state density problem of the channel of wide bandgap semiconductor material devices and improving the channel mobility of the device.

[0101] Furthermore, in the embodiment of the present invention, the second MOSFET 201 is used to control the conduction of the field-effect transistor, so the device is fully compatible with the driving scheme of the low-bandgap semiconductor material device, namely the second MOSFET 201. At the same time, the second MOSFET 201 is used to control the turn-off of the field-effect transistor. Therefore, the portion directly performing voltage drive is the low-bandgap semiconductor material device corresponding to the second MOSFET 201, which can avoid the low reliability problem of the gate dielectric layer 9, such as the gate oxide layer, of the wide-bandgap semiconductor material device.

[0102] In addition, in the embodiment of the present invention, the first source region 4 of the first JFET 202 and the second drain region 11b of the second MOSFET 201 are connected through a first floating metal contact hole 13a. Since the first floating metal contact hole 13a passes through the heterojunction formed by the first epitaxial layer 2 and the second epitaxial layer 5, the forward conduction current does not cross the potential barrier of the heterojunction, thereby avoiding the adverse effects of the heterojunction on the conduction characteristics of the device.

[0103] At the same time, the deep contact hole at the top of the first gate region 3 also passes through the heterojunction. When the device is reversely cut off, the first JFET202 bears the high voltage, and the reverse leakage current will pass through the first gate region 3 and the deep contact hole and the source contact at the top of the deep contact hole. Therefore, the reverse leakage current will not pass through the heterojunction, thereby avoiding the problem of increased leakage caused by heterogeneous crystal lattice mismatch.

[0104] Therefore, the embodiment of the present invention can have the advantages of wide bandgap semiconductor material devices while overcoming the problems of high channel carrier mobility, high driving voltage and poor reliability of the gate dielectric layer 9 of wide bandgap semiconductor material devices; it can also avoid the adverse effects of the heterojunction barrier on forward conduction current and reverse current.

[0105] like Figures 5A to 5L , which is a schematic diagram of the device structure in each step of the method for manufacturing a field effect transistor according to an embodiment of the present invention; the method for manufacturing a field effect transistor according to an embodiment of the present invention includes the following steps:

[0106] Step 1: Figure 5A As shown, a first epitaxial layer 2 doped with a first conductivity type and composed of a first semiconductor material is formed on a first semiconductor material substrate. The first semiconductor substrate has a heavily doped region of the first conductivity type and serves as a first drain region 1 of the first JFET 202 .

[0107] In the embodiment of the present invention, the first semiconductor material includes SiC. In other embodiments, the first semiconductor material can be selected as needed to ensure that the band gap of the first semiconductor material is larger than the band gap of the subsequent second semiconductor material.

[0108] Step 2: forming a first gate region 3 of the first JFET 202 composed of a second conductivity type doped region in the first epitaxial layer 2 .

[0109] In the method of the embodiment of the present invention, the first semiconductor material includes SiC.

[0110] The steps of forming the first gate region 3 include:

[0111] Step 21: Figure 5B As shown, two first buried layers 3 a are formed at a selected depth of the first epitaxial layer 2 , with a first lateral spacing region between the two first buried layers 3 a , and the first lateral spacing region serves as a longitudinal extension region of the first channel region of the first JFET 202 .

[0112] The formation area of ​​the first buried layer 3a is defined by photolithography. Before the photolithography process is performed, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In this case, the first buried layer 3a is a P-type buried layer, and the impurities implanted in the first buried layer 3a include P-type impurities such as Al or B. The implantation temperature condition is 300K to 1000K. In other embodiments, the field effect transistor can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. In this case, the first buried layer 3a is an N-type buried layer.

[0113] Step 22: Figure 5C As shown, a second buried layer 3b is formed in the top surface area of ​​the first epitaxial layer 2; the top surface of each first buried layer 3a is located at the bottom of the bottom surface of the second buried layer 3b; the second buried layer 3b and the bottom first buried layer 3a have a first intersection area and the first intersection area serves as a lateral extension area of ​​the first channel region.

[0114] In the method of this embodiment of the present invention, the region for forming the second buried layer 3b is defined by photolithography. Prior to the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer is patterned before ion implantation. The ion implantation mask layer is then removed and the surface cleaned. The implanted impurities in the second buried layer 3b include P-type impurities such as Al or B. The implantation temperature is between 300K and 1000K.

[0115] Step 3: Figure 5D As shown, a first source region 4 of the first conductivity type heavily doped with the first JFET 202 is formed in the front surface area of ​​the first epitaxial layer 2; the first epitaxial layer 2 surrounded by the first gate region 3 constitutes a first channel region of the first JFET 202, and the first channel region is located between the first source region 4 and the first drain region 1.

[0116] In this embodiment of the present invention, the formation area of ​​the first source region 4 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer is patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. The impurities implanted into the first source region 4 include N-type impurities such as phosphorus (P) or nitrogen (N). The implantation temperature is 300K to 1000K.

[0117] Step 4: Figure 5E As shown, a second epitaxial layer 5 doped with a first conductive type and composed of a second semiconductor material is formed on the top surface of the first epitaxial layer 2. The band gap width of the first semiconductor material is greater than the band gap width of the second semiconductor material. The contact surface between the first epitaxial layer 2 and the second epitaxial layer 5 is a heterojunction.

[0118] In the embodiment of the present invention, the second semiconductor material includes Si and is formed by chemical vapor deposition. In other embodiments, the second semiconductor material can also be other suitable materials, but the band gap of the first semiconductor material must be greater than the band gap of the second semiconductor material.

[0119] Step 5: Figure 5F As shown, a second channel region of the second MOSFET 201 doped with the second conductivity type is formed in the second epitaxial layer 5 by adopting a well region forming process.

[0120] In the embodiment of the present invention, the second channel region is formed by a P-type doped well region 6. The well region 6 is formed in the surface region of the second epitaxial layer 5 by P-type impurity ion implantation, such as boron ion implantation, and high-temperature push-in.

[0121] Step 6: Figure 5G As shown, etching is performed to simultaneously form contact hole trenches 7 passing through the second epitaxial layer 5 on the top of the first source region 4 and the top of the lead-out region of the first gate region.

[0122] Step 7: Figure 5H As shown, a first dielectric layer 8 is formed on the inner surface of the contact hole trench 7 , and the first dielectric layer 8 also extends to the surface of the second epitaxial layer 5 outside the contact hole trench 7 .

[0123] In the method of the embodiment of the present invention, the material of the first dielectric layer 8 includes an oxide layer, which is formed by a thermal oxidation process.

[0124] Step 8: Figure 5I As shown, a gate dielectric layer 9 and a gate conductive material layer 10 of a second gate structure of a second MOSFET are sequentially formed on the top surface of the second channel region. After the gate conductive material layer 10 is deposited, it is necessary to perform pattern etching so that the remaining gate conductive material layer 10 is only located in the formation area of ​​the second gate structure.

[0125] In the method of the embodiment of the present invention, the gate dielectric layer 9 includes a gate oxide layer, which is formed by a thermal oxidation process.

[0126] In some embodiments, the gate dielectric layer 9 is formed with the first dielectric layer 8 . In other embodiments, the gate dielectric layer 9 and the first dielectric layer 8 can be formed independently of each other and can be configured according to their respective needs.

[0127] The gate conductive material layer 10 includes a polysilicon gate, which is formed by depositing polysilicon and performing patterning etching.

[0128] Figure 5I , two second gate structures are shown, each second gate structure corresponding to a second MOSFET 201 .

[0129] Step 9: Figure 5I As shown, a second source region 11 a and a second drain region 11 b heavily doped with the first conductivity type are formed on both sides of the second gate structure in a self-aligned manner.

[0130] In the method of the embodiment of the present invention, the second source region 11a and the second drain region 11b are both N+ implanted, the implanted impurities include phosphorus, the second gate structure is directly used as a mask for zero ion implantation, and high-temperature push-in junction is performed after the ion implantation is completed; after the second source region 11a and the second drain region 11b are formed, the well region 6 between the second source region 11a and the second drain region 11b covered by the second gate structure is self-aligned as a second channel region.

[0131] Step 10: Figure 5J As shown, the first dielectric layer 8 on the bottom surface of each contact hole trench 7 is removed, and the first dielectric layer 8 or gate dielectric layer 9 on the top of the contact area of ​​the second source region 11a and the second drain region 11b outside the contact hole trench 7 is removed.

[0132] Step 11: Figure 5J As shown, an ohmic contact alloy 12 is formed on the bottom surface of each contact hole trench 7 and the top surface of the contact region of the second source region 11a and the second drain region 11b.

[0133] In some exemplary methods, the ohmic contact alloy 12 is obtained by depositing a Ni alloy and then annealing the alloy at a temperature of 900-1200°C.

[0134] Step 12: Figure 5K As shown, a metal layer is filled in each contact hole trench 7 and the filled metal layer also extends to the surface of the ohmic contact alloy 12 outside the contact hole trench 7 to form contact holes 13a and 13b, and the contact hole 13a at the top of the first source region 4 constitutes a first floating metal contact hole 13a.

[0135] In some exemplary methods, the contact holes 13 a and 13 b are formed by methods including but not limited to sputtering, evaporation, and tungsten plug filling.

[0136] Step 13: Figure 5K As shown, an interlayer film 14 is formed.

[0137] like Figure 5LAs shown, a through hole 15 passes through the interlayer film 14, a through hole 15 is formed on the top of the contact hole at the top of the lead-out region of the first gate region, and the contact hole at the top of the lead-out region of the first gate region and the through hole 15 at the top are connected to form a deep contact hole.

[0138] Step 14: Return Figure 1 As shown, a front metal layer 16 is formed and patterned to form a source electrode, a top portion of a deep contact hole and a source electrode connection.

[0139] In some exemplary methods, the front metal layer 16 is formed by sputtering or evaporation.

[0140] Step 15: Figure 1 As shown, a drain electrode composed of a back metal layer 17 is formed on the back side of the first drain region 1. In some embodiments, the back metal layer 17 is formed by sputtering or evaporation.

[0141] In some embodiments, an ohmic contact can be formed on the back side of the first drain region 1 before forming the back side metal layer 17 .

[0142] In the embodiment of the present invention, the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the field effect transistor may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0143] In the heterojunction cascode field effect transistor of the embodiment of the present invention, when the device is working normally, a forward voltage is applied to the gate of the upper SiMOSFET, i.e., the second MOSFET, and the channel is turned on. The current Ids flows from the drain of the silicon carbide JFET, i.e., the first JFET, through the first source region 4, the first floating metal contact hole 13a, the second source region 11a, and reaches the source front metal layer. Figure 2 As shown by the arrow line corresponding to the mark 101 in the figure. Therefore, when the device is working normally, the forward current Ids does not flow through the SiC / Si heterojunction, which can avoid the influence of the heterojunction barrier on the conduction characteristics and reduce the device on-resistance. When the device is turned off and in the reverse cutoff state, the Si MOSFET gate is applied with zero potential or negative voltage, the channel is closed, the second buried layer 3b is connected to the source potential, and the second buried layer 3b, the first buried layer 3a and the first epitaxial layer 2 form a depletion region. The boundary of the depletion region is shown as Figure 3As shown by the dashed line corresponding to the marker 102 in FIG, the lateral and vertical JFET regions are pinched off, thereby pinching off the lateral and vertical extensions of the first channel region, thereby reducing the reverse leakage of the device. Therefore, when the device is in the reverse cutoff state, the SiC JFET bears the high voltage, while the lateral and vertical JFET regions shield the high electric field at the drain. The reverse leakage current Isd flows from the drain through the second buried layer 3b to the source front metal layer and out. The reverse leakage current Isd does not flow through the SiC / Si heterojunction, thus avoiding the risk of increased leakage due to heterogeneous lattice mismatch.

[0144] The field-effect transistor of the embodiment of the present invention comprises a first JFET and a second MOSFET formed of materials with different bandgap widths. The first JFET and the second MOSFET are connected via a cascode to form a field-effect transistor with a heterojunction cascode structure. The cascode structure of the low-voltage Si MOSFET and the high-voltage SiC JFET is monolithically integrated via the heterojunction. The embodiment of the present invention has the following advantages:

[0145] 1) The Si MOSFET channel is used for current conduction, which avoids the problem of high interface state density in the SiC MOS channel and improves the channel mobility of the device.

[0146] 2) Si MOS is used to switch the device, so the device of this invention is fully compatible with the driving scheme of Si MOSFET.

[0147] 3) Si MOS is used to switch the device, so the part that directly drives the voltage is Si MOS, which avoids the problem of low reliability of the SiC MOS gate oxide layer.

[0148] In addition, compared with the existing traditional heterojunction integration scheme, the embodiments of the present invention have the following advantages: 1) the forward conduction current does not cross the heterojunction barrier, avoiding the influence of the heterojunction on the conduction characteristics; 2) the reverse current does not pass through the heterojunction epitaxial layer, avoiding the problem of increased leakage due to lattice mismatch.

[0149] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A field effect transistor, characterized in that: include: a first epitaxial layer doped with a first conductivity type and composed of a first semiconductor material, and a second epitaxial layer doped with the first conductivity type and composed of a second semiconductor material, wherein the band gap of the first semiconductor material is greater than the band gap of the second semiconductor material, the second epitaxial layer is formed on a top surface of the first epitaxial layer, and a contact surface between the first epitaxial layer and the second epitaxial layer forms a heterojunction; A first JFET is formed in the first epitaxial layer, and a second MOSFET is formed in the second epitaxial layer; The first JFET comprises: a first drain region heavily doped with a first conductivity type, a first gate region, and a first source region heavily doped with a first conductivity type; The first drain region is formed on the back side of the first epitaxial layer; The first source region is formed on the front surface of the first epitaxial layer; The first gate region is composed of a second conductivity type doped region formed in the first epitaxial layer, the first epitaxial layer surrounded by the first gate region constitutes a first channel region, and the first channel region is located between the first source region and the first drain region; The second MOSFET comprises: a second source region heavily doped with the first conductivity type, a second gate structure, and a second drain region heavily doped with the first conductivity type; The second gate structure includes a gate dielectric layer and a gate conductive material layer sequentially stacked on the surface of the second epitaxial layer; The second source region and the second drain region are self-aligned and formed on both sides of the second gate structure; forming a second channel region doped with a second conductivity type in the region covered by the second gate structure; The first source region and the second drain region are connected via a first floating metal contact hole that passes through the heterojunction; a first dielectric layer is provided between the first floating metal contact hole and the second channel region and the second epitaxial layer at the bottom of the second channel region; The first gate region is connected to a source electrode composed of a front metal layer through a deep contact hole passing through the heterojunction; the second source region is connected to the source electrode; a first dielectric layer is separated between the deep contact hole and the second channel region passed through and the second epitaxial layer at the bottom of the second channel region; The back side of the first drain region is connected to a drain electrode formed by a back side metal layer.

2. The field effect transistor according to claim 1, wherein: The first semiconductor material includes SiC.

3. The field effect transistor according to claim 2, wherein: The second semiconductor material includes Si.

4. The field effect transistor according to claim 1, wherein: The first gate region comprises two first buried layers and a second buried layer; the second buried layer being formed in a top surface region of the first epitaxial layer; The top surface of each of the first buried layers is located below the bottom surface of the second buried layer; A first lateral spacing region is provided between the two first buried layers, and the first lateral spacing region serves as a longitudinal extension region of the first channel region; The second buried layer and the first buried layer at the bottom have a first intersection region, and the first intersection region serves as a lateral extension region of the first channel region; The first gate region is connected to the source through the deep contact hole formed on the top of the second buried layer.

5. The field effect transistor according to claim 4, wherein: The second source region is also connected to the source electrode through the deep contact hole on the top of the second buried layer.

6. The field effect transistor according to claim 5, wherein: Above the top surface of the second epitaxial layer, the width of the first floating metal contact hole increases and extends above the top surface of the second drain region, and the width of the deep contact hole increases and extends above the top surface of the second source region; Ohmic contact alloys are formed at the contact positions of the first floating metal contact hole and the top surface of the second drain region, the contact positions of the first floating metal contact hole and the top surface of the first source region, the contact positions of the deep contact hole and the top surface of the second source region, and the contact positions of the deep contact hole and the top surface of the second buried layer.

7. The field effect transistor according to claim 1, wherein: The gate dielectric layer includes a gate oxide layer, and the gate conductive material layer includes a polysilicon gate.

8. The field effect transistor according to claim 1, wherein: The material of the first dielectric layer includes an oxide layer.

9. The field effect transistor according to any one of claims 1 to 8, characterized in that: The field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the field effect transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

10. A method for manufacturing a field effect transistor, characterized in that: The steps include: forming a first epitaxial layer doped with a first conductivity type and composed of a first semiconductor material on a first semiconductor material substrate, wherein the first semiconductor substrate has a heavily doped region of the first conductivity type and serves as a first drain region of a first JFET; forming a first gate region of a first JFET composed of a second conductivity type doped region in the first epitaxial layer; A first source region of the first JFET that is heavily doped with a first conductivity type is formed in the front surface area of ​​the first epitaxial layer; the first epitaxial layer surrounded by the first gate region constitutes a first channel region of the first JFET, and the first channel region is located between the first source region and the first drain region; forming a second epitaxial layer doped with a first conductivity type and composed of a second semiconductor material on a top surface of the first epitaxial layer, wherein the band gap of the first semiconductor material is greater than the band gap of the second semiconductor material, and a contact surface between the first epitaxial layer and the second epitaxial layer forms a heterojunction; forming a second channel region of a second MOSFET doped with a second conductivity type in the second epitaxial layer by using a well region forming process; Performing etching to simultaneously form contact hole trenches penetrating the second epitaxial layer on the top of the first source region and the top of the lead-out region of the first gate region; forming a first dielectric layer on the inner surface of the contact hole trench, wherein the first dielectric layer further extends to the surface of the second epitaxial layer outside the contact hole trench; forming a gate dielectric layer and a gate conductive material layer of a second gate structure of the second MOSFET in sequence on a top surface of the second channel region; forming a second source region and a second drain region heavily doped with the first conductivity type on both sides of the second gate structure in a self-aligned manner; removing the first dielectric layer on the bottom surface of each contact hole trench and removing the first dielectric layer or the gate dielectric layer on the top of the contact region between the second source region and the second drain region outside the contact hole trench; forming an ohmic contact alloy on the bottom surface of each of the contact hole trenches and the top surface of the contact region between the second source region and the second drain region; Filling a metal layer in each of the contact hole trenches, and the filled metal layer also extends to the surface of the ohmic contact alloy outside the contact hole trench to form a contact hole, wherein the contact hole on the top of the first source region constitutes a first floating metal contact hole; forming an interlayer film, a through hole passing through the interlayer film, the through hole being formed on the top of the contact hole located at the top of the lead-out region of the first gate region, and the contact hole located at the top of the lead-out region of the first gate region and the through hole at the top being connected to form a deep contact hole; forming a front metal layer and patterning it to form a source electrode, wherein the top of the deep contact hole is connected to the source electrode; A drain electrode composed of a back metal layer is formed on the back side of the first drain region.

11. The method for manufacturing a field effect transistor according to claim 10, wherein: The first semiconductor material includes SiC.

12. The method for manufacturing a field effect transistor according to claim 11, wherein: The second semiconductor material includes Si.

13. The method for manufacturing a field effect transistor according to claim 10, wherein: The steps of forming the first gate region include: forming two first buried layers at a selected depth of the first epitaxial layer, with a first lateral spacing region between the two first buried layers, and the first lateral spacing region serving as a longitudinal extension region of the first channel region; A second buried layer is formed in the top surface area of ​​the first epitaxial layer; the top surface of each first buried layer is located at the bottom of the bottom surface of the second buried layer; the second buried layer and the first buried layer at the bottom have a first intersection area and the first intersection area serves as a lateral extension area of ​​the first channel region; the first gate region is connected to the source through the deep contact hole formed on the top of the second buried layer.

14. The method for manufacturing a field effect transistor according to claim 10, wherein: The gate dielectric layer includes a gate oxide layer, and the gate conductive material layer includes a polysilicon gate.

15. The method for manufacturing a field effect transistor according to claim 10, wherein: The material of the first dielectric layer includes an oxide layer, which is formed by a thermal oxidation process.

16. The method for manufacturing a field effect transistor according to any one of claims 9 to 15, wherein: The field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the field effect transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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