Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The method includes: providing a substrate, the substrate including a first isolation region, a device region, and a second isolation region, the widths of the first isolation region and the second isolation region being different; forming a first initial mask structure, a plurality of second mask structures, and a third initial mask structure on the device region, the first initial mask structure being adjacent to the first isolation region, the third initial mask structure being adjacent to the second isolation region, and the plurality of second mask structures being located between the first initial mask structure and the third initial mask structure; performing a plurality of cyclic processes to reduce the width difference between the width of the first initial mask structure and the width of the third initial mask structure, thereby forming a first mask structure and a third mask structure; using the first mask structure, the plurality of second mask structures, and the third mask structure as masks to etch the first isolation region, the device region, and the second isolation region, thereby forming a substrate and a plurality of fins located on the substrate. Thus, a semiconductor structure with uniform and stable electrical characteristics can be formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the improvement of the integration degree of semiconductor devices, the critical dimensions of transistors are continuously reduced. However, with the sharp reduction of transistor size, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, which makes it more difficult to suppress the short-channel effect and increases the channel leakage current of the transistor.

[0003] The gate of a fin field-effect transistor (FinFET) forms a fork-shaped 3D structure similar to a fish fin. The channel of the FinFET protrudes from the substrate surface to form fins, and the gate covers the top surface and side walls of the fins, so that an inversion layer is formed on each side of the channel, and the on and off of the circuit can be controlled on both sides of the fins. This design can increase the control of the gate over the channel region, thus being able to well suppress the short-channel effect of the transistor. However, the fin field-effect transistor still has the short-channel effect.

[0004] In a method for forming a semiconductor structure in the prior art, a mask material layer is formed on a substrate. The substrate includes a first isolation region, an active region, and a second isolation region, and in a direction perpendicular to the extending direction of the fins, the first isolation region, the active region, and the second isolation region are arranged in sequence and adjacent to each other in pairs. Then, the mask material layer is etched to form a plurality of fin mask structures on the active region. Next, the substrate is etched using the plurality of fin mask structures as masks to form a plurality of fins.

[0005] However, when the widths of the first isolation region and the second isolation region are different, the etching process of the mask material layer forms different etching loads at the junctions of the first isolation region and the active region and at the junctions of the second isolation region and the active region, resulting in a large width deviation between the fin mask structures adjacent to the first isolation region and the fin mask structures adjacent to the second isolation region on the active region, causing a large width deviation between the fins adjacent to the first isolation region and the fins adjacent to the second isolation region. Thus, the formed semiconductor structure has poor uniformity and instability in electrical characteristics everywhere. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so that the electrical characteristics of the semiconductor structure are uniform and stable.

[0007] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first isolation region, a device region, and a second isolation region arranged along a first direction, the widths of the first isolation region and the second isolation region in the first direction being different; forming a first initial mask structure, a plurality of second mask structures, and a third initial mask structure that are separated from each other on the device region, the first initial mask structure being adjacent to the first isolation region, the third initial mask structure being adjacent to the second isolation region, and the plurality of second mask structures being located between the first initial mask structure and the third initial mask structure; performing a plurality of cyclic processes to reduce the width difference between the width of the first initial mask structure and the width of the third initial mask structure, forming a first mask structure and a third mask structure; using the first mask structure, the plurality of second mask structures, and the third mask structure as masks to etch the first isolation region, the device region, and the second isolation region, forming a substrate and a plurality of fin portions located on the substrate; wherein, the method for each cyclic process includes: forming a sacrificial film on the surfaces of the first isolation region, the device region, the second isolation region, the first initial mask structure, the plurality of second mask structures, and the third initial mask structure; etching the sacrificial film, the first initial mask structure, and the third initial mask structure until the sidewall surfaces of the second mask structures are exposed.

[0008] Optionally, the widths of the first initial mask structure and the third initial mask structure are both greater than the width of the second mask structure.

[0009] Optionally, the forming of the first initial mask structure, the plurality of second mask structures, and the third initial mask structure that are separated from each other on the device region includes: forming a mask structure material layer on the surfaces of the first isolation region, the device region, and the second isolation region; using a self-aligned dual imaging process or a self-aligned multiple imaging process to form a plurality of sidewalls that are separated from each other on the surface of the mask structure material layer on the device region; using the plurality of sidewalls as masks to perform dry etching on the mask structure material layer until the surfaces of the first isolation region, the device region, and the second isolation region are exposed, and in the dry etching process, the rate of reaction to form etching by-products is greater than the volatilization rate of the etching by-products.

[0010] Optionally, an in-situ atomic layer etching process is used to etch the sacrificial film, the first initial mask structure, and the third initial mask structure along a direction parallel to the surface of the substrate.

[0011] Optionally, the width of the first isolation region is less than the width of the second isolation region, and the width of the first initial mask structure is less than the width of the third initial mask structure.

[0012] Optionally, in a direction parallel to the substrate surface, the etching rate of the first initial mask structure and the sacrificial film on the surface of the first initial mask structure by the in-situ atomic layer etching process is less than the etching rate of the third initial mask structure and the sacrificial film on the surface of the third initial mask structure, and the widths of the first mask structure and the third mask structure are both greater than the width of the second mask structure.

[0013] Optionally, in the cyclic process, an in-situ atomic layer deposition process is used to form a sacrificial film on the first isolation region, the device region, the second isolation region, the first initial mask structure, several second mask structures, and the third initial mask structure.

[0014] Optionally, the material of the sacrificial film includes silicon oxide.

[0015] Optionally, the gases used in the in-situ atomic layer deposition process include aminosilane and oxygen.

[0016] Optionally, the parameters of the in-situ atomic layer etching process include: the reaction gas includes C X H Y F Z , and the range of X / Z is 1:4 to 1:1; the bias voltage is 0 V; the pressure range is 5 mTorr to 50 mTorr; the source power is 50 W to 300 W.

[0017] Optionally, the in-situ atomic layer deposition process and the in-situ atomic layer etching process are carried out in the same reaction chamber.

[0018] Optionally, the temperature deviation between the in-situ atomic layer deposition process and the in-situ atomic layer etching process is within 50 °C.

[0019] Optionally, the parameters of the in-situ atomic layer deposition process further include a temperature range of 50 °C to 120 °C, and the parameters of the in-situ atomic layer etching process further include a temperature range of 50 °C to 120 °C.

[0020] Optionally, the several fin portions include a first fin adjacent to the first isolation region, a third fin adjacent to the second isolation region, and several second fins located between the first fin and the third fin. The width difference between the width of the first fin and the width of the third fin is within 5% of the width of the second fin, and the widths of the first fin and the third fin are both greater than the width of the second fin.

[0021] Optionally, the first initial mask structure, several second mask structures, and the third initial mask structure are made of the same material, and the material of the first initial mask structure includes silicon nitride.

[0022] Optionally, the material of the first mask structure further includes silicon oxide.

[0023] Optionally, it further includes: forming an isolation layer on the surfaces of the first isolation region, the device region, and the second isolation region, and the surface of the isolation layer is lower than the top surfaces of a plurality of fin portions.

[0024] Correspondingly, the technical solution of the present invention further provides a semiconductor structure, including: a substrate, the substrate includes a first isolation region, a device region, and a second isolation region arranged along a first direction, and the widths of the first isolation region and the second isolation region in the first direction are different; a plurality of fin portions on the substrate in the device region, the plurality of fin portions include a first fin adjacent to the first isolation region, a third fin adjacent to the second isolation region, and a plurality of second fins located between the first fin and the third fin, and the width difference between the width of the first fin and the width of the third fin is within 5% of the width of the second fin.

[0025] Optionally, the widths of the first fin and the third fin are both greater than the width of the second fin, and the width of the first fin is equal to the width of the third fin.

[0026] Optionally, it further includes: an isolation layer on the surfaces of the first isolation region, the device region, and the second isolation region, and the surface of the isolation layer is lower than the top surfaces of a plurality of fin portions.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the widths of the first isolation region and the second isolation region in the first direction are different; forming a first initial mask structure, a plurality of second mask structures, and a third initial mask structure that are separated from each other on the device region, the first initial mask structure is adjacent to the first isolation region, the third initial mask structure is adjacent to the second isolation region, and the plurality of second mask structures are located between the first initial mask structure and the third initial mask structure; performing a plurality of cyclic processes to reduce the width difference between the width of the first initial mask structure and the width of the third initial mask structure to form a first mask structure and a third mask structure; using the first mask structure, the plurality of second mask structures, and the third mask structure as masks to etch the first isolation region, the device region, and the second isolation region to form a substrate and a plurality of fin portions on the substrate; wherein, the method of each cyclic process includes: forming a sacrificial film on the surfaces of the first isolation region, the device region, the second isolation region, the first initial mask structure, the plurality of second mask structures, and the third initial mask structure; etching the sacrificial film, the first initial mask structure, and the third initial mask structure until the sidewall surfaces of the second mask structures are exposed. Therefore, a semiconductor structure with uniform and stable electrical characteristics can be formed. Description of the Drawings

[0029] Figures 1 to 9It is a schematic cross-sectional structure diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed implementation manners

[0030] As described in the background art, in the prior art, when the widths of the first isolation region and the second isolation region are different, the process of etching the mask material layer forms different etching loads at the junctions of the first isolation region and the active region and the second isolation region and the active region, resulting in a large width deviation between the fin mask structures adjacent to the first isolation region and the fin mask structures adjacent to the second isolation region on the active region, causing a large width deviation between the fin portions adjacent to the first isolation region and the fin portions adjacent to the second isolation region. As a result, the formed semiconductor structure has poor uniformity and instability in electrical characteristics everywhere.

[0031] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same. By performing several cyclic processes to reduce the width difference between the width of the first initial mask structure and the width of the third initial mask structure, a first mask structure and a third mask structure are formed, and a semiconductor structure with uniform and stable electrical characteristics can be formed.

[0032] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0033] Figures 1 to 9 It is a schematic cross-sectional structure diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0034] Please refer to Figure 1 , a substrate 100 is provided. The substrate 100 includes a first isolation region I, a device region A, and a second isolation region II arranged along a first direction X. The widths of the first isolation region I and the second isolation region II in the first direction X are different.

[0035] In this embodiment, the width W1 of the first isolation region I (as Figure 1 shown) is smaller than the width W2 of the second isolation region II (as Figure 1 shown).

[0036] The material of the substrate 100 includes a semiconductor material.

[0037] In this embodiment, the material of the substrate 100 includes silicon.

[0038] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0039] Next, a first initial mask structure, a plurality of second mask structures, and a third initial mask structure are formed separately on the device region A. For the specific steps of forming the first initial mask structure, a plurality of second mask structures, and a third initial mask structure, please refer to Figures 2 to 4 .

[0040] Please refer to Figure 2 , and a mask structure material layer 110 is formed on the surfaces of the first isolation region I, the device region A, and the second isolation region II.

[0041] The mask structure material layer 110 provides materials for subsequently forming the first initial mask structure, a plurality of second mask structures, and a third initial mask structure.

[0042] In this embodiment, the mask structure material layer 110 includes a first material layer (not shown) and a second material layer (not shown) located on the first material layer.

[0043] The material of the first material layer includes silicon nitride, and the material of the second material layer includes silicon oxide.

[0044] Please refer to Figure 3 , and a plurality of sidewalls 120 are formed separately on the surface of the mask structure material layer 110 on the device region A by using a self-aligned multiple imaging process.

[0045] By using the self-aligned multiple imaging process, the dimensional limitations of the lithography process limit on the width of the fin and the pitch between adjacent fins (Fin Pitch) can be reduced, and the integration degree of the semiconductor structure can be greatly improved.

[0046] In addition, in this embodiment, a process method of preferentially transferring isolation patterns (ARH cut first scheme) is adopted, that is: before forming the mask structure, the sidewalls of the first isolation region I and the second isolation region II are removed, so that a mask structure for transferring fin patterns is not formed on the first isolation region I and the second isolation region II subsequently.

[0047] Since the height of the sidewall 120 is lower than the height of a plurality of subsequent fins formed, the aspect ratio between adjacent sidewalls 120 can be made smaller than the aspect ratio between adjacent fins. Moreover, since the sidewall 120 grows along the sidewall of the second core structure, the sidewall 120 has a better morphology and a high sidewall perpendicularity. Therefore, compared with the process method of using isolation pattern lag transfer (ARH cut last scheme), that is, the process method of etching and removing the fins in the first isolation region I, the device region A, and the second isolation region II after forming a plurality of fins in all of them, the process method of using the ARH cut first scheme can reduce the etching load, improve the fin morphology, and reduce the etching load difference between the first isolation region I, the second isolation region II, and the device region A, so as to better improve the performance and reliability of the semiconductor structure.

[0048] Specifically, the method for forming a plurality of mutually separated sidewalls 120 on the device region A includes: forming a second core material layer (not shown) on the surface of the mask structure material layer 110; forming a plurality of mutually separated first core structures (not shown) on the surface of the second core material layer; forming a sacrificial sidewall film (not shown) on the surfaces of the plurality of first core structures and the exposed second core material layer; etching the sacrificial sidewall film by using an anisotropic etching process until the top surfaces of the plurality of first core structures and the surface of the second core material layer are exposed, so as to form a plurality of sacrificial sidewalls (not shown); after forming the plurality of sacrificial sidewalls, removing the plurality of first core structures; after removing the plurality of first core structures, etching the second core material layer by using the plurality of sacrificial sidewalls as a mask until the surface of the mask structure material layer 110 is exposed, so as to form a plurality of mutually separated second core structures (not shown); after forming the plurality of mutually separated second core structures, removing the plurality of sacrificial sidewalls; after removing the plurality of sacrificial sidewalls, forming a sidewall film (not shown) on the surfaces of the plurality of second core structures and the mask structure material layer 110; etching the sidewall film by using an anisotropic etching process until the top surfaces of the plurality of second core structures and the surface of the mask structure material layer 110 are exposed, so as to form a plurality of sidewalls 120; forming a patterned layer (not shown) on the mask structure material layer 110 and the plurality of sidewalls 120, and the patterned layer exposes the plurality of sidewalls 120 on the first isolation region I and the second isolation region II; etching the exposed plurality of sidewalls 120 by using the patterned layer as a mask until the exposed plurality of sidewalls 120 are removed, so as to form a plurality of mutually separated sidewalls 120 on the device region A.

[0049] In other embodiments, a plurality of mutually separated sidewalls are formed on the device region by using a self-aligned double imaging process.

[0050] Please refer to Figure 4, using several sidewalls 120 as a mask, dry-etch the mask structure material layer 110 until the surfaces of the first isolation region I, the device region A, and the second isolation region II are exposed, and form discrete first initial mask structures 111, several second mask structures 112, and third initial mask structures 113 on the device region A. The first initial mask structure 111 is adjacent to the first isolation region I, the third initial mask structure 113 is adjacent to the second isolation region II, and several second mask structures 112 are located between the first mask structure 111 and the third mask structure 113.

[0051] The first initial mask structure 111 is used to form the first mask structure, and the third initial mask structure 113 is used to form the third mask structure.

[0052] The first mask structure, several second mask structures 112, and the third mask structure are masks for subsequent etching of the substrate 100 to form several fins.

[0053] Specifically, the first mask structure is used to form the first fin adjacent to the first isolation region I, several second mask structures 112 are used to form several second fins, and the third mask structure is used to form the third fin adjacent to the second isolation region II. Among them, several second fins are located between the first fin and the third fin.

[0054] In this embodiment, the width M1 of the first initial mask structure 111 and the width M3 of the third initial mask structure 113 are both greater than the width M2 of the second mask structure 112.

[0055] Since more isolation layer materials need to be formed in the first isolation region I and the second isolation region II than in the device region A later, and the materials of the isolation layer include oxides, compared with several second fins, the isolation layer exerts greater stress on the first fin and the third fin, and the first fin and the third fin are also more easily oxidized.

[0056] In this embodiment, by forming the first initial mask structure 111 and the third initial mask structure 113 wider than the second mask structure 112, the first mask structure and the third mask structure wider than the second mask structure 112 can be formed subsequently, so as to form the first fin and the third fin wider than the second fin. Therefore, not only the first fin and the third fin have stronger stress resistance, and defects such as fin bending and fin merging can be reduced, but also the first fin and the third fin provide materials for more serious oxidation loss, which can increase the effective widths of the first fin and the third fin, make the effective widths of the first fin and the second fin more consistent, and make the effective widths of the third fin and the second fin more consistent. Thus, not only the reliability of the semiconductor structure is improved, but also the uniformity and stability of the electrical characteristics are better enhanced.

[0057] In this embodiment, in the process of dry etching the mask structure material layer 110, the rate of reaction to form etching by-products is greater than the volatilization rate of the etching by-products.

[0058] Since there is no mask structure on the first isolation region I and the second isolation region II, and there is a mask structure on the device region A, therefore, compared with the device region A, etching by-products are more likely to be formed on the first isolation region I and the second isolation region II. Correspondingly, in the junction regions between the device region A and the first isolation region I, and between the device region A and the second isolation region II, etching by-products are more likely to be formed than in the remaining regions of the device region A.

[0059] On this basis, in the process of dry etching the mask structure material layer 110, by making the rate of reaction to form etching by-products greater than the volatilization rate of the etching by-products, the volatilization of the etching by-products can be reduced or eliminated. Therefore, in the junction regions between the device region A and the first isolation region I, and between the device region A and the second isolation region II, more etching by-products will accumulate than in the remaining regions of the device region A. Thus, among the formed first initial mask structure 111, several second mask structures 112, and third initial mask structure 113, the width M1 of the first initial mask structure 111 adjacent to the first isolation region I and the width M3 of the third initial mask structure 113 adjacent to the second isolation region II can both be greater than the width M2 of the second mask structure 112.

[0060] However, since the width W1 of the first isolation region I is smaller than the width W2 of the second isolation region II, therefore, during the dry etching process, compared with the junction region between the device region A and the first isolation region I, etching by-products are more likely to be formed in the junction region between the device region A and the second isolation region II, resulting in more etching by-products accumulating in the junction region between the device region A and the second isolation region II. Thus, in this embodiment, the width M1 of the first initial mask structure 111 is smaller than the width M3 of the third initial mask structure 113, and the magnitude of the width difference between the width M1 and the width M3 is not easy to control.

[0061] Specifically, the parameters of the process of dry etching the mask structure material layer 110 include: the carbon-fluorine ratio range of the reaction gas is 1:3 to 1:1, and the pressure range is 30 mTorr to 100 mTorr. Thus, by using a reaction gas with a higher carbon-fluorine ratio, the formation of etching by-products is accelerated, and by using a higher reaction chamber pressure, the volatilization rate of the etching by-products is reduced, thereby achieving a rate of reaction to form etching by-products greater than the volatilization rate of the etching by-products.

[0062] In this embodiment, the materials of the first initial mask structure 111, several second mask structures 112, and third initial mask structure 113 are the same.

[0063] Specifically, since the mask structure material layer 110 includes the first material layer and the second material layer, the materials of the first initial mask structure 111, several second mask structures 112, and the third initial mask structure 113 include silicon nitride and silicon oxide.

[0064] In other embodiments, the materials of the first initial mask structure, several second mask structures, and the third initial mask structure include silicon nitride.

[0065] Next, several cyclic processes are performed to reduce the width difference between the width M1 of the first initial mask structure 111 and the width M3 of the third initial mask structure 113, forming the first mask structure and the third mask structure.

[0066] Among them, the method of each cyclic process includes: forming a sacrificial film on the surfaces of the first isolation region I, the device region A, the second isolation region II, the first initial mask structure 111, several second mask structures 112, and the third initial mask structure 113; etching the sacrificial film, the first initial mask structure 111, and the third initial mask structure 113 until the sidewall surfaces of the second mask structures 112 are exposed.

[0067] Since the widths of the first isolation region I and the second isolation region II in the first direction X are different, and the first initial mask structure 111 is adjacent to the first isolation region I, the third initial mask structure 113 is adjacent to the second isolation region II, and several second mask structures 112 are located between the first initial mask structure 111 and the third initial mask structure 113, the first initial mask structure 111 and the sacrificial film on its surface, the sacrificial film on the surface of the second mask structures 112, and the third initial mask structure 113 and the sacrificial film on its surface have different etching environments.

[0068] On this basis, since several cyclic processes are performed to reduce the width difference between the width M1 of the first initial mask structure 111 and the width M3 of the third initial mask structure 113, forming the first mask structure and the third mask structure, and the method of each cyclic process includes: forming a sacrificial film on the surfaces of the first isolation region I, the device region A, the second isolation region II, the first initial mask structure 111, several second mask structures 112, and the third initial mask structure 113; etching the sacrificial film, the first initial mask structure 111, and the third initial mask structure 113 until the sidewall surfaces of the second mask structures 112 are exposed. Therefore, a semiconductor structure with uniform and stable electrical characteristics can be formed.

[0069] Specifically, in the cyclic process, by forming the sacrificial film, materials that can be pre-consumed are reserved for the etching in the cyclic process. Meanwhile, in the etching of the cyclic process, different etching environments can be utilized to adjust the etching rates of the first initial mask structure 111 and the sacrificial film on its surface, the sacrificial film on the surface of the second mask structure 112, and the third initial mask structure 113 and the sacrificial film on its surface. Specifically, the etching rate of the sacrificial film on the surface of the second mask structure 112 can be made the slowest in the etching of the cyclic process. Meanwhile, the wider one of the first initial mask structure 111 or the third initial mask structure 113 and the sacrificial film on its surface can be etched at the fastest etching rate. Thus, through the cyclic process, while maintaining the width M2 of the second mask structure 112, the width difference between the width M1 of the first initial mask structure 111 and the width M3 of the third initial mask structure 113 can be reduced, and a semiconductor structure with the widths of the first mask structure and the third mask structure being close to or consistent can be formed. Thereby, the uniformity of the widths of several fin portions is improved, and a semiconductor structure with uniform and stable electrical characteristics everywhere is formed.

[0070] For the detailed steps of specifically performing one cycle of the process, please refer to Figures 5 to 6 , Figure 7 is a schematic structural diagram of a semiconductor structure formed by several cycles of the process.

[0071] Please refer to Figure 5 , a sacrificial film 130 is formed on the surfaces of the first isolation region I, the device region A, the second isolation region II, the first initial mask structure 111, several second mask structures 112, and the third initial mask structure 113.

[0072] In this embodiment, an in-situ atomic layer deposition process (In-situ ALE) is adopted to form a sacrificial film 130 on the surfaces of the first isolation region I, the device region A, the second isolation region II, the first initial mask structure 111, several second mask structures 112, and the third initial mask structure 113.

[0073] The atomic layer deposition process (ALD) has the process characteristics of slow film formation speed, high control precision, and good film formation uniformity. Therefore, through the in-situ atomic layer deposition process, a thin, precisely thick, and uniform-thickness sacrificial film 130 can be formed on the surfaces of the first isolation region I, the device region A, the second isolation region II, the first initial mask structure 111, several second mask structures 112, and the third initial mask structure 113.

[0074] In this embodiment, the material of the sacrificial film 130 includes silicon oxide.

[0075] In this embodiment, the film thickness of the sacrificial film 130 is below 2 nanometers.

[0076] On the one hand, the film formation rate of the in-situ atomic layer deposition process is slow. On the other hand, in this embodiment, the etching of the cyclic process is performed by using the in-situ atomic layer etching process to improve the etching accuracy, and the etching rate of the in-situ atomic layer etching process is slow. Therefore, an overly thick film thickness will result in low efficiency of the manufacturing process. Thus, by using the sacrificial film 130 with a film thickness of less than 2 nanometers, while reserving sufficient materials for consumption in the in-situ atomic layer etching process, the efficiency of the manufacturing process can be greatly improved. In this embodiment, the parameters of the in-situ atomic layer deposition process further include: the temperature range is 50 degrees Celsius to 120 degrees Celsius.

[0077] Please refer to Figure 6 , etch the sacrificial film 130, the first initial mask structure 111, and the third initial mask structure 113 until the sidewall surface of the second mask structure 112 is exposed.

[0078] Thus, after several cyclic processes, the first mask structure 211 (as Figure 7 shown) and the third mask structure 213 (as Figure 7 shown) are formed.

[0079] It should be understood that since the widths of several fins are defined by the widths of the first mask structure 211, the second mask structure 112, and the third mask structure 213, therefore, whether the sacrificial film 130 remains on the top surfaces of the first mask structure 211, the second mask structure 112, and the third mask structure 213 does not affect the effect of the technical solution of the present invention. In addition, in an ideal state, the cyclic process does not cause loss of the second mask structure 112, but in actual application scenarios, due to the accuracy of the etching process, a slight loss may be formed on the second mask structure 112.

[0080] In this embodiment, the in-situ atomic layer etching process is used to etch the sacrificial film 130, the first initial mask structure 111, and the third initial mask structure 113 along a direction parallel to the surface of the substrate 100.

[0081] Since the in-situ atomic layer deposition process and the in-situ atomic layer etching process are used for the cyclic process, therefore, the cyclic process does not break the vacuum and has strong operability.

[0082] Moreover, the in-situ atomic layer deposition process and the in-situ atomic layer etching process have high process accuracy and good controllability, and can perform more precise width adjustment on the first initial mask structure 111 and the third initial mask structure 113. Therefore, the width M2 of the second mask structure 112 can be better maintained, and the width difference between the width of the first mask structure 211 and the width of the third mask structure 213 can be further reduced to form a semiconductor structure with better electrical property uniformity and stability.

[0083] Specifically, after the sacrificial film 130 with a thin, precise thickness, and uniform film thickness is formed by the in-situ atomic layer deposition process, the in-situ atomic layer etching process with high process precision and good controllability is used to etch the sacrificial film 130, the first initial mask structure 111, and the third initial mask structure 113 until the sidewall surface of the second mask structure 112 is exposed. Therefore, in each cycle process, the etching of the sacrificial film 130, the first initial mask structure 111, and the third initial mask structure 113 is accurately controlled, which not only better reduces the risk of damage to the second mask structure 112, but also can perform trace etching of different degrees on the first initial mask structure 111 and the third initial mask structure 113. Thus, after several cycle processes, not only the width M2 of the second mask structure 112 is better maintained, but also the width difference between the width of the first mask structure 211 and the width of the third mask structure 213 is further reduced.

[0084] In addition, in the in-situ atomic layer etching process, etching is performed along the direction parallel to the surface of the substrate 100. Therefore, not only the damage to the surface of the substrate 100 is reduced, but also the height loss of the first mask structure 211, the second mask structure 112, and the third mask structure 213 is reduced, so as to reduce the risk that the first mask structure 211, the second mask structure 112, and the third mask structure 213 are completely consumed in the subsequent etching process for forming a plurality of fins.

[0085] In this embodiment, since the first initial mask structure 111 and the third initial mask structure 113 wider than the second mask structure 112 are formed, combining the in-situ atomic layer deposition process and the in-situ atomic layer etching process can not only better ensure that after several cycle processes, the first mask structure 211 and the third mask structure 213 wider than the second mask structure 112 are still formed, but also more accurately control the width difference between the width of the first mask structure 211 and the width of the second mask structure 112, and the width difference between the width of the third mask structure 213 and the width of the second mask structure 112. Thus, the consistency of the effective widths of the subsequently formed first fin, second fin, and third fin is further improved, and further, the uniformity and stability of the electrical characteristics of the semiconductor structure are further improved.

[0086] Preferably, the number of cycles of the cycle process ranges from 2 to 20 times. Thus, while better reducing the width deviation between the first mask structure 111 and the third mask structure 113, the efficiency of the manufacturing process is better balanced.

[0087] Preferably, the method of performing several cycles of processing further includes: performing several cycles of processing until the width difference between the first mask structure and the third mask structure is within 5% of the width of the second mask structure. Thereby, the consistency between the width of the first mask structure and the width of the third mask structure is better ensured.

[0088] In this embodiment, in the direction parallel to the surface of the substrate 100, the etching rate of the in-situ atomic layer etching process on the first initial mask structure 111 and the sacrificial film 130 on the surface of the first initial mask structure 111 is less than the etching rate on the third initial mask structure 113 and the sacrificial film 130 on the surface of the third initial mask structure 113.

[0089] Thus, when the width M3 of the third initial mask structure 113 is greater than the width M1 of the first initial mask structure 111, the reduction of the width difference between the two can be achieved.

[0090] Specifically, in the in-situ atomic layer etching process of this embodiment, the speed of forming etching by-products in the reaction is less than the volatilization speed of the etching by-products.

[0091] Since there is no mask structure on the first isolation region I and the second isolation region II, and the width W1 of the first isolation region I is less than the width W2 of the second isolation region II, therefore, in the in-situ atomic layer etching process, compared with the junction region between the device region A and the first isolation region I, the etching by-products are more likely to form and volatilize in the junction region between the device region A and the second isolation region II. On this basis, since the formation speed of the etching by-products in the in-situ atomic layer etching process is less than the volatilization speed, therefore, through the in-situ atomic layer etching process, the material in the junction region between the device region A and the second isolation region II can be etched faster.

[0092] In this embodiment, the parameters of the in-situ atomic layer etching process include: the reaction gas includes C X H Y F Z ; the bias voltage is 0 V; the pressure range is 5 mTorr to 50 mTorr; the source power is 50 W to 300 W.

[0093] In this embodiment, the carbon content percentage of the reaction gas in the in-situ atomic layer etching process is higher than the carbon content percentage of the reaction gas for dry etching the mask structure material layer 110.

[0094] Specifically, the range of X / Z is 1:4 to 1:1.

[0095] Thus, by controlling the range of X / Z of the reaction gas, the formation rate of the etching by-products is controlled, and by maintaining a relatively low reaction chamber pressure, the volatilization rate of the etching by-products is increased. In this way, in the in-situ atomic layer etching process, the formation rate of the etching by-products is less than the volatilization rate.

[0096] In addition, by applying a bias voltage of 0 V and a relatively low source power, the in-situ atomic layer etching process mainly etches in a direction parallel to the surface of the substrate 100, reducing the damage to the surface of the substrate 100 and better improving the performance of the semiconductor structure.

[0097] It should be noted that C X H Y F Z can be a composite gas. For example, C X H Y F Z can be a composite gas composed of the gases CHF3, CH3F, and CH2F2.

[0098] In this embodiment, the range of Y is 0 to 4.

[0099] The in-situ atomic layer deposition process and the in-situ atomic layer etching process are carried out in the same reaction chamber.

[0100] In this embodiment, the in-situ atomic layer deposition process and the in-situ atomic layer etching process are carried out in the reaction chamber of the atomic layer etching process equipment.

[0101] Since aminopropylsilane and oxygen can react at a relatively low temperature to form silicon oxide (the material of the sacrificial film 130), the temperature of the in-situ atomic layer deposition process in this embodiment can be close to the temperature of the in-situ atomic layer etching process. Thus, the in-situ atomic layer deposition process can be carried out in the reaction chamber of the atomic layer etching process equipment for the in-situ atomic layer etching process.

[0102] In this embodiment, the temperature deviation between the in-situ atomic layer deposition process and the in-situ atomic layer etching process is within 50 degrees Celsius.

[0103] In this embodiment, the parameters of the in-situ atomic layer etching process further include: the temperature range is 50 degrees Celsius to 120 degrees Celsius.

[0104] In another embodiment, the width of the first initial mask structure is greater than the width of the third initial mask structure. Therefore, an in-situ atomic layer etching process with a reaction rate for forming etching by-products greater than the volatilization rate of the etching by-products can be used to reduce the width difference between the first initial mask structure and the third initial mask structure.

[0105] Please refer to Figure 8, using the first mask structure 211, several second mask structures 112, and the third mask structure 213 as masks, etch the first isolation region I, the device region A, and the second isolation region II to form the substrate 101 and several fin portions located on the substrate 101.

[0106] In this embodiment, the several fin portions include: a first fin 141 adjacent to the first isolation region I, a third fin 143 adjacent to the second isolation region II, and several second fins 142 located between the first fin 141 and the third fin 143.

[0107] In the first direction X, the width difference between the width of the first fin 141 and the width of the third fin 143 is within 5% of the width of the second fin 142, and the width of the first fin 141 and the width of the third fin 143 are both greater than the width of the second fin 142.

[0108] The first direction X is perpendicular to the extending directions of the first fin 141, the second fins 142, and the third fin 143.

[0109] In this embodiment, the range of the width difference between the width of the first fin 141 and the width of the third fin 143 is 0 nanometers to 1 nanometer.

[0110] Preferably, in the first direction X, the width of the first fin 141 is equal to the width of the third fin 143.

[0111] In this embodiment, before etching the first isolation region I, the device region A, and the second isolation region II, an atomic layer deposition process is used to deposit a compensation film (not shown) on the surfaces of the first mask structure 211, several second mask structures 112, and the third mask structure 213 to improve the damage suffered by the surfaces of the first mask structure 211, several second mask structures 112, and the third mask structure 213, realize the improvement of the morphologies of the first fin 141, several second fins 142, and the third fin 143, and improve the width accuracy of the first fin 141, several second fins 142, and the third fin 143.

[0112] In other embodiments, the compensation film is not formed.

[0113] In this embodiment, after forming several fin portions, the first mask structure 211, several second mask structures 112, and the third mask structure 213 are removed.

[0114] Please refer to Figure 9 , an isolation layer 150 is formed on the surfaces of the first isolation region I, the device region A, and the second isolation region II, and the surface of the isolation layer 150 is lower than the top surfaces of several fin portions.

[0115] The material of the isolation layer 150 includes silicon oxide.

[0116] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figure 9 , including: a substrate 101, the substrate 101 includes a first isolation region I, a device region A, and a second isolation region II arranged along a first direction X, and the widths of the first isolation region I and the second isolation region II in the first direction X are different; a plurality of fin portions on the substrate 101 in the device region A, the plurality of fin portions include a first fin 141 adjacent to the first isolation region I, a third fin 143 adjacent to the second isolation region II, and a plurality of second fins 142 located between the first fin 141 and the third fin 143, and, in the first direction X, the width difference between the width of the first fin 141 and the width of the third fin 143 is within 5% of the width of the second fin 142.

[0117] In this embodiment, the range of the width difference between the width of the first fin 141 and the width of the third fin 143 is 0 nanometers to 1 nanometer.

[0118] Preferably, the width of the first fin 141 is equal to the width of the third fin 143, and the widths of the first fin 141 and the third fin 143 are both greater than the width of the second fin 142.

[0119] In this embodiment, the semiconductor structure further includes: an isolation layer 150 on the surfaces of the first isolation region I, the device region A, and the second isolation region II.

[0120] The surface of the isolation layer 150 is lower than the top surfaces of the plurality of fin portions, and the material of the isolation layer 150 includes silicon oxide.

[0121] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a first isolation region, a device region, and a second isolation region arranged along a first direction, the widths of the first isolation region and the second isolation region in the first direction being different; Forming a mutually separated first initial mask structure, a plurality of second mask structures, and a third initial mask structure on the device region, the first initial mask structure being adjacent to the first isolation region, the third initial mask structure being adjacent to the second isolation region, and the plurality of second mask structures being located between the first initial mask structure and the third initial mask structure; Performing a plurality of cycle processes to reduce the width difference between the width of the first initial mask structure and the width of the third initial mask structure, forming a first mask structure and a third mask structure; Using the first mask structure, the plurality of second mask structures, and the third mask structure as masks to etch the first isolation region, the device region, and the second isolation region, forming a substrate and a plurality of fins located on the substrate; Wherein, the method of each cycle process includes: forming a sacrificial film on the surfaces of the first isolation region, the device region, the second isolation region, the first initial mask structure, the plurality of second mask structures, and the third initial mask structure; etching the sacrificial film, the first initial mask structure, and the third initial mask structure until the sidewall surfaces of the second mask structures are exposed.

2. The method for forming a semiconductor structure according to claim 1, wherein, The widths of both the first initial mask structure and the third initial mask structure are greater than the width of the second mask structure.

3. The method for forming a semiconductor structure according to claim 1, wherein, The forming of the mutually separated first initial mask structure, the plurality of second mask structures, and the third initial mask structure on the device region includes: Forming a mask structure material layer on the surfaces of the first isolation region, the device region, and the second isolation region; Using a self-aligned double imaging process or a self-aligned multiple imaging process to form a plurality of mutually separated sidewalls on the surface of the mask structure material layer on the device region; Using the plurality of sidewalls as masks to perform dry etching on the mask structure material layer until the surfaces of the first isolation region, the device region, and the second isolation region are exposed. In the dry etching process, the rate of reaction to form etching by-products is greater than the volatilization rate of the etching by-products.

4. The method for forming a semiconductor structure according to claim 1, wherein, Using an in-situ atomic layer etching process to etch the sacrificial film, the first initial mask structure, and the third initial mask structure along a direction parallel to the substrate surface.

5. The method for forming a semiconductor structure according to claim 4, wherein, The width of the first isolation region is less than the width of the second isolation region, and the width of the first initial mask structure is less than the width of the third initial mask structure.

6. The method for forming a semiconductor structure according to claim 4, wherein In a direction parallel to the substrate surface, the etching rate of the in-situ atomic layer etching process for the first initial mask structure and the sacrificial film on the surface of the first initial mask structure is less than the etching rate for the third initial mask structure and the sacrificial film on the surface of the third initial mask structure, and the widths of both the first mask structure and the third mask structure are greater than the width of the second mask structure.

7. The method for forming a semiconductor structure according to claim 4, wherein, In the cycle process, using an in-situ atomic layer deposition process to form a sacrificial film on the surfaces of the first isolation region, the device region, the second isolation region, the first initial mask structure, the plurality of second mask structures, and the third initial mask structure.

8. The method for forming a semiconductor structure according to claim 7, wherein, The material of the sacrificial film includes silicon oxide.

9. The method for forming a semiconductor structure according to claim 7, wherein The gases used in the in-situ atomic layer deposition process include aminosilane and oxygen.

10. The method for forming a semiconductor structure according to claim 7, wherein, The parameters of the in-situ atomic layer etching process include: the reaction gas includes C X H Y F Z , and the range of X / Z is 1:4 to 1:1; the bias voltage is 0 V; the pressure range is 5 mTorr to 50 mTorr; the source power is 50 W to 300 W.

11. The method for forming a semiconductor structure according to claim 7, wherein The in-situ atomic layer deposition process and the in-situ atomic layer etching process are carried out in the same reaction chamber.

12. The method for forming a semiconductor structure according to claim 11, wherein, The temperature deviation between the in-situ atomic layer deposition process and the in-situ atomic layer etching process is within 50 degrees Celsius.

13. The method for forming a semiconductor structure according to claim 11, wherein The parameters of the in-situ atomic layer deposition process further include a temperature range of 50 degrees Celsius to 120 degrees Celsius, and the parameters of the in-situ atomic layer etching process further include a temperature range of 50 degrees Celsius to 120 degrees Celsius.

14. The method for forming a semiconductor structure according to claim 1, wherein, The plurality of fins include a first fin adjacent to the first isolation region, a third fin adjacent to the second isolation region, and a plurality of second fins located between the first fin and the third fin. The width difference between the width of the first fin and the width of the third fin is within 5% of the width of the second fin, and the width of the first fin and the width of the third fin are both greater than the width of the second fin.

15. The method for forming a semiconductor structure according to claim 1, wherein, The materials of the first initial mask structure, the plurality of second mask structures, and the third initial mask structure are the same, and the material of the first initial mask structure includes silicon nitride.

16. The method for forming a semiconductor structure according to claim 15, wherein, The material of the first mask structure further includes silicon oxide.

17. The method for forming a semiconductor structure according to claim 1, wherein Further included: Forming an isolation layer on the surfaces of the first isolation region, the device region, and the second isolation region, and the surface of the isolation layer is lower than the top surfaces of the plurality of fins.

18. A semiconductor structure formed by a method of forming a semiconductor structure as described in any one of claims 1 to 17, characterized in that, Including: A substrate, the substrate includes a first isolation region, a device region, and a second isolation region arranged along a first direction, and the widths of the first isolation region and the second isolation region in the first direction are different; A plurality of fins on the substrate in the device region, the plurality of fins include a first fin adjacent to the first isolation region, a third fin adjacent to the second isolation region, and a plurality of second fins located between the first fin and the third fin, and the width difference between the width of the first fin and the width of the third fin is within 5% of the width of the second fin.

19. The semiconductor structure according to claim 18, wherein, The width of the first fin and the width of the third fin are both greater than the width of the second fin, and the width of the first fin is equal to the width of the third fin.

20. The semiconductor structure according to claim 18, wherein, Further included: An isolation layer on the surfaces of the first isolation region, the device region, and the second isolation region, and the surface of the isolation layer is lower than the top surfaces of the plurality of fins.

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