Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate having a plurality of initial composite layers, each initial composite layer including an initial sacrificial layer and an initial channel layer; forming a plurality of mutually discrete fin mask structures on the plurality of initial composite layers; and performing a plurality of cyclic processing on the plurality of initial composite layers based on the fin mask structures to form a plurality of mutually discrete first fin structures on the substrate. Each first fin structure includes a plurality of first composite layers overlapping in the normal direction of the substrate surface, each first composite layer including a first sacrificial layer and a first channel layer located on the first sacrificial layer. Each cyclic processing step includes: etching and in-situ passivation of a predetermined number of initial composite layers. This improves the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the current semiconductor field, the FinFET (Fin Field-Effect Transistor) is an emerging multi-gate device. Compared with planar metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFETs have stronger short-channel rejection and higher operating current, and are now widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor size has shrunk to below a few nanometers. The size of FinFETs themselves has been reduced to its limit. Limitations in fin spacing, short-channel effect, leakage current, and materials have made transistor manufacturing precarious, and even the physical structure cannot be completed.

[0003] Gate-all-around (GAA) devices have become a new direction for research and development in the industry. This technology is characterized by the gate completely surrounding the channel on all four sides. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally and perpendicularly to the gate in linear (rod-like), planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET. This design largely solves various problems caused by reducing the gate spacing, including capacitance effects. Furthermore, since the channel is surrounded by the gate on all four sides, the channel current flows more smoothly than with the three-sided enclosure of a FinFET.

[0004] However, as an important direction for development in the industry, gate-all-around devices still require further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor structures.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a plurality of initial composite layers overlapping along the normal direction of the substrate surface, each initial composite layer including an initial sacrificial layer and an initial channel layer located on the initial sacrificial layer; forming a plurality of mutually discrete fin mask structures on the plurality of initial composite layers; and performing a plurality of cyclic processing on the plurality of initial composite layers based on the fin mask structures to form a plurality of mutually discrete first fin structures on the substrate, each first fin structure including a plurality of first composite layers overlapping along the normal direction of the substrate surface, each first composite layer including a first sacrificial layer and a first channel layer located on the first sacrificial layer, wherein each cyclic processing method includes: etching a predetermined number of initial composite layers and performing in-situ passivation processing; wherein the etching rate of the initial sacrificial layer material is greater than the etching rate of the initial channel layer material, and the in-situ passivation processing has a greater etching rate of the initial channel layer material than the etching rate of the initial sacrificial layer material in a direction parallel to the substrate surface.

[0007] Optionally, the material of the initial sacrificial layer includes germanium silicon, the material of the initial channel layer includes silicon, and the in-situ passivation process includes a low-temperature hydrogen plasma treatment process.

[0008] Optionally, the gas used in the low-temperature hydrogen plasma treatment process includes hydrogen.

[0009] Optionally, the parameters of the low-temperature hydrogen plasma treatment process also include: the source power is 500W~1200W.

[0010] Optionally, the parameters of the low-temperature hydrogen plasma treatment process also include: the bias voltage is below 50 volts.

[0011] Optionally, the method for etching and in-situ passivation of the initial composite layer with a preset number of layers includes: using the fin mask structure as a mask, etching the initial composite layer with a preset number of layers to form a corresponding intermediate composite layer; and performing the in-situ passivation on the intermediate composite layer.

[0012] Optionally, the intermediate composite layer includes an intermediate sacrificial layer and an intermediate channel layer located on the intermediate sacrificial layer; the in-situ passivation method further includes: performing the in-situ passivation until the sidewall of the intermediate sacrificial layer of the intermediate composite layer protrudes beyond the sidewall of the intermediate channel layer of the intermediate composite layer; after the several cycles of processing, the sidewall of the first sacrificial layer of the first fin structure protrudes beyond the sidewall of the first channel layer.

[0013] Optionally, it further includes: after the aforementioned several cycles of processing, using a wet etching process and employing several fin mask structures as masks, etching several first fin structures to form several second fin structures. The second fin structure includes several second composite layers overlapping along the normal direction of the substrate surface. Each second composite layer includes a second sacrificial layer and a second channel layer located on the second sacrificial layer, and the sidewall of the second sacrificial layer is flush with the sidewall of the second channel layer.

[0014] Optionally, the intermediate composite layer includes an intermediate sacrificial layer and an intermediate channel layer located on the intermediate sacrificial layer; the in-situ passivation method further includes: performing the in-situ passivation until the sidewall of the intermediate sacrificial layer of the intermediate composite layer is flush with the sidewall of the intermediate channel layer of the intermediate composite layer; after the several cycles of processing, the sidewall of the first sacrificial layer of the first fin structure is flush with the sidewall of the first channel layer.

[0015] Optionally, the intermediate composite layer includes an intermediate sacrificial layer and an intermediate channel layer located on the intermediate sacrificial layer, wherein the width of the intermediate sacrificial layer and the intermediate channel layer are both greater than the width of the fin mask structure.

[0016] Optionally, the number of preset layers is 1, and the etching process further includes: using the fin mask structure as a mask, etching 1 initial composite layer until the surface of the initial composite layer or the substrate adjacent to the 1 initial composite layer is exposed.

[0017] Optionally, the etching process may be performed using a first dry etching process.

[0018] Optionally, the first dry etching process includes: a plasma etching process using halogen gases.

[0019] Optionally, after forming a plurality of mutually independent first fin structures on the substrate, the method further includes: using a second dry etching process and etching the substrate with a plurality of fin mask structures as masks to form a substrate and isolation fins located between the substrate and the first fin structures; forming an isolation structure between adjacent isolation fins, wherein the surface of the isolation structure is flush with or higher than the top surface of the isolation fin.

[0020] Optionally, the substrate material includes silicon, the initial channel layer material includes silicon, and in the second dry etching process, the etching rate of the substrate and the initial channel layer material is greater than the etching rate of the initial sacrificial layer material.

[0021] Optionally, the fin mask structure may be formed using a self-aligned dual imaging process or a self-aligned multiple imaging process.

[0022] Accordingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate; a plurality of second fin structures located on the substrate and discrete from each other, the second fin structures including a plurality of second composite layers overlapping along the normal of the surface of the substrate, each second composite layer including a second sacrificial layer and a second channel layer located on the second sacrificial layer, and the sidewall surface of the second sacrificial layer being flush with the sidewall surface of the second channel layer.

[0023] Optionally, it may also include: an isolation fin located between the substrate and the second fin structure; and an isolation structure located between adjacent isolation fins, the surface of the isolation structure being flush with or higher than the top surface of the isolation fin.

[0024] Optionally, the material of the second sacrificial layer includes germanium silicon, and the material of the second channel layer includes silicon.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0026] In the semiconductor structure formation method provided by the technical solution of the present invention, each cycle process includes: etching and in-situ passivation of a predetermined number of initial composite layers. Furthermore, the etching rate of the initial sacrificial layer material is greater than the etching rate of the initial channel layer material, and the in-situ passivation rate of the initial channel layer material is greater than the etching rate of the initial sacrificial layer material in a direction parallel to the substrate surface. Therefore, each in-situ passivation process can thin the etched initial channel layer without breaking the vacuum along a direction parallel to the substrate surface. Moreover, the material of the etched initial sacrificial layer is consumed little or no compared to the etched initial channel layer. Thus, after several cycles, the degree of concavity of the sidewall of the first sacrificial layer relative to the sidewall of the first channel layer can be reduced. This reduces or avoids dummy gate residue in subsequent gate-after-processing, improving the performance of the semiconductor structure.

[0027] Furthermore, the initial sacrificial layer is made of germanium-silicon, the initial channel layer is made of silicon, and the in-situ passivation process includes a low-temperature hydrogen plasma treatment process. On one hand, in the low-temperature hydrogen plasma treatment process, the atomic nuclei of hydrogen plasma are small, allowing them to easily penetrate the material surface without breaking chemical bonds. Moreover, more ion energy is stored in the material surface, and the specific incident depth depends on the ion energy, which can be adjusted by modifying the source power and bias voltage in the process parameters. On the other hand, silicon materials mainly react with free radicals and are less affected by the incident ion energy; the reaction rate changes less significantly with the ion incident depth. In contrast, germanium-containing materials (such as germanium-silicon) mainly react with ions. Specifically, as the incident ion energy increases, the etching rate of silicon materials decreases more slowly, while the etching rate of germanium-containing materials decreases more rapidly. Therefore, through the in-situ passivation treatment of the aforementioned low-temperature hydrogen plasma processing technology, the hydrogen plasma penetrates the material surface of the initial sacrificial layer and the initial channel layer with minimal disruption to the chemical bonds in the material. Furthermore, the reaction rate of the initial channel layer and the initial sacrificial layer material in the low-temperature hydrogen plasma processing technology is strongly correlated with the incident ion energy and incident depth. As the ion energy and incident depth increase, the energy stored in the material surface of the initial sacrificial layer and the initial channel layer decreases (more energy diffuses to deeper regions), resulting in a higher etching rate for silicon material than for germanium-containing material. Consequently, in a direction parallel to the substrate surface, the etching rate of the initial channel layer material is greater than that of the initial sacrificial layer material.

[0028] Furthermore, since the in-situ passivation method further includes performing the in-situ passivation until the sidewall of the intermediate sacrificial layer of the intermediate composite layer protrudes from the sidewall of the intermediate channel layer of the intermediate composite layer, after the several cycles of processing, the sidewall of the first sacrificial layer of the first fin structure can protrude from the sidewall of the first channel layer. Thus, material of the first sacrificial layer that can be etched is reserved for subsequent wet etching of several first fin structures using several fin mask structures as masks. Consequently, after the wet etching, a fin structure with smooth and vertical sidewalls can be formed to better reduce or avoid pseudo-gate residue. Attached Figure Description

[0029] Figures 1 to 3 This is a cross-sectional structural diagram of each step in a method for forming a semiconductor structure;

[0030] Figures 4 to 10 This is a schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, the performance of semiconductor devices formed in the prior art needs improvement. The following analysis will illustrate this with reference to the structure of a semiconductor.

[0032] Figures 1 to 3 This is a cross-sectional schematic diagram of each step in a method for forming a semiconductor structure.

[0033] Please refer to Figure 1 Provides a base of 100.

[0034] Please continue to refer to this. Figure 1 A plurality of sacrificial material layers 110 and a plurality of channel material layers 120 are deposited alternately on a substrate 100. The sacrificial material layers 110 are made of germanium-silicon, and the channel material layers 120 are made of silicon.

[0035] Please continue to refer to this. Figure 1 Several mutually independent mask structures 130 are formed on several sacrificial material layers 110 and several channel material layers 120.

[0036] Please refer to Figure 2 The plasma etching process using halogen gas is employed, with several mask structures 130 as masks, to etch several sacrificial material layers 110 and several channel material layers 120 until the surface of the substrate 100 is exposed, forming several mutually independent fin structures 140, wherein the fin structure 140 includes several sacrificial layers 111 and several channel layers 121 stacked alternately.

[0037] Please continue to refer to this. Figure 2 After forming several fin structures 140, the substrate 100 is etched using several mask structures 130 as masks to form a substrate 101 and an isolation fin 150 between the substrate 101 and the fin structures 140.

[0038] Please continue to refer to this. Figure 2 An isolation layer 160 is formed between adjacent isolation fins 150.

[0039] Please refer to Figure 3 A pseudo-gate 170 is formed on the isolation layer 160, spanning several fin structures 140.

[0040] The dummy gate 170 is used for positioning in the subsequent gate process to form the metal gate. The dummy gate 170 needs to be removed and replaced with the metal gate.

[0041] However, in the above method, since the sacrificial material layer 110 contains germanium, which is more reactive than silicon, during the formation of the fin structure 140 using a halogen gas plasma etching process, the sacrificial material layer 110 is more prone to chemical bond breaking and reaction than the channel material layer 120. This results in a faster etching rate for the sacrificial material layer 110 compared to the channel material layer 120. Consequently, the sidewall of the sacrificial layer 111 in the fin structure 140 is recessed relative to the sidewall of the channel layer 121 (e.g., ...). Figure 2 (As shown in region A).

[0042] Because the sidewalls of the sacrificial layer 111 are recessed relative to the sidewalls of the channel layer 121, the dummy gate 170 is difficult to remove at the recessed area and tends to remain. This results in poor performance of the semiconductor structure.

[0043] To address the aforementioned technical problems, the present invention provides a semiconductor structure and its formation method. In each cycle of processing, a predetermined number of initial composite layers are etched and passivated in situ. Furthermore, the etching rate of the initial sacrificial layer is greater than that of the initial channel layer, and the in-situ passivation process has a greater etching rate of the initial channel layer than the initial sacrificial layer in a direction parallel to the substrate surface. Therefore, the degree of concavity between the sidewalls of the first sacrificial layer and the sidewalls of the first channel layer in the formed first fin structure can be reduced. This reduces or avoids dummy gate residue in subsequent gate-after processes, thereby improving the performance of the semiconductor structure.

[0044] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] Figures 4 to 10 This is a schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0046] Please refer to Figure 4 Provides a base of 200.

[0047] The substrate 200 is made of semiconductor materials.

[0048] In this embodiment, the material of the substrate 200 includes silicon.

[0049] In other embodiments, the substrate material includes silicon carbide, silicon-germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0050] Please continue to refer to this. Figure 4 A plurality of initial composite layers 210 are formed on the substrate 200, overlapping along the normal direction of the surface of the substrate 200. Each initial composite layer 210 includes an initial sacrificial layer 211 and an initial channel layer 212 located on the initial sacrificial layer 211.

[0051] The initial composite layer 210 provides materials for forming the composite layer. Specifically, the initial sacrificial layer 211 provides materials for forming the sacrificial layer, and the initial channel layer 212 provides materials for forming the channel layer.

[0052] In this embodiment, the initial sacrificial layer 211 is made of germanium-containing material, and the initial channel layer 212 is made of silicon-containing material. Specifically, the initial sacrificial layer 211 is made of germanium-silicon, and the initial channel layer 212 is made of silicon.

[0053] The process for forming the initial sacrificial layer 211 includes chemical vapor deposition, physical vapor deposition, or epitaxial growth processes.

[0054] The process for forming the initial channel layer 212 includes chemical vapor deposition, physical vapor deposition, or epitaxial growth processes.

[0055] Please continue to refer to this. Figure 4 Several mutually independent fin mask structures 213 are formed on several initial composite layers 210.

[0056] The material of the fin mask structure 213 includes silicon nitride, or a combination of silicon nitride and silicon oxide.

[0057] In this embodiment, the fin mask structure 213 includes: a first fin mask layer (not shown) and a second fin mask layer (not shown) located on the first fin mask layer. The first fin mask layer is made of silicon nitride, and the second fin mask layer is made of silicon oxide.

[0058] In this embodiment, the fin mask structure 213 is formed using a self-aligned dual imaging process (SADP) or a self-aligned multiple imaging process (SAQP).

[0059] Specifically, the method for forming the fin mask structure 213 includes: depositing a fin mask structure material layer on the surface of a plurality of initial composite layers 210, the fin mask structure material layer including a third fin mask material layer (not shown), a first fin mask material layer (not shown) located on the surface of the third fin mask material layer, and a second fin mask material layer (not shown) located on the first fin mask material layer; and patterning the first fin mask material layer and the second fin mask material layer using a self-aligned dual imaging process or a self-aligned multiple imaging process to form the first fin mask layer and the second fin mask layer.

[0060] In this embodiment, before depositing the fin mask structure material layer, an etch stop film (not shown) is formed on the surface of several initial composite layers 210. The etch stop film serves to stop the etching process when patterning the first fin mask material layer and the second fin mask material layer. The material of the etch stop film includes silicon oxide.

[0061] Next, based on several fin mask structures 213, several initial composite layers 210 are subjected to several cycles of processing to form several mutually independent first fin structures on the substrate 200.

[0062] Each cycle of the process includes: using a number of fin mask structures as masks, etching and in-situ passivation of a predetermined number of initial composite layers; wherein the etching rate of the initial sacrificial layer material is greater than the etching rate of the initial channel layer material, and the in-situ passivation of the initial channel layer material is greater than the etching rate of the initial sacrificial layer material in a direction parallel to the substrate surface.

[0063] For detailed steps on performing several cycles of processing on several initial composite layers 210 to form several first fin structures, please refer to [link to documentation]. Figures 5 to 7 .in, Figure 5 and Figure 6 These are the detailed steps for one cycle of processing. Figure 7 This is a schematic diagram of the structure after several cycles of processing.

[0064] Please refer to Figure 5 Using several fin mask structures 213 as masks, the initial composite layer 210 of a predetermined number of layers is etched to form an intermediate composite layer 220 of the corresponding number of layers.

[0065] The etching process has a higher etching rate for the material of the initial sacrificial layer 211 than for the material of the initial channel layer 212.

[0066] The intermediate composite layer 220 includes an intermediate sacrificial layer 221 and an intermediate channel layer 222 located on the intermediate sacrificial layer 221.

[0067] Since the etching rate of the initial sacrificial layer 211 is greater than that of the initial channel layer 212, the intermediate sacrificial layer 221 tends to be recessed relative to the sidewall of the intermediate channel layer 222 in a direction parallel to the surface of the substrate 200.

[0068] Specifically, the etching process is performed using a first dry etching process.

[0069] The first dry etching process includes: a plasma etching process using halogen gas.

[0070] In this embodiment, the plasma etching process using halogen gas mainly achieves etching by breaking the chemical bonds in the material through a chemical reaction between the plasma and the material. Compared to the material of the initial channel layer 212, the material of the initial sacrificial layer 211 is more reactive due to its germanium content. Therefore, during the etching process using the first dry etching process, the material of the initial sacrificial layer 211 is more easily etched as its chemical bonds are broken and a reaction occurs. That is, in the etching process, the etching rate of the material of the initial sacrificial layer 211 is greater than the etching rate of the material of the initial channel layer 212.

[0071] It is important to understand that halogens such as fluorine, chlorine, and bromine have relatively large atomic radii, making it difficult for them to penetrate the materials of the initial sacrificial layer 211 and the initial channel layer 212. Therefore, it is difficult to achieve penetration without breaking the chemical bonds in the materials.

[0072] In this embodiment, in the intermediate composite layer 220 formed by the etching process, the widths of the intermediate channel layer 222 and the intermediate sacrificial layer 221 are both greater than the width of the fin mask structure 213. This reserves material for subsequent in-situ passivation and subsequent cycles, allowing for the formation of a second fin structure with a smaller deviation from the target width.

[0073] In this embodiment, the number of preset number layers is 1.

[0074] Accordingly, the etching process further includes: using the fin mask structure 213 as a mask, etching an initial composite layer 210 until the surface of the initial composite layer 210 or the substrate 200 adjacent to the initial composite layer 210 is exposed.

[0075] It should be noted that, for ease of explanation and understanding, Figure 5 The image schematically illustrates the etching process performed on the initial composite layer 210 at the top layer, and the corresponding formation of an intermediate composite layer 220.

[0076] Since the preset number of layers is one, not only is the control over the morphology and size of each intermediate composite layer 220 further improved when the etching process forms the intermediate composite layer 220, but the subsequent in-situ passivation process also allows for more thorough thinning of the intermediate channel layer 222, while simultaneously improving the control over the morphology and size during thinning. Therefore, after several cycles of processing, a first fin structure that more closely matches the expected morphology and size can be formed.

[0077] In other embodiments, the preset number of layers is two or more to improve process efficiency.

[0078] Please refer to Figure 6 The intermediate composite layer 220 is subjected to in-situ passivation treatment, wherein the etching rate of the material of the initial channel layer 212 in the direction parallel to the surface of the substrate 200 is greater than the etching rate of the material of the initial sacrificial layer 211.

[0079] Since the initial composite layer 210 of a predetermined number of layers is etched and passivated in each cycle, the intermediate channel layers 222 after etching can be thinned in a direction parallel to the surface of the substrate 200 without breaking the vacuum. At the same time, the intermediate sacrificial layer 221 is not consumed or is thinned to a smaller thickness. Therefore, after several cycles, the degree of concavity of the sidewall of the first sacrificial layer relative to the sidewall of the first channel layer can be reduced. This reduces or avoids dummy gate residue in subsequent gate-back processes and improves the performance of the semiconductor structure.

[0080] In this embodiment, the in-situ passivation process includes: low-temperature hydrogen plasma treatment.

[0081] On the one hand, in low-temperature hydrogen plasma processing, the small atomic nuclei of hydrogen plasma allow it to easily penetrate the material surface without breaking chemical bonds. Furthermore, the ion energy is largely stored in the material's surface, and the specific incident depth depends on the ion energy, which can be adjusted by controlling the source power and bias voltage in the process parameters. On the other hand, silicon materials primarily react with free radicals and are less affected by the incident ion energy; the reaction rate changes less significantly with the ion incident depth. In contrast, germanium-containing materials (such as germanium-silicon) primarily react with ions. Specifically, as the incident ion energy increases, the etching rate of silicon materials decreases more slowly, while the etching rate of germanium-containing materials decreases more rapidly.

[0082] Based on the above principles, it can be seen that through the in-situ passivation treatment of the low-temperature hydrogen plasma processing technology, the hydrogen plasma penetrates the material surface of the initial sacrificial layer 211 and the initial channel layer 212 with minimal disruption to the chemical bonds in the material. Furthermore, the reaction rate of the low-temperature hydrogen plasma processing technology on the material of the initial channel layer 212 and the initial sacrificial layer 211 is strongly correlated with the incident ion energy and incident depth. As the ion energy and incident depth increase, the energy stored on the material surface of the initial sacrificial layer 211 and the initial channel layer 212 decreases (more energy diffuses to deeper regions), resulting in a higher etching rate for silicon than for germanium-containing materials. Therefore, in the direction parallel to the surface of the substrate 200, the etching rate of the material of the initial channel layer 212 (silicon material) is greater than the etching rate of the material of the initial sacrificial layer 211 (germanium-containing material).

[0083] In this embodiment, the reactant gas used in the low-temperature hydrogen plasma processing process includes hydrogen. Thus, by dissociating the hydrogen, a high-purity hydrogen plasma is formed, thereby improving the etching precision of the low-temperature hydrogen plasma processing process.

[0084] In this embodiment, by adjusting the dissociation voltage, i.e. the source voltage, the incident ion energy and incident depth are adjusted to adjust the etching selectivity ratio of the material of the initial sacrificial layer 211 and the material of the initial channel layer 212, so that the etching rate of the material of the initial channel layer 212 is greater than the etching rate of the material of the initial sacrificial layer 211 in the direction parallel to the surface of the substrate 200.

[0085] In some other embodiments, the ratio of free radicals to ions can be adjusted by filtering the hydrogen plasma formed by dissociation through the formation of a bias electric field and the adjustment of the voltage of the bias electric field, thereby achieving the adjustment of the etching selectivity ratio of the materials of the initial sacrificial layer 211 and the initial channel layer 212.

[0086] In other embodiments, the etching selectivity ratio of the materials of the initial sacrificial layer 211 and the initial channel layer 212 is adjusted by regulating the dissociation voltage and forming a bias electric field.

[0087] In this embodiment, the parameters of the low-temperature hydrogen plasma processing technology also include: the source power is 500W~1200W.

[0088] When the source power is 500W~1200W, the etching selectivity ratio of the initial channel layer 212 material and the initial sacrificial layer 211 material in the in-situ passivation process can be greater than 5:1. In this way, the intermediate channel layer 222 can be thinned more fully, and the consumption of the intermediate sacrificial layer 221 can be further reduced. Thus, the degree of depression of the first sacrificial layer relative to the first channel layer in the first fin structure can be better reduced.

[0089] In this embodiment, the parameters of the low-temperature hydrogen plasma treatment process also include: the bias voltage is below 50 volts.

[0090] A bias voltage below 50 volts enables the low-temperature hydrogen plasma processing to primarily etch the material of the initial channel layer 212 in a direction parallel to the surface of the substrate 200, and reduces the etching of the material of the initial channel layer 212 and the initial sacrificial layer 211 along the normal direction of the surface of the substrate 200. This not only allows for sufficient thinning of the intermediate channel layer 222 in a direction parallel to the surface of the substrate 200 without breaking the vacuum, and ensures that the intermediate sacrificial layer 221 is not consumed or has a smaller material thickness, but also better reduces the loss of the initial composite layer 210 that has not undergone etching.

[0091] Preferably, the bias voltage is 0 volts.

[0092] It should be noted that, in this embodiment, since the etching stop film is formed, the exposed etching stop film is consumed by the same etching process as the etching process before the cycle process is performed.

[0093] In this embodiment, the in-situ passivation process further includes: performing the in-situ passivation process until the sidewall of the intermediate sacrificial layer 221 of the intermediate composite layer 220 protrudes from the sidewall of the intermediate channel layer 222 of the intermediate composite layer 220.

[0094] Since the in-situ passivation method further includes performing the in-situ passivation until the sidewall of the intermediate sacrificial layer 221 of the intermediate composite layer 220 protrudes from the sidewall of the intermediate channel layer 222 of the intermediate composite layer 220, after several cycles of processing, the sidewall of the first sacrificial layer of the first fin structure can protrude from the sidewall of the first channel layer. This reserves excess material of the first sacrificial layer for subsequent wet etching of several first fin structures using several fin mask structures 213 as masks. Furthermore, after the wet etching, a fin structure with smooth and vertical sidewalls (i.e., the second fin structure subsequently formed in this embodiment) can be formed, thereby better reducing or avoiding spurious gate residue.

[0095] In another embodiment, the in-situ passivation method further includes: performing the in-situ passivation until the sidewall of the intermediate sacrificial layer of the intermediate composite layer is flush with the sidewall of the intermediate channel layer of the intermediate composite layer.

[0096] Please refer to Figure 7 The process is repeated several times to form a plurality of mutually independent first fin structures 230 on the substrate 200. Each first fin structure 230 includes a plurality of first composite layers (not shown) overlapping in the normal direction of the surface of the substrate 200. Each first composite layer includes a first sacrificial layer 231 and a first channel layer 232 located on the first sacrificial layer 231.

[0097] In this embodiment, the sidewall of the first sacrificial layer 231 of the first fin structure 230 protrudes from the sidewall of the first channel layer 232. Therefore, sufficient excess material can be reserved for subsequent wet etching, thereby forming a second fin structure with smooth and vertical sidewalls after wet etching, which can better reduce or avoid dummy gate residue.

[0098] In another embodiment, after the plurality of cycles, the sidewall of the first sacrificial layer of the first fin structure is flush with the sidewall of the first channel layer.

[0099] In this embodiment, the material of the first sacrificial layer 231 includes germanium silicon, and the material of the first channel layer 232 includes silicon.

[0100] Please refer to Figure 8 The second dry etching process is used, and several fin mask structures 213 are used as masks to etch the substrate 200 to form a substrate 201 and an isolation fin 202 located between the substrate 201 and the first fin structure 230.

[0101] In the second dry etching process, the etching rate of the material of the substrate 200 and the initial channel layer 212 is greater than the etching rate of the material of the initial sacrificial layer 211.

[0102] The etching rate of the initial channel layer 212 material in the second dry etching process is less than the etching rate of the initial channel layer 212 material in the first dry etching process. This allows for the refinement of the morphology of the first channel layer 232 while forming the isolation fins 202.

[0103] Please refer to Figure 9 A wet etching process is used, and several fin mask structures 213 are used as masks to etch several first fin structures 230 to form several second fin structures 240.

[0104] By employing a wet etching process and using several fin mask structures 213 as masks to etch several first fin structures 230, on the one hand, etching byproducts remaining from several cycles of processing and the second etching process can be removed; on the other hand, the damaged sidewall surface layer of the first fin structures 230 after the first and second dry etching processes bombard the material surface can be removed, forming fin structures (second fin structures 240) with better interface states and morphology. Thus, the performance of the semiconductor structure is significantly improved.

[0105] In this embodiment, the second fin structure 240 includes a plurality of second composite layers (not shown) overlapping along the normal direction of the surface of the substrate 201. Each second composite layer includes a second sacrificial layer 241 and a second channel layer 242 located on the second sacrificial layer 241. The sidewall of the second sacrificial layer 241 is flush with the sidewall of the second channel layer 242.

[0106] It should be understood that, since the material of the first sacrificial layer 231 is more reactive than the material of the first channel layer 232, the reaction solution in the wet etching process reacts more easily with the material of the first sacrificial layer 231, resulting in a higher etching rate of the first sacrificial layer 231 than the etching rate of the material of the first channel layer 232 in the wet etching process.

[0107] In this embodiment, the first sacrificial layer 231 with protruding sidewalls provides sufficient excess material for the wet etching process, thus enabling the formation of a second sacrificial layer 241 and a second channel layer 242 with flush sidewalls. This better reduces or avoids spurious gate residue.

[0108] Please refer to Figure 10 After the second fin structure 240 is formed, an isolation structure 250 is formed between adjacent isolation fins 202, the surface of the isolation structure 250 being flush with or higher than the top surface of the isolation fin 202.

[0109] The material of the isolation structure 250 is a dielectric material.

[0110] The isolation structure 250 is used for electrical insulation between adjacent devices.

[0111] Preferably, the surface of the isolation structure 250 is higher than the top surface of the isolation fin 202 to further reduce the risk of short circuits between adjacent devices.

[0112] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed by the above method. Please refer to [further details]. Figure 10The system includes: a substrate 201; and a plurality of second fin structures 240 disposed on the substrate 201 and disposed separately from each other. The second fin structure 240 includes a plurality of second composite layers overlapping along the normal to the surface of the substrate 201. Each second composite layer includes a second sacrificial layer 241 and a second channel layer 242 disposed on the second sacrificial layer 241, and the sidewall of the second sacrificial layer 241 is flush with the sidewall of the second channel layer 242.

[0113] The substrate 201 is made of semiconductor material.

[0114] In this embodiment, the substrate 201 is made of silicon.

[0115] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0116] In this embodiment, the material of the second sacrificial layer 241 is a germanium-containing material, and the material of the second channel layer 242 is a silicon-containing material.

[0117] Specifically, the material of the second sacrificial layer 241 includes germanium silicon, and the material of the second channel layer 242 includes silicon.

[0118] In this embodiment, the semiconductor structure further includes an isolation fin 202 located between the substrate 201 and the second fin structure 240.

[0119] The material of the isolation fin 202 includes silicon.

[0120] In this embodiment, the semiconductor structure further includes an isolation structure 250 located between adjacent isolation fins 202, the surface of the isolation structure 250 being flush with or higher than the top surface of the isolation fins 202.

[0121] The material of the isolation structure 250 is a dielectric material.

[0122] The isolation structure 250 is used for electrical insulation between adjacent devices.

[0123] Preferably, the surface of the isolation structure 250 is higher than the top surface of the isolation fin 202 to further reduce the risk of short circuits between adjacent devices.

[0124] Those skilled in the art will understand that the above-mentioned semiconductor structure can be generated by the aforementioned semiconductor structure formation method.

[0125] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a plurality of initial composite layers overlapping along the normal direction of the substrate surface, each initial composite layer including an initial sacrificial layer and an initial channel layer located on the initial sacrificial layer; Several mutually independent fin mask structures are formed on several initial composite layers; Based on the fin mask structure, the initial composite layers are subjected to several cycles of processing to form several mutually independent first fin structures on the substrate. The first fin structure includes several first composite layers overlapping in the normal direction of the substrate surface. Each first composite layer includes a first sacrificial layer and a first channel layer located on the first sacrificial layer. The method of each cycle of processing includes: etching and in-situ passivation of a predetermined number of initial composite layers. The etching process has a higher etching rate for the initial sacrificial layer material than for the initial channel layer material, and the in-situ passivation process has a higher etching rate for the initial channel layer material than for the initial sacrificial layer material in a direction parallel to the substrate surface.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the initial sacrificial layer includes germanium silicon, the material of the initial channel layer includes silicon, and the in-situ passivation process includes a low-temperature hydrogen plasma treatment process.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The gas used in the low-temperature hydrogen plasma treatment process includes hydrogen.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The parameters of the low-temperature hydrogen plasma processing technology also include: the source power is 500W~1200W.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The parameters of the low-temperature hydrogen plasma treatment process also include: the bias voltage is below 50 volts.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for etching and in-situ passivation of the initial composite layer with a predetermined number of layers includes: Using the fin mask structure as a mask, the etching process is performed on the initial composite layer of a predetermined number of layers to form the corresponding intermediate composite layer; The intermediate composite layer is subjected to the in-situ passivation treatment.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The intermediate composite layer includes an intermediate sacrificial layer and an intermediate channel layer located on the intermediate sacrificial layer; The in-situ passivation method further includes: performing the in-situ passivation until the sidewall of the intermediate sacrificial layer of the intermediate composite layer protrudes from the sidewall of the intermediate channel layer of the intermediate composite layer. After several cycles of processing, the sidewall of the first sacrificial layer of the first fin structure protrudes from the sidewall of the first channel layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: After several cycles of processing, a wet etching process is used, and several first fin structures are etched using several fin mask structures as masks to form several second fin structures. The second fin structure includes several second composite layers overlapping along the normal direction of the substrate surface. Each second composite layer includes a second sacrificial layer and a second channel layer located on the second sacrificial layer, and the sidewall of the second sacrificial layer is flush with the sidewall of the second channel layer.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, The intermediate composite layer includes an intermediate sacrificial layer and an intermediate channel layer located on the intermediate sacrificial layer; The in-situ passivation method further includes: performing the in-situ passivation until the sidewall of the intermediate sacrificial layer of the intermediate composite layer is flush with the sidewall of the intermediate channel layer of the intermediate composite layer. After several cycles of processing, the sidewall of the first sacrificial layer of the first fin structure is flush with the sidewall of the first channel layer.

10. The method for forming a semiconductor structure as described in claim 6, characterized in that, The intermediate composite layer includes an intermediate sacrificial layer and an intermediate channel layer located on the intermediate sacrificial layer, wherein the width of the intermediate sacrificial layer and the intermediate channel layer are both greater than the width of the fin mask structure.

11. The method for forming a semiconductor structure as described in claim 6, characterized in that, The preset number of layers is 1 layer, and the etching process further includes: using the fin mask structure as a mask, etching 1 initial composite layer until the surface of the initial composite layer or the substrate adjacent to the 1 initial composite layer is exposed.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching process is performed using a first dry etching process.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The first dry etching process includes: a plasma etching process using halogen gas.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming a plurality of mutually independent first fin structures on the substrate, the method further includes: using a second dry etching process and etching the substrate with a plurality of fin mask structures as masks to form a substrate and isolation fins located between the substrate and the first fin structures; forming an isolation structure between adjacent isolation fins, wherein the surface of the isolation structure is flush with or higher than the top surface of the isolation fin.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The substrate is made of silicon, the initial channel layer is made of silicon, and in the second dry etching process, the etching rate of the substrate and the initial channel layer is greater than the etching rate of the initial sacrificial layer.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The fin mask structure is formed using a self-aligned dual imaging process or a self-aligned multiple imaging process.

17. A semiconductor structure, characterized in that, The semiconductor structure is formed using the semiconductor structure forming method according to any one of claims 1 to 16, and the semiconductor structure comprises: Substrate; A plurality of second fin structures are located on the substrate and are independent of each other, the sidewalls of the second fin structures are flush with each other; the second fin structure includes a plurality of second composite layers overlapping along the normal of the surface of the substrate, each second composite layer includes a second sacrificial layer and a second channel layer located on the second sacrificial layer, and the sidewall surface of the second sacrificial layer is flush with the sidewall surface of the second channel layer.

18. The semiconductor structure as claimed in claim 17, characterized in that, The material of the second sacrificial layer includes germanium silicon, and the material of the second channel layer includes silicon.

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